# Patent

## Title
Flat flexible cable with pseudo-twisted conductors

## Abstract

This is a Continuation of International Appln. No. PCT/GB96/01259 filed May 28, 1996 which designated the U.S.

## Background
The present invention relates to methods and apparatus for processing an input signal (particularly QPSK and .pi./4 QPSK signals), or components thereof, to provide highly efficient linear amplification, modulation and demodulation.

A LINC amplifier has been proposed (see D. C. Cox, "Linear Amplification Using Non-Linear Components", IEEE Transactions on Communications, Vol. COM-22, 1974, pages 1942 to 1945) in which a modulating signal is split into two phase modulated components with constant envelopes which can be amplified separately using highly non-linear but power efficient amplifiers. Combining the two output signals yields the desired linearly amplified signal. With a LINC amplifier the potential for dc to RF conversion efficiency can approach 100%, assuming ideal matching amplifiers. However, in practical LINC amplifiers, the suppression of broadband phase modulation relies on a very tight tolerance on the gain and phase match between the two paths. A gain error of 0.01 dB and a phase error of 0.1.degree. give a component suppression of only 54 dB. Such a tolerance is impossible to achieve in a open loop system where much greater gain and phase variations can occur with changes in operating frequency, output power and temperature, and the ageing of components.

International Application No. WO 93/23921-A, the entire contents of which is incorporated herein by reference, has the same overall objectives as the present invention. The arrangements described in the above application are complicated by stability problems leading to switching complexity from certain phases of input signals. Also some of these circuits suffer to some extent from noise problems when the envelope of an applied input signal such as a QPSK or a .sup..pi./ 4 QPSK signal goes through zero. The phase locked loops, containing the Voltage Controlled Oscillators (VCOs), of these circuits are stable only when the input signals are in a certain phase range. The switching arrangement attempts to switch the input signal into stable region of operation. The disadvantage of the above arrangements are that the switching is only triggered when the input signal crosses from the stable quadrant into an unstable quadrant. This results in noise being generated when the switching occurs, and the input and output vectors may be out of lock because the VCOs cannot respond with sufficient speed.

U.S. Pat. No. 5,105,168 describes a vector locked loop (VLL) which suffers from an input amplitude response which rises with the input signal amplitude. The Voltage Controlled Oscillators (VCO) have an output frequency that is very sensitive to noise and temperature. In the configuration shown in FIG. 8, in particular, the apparatus may have some initial difficulty in acquiring a lock on the signal because the two VCOs may have output frequencies which are far away from the carrier frequency. Since the two VCO outputs are combined to form the output signal, which is then mixed down and fed back into the input, the feedback signal may be outside the working bandwidth of the circuit. Thus the circuit cannot function properly to pull the VCO back into the working frequency and cannot acquire a lock on the input signal.

According to a first aspect of the present invention there is provided apparatus for processing an input signal to generate an output signal, the processing arrangement comprising respective output signal components and ensuring that the components are correctly in phase for this purpose, phase which is variable in response to a control signal, for generating a loop output signal which forms one of the components of the output signal, or from which one such component is derived, and a comparator for generating the control signal, and representative of the output signal or signals representative of components of the output signal, and dependent on the representative signal or representative signals and in phase quadrature with one another, the comparator and another input of the comparator being coupled to receive a component of the input signal

characterised in that stable whatever the phase of the output signal relative to the input signal.

The VCOs of sensitivity c may receive first and second control signals (v.sub.1 and v.sub.2) according to the equations ##EQU1## where .DELTA..phi. and .DELTA.r are the phase and amplitude differences, respectively, between the input signal to be processed and the processed output signal, signal back to the detectors.

An advantage of the invention is that the system is stable and no switching of the input signals is necessary.

The means for providing feedback loop operating signals may include an oscillator having quadrature output signals, and first and second mixers, one for each loop, for generating the first and second feedback loop operating signals, the mixers both being coupled to receive the said representative signal as one input, and to receive respective quadrature output signals from the oscillator as another input.

The apparatus may also include an amplifier for each loop connected between the voltage controlled oscillator for that loop and a respective input of the combining means.

The input signal may be in the form of Cartesian components x and y and the signal-stability means and the comparators may derive control signals v.sub.1 and v.sub.2 for the respective VCOs: ##EQU2## where k=the loop gain of the feedback loops, y, corresponding Cartesian component of the processed output signal, and corresponding Cartesian component of the processed output signal.

The above equations are simplified versions of equations which provide the optimum driving signals for the VCOs.

In other embodiments of the invention the phase of a vector representing the input signal is, in effect, changed continuously to always occupy an optimum position for stability.

As an alternative, in some embodiments of the invention the input signal vector is so biassed that when the envelope of the input passes through zero, the envelope of the biassed signal does not. Such an arrangement not only reduces noise but also ensures stability.

According to a second aspect of the present invention there is provided apparatus for processing an input signal to provide a processed output signal, comprising signal to be processed and a feedback signal as inputs, having frequencies or phases which are variable in response to first and second control signals, processed output signal, components thereof, the phase detector and a corrected signal derived from the output signal of the amplitude detector to generate the first control signal, signal of the phase detector to generate the second control signal, and to be processed to reduce the dependence of the amplitude response of the apparatus on the amplitude of the input signal.

Methods equivalent to the first and second aspects of the invention and the apparatus claimed also form part of the invention, such as a method of processing a input signal to generate an output signal including the steps of respective output signal components and ensuring that the components are correctly in phase for this purpose, frequency or phase which is variable in response to a control signal, a loop output signal which forms one of the components of the output signal, or from which one such component is derived, representative of the output signal or signals representative of components of the output signal, another, from the representative signal or representative signals, one for each loop, and component of the input signal to provide the respective control signal signal relative to the input signal.

In order to avoid the disadvantages outlined above in respect of VCOs, the VCOs may be allowed to phase lock onto a voltage controlled crystal oscillator (VCXO). The frequency of the VCXO may be changed by a small fraction by applying a control voltage, and the output frequency is precise and more stable than a normal VCXO.

Embodiments of the invention will now be described by reference to the following drawings, in which:

FIG. 1 is a block diagram of a modulator according to the invention,

FIG. 2 is a diagram showing vectors relevant to the operation of FIG. 1,

FIG. 3 is a block diagram of a modulator according to the invention in which control signals according to certain equations are derived from Cartesian components of an input signal,

FIG. 4 is a simplified version of FIG. 3 in which the derivation of the control signals avoids the operation of division,

FIG. 5 is a diagram showing the zone which an input vector must occupy for stable operation of the invention,

FIG. 6 is a block diagram of a modulator according to the invention in which, in effect, the phase of the input signal is changed to always be optimum for stability,

FIG. 7 is a diagram of a modulator according to the invention, in which the input signal is, in effect, biassed from a position where its envelope may go through zero to a position where it cannot do so,

FIG. 8 is a diagram of a synthesizer according to the invention employing phase and amplitude detectors and, optionally, means for generating a correction signal, and

FIG. 9 is a diagram used in explaining how first order modulators according to the invention may be implemented, and

FIG. 10 is a diagram of another synthesizer according to the invention employing phase and amplitude detectors and, optionally, means for generating a correction signal.

FIG. 1 shows the basic structure of a modulator employing two feedback loops, each comprising a VCO 10,11, a non-linear radio-frequency amplifier 12,13 and a mixer 14,15, to synthesize an output signal at the output of a summing circuit 16. The input for the circuit is the Cartesian components I and Q, of a signal s(t) separated in a known way or already existing for example in a DSP, and applied as signals x and y to a control signal generator 17. The mixers 14 and 15 receive the output of the circuit 16 and respective quadrature demodulating signals cos .omega..sub.c t and sin .omega..sub.c t, where .omega..sub.c is the difference in frequency between the signals x and y and the output signals of the VCOs. The output signals of the mixers 14 and 15 are applied to the generator 17.

A vector diagram showing signals relevant to FIG. 1 is shown in FIG. 2 where the signal s(t) is represented by a vector (18), r, .phi., vectors 19 and 20 represent the output signals R.theta..sub.1 and R.theta..sub.2 of the VCOs 10 and 11, respectively, and a vector 21 represents the output signal l,.alpha. of the summing circuit 16. The vectors 19 and 20 are each separated by an angle .theta. from the vector 21.

It can be seen that, ##EQU3## where .alpha. is the output signal phase from summing circuit 16, .phi. is the phase of the input signal r, .phi., .DELTA..phi. is the phase difference between the input and output signals and l is the output signal amplitude.

It can be shown that in an ideal closed loop configuration of FIG. 1 where changes in the input signals x and y are compensated by changes in the output signals of the VCOs 10 and 11, the control signals v.sub.1 and v.sub.2 applied to these VCOs, respectively are given by ##EQU4## where c is the sensitivities of the VCOs 10 and 11, r' is ##EQU5##

In order to realise a practical physical implementation of these equations some simple approximations may be made. For example, it can be assumed that .delta.x/.delta.t is proportional to .delta.x, and .delta.x can be approximated by .DELTA.x which is the difference between the x component of the input signal and the x component of the system output signal. The same approximation can be applied to .delta.y/.delta.t, .omega. and r'. The control process can then be described by, ##EQU6## where k is the loop gain of the system.

From these equations it is possible to devise two generic forms of control circuit implementation--one using Cartesian (IQ) feedback, the other using vector (phase and amplitude) feedback.

FIG. 3 shows a modulator which implements equations 4 and 6 and uses Cartesian feedback paths by way of the mixers 14 and 15. The control signal generator 17 comprises a DSP 22 which may either receive the signals x and y or these signals may already be present in the DSP as part of other signal processing. The DSP generates signals a1, a2, a3 and a4 where ##EQU7##

The signals a1, a2, a3 and a4 are applied by way of connections 23 and 25 to a multiplying matrix 24 comprising four multipliers. Two comparators 26 and 27 form .DELTA.x and .DELTA.y from the signals x and y (sent by way of the DSP 22) and the outputs of the mixers 14 and 15. The output signal amplitude R of the VCOs 10 and 11 is known, and thus the matrix 24 is able to generate the control signals v.sub.1 and v.sub.2 for the VCOs. The matrix 24 may be constructed from commercially available analogue multipliers when digital-to-analogue converters (not shown) are positioned at the outputs of the DSP 22 or the matrix 24 may be formed by multiplying digital-to-analogue converters at the DSP outputs.

For an input signal phase of .phi. and an output signal phase of a, the stable locked condition occurs when .alpha. equals .phi., and all the derivatives of .alpha. at .alpha.=.phi. are zero. Using these stability criterion, it can be seen that the modulator of FIG. 3 is stable for any input signal phase without the use of the switching arrangements described in the above mentioned application WO 93/23921-A.

The division process implicit in equations 4 and 6 can be avoided by simplification to the following equations: ##EQU8##

Equations 7 and 8 can be implemented using the arrangement of FIG. 4 where a summing junction 28 and a summing junction 29, arranged to subtract, generate the following signals x+y and x-y for the multiplying matrix 24.

A simplified version can be derived from equations 7 and 8 by hard-limiting the terms (x-y) and (x+y). ##EQU9## After scaling and rotating the system by 45.degree. ##EQU10##

As is known from the above mentioned application WO 93/23921-A, the phase locked loops embodying the VCOs are stable only when input signals are in a certain phase range. As a result some two-feedback loop arrangements are only stable when the input vector r, .phi. is in the semicircular shaded region 31 of FIG. 5. The switching arrangements are provided to ensure that the Cartesian components of the input vector are shifted so that this vector is translated to the stable region 31. It can be shown that the optimum phase position of this vector is -45.degree.+2.pi.n, where n is an integer as shown at 32.

In the said above mentioned application, the input signal is restricted by four quadrature switching to one quadrant (the 4th quadrant). From equations 9 and 10 the control signals become: ##EQU11##

The synthesizer of FIG. 6 includes summing circuits 34 and 35, and a phase shifter 33 to shift the phases of the input signals for the VCOs 10 and 11 as though the vector r, .phi. were continuously held in the optimum position shown at 32, as the input vector varies in phase. As a result the output vector 1, .alpha. always lags 45.degree. behind the input vector r, .phi. in the steady state.

The phase shifter 33 ensures that whatever the phase of the input vector, the input signals for the VCOs represent the input vector shifted to the fourth quadrant (bottom right in FIG. 5) but the shifted vector tends to settle on either the x or y axis not the position 32. By adding the x and y signals in the summing circuit 34 and subtracting them in the summing circuit 35, the input signals for the comparators 26 and 27 represent an input signal shifted by 45.degree. to the optimum position 32.

If the input signal is considered to be re.sup.j.beta., where .beta. is its phase angle, then the phase shifter 33 performs the following complex multiplication ##EQU12##

The real part of this equation is the control signal for the VCO 10 and the imaginary part is the control signal for the VCO 11. The denominator normalises the control signals.

Most versions of the modulator of FIG. 1, using either Cartesian or Vector feedback, cannot respond fast enough when the envelope of the vector r, .phi. crosses zero. The control signal generator cannot respond sufficiently fast to prevent the input and output vectors being out of lock and noise being generated as a consequence. An arrangement which overcomes this problem is shown in FIG. 7 where an extra VCO 36 and non-linear amplifier 37 provide an additional input for the summing circuit 16. The output of the amplifier 37 is demodulated using a sin .omega..sub.c signal in a mixer 38 with output connected to the inverting input of a comparator 39 which receives they signal at its non-inverting input.

Since the VCO 36 receives the difference between the y signal and its own Q output component after amplification, its output is nearly equal to the Q component of the output signal, plus a time varying portion of the I component. The control signals for the VCOs 10 and 11 are based on the resultant output signal from the summing circuit 16, and thus the output signals of these VCOs compensate for the output signal of the VCO 36 at that sunning circuit. Hence the combined output of the VCOs 10 and 11 is biased to oppose the I component from the VCO 36, which has the effect that when the input signal envelope crosses zero the operating point of the VCO 10 is shifted from zero and so the zero crossing does not affect the control circuit and noise is not generated. Incidentally since most of the Q component is provided by the VCO 36, the VCOs 10 and 11 only provide a small correcting Q component. Since the loops containing the VCOs 10 and 11 function in the normal way the bias, together with any I and Q error at the output is removed at the output as in previous examples. By adding the VCO 36, the inputs to the other VCOs (10 and 11) are mapped to a new position on the vector diagram as follows ##EQU13## Thus the input signal is mapped to the stable region 31 of FIG. 5 and no switching or phase shifting (for example in a multiplying matrix) is required.

The operation of the circuit is substantially the same when an optional inverting amplifier 40 with gain equal to 0.5 and an addition circuit 41 are added as shown in dashed lines.

A vector locked loop (VLL) system based on equations 3 and 5 is now described and shown in FIG. 8. The phases and amplitudes of an input signal s(t) and a modulated output signal present at the output of a summing circuit 43 are compared in phase and amplitude detector circuits 44 and 45. VCOs 46 and 47 receive input signals from the detectors 44 and 45 by way of a summing circuit 47, arranged to subtract, and a summing circuit 48. Non-linear amplifiers 49 and 50 provide amplified output signals from the VCOs 46 and 47 as input signals to the summing circuit 43. The output signal of this summing circuit is demodulated using a mixer 51 supplied with a local oscillator signal at a frequency equal to the difference between the output signal frequency of the VCOs 46 and 47 and the frequency of the input signal s(t), and the mixer output is fed back to the detectors 44 and 45.

The signals v.sub.1 and v.sub.2 applied at the inputs to the VCOs 46 and 47 are given by: ##EQU14## where .DELTA..phi. is the phase difference between the input signal phase and output signal phase and .DELTA.l is the magnitude difference.

The phase response of the feedback loops of FIG. 8 is independent of the input signal but the amplitude is a positive function of the input amplitude which increases with input amplitude. To improve performance a correction-signal generator 53 and a multiplying circuit 54 can be added as shown in dashed lines.

The signal generated by the correction-signal generator 53 equals ##EQU15## and when used as a multiplier for the .DELTA.r signal in the multiplier 54, the VCO input signals conform to equations 3 and 5.

Some other functions which have a positive relationship with the input signal amplitude r can also be used as the correction signal. For example the signal generated by the correction-signal generator may equal ##EQU16##

The correction signal generator may for example comprise a commercially available anti-log, circuit or be implemented as part of a DSP program, in a DSP which may form part of an overall system including FIG. 8.

The tracking performance of the modulators of FIGS. 3, 4 and 6 to 8 and other modulators or synthesizers using VCOs or equivalent based on FIG. 1, can be improved by adding a loop filter known from VCO theory, at the input to each VCO, thus providing first order modulators or synthesizers. A suitable filter is shown in FIG. 9 and comprises an integrator 55, a linear amplifier 56 having a gain of k' (a constant value not dk/dt) and summing circuit 57 adding the usual VCO input applied by way of a path 58 to the output of the amplifier 56. The output of the circuit 57 may be applied as the control signal for each of the VCOs in any of the modulators described, for example one circuit of FIG. 9 may be connected between each output of the generator 17 and the respective VCOs 10 and 11 to replace the connections shown in FIG. 3. A significant 15 dB improvement in intermodulation suppression has been achieved over a zero order VLL modulator of the type shown in FIG. 8 by converting the first order.

An alternative to the vector locked loop system of FIG. 8 is shown in FIG. 10. In this embodiment the two VCOs, 71 and 72, are synchronised, driven by the amplitude detector 61. In a system where the VCOs function independently, (such as FIG. 8) the centre frequencies of the VCOs may drift so far apart as to prevent the system from locking. Therefore the VCOs 71 and 72 may be allowed to phase lock onto a voltage controlled crystal oscillator reference (VCXO 64) using phase locked loops. When functioning, the phase output of the two VCOs 71 and 72 will be the same as the output of the reference VCXO 64. These two phase outputs are combined by the combiner 73 to give the system output. The output signal of this combining circuit is demodulated using a mixer 74 supplied with a local oscillator signal at a frequency equal to the difference between the output signal frequency and the frequency of the input signal s(t), and the mixer output is fed back to the detectors 60 and 61. The output of the amplitude detector 61 is used to drive the VCOs in opposite directions, modifying the relative phase of the two VCO outputs, thus changing the amplitude of the output envelope. The output frequency of the two VCOs 71 and 72 will always be N times the reference signal, where N is the division ratio of the two phase locked loops. The components 75 and 76 which produce this modification of the reference signal may be programmable dividers.

It will be realised that the invention can be put into operation in many other ways than those specifically described. For example the VCOs may be any frequency generator having an output signal which can be controlled using a control signal, for example some forms of unstable amplifier or direct digital synthesizers. Other forms of loop filters may be used for first order systems and the control signal generator 17 may be completely or partially implemented in hardware, or computer programs such as a programmed DSP, provided conversion of the DSP output signals to analogue is provided.

As described in the above mentioned application WO 93/23921-A the modulators described may be reconfigured as demodulators, or as amplifiers without frequency translation, when the multipliers 14 and 15 are omitted, or the modulators may provide frequency translation without the use of a carrier wave.

## Claims

1. Apparatus for processing an input signal to generate a combined signal, said apparatus comprising signal, first and second loop output signals, respectively, and ensuring that the loop output signals have a phase relation corresponding to one among a set of predetermined phase relations, oscillator, having one of a frequency and a phase which is variable in response to a signal v.sub.1, for generating a first oscillator signal, said first loop output signal being based at least in part on the first oscillator signal, and a first comparator for generating a first control signal, the signal v.sub.1 being based at least in part on the first control signal, oscillator, having one of a frequency and a phase which is variable in response to a signal v.sub.2, for generating a second oscillator signal, said second loop output signal being based at least in part on the second oscillator signal, and a second comparator for generating a second control signal, the signal v.sub.2 being based at least in part on the second control signal, and combined signal, and at least in part on the combined signal and in phase quadrature with one another, and for each loop, applying the feedback loop operating signal to one input of the comparator one of a first loop input signal and a second loop input signal, and ensuring that the combined signal is stable whatever the phase of the combined signal relative to the input signal, said signal-stability means receiving the input signal and outputting the first and second loop input signals.

2. Apparatus according to claim 1 wherein the means for providing the feedback loop operating signals includes second feedback loop operating signals, the mixers both being coupled to receive the combined signal as one input, and to receive respective quadrature output signals from the oscillator as another input.

3. Apparatus according to claim 1 including an amplifier for each loop connected between the voltage controlled oscillator and a respective input of the combining means.

4. Apparatus according to claim 2 wherein signal for the combining means which has the effect of so biassing the input signal that when the envelope of the unbiassed signal passes through zero the envelope of the biassed signal, as represented by the loop input signals, does not, and signal-stability comparator, signal-stability means for generating a loop output signal having a frequency or phase which is variable in response to a control signal, a signal-stability amplifier connected at the output of the signal-stability means for generating a loop output signal and a signal-stability multiplier for demodulating the amplifier output signal using a signal in phase with one of the quadrature output signals to provide one input to the signal-stability comparator, the other input to the signal-stability comparator being one of the x and y signals.

5. Apparatus according to claim 4 including comparators to the feedback signal applied to the other of the first and second comparators.

6. Apparatus according to claim 2 including an amplifier for each loop connected between the voltage controlled oscillator and a respective input of the combining means.

7. Apparatus according to claim 6 wherein the signal-stability means comprises means for providing an additional signal for the combining means which has the effect of so biassing the input signal that when the envelope of the unbiassed signal passes through zero the envelope of the biassed signal, as represented by the loop input signals, does not, and signal-stability comparator, signal-stability means for generating a loop output signal having a frequency or phase which is variable in response to a control signal, a signal-stability amplifier connected at the output of the signal-stability means for generating a loop output signal and a signal-stability multiplier for demodulating the amplifier output signal using a signal in phase with one of the quadrature output signals to provide one input to the signal-stability comparator, the other input to the signal-stability comparator being one of the x and y signals.

8. An apparatus according to claim 7 including means for adding a proportion of the output of one of the first and second comparators to the feedback signal applied to the other of the first and second comparators.

9. Apparatus according to claim 1, claim 2, claim 3, or claim 6, wherein the input signal has Cartesian components x and y, and, in each loop the signal-stability means and the comparators derive control signals v.sub.1 and v.sub.2 for the respective VCOs: ##EQU17## where k=the loop gain of first and second feedback loops, each of said feedback loops including a respective one of the feedback loop units, y, corresponding Cartesian component of the combined signal, and corresponding Cartesian component of the combined signal.

10. Apparatus according to claim 9 wherein signal and to generate the following signals: ##EQU18## and, multiplier means connected to receive the signals .alpha.1, .alpha.2, .alpha.3, .alpha.4, .DELTA.x and .DELTA.y and to generate the control signals v.sub.1 and v.sub.2 therefrom.

11. An apparatus according to claim 10 including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

12. Apparatus according to claim 9 wherein and input signal and the output signals of the comparators, and to derive the signals v.sub.1 and v.sub.2, and addition means and the difference means as the loop input signals.

13. An apparatus according to claim 12 including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

14. An apparatus according to claim 9 including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

15. Apparatus according to claim 1, claim 2, claim 3, or claim 6, wherein the input signal has Cartesian component signals x and y, and the comparators are connected to derive .DELTA.x and .DELTA.y where corresponding Cartesian component of the combined signal, and corresponding Cartesian component of the combined signal, and of the input signal, and the addition means and the difference means, and to derive the signals v.sub.1 and v.sub.2.

16. An apparatus according to claim 15 including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

17. Apparatus according to claim 1, claim 2, claim 3, or claim 6, wherein signal for the combining means which has the effect of so biassing the input signal that when the envelope of the unbiassed signal passes through zero the envelope of the biassed signal, as represented by the loop input signals, does not.

18. An apparatus according to claim 17 including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

19. Apparatus according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, or claim 8, including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

20. Apparatus for processing an input signal to provide a combined signal, said apparatus comprising signal and a feedback signal as inputs, having frequencies or phases which are variable in response to signals v.sub.1 and v.sub.2, combined signal, components thereof, the phase detector and a correction signal derived from the output signal of the amplitude detector to generate the signal v.sub.1, signal of the phase detector to generate the signal v.sub.2, and to reduce the dependence of the amplitude response of the apparatus on the amplitude of the input signal.

21. Apparatus according to claim 20 including thereof in providing the feedback signal by an amount equal to the difference in frequency between the outputs of the said first and second means, and the input signal.

22. Apparatus according to claim 20 or 21 wherein the first and second means are VCOs of sensitivity c and receive signals v.sub.1 and v.sub.2 according to the equations ##EQU19## where .DELTA..phi. and .DELTA.r are the phase and amplitude differences, respectively, between the input signal and the combined signal, back to the detectors.

23. An apparatus according to claim 22 including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

24. Apparatus according to claim 20 or 21 wherein the first and second means are VCOs of sensitivity c and receive signals v.sub.1 and v.sub.2 according to the equations ##EQU20## where .DELTA..phi. and .DELTA.r are the phase and amplitude differences, respectively, between the input signal and the combined signal, back to the detectors.

25. An apparatus according to claim 24 including a respective integration and addition circuit for receiving as a loop signal a respective one among the signals v.sub.1 and v.sub.2 and adding the integral of the loop signal to the loop signal.

26. A method of processing an input signal to generate a combined signal including the steps of first and second loop output signals, respectively, and ensuring that the loop output signals have a phase relation corresponding to one among a set of predetermined phase relations, of a frequency and a phase which is variable in response to a control signal, a respective one among the loop output signals, signal, another, from the combined signal, one for each loop, and component of the input signal to provide the respective control signal and continuously ensure that the combined signal is stable whatever the phase of the combined signal relative to the input signal.

27. A method of processing an input signal to provide a combined signal, comprising frequency and a phase which is variable in response to a respective one among first and second control signals, signal, correction signal derived from the output signal of a amplitude detector to generate the first control signal, to generate the second control signal, and dependence of the amplitude response of the apparatus on the amplitude of the input signal.

28. Apparatus for processing an input signal, said apparatus comprising: generating a first loop output signal, said first feedback loop unit comprising first loop input signal and generating a first control signal; and first oscillator having a frequency or phase which is variable in response to a signal v.sub.1, the signal v.sub.1 being based at least in part on the first control signal; and generating a second loop output signal, said second feedback loop unit comprising the second loop input signal and generating a second control signal; and second oscillator having a frequency or phase which is variable in response to a signal v.sub.2, the signal v.sub.2 being based at least in part on the second control signal; loop output signal, the first loop output signal being based at least in part on the first oscillator signal and the second loop output signal being based at least in part on the second oscillator signal, and outputting a combined signal; and second loop operating signals being in phase quadrature with one another and each being based at least in part on the combined signal; and the first and second loop input signals, first loop operating signal, and the second loop feedback signal is based at least in part on the second loop operating signal, and corresponding to one among a set of predetermined phase relations, and combined signal regardless of the relation between the phase of the combined signal and the phase of the input signal.

29. An apparatus for processing an input signal, said apparatus comprising: outputting a phase signal; signal and outputting an amplitude signal; frequency or phase which is variable in response to a signal v.sub.1 ; frequency or phase which is variable in response to a signal v.sub.2 ; outputting a combined signal; and outputting the feedback signal; correction signal to generate the signal v.sub.1 ; to generate the signal v.sub.2 ; and outputting the correction signal, of the apparatus on the amplitude of the input signal to be reduced.

30. A method of processing a input signal, including: output signals, respectively, from said input signal, said first and second output loop signals being substantially phase-matched with respect to each other, output signals from a voltage controlled oscillator, said voltage controlled oscillator having a frequency or phase which is variable in response to a corresponding one among first and second control signals, signal, corresponding one of the loop operating signals, the feedback loop operating signals being in phase quadrature with one another, and the input signal to provide the first control signal, regardless of the relation of the phase of the output signal to the phase of the input signal.

31. A method of processing an input signal, said method comprising: variable in response to a first control signal, variable in response to a second control signal, signal, combined signal, correction signal to generate the first control signal, said phase detector receiving the input signal and the feedback signal, to generate the second control signal, and detector receiving the input signal and the feedback signal, said correction signal causing a dependence of the amplitude response of the apparatus on the amplitude of the input signal to be reduced.