# Patent

## Title
Digital to analog converter and method thereof

## Abstract

A digital to analog converter (DAC) has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes, such that an output voltage of the DAC could be adjusted precisely based on the equivalent resistance.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of U.S. provisional application Ser. No. 61/089,610, filed Aug. 18, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.


BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention is related to a digital to analog converter and method thereof, and more particularly, to a digital to analog converter and method thereof for outputting an output voltage at a desired voltage level precisely.
2. Description of Related Art
The digital to analog converter (DAC) is widely used in current digital circuits. Most microcontrollers have a DAC to perform the digital to analog conversion operation. Please refer to FIG. 1, which is a circuit diagram of a DAC 10 according to the prior art. The DAC 10 has a negative feedback regulator 12, a ladder circuit 16, and a reference resistor RREF. The negative feedback regulator 12 has an operational amplifier 14. The operational amplifier 14 has a positive input terminal coupled to a reference voltage VREF, a negative input terminal coupled to an end of the ladder circuit 16, and an output terminal for outputting an output voltage VOUT. The ladder circuit 16 has a plurality of transistor-resistor units A0-AN, where N is a positive integer. Each of the transistor-resistor units A0-AN has a transistor and a resistor coupled to the transistor in series. For example, the transistor-resistor units A0 has a transistor M0 and a resistor R0, and the transistor M0 is coupled to the resistor R0 in series. Additionally, except the resistor R0 of the transistor-resistor unit A0, the resistance of the resistor R1-RN of each of the transistor-resistor units A1-AN is 2i times of that of the resistor R0, where i is a positive integer. For example, R1=21×R0, RN=2N×R0, etc. The gates of the transistors M0-MN are biased by control voltages that are associated with digital codes B0 to BN. For each of the control voltages, the control voltage is high while the associated digital code is “1”, and the control voltage is low while the associated digital code is “0”. For example, when the digital code B0  is “1”, the gate of the transistor M0 is biased by a high-level control voltage, such that the transistor M0 is turned on. When the digital code B0 is “0”, the gate of the transistor M0 is biased by a low-level control voltage, such that the transistor M0 is turned off. Therefore, each of the digital codes B0 to BN is used to turn on/off a corresponding one of the transistors M0-MN, and the output voltage VOUT could be determined as:




  
    
      
        
          V
          OUT
        
        =
        
          
            
              [
              
                
                  
                    
                      
                        
                          R
                          ON
                        
                        ×
                        
                          (
                          
                            
                              
                                B
                                0
                              
                              _
                            
                            +
                            
                              
                                B
                                1
                              
                              _
                            
                            +
                            ...
                            +
                            
                              
                                B
                                N
                              
                              _
                            
                          
                          )
                        
                      
                      +
                    
                  
                
                
                  
                    
                      (
                      
                        
                          
                            R
                            0
                          
                          ⁢
                          
                            B
                            0
                          
                        
                        +
                        
                          
                            R
                            1
                          
                          ⁢
                          
                            B
                            1
                          
                        
                        +
                        ...
                        +
                        
                          
                            R
                            N
                          
                          ⁢
                          
                            B
                            N
                          
                        
                      
                      )
                    
                  
                
              
              ]
            
            ×
            
              
                V
                REF
              
              
                R
                REF
              
            
          
          +
          
            V
            REF
          
        
      
    
    
      
        (
        1
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          =
          
            
              
                [
                
                  
                    
                      
                        
                          
                            R
                            ON
                          
                          ×
                          
                            (
                            
                              
                                
                                  B
                                  0
                                
                                _
                              
                              +
                              
                                
                                  B
                                  1
                                
                                _
                              
                              +
                              ...
                              +
                              
                                
                                  B
                                  N
                                
                                _
                              
                            
                            )
                          
                        
                        +
                      
                    
                  
                  
                    
                      
                        (
                        
                          
                            
                              
                                
                                  
                                    
                                      2
                                      ⁢
                                      
                                        
                                      
                                    
                                    0
                                  
                                  ⁢
                                  
                                    R
                                    0
                                  
                                  ⁢
                                  
                                    B
                                    0
                                  
                                
                                +
                              
                            
                          
                          
                            
                              
                                
                                  
                                    
                                      2
                                      ⁢
                                      
                                        
                                      
                                    
                                    1
                                  
                                  ⁢
                                  
                                    R
                                    0
                                  
                                  ⁢
                                  
                                    B
                                    1
                                  
                                
                                +
                                ...
                                +
                                
                                  
                                    2
                                    N
                                  
                                  ⁢
                                  
                                    R
                                    0
                                  
                                  ⁢
                                  
                                    B
                                    N
                                  
                                
                              
                            
                          
                        
                        )
                      
                    
                  
                
                ]
              
              ×
              
                
                  V
                  REF
                
                
                  R
                  REF
                
              
            
            +
            
              V
              REF
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




where RON represents the resistance of each turned-on transistor M0-MN, and each of B0 to BN represents an digital code that is complementary to a corresponding one of the digital codes B0 to BN. For example, B0 and B0 are complementary to each other; B1 and B1 are complementary to each other; and BN and BN are complementary to each other.

Each of combinations of the digital codes B0 to BN is used to determine a corresponding voltage level of the output voltage VOUT. In this case, it is assumed that a resistance RM is described as follows:

RM=RON×( B0+ B1+. . . + BN)  (3)

Therefore, the above equation (2) could be written as:




  
    
      
        
          V
          OUT
        
        =
        
          
            
              [
              
                
                  R
                  M
                
                +
                
                  (
                  
                    
                      
                        
                          
                            
                              
                                2
                                ⁢
                                
                                  
                                
                              
                              0
                            
                            ⁢
                            
                              R
                              0
                            
                            ⁢
                            
                              B
                              0
                            
                          
                          +
                        
                      
                    
                    
                      
                        
                          
                            
                              
                                2
                                ⁢
                                
                                  
                                
                              
                              1
                            
                            ⁢
                            
                              R
                              0
                            
                            ⁢
                            
                              B
                              1
                            
                          
                          +
                          ...
                          +
                          
                            
                              2
                              N
                            
                            ⁢
                            
                              R
                              0
                            
                            ⁢
                            
                              B
                              N
                            
                          
                        
                      
                    
                  
                  )
                
              
              ]
            
            ×
            
              
                V
                REF
              
              
                R
                REF
              
            
          
          +
          
            V
            REF
          
        
      
    
    
      
        (
        4
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          =
          
            
              
                (
                
                  
                    
                      
                        
                          
                            
                              2
                              ⁢
                              
                                
                              
                            
                            0
                          
                          ⁢
                          
                            R
                            0
                          
                          ⁢
                          
                            B
                            0
                          
                        
                        +
                      
                    
                  
                  
                    
                      
                        
                          
                            
                              2
                              ⁢
                              
                                
                              
                            
                            1
                          
                          ⁢
                          
                            R
                            0
                          
                          ⁢
                          
                            B
                            1
                          
                        
                        +
                        ...
                        +
                        
                          
                            2
                            N
                          
                          ⁢
                          
                            R
                            0
                          
                          ⁢
                          
                            B
                            N
                          
                        
                      
                    
                  
                
                )
              
              ×
              
                
                  V
                  REF
                
                
                  R
                  REF
                
              
            
            +
            
              
                (
                
                  1
                  +
                  
                    
                      R
                      M
                    
                    
                      R
                      REF
                    
                  
                
                )
              
              ⁢
              
                V
                REF
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




Generally, in order to output the output voltage VOUT at a desired level more precisely, it is desired that the value of




  (
  
    
      (
      
        1
        +
        
          
            R
            M
          
          
            R
            REF
          
        
      
      )
    
    ×
    
      V
      REF
    
  
  )




is a constant. However, according to the equation (3), the resistance RM varies with the digital codes B0 to BN, such that it is difficult to precisely output the output voltage VOUT at a desired level.

SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a digital to analog converter for outputting a desired output voltage precisely. The digital to analog converter comprises an operational amplifier and a ladder circuit. The operational amplifier has an output terminal for outputting an output voltage. The ladder circuit is coupled to the output terminal and has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units has a resistor, a first transistor coupled to the resistor in series, and a second transistor coupled to the resistor and the first transistor in parallel.
A further object of the present invention is to provide a digital to analog converting method for converting a plurality of digital codes into an output voltage. The method comprises inputting the plurality of digital codes; generating a pair of complementary control signals for each of the digital codes; applying the pairs of complementary control signals to a series of pairs of transistors to determine an equivalent resistance; and outputting the output voltage based on the equivalent resistance.
According to an exemplary embodiment of the present invention, the method further comprises providing a reference voltage and comparing the reference voltage with a terminal voltage of the series of pairs of transistors to refresh the output voltage.
According to an exemplary embodiment of the present invention, the first transistor is turned on while the second transistor is turned off, and the first transistor is turned off while the second transistor is turned on.
According to an exemplary embodiment of the present invention, a turned-on resistance of the first transistor is equal to a turned-on resistance of the second transistor.
According to an exemplary embodiment of the present invention, the operational amplifier further has a first input terminal coupled to a reference voltage and a second input terminal coupled to one end of the ladder circuit.
According to an exemplary embodiment of the present invention, the digital to analog converter further comprises a reference resistor coupled between the second input terminal and a ground terminal.
According to an exemplary embodiment of the present invention, the first transistor and the second transistor are n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs). Each of the NMOSFETs has a body and a source coupled to the body.
According to an exemplary embodiment of the present invention, the first transistor and the second transistor are p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). Each of the PMOSFETs has a body and a source coupled to the body.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, several preferred embodiments accompanied with figures are described in detail below.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a circuit diagram of a DAC according to the prior art.
FIG. 2 is a circuit diagram of a DAC according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a DAC according to another embodiment of the present invention.
FIG. 4 is a circuit diagram of a DAC according to another embodiment of the present invention.



DESCRIPTION OF EMBODIMENTS
Please refer to FIG. 2, which is a circuit diagram of a DAC 20 according to an embodiment of the present invention. The DAC 20 has the negative feedback regulator 12, the reference resistor RREF, and a ladder circuit 22. The positive input terminal of the operational amplifier 14 of the negative feedback regulator 12 is coupled to the reference voltage VREF, the negative input terminal of the operational amplifier 14 is coupled to an end Y of the ladder circuit 16, and the output terminal of the operational amplifier 14 outputs the output voltage VOUT. The reference resistor RREF is coupled between the negative input terminal of the operational amplifier 14 and a ground terminal. An end X of the ladder circuit 22 is coupled to the output terminal of the operational amplifier 14, and the other end Y of the ladder circuit 22 is coupled to the reference resistor RREF and the negative input terminal of the operational amplifier 14. A terminal voltage Vb of the ladder circuit 22 at the end Y is inputted to the negative input terminal of the operational amplifier 14, such that the operational amplifier 14 would compare the reference voltage VREF with the terminal voltage Vb to refresh the output voltage VOUT. The ladder circuit 22 has a plurality of transistor-resistor units I0-IN connected in a string, where N is a positive integer. Each of the transistor-resistor units I0-IN has a resistor, a first transistor coupled to the resistor in series, and a second transistor coupled to the resistor and the first transistor in parallel. For example, the transistor-resistor units I0 has resistor R0, a first transistor Q0 coupled to the resistor R0 in series, and a second transistor M0 coupled to the resistor R0 and the first transistor Q0 in parallel. Additionally, except the resistor R0 of the transistor-resistor unit I0, the resistance of the resistor R1-RN of each of the transistor-resistor units A1-AN is 2i times of that of the resistor R0, where i is a positive integer. For example, R1=21×R0, RN=2N×R0, etc. The gates of the first transistors Q0-QN are biased by control voltages that are associated with digital codes B0-BN, and the gates of the second transistors M0-MN are biased by control voltages that are associated with digital codes B0 to BN. Each of the digital codes B0 to BN represents a digital code that is complementary to a corresponding one of the digital codes B0 to BN. For example, B0 and B0 are complementary to each other; B1 and B1 are complementary to each other; and BN and BN are complementary to each other. For each of the control voltages, the control voltage is high while the associated digital code is “1”, and the control voltage is low while the associated digital code is “0”. For example, when the digital code B0 is “1”, the gate of the first transistor Q0 is biased by a high-level control voltage, such that the first transistor Q0 is turned on. Meanwhile, the digital code B0 is “0”, and the gate the second transistor M0 is biased by a low-level control voltage, such that the second transistor M0 is turned off. On the other hand, when the digital code B0 is “0”, the gate of the first transistor Q0 is biased by a low-level control voltage, such that the first transistor Q0 is turned off. Meanwhile, the digital code B0 is “1”, and the gate the second transistor M0 is biased by a high-level control voltage, such that the second transistor M0 is turned on. Briefly, for each of the digital codes B0-BN, a pair of complementary control signals are generated and applied to a pair of the first transistor and the second transistor of a corresponding one of the transistor-resistor units A1-AN, such that an equivalent resistance REQ of the ladder circuit 22 could be determined as:




  
    
      
        
          
            R
            EQ
          
          =
          
            [
            
              
                
                  (
                  
                    
                      R
                      0
                    
                    +
                    
                      R
                      ON
                    
                  
                  )
                
                ×
                
                  B
                  0
                
              
              +
              
                
                  (
                  
                    
                      R
                      1
                    
                    +
                    
                      R
                      ON
                    
                  
                  )
                
                ×
                
                  B
                  1
                
              
              +
              ...
              +
              
                
                  (
                  
                    
                      R
                      N
                    
                    +
                    
                      R
                      ON
                    
                  
                  )
                
                ×
                
                  B
                  N
                
              
            
            ]
          
        
      
      
        
          (
          6
          )
        
      
    
  
  +
  
    
      R
      ON
    
    ×
    
      (
      
        
          
            B
            0
          
          _
        
        +
        
          
            B
            1
          
          _
        
        +
        ...
        +
        
          
            B
            N
          
          _
        
      
      )
    
  




where RON represents the resistance of each turned-on transistor among the first transistors Q0-QN and the second transistors M0-MN. In other words, each of the first transistors Q0-QN and the second transistors M0-MN has the same turned-on resistance.

The output voltage VOUT could be determined based on the equivalent resistance REQ as follows:




  
    
      
        
          V
          OUT
        
        =
        
          
            
              R
              EQ
            
            ×
            
              
                V
                REF
              
              
                R
                REF
              
            
          
          +
          
            V
            REF
          
        
      
    
    
      
        (
        7
        )
      
    
  




Additionally, the equation (7) could be rewritten according to the equation (6), such that the output voltage VOUT could be calculated as follow:




  
    
      
        
          V
          OUT
        
        =
        
          
            
              [
              
                
                  
                    
                      
                        
                          (
                          
                            
                              R
                              0
                            
                            +
                            
                              R
                              ON
                            
                          
                          )
                        
                        ×
                        
                          B
                          0
                        
                      
                      +
                      
                        
                          (
                          
                            
                              R
                              1
                            
                            +
                            
                              R
                              ON
                            
                          
                          )
                        
                        ×
                      
                    
                  
                
                
                  
                    
                      
                        B
                        1
                      
                      +
                      ...
                      +
                      
                        
                          (
                          
                            
                              R
                              N
                            
                            +
                            
                              R
                              ON
                            
                          
                          )
                        
                        ×
                        
                          B
                          N
                        
                      
                      +
                    
                  
                
                
                  
                    
                      
                        R
                        ON
                      
                      ×
                      
                        (
                        
                          
                            
                              B
                              0
                            
                            _
                          
                          +
                          
                            
                              B
                              1
                            
                            _
                          
                          +
                          ...
                          +
                          
                            
                              B
                              N
                            
                            _
                          
                        
                        )
                      
                    
                  
                
              
              ]
            
            ×
            
              
                V
                REF
              
              
                R
                REF
              
            
          
          +
          
            V
            REF
          
        
      
    
    
      
        (
        8
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          =
          
            
              
                {
                
                  
                    R
                    ON
                  
                  ×
                  
                    
                      
                        
                          
                            [
                            
                              
                                
                                  
                                    
                                      (
                                      
                                        
                                          
                                            B
                                            0
                                          
                                          _
                                        
                                        +
                                        
                                          
                                            B
                                            1
                                          
                                          _
                                        
                                        +
                                        ...
                                        +
                                        
                                          
                                            B
                                            N
                                          
                                          _
                                        
                                      
                                      )
                                    
                                    +
                                  
                                
                              
                              
                                
                                  
                                    (
                                    
                                      
                                        B
                                        0
                                      
                                      +
                                      
                                        B
                                        1
                                      
                                      +
                                      ...
                                      +
                                      
                                        B
                                        N
                                      
                                    
                                    )
                                  
                                
                              
                            
                            ]
                          
                          +
                        
                      
                    
                    
                      
                        
                          (
                          
                            
                              
                                R
                                0
                              
                              ⁢
                              
                                B
                                0
                              
                            
                            +
                            
                              
                                R
                                1
                              
                              ⁢
                              
                                B
                                1
                              
                            
                            +
                            ...
                            +
                            
                              
                                R
                                N
                              
                              ⁢
                              
                                B
                                N
                              
                            
                          
                          )
                        
                      
                    
                  
                
                }
              
              ×
              
                
                  V
                  REF
                
                
                  R
                  REF
                
              
            
            +
            
              V
              REF
            
          
        
        ⁢
        
          
        
      
    
    
      
        (
        9
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          =
          
            
              
                {
                
                  
                    
                      
                        
                          
                            R
                            ON
                          
                          ×
                          N
                        
                        +
                      
                    
                  
                  
                    
                      
                        (
                        
                          
                            
                              
                                
                                  
                                    2
                                    0
                                  
                                  ⁢
                                  
                                    R
                                    0
                                  
                                  ⁢
                                  
                                    B
                                    0
                                  
                                
                                +
                              
                            
                          
                          
                            
                              
                                
                                  
                                    2
                                    1
                                  
                                  ⁢
                                  
                                    R
                                    0
                                  
                                  ⁢
                                  
                                    B
                                    1
                                  
                                
                                +
                                ...
                                +
                                
                                  
                                    2
                                    N
                                  
                                  ⁢
                                  
                                    R
                                    0
                                  
                                  ⁢
                                  
                                    B
                                    N
                                  
                                
                              
                            
                          
                        
                        )
                      
                    
                  
                
                }
              
              ×
              
                
                  V
                  REF
                
                
                  R
                  REF
                
              
            
            +
            
              V
              REF
            
          
        
      
    
    
      
        (
        10
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          =
          
            
              
                (
                
                  
                    
                      
                        
                          
                            2
                            0
                          
                          ⁢
                          
                            R
                            0
                          
                          ⁢
                          
                            B
                            0
                          
                        
                        +
                      
                    
                  
                  
                    
                      
                        
                          
                            2
                            1
                          
                          ⁢
                          
                            R
                            0
                          
                          ⁢
                          
                            B
                            1
                          
                        
                        +
                        ...
                        +
                        
                          
                            2
                            N
                          
                          ⁢
                          
                            R
                            0
                          
                          ⁢
                          
                            B
                            N
                          
                        
                      
                    
                  
                
                )
              
              ×
              
                
                  V
                  REF
                
                
                  R
                  REF
                
              
            
            +
            
              
                (
                
                  1
                  +
                  
                    
                      
                        R
                        ON
                      
                      ×
                      N
                    
                    
                      R
                      REF
                    
                  
                
                )
              
              ×
              
                V
                REF
              
            
          
        
      
    
    
      
        (
        11
        )
      
    
  




In the equation (11), the term




  (
  
    
      (
      
        1
        +
        
          
            
              R
              ON
            
            ×
            N
          
          
            R
            REF
          
        
      
      )
    
    ×
    
      V
      REF
    
  
  )




is a constant. Therefore, the voltage level of the output voltage VOUT could be precisely adjusted according to the digital codes B0-BN.

Please refer to FIG. 3, which is a circuit diagram of a DAC 30 according to another embodiment of the present invention. The DAC 30 is similar to the DAC 20 shown in FIG. 2. The major difference between the DAC 30 and the DAC 20 is that the first transistors Q0-QN and the second transistors M0-MN of the DAC 20 are replaced with the n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) N0-NN and NM0-NMN. Each of the NMOSFETs N0-NN and NM0-NMN has a body and a source coupled to the body. The DAC 30 also has the negative feedback regulator 12, the reference resistor RREF, and a ladder circuit 32. The ladder circuit 32 has a plurality of transistor-resistor units G0-GN connected in a string. In the embodiment, the resistance of each turned-on transistor RON could be calculated as follows:




  
    
      
        
          R
          ON
        
        =
        
          μ
          ×
          
            C
            OX
          
          ×
          
            W
            L
          
          ⁢
          
            (
            
              
                V
                GS
              
              -
              
                V
                T
              
            
            )
          
        
      
    
    
      
        (
        12
        )
      
    
  




where μ represents the mobility of the turned-on transistor;

COX represents the gate oxide capacitance per unit area;
W represents the gate width of the turned-on transistor;
L represents the gate length of the turned-on transistor;
VGS represents the gate-source voltage of the turned-on transistor; and
VT represents the threshold voltage of the turned-on transistor.
The threshold voltage VT could be determined as follows:

VT=VTO+γ(√{square root over (VSB+2φ)}−√{square root over (2φ)})  (13)

where VSB represents the source-body voltage of the turned-on transistor;

VTO represents the zero-VSB value of threshold voltage;
γ represents a body-effect parameter; and
2φ represents the surface potential parameter.
In the embodiment, because the source and the body of the turned-on transistor are coupled together, the source-body voltage VSB is 0 volt. Moreover, since the zero-VSB value VTO, the body-effect parameter γ, and the surface potential parameter 2φ are constants, the transistors N0-NN and NM0-NMN have the same threshold voltage VT. Therefore, if the transistors N0-NN and NM0-NMN have an identical ratio W/L, the transistors N0-NN and NM0-NMN would have an identical turned-on transistor RON. Generally, the output voltage VOUT of the DAC 30 could be calculated according the equations (8)-(11).
Please refer to FIG. 4, which is a circuit diagram of a DAC 40 according to another embodiment of the present invention. The DAC 40 is similar to the DAC 30 shown in FIG. 3. The major difference between the DAC 40 and the DAC 30 is that the NMOSFETs N0-NN and NM0-NMN are replaced with the p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) P0-PN and PM0-PMN. Each of the PMOSFETs P0-PN and PM0-PMN has a body and a source coupled to the body. The DAC 40 also has the negative feedback regulator 12, the reference resistor RREF, and a ladder circuit 42. The ladder circuit 42 has a plurality of transistor-resistor units U0-UN connected in a string. In the embodiment, the resistance of each turned-on transistor RON could be calculated as follows:




  
    
      
        
          R
          ON
        
        =
        
          μ
          ×
          
            C
            OX
          
          ×
          
            W
            L
          
          ⁢
          
            (
            
              
                V
                SG
              
              -
              
                V
                T
              
            
            )
          
        
      
    
    
      
        (
        14
        )
      
    
  




where VSG represents the source-gate voltage of the turned-on transistor.

The threshold voltage VT could be determined as follows:

VT=VTO+γ(√{square root over (VBS+2φ)}−√{square root over (2φ)})  (15)

where VBS represents the body-source voltage of the turned-on transistor;

VTO represents the zero-VBS value of threshold voltage.
In the embodiment, because the source and the body of the turned-on transistor are coupled together, the body-source voltage VBS is 0 volt. Moreover, since the zero-VBS value VTO, the body-effect parameter γ, and the surface potential parameter 2φ are constants, the transistors P0-PN and PM0-PMN have the same threshold voltage VT. Therefore, if the transistors P0-PN and PM0-PMN have an identical ratio W/L, the transistors P0-PN and PM0-PMN would have an identical turned-on transistor RON. Generally, the output voltage VOUT of the DAC 40 could be calculated according the equations (8)-(11).
In view of the above, according to the present invention, each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes. Therefore, an output voltage of the DAC could be adjusted precisely based on the equivalent resistance.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

## Claims

1. A digital to analog converter, comprising:
an operational amplifier having an output terminal for outputting an output voltage; and
a ladder circuit coupled to the output terminal, the ladder circuit having a plurality of transistor-resistor units connected in a string, each of the transistor-resistor units having a resistor, a first transistor coupled to the resistor in series, and a second transistor coupled to the resistor and the first transistor in parallel;
wherein the first transistor is turned on while the second transistor is turned off, and the first transistor is turned off while the second transistor is turned on.

2. The digital to analog converter as claimed in claim 1, wherein a pair of complementary control signals is applied to the first transistor and the second transistor to turn on/off the first transistor and the second transistor.

3. The digital to analog converter as claimed in claim 1, wherein a turned-on resistance of the first transistor is equal to a turned-on resistance of the second transistor.

4. The digital to analog converter as claimed in claim 1, wherein the operational amplifier further has a first input terminal coupled to a reference voltage and a second input terminal coupled to one end of the ladder circuit.

5. The digital to analog converter as claimed in claim 4 further comprising a reference resistor coupled between the second input terminal and a ground terminal.

6. The digital to analog converter as claimed in claim 1, wherein the first transistor and the second transistor are n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs), each of the NMOSFETs has a body and a source coupled to the body.

7. The digital to analog converter as claimed in claim 1, wherein the first transistor and the second transistor are p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs), each of the PMOSFETs has a body and a source coupled to the body.

8. A digital to analog converting method for converting a plurality of digital codes into an output voltage, the method comprising:
inputting the plurality of digital codes;
generating a pair of complementary control signals for each of the digital codes;
applying the pairs of complementary control signals to a series of pairs of transistors to determine an equivalent resistance; and
outputting the output voltage based on the equivalent resistance;
wherein each of the pairs of transistors has a first transistor and a second transistor, the first transistor and the second transistor are connected in parallel, the first transistor is turned on while the second transistor is turned off, and the first transistor is turned off while the second transistor is turned on.

9. The method as claimed in claim 8 further comprising:
providing a reference voltage; and
comparing the reference voltage with a terminal voltage of the series of pairs of transistors to refresh the output voltage.

10. The method as claimed in claim 8, wherein each of the pairs of transistors further has a resistor, the resistor and the first transistor are connected in series.

11. The method as claimed in claim 8, wherein a turned-on resistance of the first transistor is equal to a turned-on resistance of the second transistor.

12. The method as claimed in claim 8, wherein the first transistor and the second transistor are n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs), each of the NMOSFETs has a body and a source coupled to the body.

13. The method as claimed in claim 8, wherein the first transistor and the second transistor are p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs), each of the PMOSFETs has a body and a source coupled to the body.

14. A digital to analog converter, comprising:
an operational amplifier having an output terminal for outputting an output voltage and a negative input terminal; and
a ladder circuit coupled between the negative input terminal and the output terminal, the ladder circuit having a plurality of transistor-resistor units connected in a string, each of the transistor-resistor units having a resistor, a first transistor coupled to the resistor in series, and a second transistor coupled to the resistor and the first transistor in parallel.