# Patent

## Title
Monolithically integrated multiplexer-translator-demultiplexer circuit and method

## Abstract

A monolithically integrated multiplexer-translator-demultiplexer and a method for multiplexing and translating an electrical signal or demultiplexing and translating an electrical signal. A multiplexer and a demultiplexer are monolithically integrated with a translator. Circuits that operate at different voltage supply levels from each other may be coupled to the multiplexer and a circuit that operates at a different voltage supply level from the circuits coupled to the multiplexer or that operates at the same voltage supply level as at least one of the circuits coupled to the multiplexer is coupled to the demultiplexer. The monolithically integrated multiplexer-translator-demultiplexer selects a signal from one of the circuits coupled to the multiplexer, translates its voltage level and provides the translated signal level as an output signal. Alternatively, the monolithically integrated multiplexer-translator-demultiplexer creates demultiplexed signals from an electrical signal and translates the voltage levels of the demultiplexed signals.

## Background
TECHNICAL FIELD
The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductor devices and structure.
BACKGROUND
Many electronic systems are implemented using integrated circuits of different logic families. For example, computer systems often use complementary metal-oxide-semiconductor (“CMOS”) circuits to perform computational functions, low voltage differential signaling (“LVDS”) circuits for disk drive data signals, and positive emitter-coupled logic (“PECL”) circuits for clock drivers. These logic circuits are typically incompatible with each other in the sense that voltage levels specified for circuits of one logic family do not fall within the voltage range specified for circuits of a different logic family. Hence, data is lost or noise immunity is substantially impaired. For this reason, a receiver-translator circuit often is used to translate between signals of different logic families.
In addition to interfacing different logic families with each other, it may be desirable to interface different systems with each other. For example, many applications it is desirable to have a microprocessor capable of transmitting data to and receiving data from a multimedia card (MMC), or to have a microprocessor capable of transmitting data to and receiving data from a secure digital input/output (SDIO) system, or to have a microprocessor capable of transmitting data to and receiving data from a plurality of systems such as an MMC and an SDIO system. The microprocessor is also referred to as a central processing unit. Thus, the microprocessor should be capable of operating with one or more systems having different voltage parameters than the microprocessor and with each other. Interfacing different logic circuits, different transceivers, and different systems requires the use of different discrete translators to allow communications between the different circuit components. For example, a system may include a multiplicity of discrete circuit components coupled to an input of a translator and a discrete circuit component coupled to the output of the translator where the discrete circuit component coupled to the output of the translator has a different operating voltage than one or more of the circuit components connected to the input of the translator. This results in a higher system cost because of the need to inventory multiple translators and, since fewer translators of each type are used, the lack of economies of scale.
In addition to a higher cost, systems that include components that operate at different voltages may require additional circuitry to overcome incompatible supply voltage levels or may be limited in the acceptable supply voltages. For example, FIG. 1 illustrates a prior art logic voltage translator 10 used in a multiplexing application in which a plurality of circuits coupled to the inputs of the translator are limited to having the same voltage supply levels. What is shown in FIG. 1 is an n-channel pass transistor 12 coupled to p-channel edge-adjusting transistors 14 and 20 through corresponding one-shots 16 and 22, respectively. Pull-up resistors 18 and 24 are connected to p-channel edge-adjusting transistors 14 and 20, respectively. More particularly, n-channel pass transistor 12 has a source connected to an input/output node 26, a drain connected to an input/output node 28 and a gate coupled for receiving a source of operating potential VCC1. The drain of pass transistor 12 is coupled to the gate of edge-adjusting transistor 14 through one-shot 16 and the source of pass transistor 12 is coupled to the gate of edge-adjusting transistor 20 through one-shot 22. The source of pass transistor 12 is connected to a drain of edge-adjusting transistor 14 and to a terminal 19 of pull-up resistor 18 and the drain of pass transistor 12 is connected to a drain of edge-adjusting transistor 20 and to a terminal 25 of pull-up resistor 24. The gate of pass transistor 12 is connected to the source of edge-adjusting transistor 14 and to a terminal 21 of pull-up resistor 18. The source of edge-adjusting transistor 20 is connected to a terminal 27 of pull-up resistor 24 and, along with terminal 27, it is coupled for receiving a source of operating potential VCC2. A source-to-body diode 13 is formed between the source and drain of pass transistor 12.
The source of pass transistor 12, the drain of edge-adjusting transistor 14, and terminal 19 of pull-up resistor 18 are commonly connected together and to input/output node 26 and the drain of edge-adjusting transistor 20 and terminal 25 of pull-up resistor 24 are commonly connected together and to input/output node 28.
Transceivers 301, 302, . . . , 30n are connected to logic translator 10. Each transceiver 301, 302, . . . , 30n includes input/output transistors 321, 322, . . . , 32n and input/output buffers 341, 342, . . . , 34n, wherein the drains of input/output transistors 321, 322, . . . , 32n and the input terminals of input/output buffers 341, 342, . . . , 34n are connected to input/output nodes 311, 312, . . . , 31n, respectively. Each transceiver 301, 302, . . . , 30n is coupled for receiving source of operating potential VCC1. The gates of input/output transistors 321, 322, . . . , 32n are connected to control circuits 361, 362, . . . , 36n, the sources of input/output transistors 321, 322, . . . , 32n are coupled for receiving a source of operating potential VSS1, and the output terminals of input/output buffers 341, 342, . . . , 34n are connected to logic circuits 381, 382, . . . , 38n, respectively. By way of example, source of operating potential VSS1 is ground. It should be noted that for purposes of clarity, control circuits 361, 362, . . . , 36n and logic circuits 381, 382, . . . , 38n are shown in block form and that the types of control and logic circuits are known to those skilled in the art. Input/output nodes 311, 312, . . . , 31n of transceivers 301, 302, . . . , 30n are connected to input/output node 26 of logic voltage translator 10.
A transceiver 40 is connected to input/output node 28 of logic voltage translator 10. Transceiver 40 includes an input/output transistor 42 and an input/output buffer 44 wherein a drain of input/output transistor 42 and an input terminal of input/output buffer 44 are connected to input/output node 56 which in turn is connected to input/output node 28. Transceiver 40 is coupled for receiving source of operating potential VCC2. The gate of input/output transistor 42 is connected to a control circuit 46, the source of input/output transistor 42 is coupled for receiving a source of operating potential VSS2, and the output terminal of input/output buffer 44 is connected to a logic circuit 48. By way of example, source of operating potential VSS2 is ground. For purposes of clarity, control circuit 46 and logic circuit 48 are shown in block form. The types of control and logic circuits are known to those skilled in the art.
Before describing the operation of logic voltage translator 10, it should be noted that for the sake of explaining its operation, supply voltage VCC2 is assumed to be greater than supply voltage VCC1 which is assumed to be greater than the threshold voltage of pass transistor 12. However, supply voltage VCC1 may be greater than, less than, or equal to supply voltage VCC2. Furthermore, the supply voltages VCC1 for each transceiver 301, 302, . . . , 30n are the same. A logic low or logic zero voltage is transmitted to transceiver 40 by turning on one of input/output transistors 321, 322, . . . , 32n of a selected transceiver 301, 302, . . . , 30n. Techniques for selecting a transceiver from a plurality of transceivers are known to those skilled in the art. Turning on one of input/output transistors 321, 322, . . . , 32n sets the voltage at the corresponding input/output node 311, 312, . . . , 31n to a logic low or a logic zero voltage level, which is transmitted to input/output node 26. The logic low voltage appearing at input/output node 26 sets the gate-to-source voltage of pass transistor 12 to be approximately equal to supply voltage VCC1. Thus, pass transistor 12 turns on, setting the voltage at input/output node 28 equal to a logic zero voltage, e.g., equal to approximately zero volts.
Transceiver 40 transmits a logic zero voltage to the selected transceiver 301, 302, . . . , 30n by turning on input/output transistor 42, which sets the voltage at input/output node 56 to a logic low or logic zero voltage. The logic zero voltage on input/output node 56 is transmitted to input/output node 28 causing body diode 13 to become forward biased, turning on pass transistor 12 and producing a logic zero voltage at input/output node 26.
A logic high or logic one voltage is transmitted from input/output node 26 to input/output node 28 or from input/output node 28 to input/output node 26 by turning off input/output transistors 321, 322, . . . , 32n and input/output transistor 42. Turning off input/output transistors 321, 322, . . . , 32n and input/output transistor 42 sets the gate-to-source voltage of pass transistor 12 to approximately zero volts, thereby turning off pass transistor 12. Because pass transistor 12 is off, the voltages appearing at input/output nodes 26 and 28 are equal to supply voltages VCC1 and VCC2, respectively. A disadvantage with logic translator 10 is that a voltage VCC1 appearing at input/output node 26 may exceed the maximum operating voltage of transceiver modules 301, 302, . . . , 30n causing an increased power consumption and eventually damaging one or more of them. Another disadvantage with logic translator 10 is that supply voltages VCC1 for each transceiver 301, 302, . . . , 30n are the same.
Accordingly, it would be advantageous to have a structure and method for multiplexing and translating at least one of a plurality of electrical signals or demultiplexing at least one of the plurality of electrical signals. It would be of further advantage for the structure and method to be cost efficient.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:
FIG. 1 is a circuit schematic of a prior art logic translator;
FIGS. 2A and 2B collectively are a circuit schematic of a monolithically integrated multiplexer-translator-demultiplexer in accordance with an embodiment of the present invention;
FIGS. 3A, 3B, 3C, and 3D collectively are a block diagram of a monolithically integrated multiplexer-translator-demultiplexer in accordance with another embodiment of the present invention;
FIG. 4 is another block diagram of the monolithically integrated multiplexer-translator-demultiplexer of FIG. 3;
FIG. 5 is a circuit schematic of a portion of an input/output stage of the monolithically integrated multiplexer-translator-demultiplexer of FIG. 4;
FIG. 6 is a circuit schematic of a portion of another input/output stage of the monolithically integrated multiplexer-translator-demultiplexer of FIG. 4; and
FIG. 7 is a block diagram of a monolithically integrated multiplexer-translator-demultiplexer in accordance with another embodiment of the present invention.



DETAILED DESCRIPTION
Generally the present invention provides a monolithically integrated bi-directional, open-drain auto sense, multiplexer-translator-demultiplexer and a method for multiplexing, translating, and demultiplexing electrical signals. In accordance with one embodiment of the present invention, the monolithically integrated multiplexer-translator-demultiplexer provides voltage level shifting that enables data transfer to systems operating at different supply voltages. More particularly, logic signals that are referenced to input voltage supplies are translated to logic signals with logic levels matched to an output voltage supply. In a similar manner, the circuit performs output to input translation by shifting input signals with logic levels referenced to the output supply voltage to a logic signal with logic levels matched to the input supply voltages. This allows voltage logic signals on an input side of a translator to be translated into voltage signals on the output side, and vice-versa. The multiplexer feature of the circuit selects one data source from a plurality of digital data input sources and provides a single channel of output signals. This allows data to be transmitted from either one of the multiple input ports to the output port or from the output port to one of the multiple input ports. In addition, the auto sense circuit enables the data channels to independently determine the direction of data flow without including a directional pin. Each data line can be configured as a uni-directional input or output data port or as a bi-directional input or output data port.
In accordance with another embodiment, a method for multiplexing and level shifting electrical signals is provided. A plurality of electrical signals is provided to a monolithically integrated circuit, which selects an electrical signal from the plurality of electrical signals. The signal level of the selected electrical signal is adjusted to form a level shifted selected electrical signal.
In accordance with another embodiment, a method for one of multiplexing and leveling shifting a first electrical signal or level shifting and demultiplexing a second electrical signal is provided. The electrical signal is multiplexed and level shifted by providing a plurality of electrical signals to a monolithically integrated circuit, using the monolithically integrated circuit to select the first electrical signal of the plurality of electrical signals; and adjusting a signal level of the selected first electrical signal to form a level shifted first electrical signal. The second electrical signal is demultiplexed by
providing a second electrical signal to the monolithically integrated circuit, using the monolithically integrated circuit to adjust the signal level of the second electrical signal to form a level shifted second electrical signal, and transmitting the level shifted second electrical signal to a plurality of input/output nodes.
It should be noted that a logic zero voltage level (VOL) is also referred to as a logic low voltage and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic zero voltage may be thirty percent of the power supply voltage level. In a five volt Translator-Translator Logic (TTL) system a logic low voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (VOH) is also referred to as a logic high voltage level and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.
In addition, the sources and drains of a transistor are referred to as current carrying electrodes, current conducting electrodes, or current carrying terminals and the gate is referred to as a control electrode or a control terminal. A transceiver is also referred to as a transceiver circuit.
FIGS. 2A and 2B are a circuit schematic of monolithically integrated multiplexer-translator-demultiplexer 100 in accordance with an embodiment of the present invention. It should be noted that FIGS. 2A and 2B together form a circuit schematic for monolithically integrated multiplexer-translator-demultiplexer 100 and are therefore collectively referred to as FIG. 2. However, for the sake of clarity circuit schematic 100 has been shown in two figures, i.e., FIG. 2A and FIG. 2B. What is shown in FIG. 2 is an n-channel pass transistor 1021 coupled to p-channel edge-adjusting transistors 1041 and 1101 through corresponding one-shots 1061 and 1121, respectively. Pull-up resistors 1081 and 1141 are connected from the sources to the drains of p-channel edge-adjusting transistors 1041 and 1101, respectively. More particularly, n-channel pass transistor 1021 has a source connected to an input/output node 1201, a drain connected to input/output node 128, and a gate coupled for receiving a source of operating potential VA1. The drain of pass transistor 1021 is coupled to the gate of edge-adjusting transistor 1041 through one-shot (“OS”) 1061 and the source of pass transistor 1021 is connected to the gate of edge-adjusting transistor 1101 through one-shot (“OS”) 1121. The source of pass transistor 1021 is also connected to a drain of edge-adjusting transistor 1041 and to a terminal 1091 of pull-up resistor 1081 and the drain of pass transistor 1021 is also connected to a drain of edge-adjusting transistor 1101 and to a terminal 1151 of pull-up resistor 1141. The gate of pass transistor 1021 is connected to the source of p-channel edge-adjusting transistor 1041 and to a terminal 1111 of pull-up resistor 1081. In addition, the gate of pass transistor 1021 is coupled for receiving source of potential VA1. The source of edge-adjusting transistor 1101 is connected to a terminal 1171 of pull-up resistor 1141. Terminal 1171 and the source of edge-adjusting transistor 1101 are coupled for receiving a source of operating potential VC. A source-to-body diode 1051 is formed from the source to the drain of pass transistor 1021.
The source of pass transistor 1021, the drain of edge-adjusting transistor 1041, and terminal 1091 of pull-up resistor 1081 that are commonly connected, i.e., connected together, also are connected to input/output node 1201 and the drain of edge-adjusting transistor 1101 and terminal 1151 of pull-up resistor 1141 that are commonly connected, i.e., connected together, also are connected to input/output node 128.
Transistors 1021 and 1041, body diode 1051, one-shot 1061, and pull-up resistor 1081 form an input stage 1031 of a channel 1191 of monolithically integrated multiplexer-translator-demultiplexer 100. Transistor 1101, resistor 1141, and one-shot 1121 form an output stage 1071 of channel 1191 of monolithically integrated multiplexer-translator-demultiplexer 100.
An n-channel pass transistor 1022 is coupled to p-channel edge-adjusting transistors 1042 and 1102 through corresponding one-shots 1062 and 1122, respectively. Pull-up resistors 1082 and 1142 are connected from the drains to the sources of p-channel edge-adjusting transistors 1042 and 1102 respectively. More particularly, n-channel pass transistor 1022 has a source connected to an input/output node 1202, a drain connected to input/output node 128, and a gate coupled for receiving a source of operating potential VA2. The drain of pass transistor 1022 is coupled to the gate of edge-adjusting transistor 1042 through a one-shot 1062 and the source of pass transistor 1022 is connected to the gate of edge-adjusting transistor 1102 through a one-shot 1122. The source of pass transistor 1022 is also connected to a drain of edge-adjusting transistor 1042 and to a terminal 1092 of pull-up resistor 1082 and the drain of pass transistor 1022 is also connected to a drain of edge-adjusting transistor 1102 and to a terminal 1152 of pull-up resistor 1142. The gate of pass transistor 1022 is connected to the source of p-channel edge-adjusting transistor 1042 and to a terminal 1112 of pull-up resistor 1082. The source of edge-adjusting transistor 1102 is connected to a terminal 1172 of pull-up resistor 1142. Terminal 1172 and the source of edge-adjusting transistor 1042 are coupled for receiving source of operating potential VC. A source-to-body diode 1052 is formed between the source and drain of pass transistor 1022.
The source of pass transistor 1022, the drain of edge-adjusting transistor 1042, and terminal 1092 of pull-up resistor 1082 that are commonly connected also are connected to an input/output node 1202 and the drain of edge-adjusting transistor 1102 and terminal 1152 of pull-up resistor 1142 that are commonly connected also are connected to an input/output node 128.
Transistors 1022 and 1042, body diode 1052, one-shot 1062, and pull-up resistor 1082 form an input stage 1032 of a channel 1192 of monolithic translator-multiplexer 100. Transistor 1102, pull-up resistor 1142, and one-shot 1122 form an output stage 1072 of channel 1192 of monolithic translator-multiplexer 100.
An n-channel pass transistor 102n is coupled to p-channel edge-adjusting transistors 104n and 110n through corresponding one-shots 106n and 112n, respectively, where n is an integer. Pull-up resistors 108n and 114n are connected from the sources to the drains of p-channel edge-adjusting transistors 104n and 110n, respectively. More particularly, n-channel pass transistor 102n has a source connected to an input/output node 120n, a drain connected to input/output node 128 and a gate coupled for receiving a source of operating potential VAn. The drain of pass transistor 102n is coupled to the gate of edge-adjusting transistor 104n through a one-shot 106n and the source of pass transistor 102n is connected to the gate of edge-adjusting transistor 110n through a one-shot 112n. The source of pass transistor 102n is connected to a drain of edge-adjusting transistor 104n and to a terminal 109n of pull-up resistor 108n and the drain of pass transistor 102n is connected to a drain of edge-adjusting transistor 110n and to a terminal 115n of pull-up resistor 114n. The gate of pass transistor 102n is connected to the source of p-channel edge-adjusting transistor 104n and to a terminal 111n of pull-up resistor 108n. The source of edge-adjusting transistor 110n is connected to a terminal 117n of pull-up resistor 114n, and the source of edge-adjusting transistor 110n and terminal 117n are coupled for receiving source of operating potential VC. A source-to-body diode 105n is formed between the source and drain of pass transistor 102n.
The source of pass transistor 102n, the drain of edge-adjusting transistor 104n, and terminal 109n of pull-up resistor 108n that are commonly connected together also are connected to an input/output node 120n and the drain of edge-adjusting transistor 110n and terminal 115n of pull-up resistor 114n that are commonly connected together also are connected to input/output node 128. The sources of edge-adjusting transistors 1021, 1102, . . . , 110n and terminals 1171, 1172, . . . , 117n of pull-up resistors 1141, 1142, . . . , 114n are commonly connected together.
Transistors 102n and 104n, body diode 105n, one-shot 106n, and pull-up resistor 108n form an input stage 103n of a channel 119n of monolithically integrated multiplexer-translator-demultiplexer 100 and transistor 110n, pull-up resistor 114n, and one-shot 112n form an output stage 107n of channel 119n of monolithically integrated multiplexer-translator-demultiplexer 100.
Transceivers 1301, 1302, . . . , 130n are connected to input/output nodes 1201, 1202, . . . , 120n, of channels 1191, 1192, . . . , 119n, respectively. Each transceiver 1301, 1302, . . . , 130n includes input/output transistors 1321, 1322, . . . , 132n and input/output buffers 1341, 1342, . . . , 134n, wherein the drains of input/output transistors 1321, 1322, . . . , 132n and the input terminals of buffers 1341, 1342, . . . , 134n are connected to input/output nodes 1311, 1312, . . . , 131n, respectively. Each transceiver 1301, 1302, . . . , 130n is coupled for receiving sources of operating potential or supply voltages VCC1, VCC2, . . . , VCCn, respectively. It should be noted that the voltages of supply voltages VCC1, VCC2, . . . , VCCn may be the same or different. The gates of input/output transistors 1321, 1322, . . . , 132n are connected to control circuits 1361, 1362, . . . , 136n, the sources of input/output transistors 1321, 1322, . . . , 132n are coupled for receiving sources of operating potential or supply voltages VSS1, VSS2, . . . , VSSn, and the output terminals of input/output buffers 1341, 1342, . . . , 134n are connected to logic circuits 1381, 1382, . . . , 138n, respectively. It should be noted that for the purposes of clarity, control circuits 1341, 1342, . . . , 134n and logic circuits 1381, 1382, . . . , 138n are shown in block form and that the types of control and logic circuits are known to those skilled in the art. Input/output nodes 1311, 1312, . . . , 131n of transceivers 1301, 1302, . . . , 130n are connected to input/output nodes 1201, 1202, . . . , 120n, respectively.
A transceiver 140 is connected to input/output node 128. Transceiver 140 includes an input/output transistor 142 and an input/output buffer 144 wherein a drain of input/output transistor 142 and an input terminal of input/output buffer 144 are connected to input/output node 156 which is connected to input/output node 128. Transceiver 140 is coupled for receiving source of operating potential VCCA. The gate of input/output transistor 142 is connected to a control circuit 146, the source of input/output transistor 142 is coupled for receiving a source of operating potential VSS, and the output terminal of input/output buffer 144 is connected to a logic circuit 148. It should be noted that for the purposes of clarity, control circuit 146 and logic circuit 148 are shown in block form and that the types of control and logic circuits are known to those skilled in the art.
In operation, an address is placed on an address node by selector circuit 126 to activate the desired transceiver and deactivate the other transceivers of the plurality of transceivers 1301, 1302, . . . , 130n. For example, it may be desirable to transmit a logic zero voltage from transceiver 1301 to transceiver 140. Thus, the address for transceiver 1301 is placed on address node 126 to activate it and deactivate transceivers 1302-130n. Control circuit 1341 turns on input/output transistor 1321 causing the voltage at input/output node 1311 to be equal to a logic zero voltage level, which is transmitted to input/output node 1201, thereby setting the voltage at the source of pass transistor 1021 at a logic zero level. The gate-to-source voltage of pass transistor 1021 is approximately equal to supply voltage VA1, which turns on pass transistor 1021 and sets the voltage at input/output node 128 equal to approximately zero volts. It should be noted that pass transistor 1021 turns on as long as voltage VA1 is greater than the threshold voltage of transistor 1021.
Transceiver 140 transmits a logic zero voltage to selected transceiver 1301 by turning on input/output transistor 142, which sets the voltage at input/output node 146 to a logic low or logic zero voltage. The logic zero voltage on input/output node 146 is transmitted to input/output node 128 causing source-to-drain body diode 1051 to become forward biased and the gate-to-source voltage of pass transistor 1021 to be equal to voltage VA1 minus the voltage drop of body diode 1051. If the gate-to-source voltage of pass transistor 1021 is greater than the threshold voltage of pass transistor 1021, pass transistor 1021 turns on and pulls down the voltage at input/output node 1201 to a logic zero voltage level. The logic zero voltage is transmitted to transceiver 1301 through input/output node 1311.
For selected transceiver 1301, a logic high or logic one voltage is transmitted from transceiver 1301 to transceiver 140 or from transceiver 140 to transceiver 1301 by turning off input/output transistors 1321 and 142. More particularly, the logic high voltage is transmitted from input/output node 1201 to input/output node 128 or from input/output node 128 to input/output node 1201 by turning off input/output transistors 1321 and 142. Turning off input/output transistors 1321 and 142 sets the gate-to-source voltage of pass transistor 1021 to approximately zero volts, thereby turning off pass transistor 1021. Because pass transistor 1021 is off, the voltages appearing at input/output nodes 1201 and 128 are equal to supply voltages VA1 and VC, respectively.
Alternatively, it may be desirable to transmit a logic low or logic zero voltage from transceiver 130n to transceiver 140. Thus, the address for transceiver 130n is placed on the address node by selector circuit 126 to activate it and deactivate transceivers 1301-130n-1. Control circuit 134n turns on input/output transistor 132n causing the voltage at input/output node 131n to be equal to a logic zero voltage, e.g., approximately zero volts. The logic zero voltage is transmitted to input/output node 120n, thereby setting the voltage at the source of pass transistor 102n to be approximately zero volts. Thus, the gate-to-source voltage of pass transistor 102n is approximately equal to supply voltage VAn, which turns on pass transistor 102n and sets the voltage at input/output node 128 equal to approximately zero volts. It should be noted that pass transistor 102n turns on as long as voltage VAn is greater than the threshold voltage of transistor 102n.
Transceiver 140 transmits a logic zero voltage to selected transceiver 130n by turning on input/output transistor 142, which sets the voltage at input/output node 156 to a logic low or logic zero voltage. The logic zero voltage on input/output node 156 is transmitted to input/output node 128 causing source-to-drain body diode 105n to become forward biased and the gate-to-source voltage of pass transistor 102n to be equal to voltage VAn minus the voltage drop of body diode 105n. If the gate-to-source voltage of pass transistor 102n is greater than the threshold voltage of pass transistor 102n, pass transistor 102n turns on and pulls down the voltage at input/output node 120n to a logic zero voltage level. The logic zero voltage is transmitted to transceiver 130n through input/output node 131n.
For selected transceiver 130n, a logic high or logic one voltage is transmitted from input/output node 120n to input/output node 128 or from input/output node 128 to input/output node 120n by turning off input/output transistors 132n and 142. Turning off input/output transistors 132n and 142 sets the gate-to-source voltage of pass transistor 102n to approximately zero volts, thereby turning off pass transistor 102n. Because pass transistor 102n is off, the voltages appearing at input/output nodes 120n and 128 are equal to supply voltages VAn and VC, respectively.
FIGS. 3A, 3B, 3C, 3D and 4 are block diagrams of a monolithically integrated multiplexer-translator-demultiplexer 200 in accordance with another embodiment of the present invention. It should be noted that FIGS. 3A, 3B, 3C, and 3D together form a circuit schematic for monolithically integrated multiplexer-translator-demultiplexer 200 and are therefore collectively referred to as FIG. 3. However, for the sake of clarity circuit schematic 200 has been shown in four figures, i.e., FIG. 3A, 3B, 3C, and FIG. 3D. It should be noted that FIGS. 3 and 4 are described together and that FIG. 4 is included to more clearly illustrate that monolithically integrated multiplexer-translator-demultiplexer 200 comprises input/output sections 2011, 2012, . . . , 201m, where m is an integer. Input/output section 2011 includes monolithically integrated multiplexer-translator-demultiplexer structures 2031, 2032, . . . , 203n, input/output section 2012 includes monolithically integrated multiplexer-translator-demultiplexer sections 2071, 2072, . . . , 207n, and input/output section 201m includes monolithically integrated multiplexer-translator-demultiplexer sections 2111, 2112, . . . 211n, respectively, where m is an integer that may be equal to m.
FIG. 4 further illustrates that monolithically integrated multiplexer-translator-demultiplexer structures 2031, 2032, . . . , 203n include a set of input/output structures 2041, 2042, . . . , 204n coupled to a corresponding set of input/output structures 2061, 2062, . . . , 206n, respectively; monolithically integrated multiplexer-translator-demultiplexer structures 2071, 2072, . . . , 207n comprise a set of input/output structures 2081, 2082, . . . , 208n coupled to a corresponding set of input/output structures 2101, 2102, . . . , 210n, respectively; and monolithically integrated multiplexer-translator-demultiplexer structures 2111, 2112, . . . , 211n comprise a set of input/output structures 2121, 2122, . . . , 212n coupled to a corresponding set of input/output structures 2141, 2142, . . . , 214n, respectively. It should be noted that input/output node 2161 is common to input/output structures 2061, 2101, . . . , 2141, input/output node 2162 is common to input/output structures 2062, 2102, . . . , 2142, and input/output node 216n is common to input/output structures 206n, 210n, . . . , 214n, and that input/output node 2181 is common to input/output structures 2061, 2101, . . . , 2141, input output/node 2182 is common to input/output structures 2062, 2102, . . . , 2142, and input/output node 218n is common to input/output structures 206n, 210n, . . . , 214n. For the sake of clarity, these common connections are not shown in FIG. 4, but are shown in FIG. 3. Thus, FIGS. 3 and 4 and their descriptions should be viewed together.
Monolithically integrated multiplexer-translator-demultiplexer structures 2031, 2032, . . . , 203n comprising input/output stages 2041-204n coupled to input/output stages 2061-206n, respectively, are also referred to as bidirectional data transmission stages, transmission channels, conduction channels, or data channels; monolithically integrated multiplexer-translator-demultiplexer structures 2071, 2072, . . . , 207n comprising input/output stages 2081-208n coupled to input/output channels 2101-210n, respectively, are also referred to as bidirectional data transmission stages, conduction channels, or transmission channels; and monolithically integrated multiplexer-translator-demultiplexer structures 2111, 2112, . . . , 211n comprising input/output stages 2121-212n coupled to input/output stages 2141-214n, respectively, are also referred to as bidirectional data transmission stages, transmission channels, conduction channels, or data channels.
FIG. 3 further illustrates an input/output node of input/output structure 2081 connected to an input/output node of input/output structure 2061 and to an input/output node of input/output structure 2101 and an output terminal of input/output structure 2081 connected to an input terminal of input/output structure 2101. Still referring to FIG. 3, an input/output node of input/output structure 2082 is connected to an input/output node of input/output structure 2062 and to an input/output node of input/output structure 2102 and an output terminal of input/output structure 2082 is connected to an input terminal of input/output structure 2102. An input/output node of input/output structure 208n is connected to an input/output node of input/output structure 206n and to an input/output node of input/output structure 210n and an output terminal of input/output structure 208n is connected to an input terminal of input/output structure 210n. An input/output node of input/output structure 2121 is coupled to an input/output node of input/output structure 2101 and connected to an input/output node of input/output structure 2141 and an output terminal of input/output structure 2121 is connected to an input terminal of input/output structure 2141. An input/output node of input/output structure 2122 is coupled to an input/output node of input/output structure 2102 and connected to an input/output node of input/output structure 2142 and an output terminal of input/output structure 2122 is connected to an input terminal of input/output structure 2142. An input/output node of input/output structure 212n is coupled to an input/output node of input/output structure 210n and connected to an input/output node of input/output structure 214n and an output terminal of input/output structure 212n is connected to an input terminal of input/output structure 214n.
Input/output structures 2041, 2042, . . . , 204n are coupled for receiving voltages VA1, VA2, . . . , VAn, input/output structures 2081, 2082, . . . , 208n are coupled for receiving voltages VB1, VB2, . . . , VBn, and input/output structures 2121, 2122, . . . , 212n are coupled for receiving voltages VZ1, VZ2, . . . , VZn, respectively.
A transceiver circuit 2291 is coupled to monolithically integrated multiplexer-translator-demultiplexer 200. Transceiver circuit 2291 includes transceiver sections or elements 2301, 2302, . . . , 230n that are connected to input/output nodes 2201, 2202, . . . , 220n, of channels 2031, 2032, . . . , 203n, respectively. Each transceiver element 2301, 2302, . . . , 230n includes input/output transistors 2321, 2322, . . . , 232n and input/output buffers 2341, 2342, . . . , 234n, wherein the drains of input/output transistors 2321, 2322, . . . , 232n and the input terminals of buffers 2341, 2342, . . . 234n are connected to input/output nodes 2311, 2312, . . . 231n, respectively. Each transceiver element 2301, 2302, . . . , 230n is coupled for receiving a source of operating potential or supply voltages VCC1. The gates of input/output transistors 2321, 2322, . . . , 232n are connected to control circuits 2361, 2362, . . . , 236n, the sources of input/output transistors 2321, 2322, . . . , 232n are coupled for receiving a source of operating potential or supply voltage VSS1, and the output terminals of input/output buffers 2341, 2342, . . . , 234n are connected to logic circuits 2381, 2382, . . . , 238n, respectively. It should be noted that for the purposes of clarity, control circuits 2361, 2362, . . . , 236n and logic circuits 2381, 2382, . . . , 238n are shown in block form and that the types of control and logic circuits are known to those skilled in the art. Input/output nodes 2311, 2312, . . . 231n of transceiver elements 2301, 2302, . . . , 230n are connected to input/output nodes 2201, 2202, . . . , 220n, respectively.
A transceiver circuit 2292 is coupled to monolithically integrated multiplexer-translator-demultiplexer 200. Transceiver circuit 2292 has transceiver sections or elements 2601, 2602, . . . , 260n that are connected to input/output nodes 2211, 2212, . . . , 221n, of channels 2071, 2072, . . . , 207n, respectively. Each transceiver element 2601, 2602, . . . , 260n includes input/output transistors 2621, 2622, . . . , 262n and input/output buffers 2641, 2642, . . . , 264n, wherein the drains of input/output transistors 2621, 2622, . . . , 262n and the input terminals of buffers 2641, 2642, . . . , 264n are connected to input/output nodes 2611, 2612, . . . , 261n, respectively. Each transceiver element 2601, 2602, . . . , 260n is coupled for receiving a source of operating potential or supply voltages VCC2. The gates of input/output transistors 2621, 2622, . . . , 262n are connected to control circuits 2661, 2662, . . . , 266n, the sources of input/output transistors 2621, 2622, . . . , 262n are coupled for receiving a source of operating potential or supply voltage VSS2 and the output terminals of input/output buffers 2641, 2642, . . . , 264n are connected to logic circuits 2681, 2682, . . . , 268n, respectively. For purposes of clarity, control circuits 2641, 2642, . . . , 264n and logic circuits 2681, 2682, . . . , 268n are shown in block form and that the types of control and logic circuits are known to those skilled in the art. Input/output nodes 2611, 2612, . . . , 261n of transceiver elements 2601, 2602, . . . , 260n are connected to input/output nodes 2211, 2212, . . . , 221n, respectively, of monolithically integrated multiplexer-translator-demultiplexer 200.
A transceiver circuit 229m is coupled to monolithically integrated multiplexer-translator-demultiplexer 200. Transceiver circuit 229m has transceiver sections or elements 2701, 2702, . . . , 270n that are connected to input/output nodes 2231, 2232, . . . , 223n, of channels 2111, 2112, . . . , 211n, respectively. Each transceiver element 2701, 2702, . . . , 270n includes input/output transistors 2721, 2722, . . . , 272n and input/output buffers 2741, 2742, . . . , 274n, wherein the drains of input/output transistors 2721, 2722, . . . , 272n and input terminals of buffers 2741, 2742, . . . , 274n are connected to input/output nodes 2711, 2712, . . . , 271n, respectively. Each transceiver element 2701, 2702, . . . , 270n is coupled for receiving a source of operating potential or supply voltages VCCn. The gates of input/output transistors 2721, 2722, . . . , 272n are connected to control circuits 2761, 2762, . . . , 276n, the sources of input/output transistors 2721, 2722, . . . , 272n are coupled for receiving sources of operating potential or supply voltages VSSn and the output terminals of input/output buffers 2741, 2742, . . . , 274n are connected to logic circuits 2781, 2782, . . . , 278n, respectively. It should be noted that for the purposes of clarity, control circuits 2761, 2762, . . . , 276n and logic circuits 2781, 2782, . . . , 278n are shown in block form and that the types of control and logic circuits are known to those skilled in the art. Input/output nodes 2711, 2712, . . . , 271n of transceiver elements 2701, 2702, . . . , 270n are connected to input/output nodes 2231, 2232, . . . , 223n, respectively, of monolithically integrated multiplexer-translator-demultiplexer 200. It should be noted that supply voltages VCC1, VCC2, . . . , VCCn may be the same or different. Likewise voltages VSS1, VSS2, . . . , VSSn may be the same or different.
A transceiver circuit 240 having input/output nodes 2431, 2432, . . . , 243n are connected to input/output nodes 2161, 2162, . . . , 216n, of channels 2031, 2032, . . . , 203n, respectively. Transceiver circuit 240 comprises transceiver sections or elements 2411, 2412, . . . , 241n which include input/output transistors 2421, 2422, . . . , 242n and input/output buffers 2441, 2442, . . . , 244n, wherein the drains of input/output transistors 2421, 2422, . . . , 242n and the input terminals of buffers 2441, 2442, . . . , 244n are connected to input/output nodes 2431, 2432, . . . , 243n, respectively. Each transceiver section 2411, 2412, . . . , 241n is coupled for receiving a source of operating potential or supply voltages VC. The gates of input/output transistors 2421, 2422, . . . , 242n are connected to control circuits 2461, 2462, . . . , 246n, the sources of input/output transistors 2421, 2422, . . . , 242n are coupled for receiving sources of operating potential or supply voltages VSS and the output terminals of input/output buffers 2441, 2442, . . . , 244n are connected to logic circuits 2481, 2482, . . . , 248n, respectively. It should be noted that for the purposes of clarity, control circuits 2461, 2462, . . . , 246n and logic circuits 2481, 2482, . . . , 248n are shown in block form and that the types of control and logic circuits are known to those skilled in the art. Input/output nodes 2431, 2432, . . . , 243n of transceiver circuit 240 are connected to input/output nodes 2161, 2162, . . . , 216n, of channels 2031, 2032, . . . , 203n, respectively.
By way of example, transceiver circuits 2291, 2292, and 240 are SDIO systems. Alternatively, transceiver circuits 2291, 2292, and 240 are MMC's. In accordance with other alternative embodiments, transceiver circuit 2291 is an SDIO system and transceiver circuit 240 is an MMC, or transceiver circuit 2291 is an MMC and transceiver circuit 240 is an SDIO system or transceiver circuits 2291 and 2292, are SDIO systems and transceiver circuit 240 is an MMC, etc.
Referring now to FIG. 5, each input/output structure 2041-204n, 2081-208n, and 2121-212n comprises an n-channel pass transistor 302 coupled to a p-channel edge-adjusting transistor 304 through a one-shot 306 and a pull-up resistor 308 connected from the source to the drain of p-channel edge-adjusting transistor 304. More particularly, n-channel pass transistor 302 has a source connected to an input/output node 310, a drain connected to an output node 316, and a gate connected to an input/output node 305. The drain of pass transistor 302 is coupled to the gate of edge-adjusting transistor 304 through one-shot 306 and to an output node 312. The gate of pass transistor 302 is connected to the source of p-channel edge-adjusting transistor 304 and to a terminal 314 of pull-up resistor 308. In addition, the gate of pass transistor 302 is connected to output node 305. The source of pass transistor 302 is also connected to a drain of edge-adjusting transistor 304 and to a terminal 318 of pull-up resistor 308. A source-to-body diode 320 is formed between the source and drain of pass transistor 302.
Referring now to FIG. 6, each input/output structure 2061-206n, 2101-210n, and 2141-214n comprises a one-shot 336 connected to a p-channel edge-adjusting transistor 334 and a pull-up resistor 338 connected from the source to the drain of p-channel edge-adjusting transistor 334. The source of edge-adjusting transistor 334 is connected to a terminal 340 of pull-up resistor 338 and to an input/output node 332. The drain of p-channel edge-adjusting transistor 334 is connected to a terminal 342 of pull-up resistor 338 and to an input/output node 344. An input of one-shot 336 is connected to an input node 346.
When input/output structures 2041-204n are connected to corresponding input/output structures 2061-206n, 2101-210n, and 2141-214n (as shown in FIGS. 3 and 4), output nodes 316 are connected to input nodes 346 and input/output nodes 312 are connected to input/output nodes 344. Thus, the sources of pass transistors 302 are connected to the inputs of one-shots 336, the drains of pass transistor 302 and edge-adjusting transistors 334 are electrically connected to each other, and the sources of edge adjusting transistors 334 and terminals 340 of pull-up resistors 338 are electrically connected to each other. Thus, the source of pass transistor 302, the drain of edge-adjusting transistor 304, and terminal 318 of resistor 308 that are commonly connected, i.e., connected together, also are connected to an input/output node 310 and the drain of edge-adjusting transistor 334 and terminal 342 of resistor 338 that are commonly connected, i.e., connected together, also are connected to an input/output node 344.
In operation, a selector circuit such as selector circuit 360 shown in FIG. 3D selects between transceiver circuits 2291, 2292, 229m, for transmitting data to transceiver 140 or receiving data from transceiver 240. In other words, selector circuit 360 selects from one of the sets of transceiver elements 2301-230n, 2621-262n, 2701-270n for transmitting data to transceiver 240 or receiving data from transceiver 240. The operation of transferring data to and from the selected transceiver circuit of the set of transceiver circuits 2291-229m is similar to that described for transceivers 1301, 1302, . . . , 130n and transceiver 140 with reference to FIG. 2.
FIG. 7 is a block diagram of a monolithically integrated multiplexer-translator-demultiplexer 400 in accordance with another embodiment of the present invention. What is shown in FIG. 7 are SDIO systems 2291, 2292, . . . , 229m, where SDIO system 2291 has input/output nodes 2311, 2312, . . . , 231n connected to input/output nodes 2201, 2202, . . . , 220n, respectively, of monolithically integrated multiplexer-translator-demultiplexer 200; SDIO system 2292 has input/output nodes 2611, 2612, . . . , 261n connected to input/output nodes 2211, 2212, . . . , 221n, respectively, of monolithically integrated multiplexer-translator-demultiplexer 200; . . . , SDIO system 229m has input/output nodes 2711, 2712, . . . , 271n connected to input/output nodes 2231, 2232, . . . , 223n, respectively, of monolithically integrated multiplexer-translator-demultiplexer 200. Input/output node 128 of monolithically integrated multiplexer-translator-demultiplexer 200 is connected to a Central Processing Unit (CPU) 402. CPU 402 includes transceiver circuit 240. It should be noted that monolithically integrated multiplexer-translator-demultiplexer 200, transceivers 2291, 2292, . . . , 229m, and transceiver circuit 240 have been described with reference to FIGS. 3A-3D.
By now it should be appreciated that a monolithically integrated multiplexer-translator-demultiplexer and a method for one of multiplexing and leveling shifting a first electrical signal or level shifting and demultiplexing a second electrical signal have been provided. This increases design versatility in permitting interfacing between many different types of systems and circuits. Because the trend in electronics is towards increasing system complexity while decreasing the operating supply voltages, systems and circuits designed using state of the art technology can be interfaced with systems and circuits designed with older and perhaps outdated technologies. For example, the monolithically integrated multiplexer-translator-demultiplexer circuit is capable of being interfaced with different systems that operate at multiple operating voltages.
Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.

## Claims

1. A monolithically integrated multiplexer-translator-demultiplexer, comprising:
a first bidirectional data transmission stage having a first node, a second node, and a third node, the third node coupled for receiving a first source of operating potential;
a second bidirectional data transmission stage having a first node, a second node, and a third node, the first node of the second bidirectional data transmission stage coupled to the second node of the first bidirectional data transmission stage, the second node of the second bidirectional data transmission stage coupled to the first node of the first bidirectional data transmission stage, and the third node of the second bidirectional data transmission stage coupled for receiving a second source of operating potential;
a third bidirectional data transmission stage having a first node, a second node, and a third node, the second node of the third bidirectional data transmission stage coupled to the first node of the second bidirectional data transmission stage and the third node of the third bidirectional data transmission stage coupled for receiving a third source of operating potential; and
a fourth bidirectional data transmission stage having a first node, a second node, and a third node, the first node of the fourth bidirectional data transmission stage coupled to the second node of the third bidirectional data transmission stage, the second node of the fourth bidirectional data transmission stage coupled to the first node of the third bidirectional data transmission stage and the third node of the fourth bidirectional data transmission stage coupled for receiving the second source of operating potential.

2. The monolithically integrated multiplexer-translator-demultiplexer of claim 1, wherein the first bidirectional data transmission stage comprises:
a first transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the first source of operating potential, the first current carrying electrode serving as the first node of the first bidirectional data transmission stage and the second current carrying electrode serving as the second node of the first bidirectional data transmission stage;
a second transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the second transistor coupled for receiving the first source of operating potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the first transistor;
a first one-shot coupled between the second current carrying electrode of the first transistor and the control electrode of the second transistor; and
a first resistor coupled from the first current carrying electrode of the second transistor to the second current carrying electrode of the second transistor.

3. The monolithically integrated multiplexer-translator-demultiplexer of claim 2, wherein the second bidirectional data transmission stage comprises:
a third transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode of the third transistor serving as the third node of the second bidirectional data transmission stage and the second current carrying electrode of the third transistor serving as the second node of the second bidirectional data transmission stage;
a second one-shot coupled between the first node of the first bidirectional data transmission stage and the control electrode of the third transistor; and
a second resistor coupled from the first current carrying electrode of the third transistor to the second current carrying electrode of the third transistor.

4. The monolithically integrated multiplexer-translator-demultiplexer of claim 3, wherein the third bidirectional data transmission stage comprises:
a fourth transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the third source of operating potential, the first current carrying electrode serving as the first node of the third bidirectional data transmission stage and the second current carrying electrode serving as the second node of the third bidirectional data transmission stage;
a fifth transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the fifth transistor coupled for receiving the first source of operating potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the fourth transistor;
a third one-shot coupled between the second current carrying electrode of the fourth transistor and the control electrode of the fifth transistor; and
a third resistor coupled from the first current carrying electrode of the fourth transistor to the second current carrying electrode of the fifth transistor.

5. The monolithically integrated multiplexer-translator-demultiplexer of claim 4, wherein the fourth bidirectional data transmission stage comprises:
a sixth transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode of the sixth transistor serving as the third node of the fourth bidirectional data transmission stage and the second current carrying electrode of the sixth transistor serving as the second node of the fourth bidirectional data transmission stage;
a fourth one-shot coupled between the first current carrying electrode of the fourth transistor and the control electrode of the sixth transistor; and
a fourth resistor coupled from the first current carrying electrode of the sixth transistor to the second current carrying electrode of the sixth transistor.

6. The monolithically integrated multiplexer-translator-demultiplexer of claim 1, further including a selector that selects at least one bidirectional data transmission stage from the first, second, third, and fourth bidirectional data transmission stages.

7. The monolithically integrated multiplexer-translator-demultiplexer of claim 1, further including first and second transceiver circuits coupled to the first and third bidirectional data transmission stages, respectively.

8. The monolithically integrated multiplexer-translator-demultiplexer of claim 7, further including a third transceiver circuit coupled to the second node of the second bidirectional data transmission stage.

9. The monolithically integrated multiplexer-translator-demultiplexer of claim 1, further including a central processing unit coupled to the second bidirectional data transmission stage and at least two SDIO systems coupled to the first bidirectional data transmission stage.

10. A monolithically integrated multiplexer-translator-demultiplexer, comprising:
a first conduction channel having at least two inputs and at least two outputs, wherein a first input of the at least two inputs is coupled for receiving a first source of potential, a second input of the at least two inputs serves as a first input/output node, a first output of the at least two outputs is coupled for receiving a second source of potential and a second output of the at least two outputs serves as a second input/output node; and
a second conduction channel having at least two inputs and at least two outputs, wherein a first input of the at least two inputs is coupled for receiving a third source of potential, a second input of the at least two inputs serves as a third input/output node, a first output of the at least two outputs is coupled to the first output of the at least two outputs of the first conduction channel and a second output of the at least two outputs is coupled to the second output of the at least two outputs of the first conduction channel.

11. The monolithically integrated multiplexer-translator-demultiplexer of claim 10, wherein the first conduction channel comprises:
a first transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the first source of potential, the first current carrying electrode serving as the first input/output node of the first conduction channel and the second current carrying electrode serving as the second input/output node of the first conduction channel;
a second transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the second transistor coupled for receiving the first source of potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the first transistor;
a first one-shot coupled between the second current carrying electrode of the first transistor and the control electrode of the second transistor;
a first resistor coupled from the first current carrying electrode of the second transistor to the second current carrying electrode of the second transistor,
a third transistor having a control electrode and first and second current carrying electrodes, the first electrode of the third transistor serving as the third node of the second conduction channel and the second electrode of the third transistor serving as the second input/output node of the second conduction channel;
a second one-shot coupled between the first node of the first conduction channel and the control electrode of the third transistor; and
a second resistor coupled from the first current carrying electrode of the third transistor to the second current carrying electrode of the third transistor.

12. The monolithically integrated multiplexer-translator-demultiplexer of claim 11, wherein the second conduction channel comprises:
a fourth transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the second source of potential, the first current carrying electrode serving as the third input/output node of the second conduction channel and the second current carrying electrode serving as the fourth input/output node of the second conduction channel;
a fifth transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the fifth transistor coupled for receiving the second source of potential and the second current carrying electrode of the fifth transistor coupled to the first current carrying electrode of the fourth transistor;
a third one-shot coupled between the second current carrying electrode of the fourth transistor and the control electrode of the fifth transistor;
a third resistor coupled from the first current carrying electrode of the fifth transistor to the second current carrying electrode of the fifth transistor;
a sixth transistor having a control electrode and first and second current carrying electrodes, the first electrode of the sixth transistor serving as the third input/output node of the second conduction channel and the second electrode of the sixth transistor serving as the second input/output node of the second conduction channel;
a fourth one-shot coupled between the first node of the second conduction channel and the control electrode of the sixth transistor; and
a fourth resistor coupled from the first current carrying electrode of the sixth transistor to the second current carrying electrode of the sixth transistor.

13. The monolithically integrated multiplexer-translator-demultiplexer of claim 10, further including:
a third conduction channel having at least two inputs and at least two outputs, wherein a first input of the at least two inputs is coupled for receiving a fourth source of potential, a second input of the at least two inputs serves as a fourth input/output node, a first output of the at least two outputs is coupled to the first output of the at least two outputs of the first conduction channel and a second output of the at least two outputs is coupled to the second output of the at least two outputs of the first conduction channel.

14. The monolithically integrated multiplexer-translator-demultiplexer of claim 13, wherein the third conduction channel comprises:
a first transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the first source of potential, the first current carrying electrode serving as the fourth input/output node of the third conduction channel and the second current carrying electrode coupled to the second input/output node of the first conduction channel;
a second transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the second transistor coupled for receiving the fourth source of potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the first transistor;
a first one-shot coupled between the second current carrying electrode of the first transistor and the control electrode of the second transistor,
a first resistor coupled from the first current carrying electrode of the second transistor to the second current carrying electrode of the second transistor;
a third transistor having a control electrode and first and second current carrying electrodes, the first electrode of the third transistor coupled to the third node of the second conduction channel and the second electrode of the third transistor serving as the second input/output node of the first conduction channel;
a second one-shot coupled between the first node of the third conduction channel and the control electrode of the third transistor; and
a second resistor coupled from the first current carrying electrode of the third transistor to the second current carrying electrode of the third transistor.

15. A method for one of multiplexing and leveling shifting a first electrical signal or level shifting and demultiplexing a second electrical signal, comprising:
multiplexing and level shifting the electrical signal by:
providing a plurality of electrical signals to a monolithically integrated circuit;
using the monolithically integrated circuit to select the first electrical signal of the plurality of electrical signals; and
adjusting a signal level of the selected first electrical signal to form a level shifted first electrical signal; or
demultiplexing the second electrical signal by:
providing a second electrical signal to the monolithically integrated circuit;
using the monolithically integrated circuit to adjust the signal level of the second electrical signal to form a level shifted second electrical signal; and
transmitting the level shifted second electrical signal to a plurality of input/output nodes.

16. The method of claim 15, wherein providing the second electrical signal includes providing the second electrical signal from a central processing unit.

17. The method of claim 15, wherein providing the plurality of electrical signals to the monolithically integrated circuit includes providing a plurality of electrical signals as a plurality of voltage signals.

18. A method for multiplexing and level shifting electrical signals, comprising:
providing a plurality of electrical signals to a monolithically integrated circuit, wherein the monolithically integrated circuit comprises a plurality of conduction channels and wherein each electrical signal of the plurality of electrical signals corresponds to a conduction channel of the plurality of conduction channels and wherein one or more of the conduction channels of the plurality of conduction channels is capable of transmitting an electrical signal in first and second directions, the second direction opposite that of the first direction;
using the monolithically integrated circuit to select an electrical signal of the plurality of electrical signals; and
adjusting a signal level of the selected electrical signal to form a level shifted selected electrical signal, wherein adjusting the signal level of the selected electrical signal includes increasing the electrical signal.

19. The method of claim 18, wherein the electrical signal is a voltage signal.

20. A method for multiplexing and level shifting electrical signals, comprising:
providing a plurality of electrical signals to a monolithically integrated circuit, wherein the monolithically integrated circuit comprises a plurality of conduction channels and wherein each electrical signal of the plurality of electrical signals corresponds to a conduction channel of the plurality of conduction channels and wherein one or more of the conduction channels of the plurality of conduction channels is capable of transmitting an electrical signal in first and second directions, the second direction opposite that of the first direction;
using the monolithically integrated circuit to select an electrical signal of the plurality of electrical signals; and
adjusting a signal level of the selected electrical signal to form a level shifted selected electrical signal, wherein adjusting the signal level of the selected electrical signal includes decreasing the electrical signal.