# Patent

## Title
Circuit and method for detecting multiple supply voltages

## Abstract

An apparatus comprises a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider divides a VCC into N states SK, and acquires the border voltages VK and VK+1 corresponding to the SK through a resistor divider. The threshold selector acquires a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine and then sends the acquired VK as VH to a first comparator, and acquires a corresponding voltage VK+1 and sends the acquired VK+1 as VL to a second comparator. The state machine determines whether or not the VH and the VL are matched with the current state SK. If matched, the OSC of the state machine will be turned off, otherwise, the next state Sk+1 or Sk−1 of the SK will be outputted.

## Background
RELATED APPLICATION
The present application claims the benefit of priority to Chinese Patent Application Ser. No. 201110111780.3, filed on Apr. 29, 2011, which is hereby incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION
The power supply voltage of an electronic system often undergoes a decrease in voltage, especially when being powered by a battery. The voltage of a battery will drop in a curve form when the power of the battery is insufficient, and too low of a voltage possibly leads to an abnormal operation of the system. Thus, an electronic system is usually provided with a circuit for detecting supply voltage to avoid the voltage too low.
FIG. 1 is a schematic diagram of a circuit for detecting supply voltages according to the related art, and as shown in FIG. 1, the circuit for detecting supply voltage consists of a reference voltage circuit 101, a resistor divider circuit 102, a Schmitt trigger comparator 103 and a latch 104, wherein a VDD is divided by resistors R1 and R2 to obtain a voltage VIN, the obtained voltage VIN is connected with the positive input terminal of the Schmitt Trigger comparator 103, and the negative input terminal of the Schmitt Trigger comparator 103 is connected with a reference voltage VREF. The working principle of the circuit lies in that the Schmitt Trigger comparator 103 outputs a high level when the VIN is lower than the VREF, and then the voltage of the output node MRK is at a high level, and on the other side, the Schmitt Trigger comparator 103 outputs a low level when the VIN is higher than the VREF, and then the voltage of the output node MRK is at a low level. Through the voltage division of the resistors R1 and R2, the change of the VDD causes a linear change in the voltage value of the VIN, but the reference voltage is not changed following the change of the VDD, thus realizing a voltage detection function according to the level change of the output node MRK.
It can be seen that, according to the approach of in FIG. 1, a plurality of comparators should be used to detect multiple voltage ranges of a single supply voltage. For instance, if detecting four power supply voltages, four comparators are required.
Due to the power consumption of each comparator, in a circuit for detecting multiple supply voltages, the power consumption of the whole circuit will be undoubtedly huge if multiple comparators are used to detect multiple supply voltages. Power consumption is a very important performance index in a circuit system, and this performance index should be considered by all developers and designers.
Overview
An object of the present invention is to provide a solution for detecting multiple supply voltages to at least solve the problem that power consumption of the existing circuit in the related art for detecting multiple supply voltages is huge.
An example of a circuit to achieve the purpose above includes a supply voltage divider, a state machine, two comparators and a threshold selector.
The supply voltage divider, connected with the threshold divider, is configured to divide a supply voltage VCC into N states SK, and to acquire the border voltages VK and VK+1 corresponding to the SK through a resistor divider, wherein K=1, 2, . . . N. The threshold selector, connected with the supply voltage divider and the state machine, is configured to acquire a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine, and then send the acquired VK as VH to a first comparator in the two comparators, and to acquire a corresponding voltage VK+1 and send the acquired VK+1 as VL to a second comparator in the two comparators, wherein the VH is greater than the VL. The first comparator is configured to compare a reference voltage Vref from a reference voltage circuit with the VH in magnitude, the second comparator is configured to compare the Vref with the VL in magnitude. The state machine is configured to determine whether or not the VH and the VL outputted by the threshold selector are matched with the current state SK, when each clock period of an oscillator (OSC) arrives, according to the output results of the first comparator and the second comparator, wherein if the VH and the VL are matched with the current state SK, the OSC of the state machine will be turned off, and otherwise, the OSC will be turned on to provide the clock of the state machine to output the next state Sk+1 or Sk−1 of the SK.
By the present invention, multiple supply voltages can be detected using two comparators, which solves the problem that power consumption of existing circuit for detecting multiple supply voltages is huge in the related art, reduces the number of comparators and improves the performance of the system.
This section is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.



BRIEF DESCRIPTION OF THE DRAWINGS
The drawings illustrated here provide a further understanding of the present invention and form a part of the present application. The exemplary embodiments and the description thereof are used to explain the present invention without unduly limiting the scope of the present invention. In the drawings:
FIG. 1 is a schematic diagram of an example of a circuit for detecting multiple supply voltages;
FIG. 2 is a schematic diagram of an example of a circuit for detecting multiple supply voltages;
FIG. 3 is a flowchart of an example of a method for detecting multiple supply voltages;
FIG. 4 is a schematic diagram of an example of division ranges of a supply voltage;
FIG. 5 is a schematic diagram of an example of a comparator;
FIG. 6 is a flowchart of another example of a method for detecting multiple supply voltages; and
FIG. 7 is a schematic diagram of an example of a state machine.



DETAILED DESCRIPTION
The examples herein are described in detail with reference to the accompanying drawings and in combination with each other. It should be noted that the examples and the features of the examples described in the present application can be combined with each other as long as no conflict is introduced by such combination. According with an embodiment of the present invention, there is provided a circuit for detecting multiple supply voltages. FIG. 2 is a schematic diagram of an example of a circuit for detecting multiple supply voltages. As shown in FIG. 2, the detection circuit may comprise: a supply voltage divider 202, a state machine 204, two comparators 206 and a threshold selector 208, each of which is described below. The supply voltage divider 202, shown connected with the threshold selector 208, can be configured to divide a supply voltage VCC into N states SK and to acquire the border voltages VK and VK+1 corresponding to the SK through a resistor divider, wherein K=1, 2, . . . N.
The threshold selector 208, shown connected with the supply voltage divider 202 and the state machine 204, can be configured to acquire a corresponding voltage VK from the supply voltage divider 202 according to the current state SK output by the state machine 204, and then send the VK , as VH, to a first comparator 2061 of the two comparators 206, and to acquire a corresponding voltage VK+1 and send the acquired VK+1 as VL, to a second comparator 2062 of the two comparators 206, wherein the VH is greater than the VL.
The first comparator 2061 can be configured to compare a reference voltage Vref from a reference voltage circuit with the VH; and the second comparator 2062 can be configured to compare the Vref with the VL in magnitude.
The state machine 204 can be configured to determine whether or not the VH and the VL output by the threshold selector 208 are matched with the current state SK, when each clock period of an oscillator (OSC) arrives, according to the output results of the first comparator 2061 and the second comparator 2062. If the VH and the VL are matched with the current state SK, the OSC of the state machine will be turned off, otherwise, the OSC will be turned on to provide the clock of the state machine 204 to output the next state Sk+1 or Sk−1 of the SK.
By the above-described detection circuit example, the multiple supply voltages can be detected using two comparators 206, which solves the problem of huge power consumption of the existing circuit for detecting multiple supply voltages in the related art. The example also reduces the number of comparators and improves the performance of the system.
For instance, if a VCC is divided into V1, V2, . . . Vn, then the VH and VL outputted by the threshold selector 208 may be as follows: Vi=VCC*Ratio (i=1, 2, . . . n), wherein the Ratioi represents the ratio of a VCC resistor divider. In the implementation process, the supply voltage divider 202 may divide the supply voltage VCC into N states Sk according to the reference voltage Vref of a reference voltage circuit.
Preferably, the first comparator 2061 can also be configured to output a high level when the Vref is greater than the VH, or to output a low level when the Vref is smaller than the VH, and the second comparator 2062 can also be configured to output a high level when the VL is greater than the Vref or to output a low level when the VL is smaller than the Vref.
Preferably, the state machine 204 can also be configured to determine that the VH and the VL outputted by the threshold selector 208 are matched with the current state SK when the first comparator 2061 and the second comparator 2062 both output a low level.
It should be noted that the next edge of the OSC clock of the state machine 204 triggers the state change. In the implementation process, the period of the OSC can be longer than the delay-guaranteeing setup period of the comparators.
In some examples, the state machine 204 can also be configured to output the next state Sk+1 of the SK when the first comparator 2061 outputs a low level and the second comparator 2062 outputs a high level, or to output the next state Sk−1 of the SK when the first comparator 2061 outputs a high level and the second comparator 2062 outputs a low level.
In some examples, the first comparator 2061 can also be configured to output a high level when the VH is greater than the Vref or to output a low level when the VH is smaller than the Vref, and the second comparator 2062 can also be configured to output a high level when the VL is greater than the Vref or to output a low level when the VL is smaller than the Vref.
In some examples, the state machine 204 can also be configured to determine that the VH and the VL outputted by the threshold selector 208 are matched with the current state SK when the first comparator 2061 outputs a high level and the second comparator 2062 outputs a low level.
In some examples, the state machine 204 can also be configured to output the next state Sk+1of the SK when the first comparator 2061 outputs a low level and the second comparator 2062 also outputs a low level, or to output the next state Sk−1of the SK when the first comparator 2061 outputs a high level and the second comparator 2062 also outputs a high level.
In some examples, the threshold selector 208 can consist of a single-pole multi-throw switch. In the implementation process, each of VH terminal and VL terminal is connected with a single-pole multi-throw switch, wherein both of VH terminal and VL terminal are pole terminals. This method has simple implement and high operability.
A method for detecting multiple supply voltages can also be provided corresponding to the above-described detection circuit. FIG. 3 is a flowchart of an example of a method for detecting multiple supply voltages according to an embodiment of the present invention.
As shown in the example of FIG. 3, the method can include the following:
at S302, a supply voltage divider 202, which can be connected with the threshold selector 208, can be configured to divide a supply voltage VCC into N states SK and to acquire the border voltages VK and VK+1 corresponding to a SK through a resistor divider, wherein K=1, 2, . . . N;
at S304, a threshold selector 208, which can be connected with the supply voltage divider 202 and a state machine 204, can be configured to acquire a corresponding voltage VK from the supply voltage divider 202 according to the current state SK outputted by the state machine 204, and then send the VK as VH to a first comparator 2061 in the two comparators 206, and to acquire a corresponding voltage VK+1 and send the acquired VK+1 as VL to a second comparator 2062 in the two comparators 206, wherein the VH is greater than the VL,
at S306, a first comparator 2061 can be configured to compare a reference voltage Vref from a reference voltage circuit with the VH in magnitude, and configuring a second comparator to compare the Vref with the VL in magnitude; and
at S308: a state machine 204 can be configured to determine whether or not the VH and the VL outputted by the threshold selector 208 are matched with the current state SK, when each clock period of an oscillator (OSC) arrives, according to the output results of the first comparator 2061 and the second comparator 2062, wherein if the VH and the VL are matched with the current state SK, the OSC of the state machine can be turned off, otherwise, the OSC can be turned on to provide the clock of the state machine 204 to output the next state Sk+1 or Sk−1 of the SK.
By adopting the method in the above example, multiple supply voltages can be detected using two comparators 206, which solves the problem that power consumption of the existing circuit for detecting multiple supply voltages in the related art can be huge. Adopting the method can also reduce the number of comparators and improve the performance of the system.
In some examples, when the High input terminal of the first comparator 2061 and the Low input terminal of the second comparator 2062 are connected with the Vref, S308 can include the state machine 204 determining that the VH and the VL output by the threshold selector 208 are matched with the current state SK if the first comparator 2061 and the second comparator 2062 both output a low level; and when the Low input terminal of the first comparator 2061 and the Low input terminal of the second comparator 2062 are both connected with the Vref, S308 can include the state machine 204 determining that the VH and the VL output by the threshold selector 208 are matched with the current state SK if the first comparator 2061 outputs a high level and the second comparator 2062 outputs a low level.
Additional examples are described hereinafter.
According to some examples, a method for detecting multiple supply voltages can include using two comparators to reduce power consumption by reducing the number of comparators. Each comparator only consumes a current of 150 nA (150 nanoamps) and the method can detect all voltage ranges.
In certain examples, the circuit for detecting multiple supply voltages comprises: a VCC resistive divider, comparators, a threshold selector for the comparators, an oscillator (OSC), and a state machine.
FIG. 4 is an example of a schematic diagram of the division ranges of a supply voltage. As shown in FIG. 4 (a), a VCC is divided into N ranges, such as range S1, S2, . . . Sn. By using the comparative range borders VH and VL of two comparators (namely, the high and low thresholds of two comparators), it is detected whether or not the VCC is in a range between the VH and the VL, wherein the oscillator (such as a low-frequency oscillator without power consumption when being disabled) will be turned on to provide the clock of the state machine if the VCC is not in the range.
FIG. 5 is an example of a schematic diagram of a comparator. As shown in FIG. 5, assuming the current state is Sn, if the comparator shows that the VCC is below the range Sn, then the next state is Sn+1; if the VCC is above the Sn, then the next state is Sn−1; and if the VCC is equal to the Sn, then the OSC is stopped. Particularly, the current state is maintained if the next state is beyond the range. The final stable state is between the VH and the VL, which means that the outputs of the two comparators are fixed, and a smallest power-consuming state can be selected for the comparators to reduce power consumption.
In the above, the VH and the VL refer respectively to the high and low thresholds of the two comparators, and the Vref refers to the other input of the comparator. When the VCC rises or drops rapidly, the Vref is always kept between the VH and the VL by a state change. Any VCC has a final stable state in which the oscillator can be turned off
In some examples, in order to determine that the next state will not be beyond the range, in the implementation process, a first range S0 and a last range Sn+, may be added, wherein it is configured that the next state of the state S0 can only be S0 or S1, and the next state of the state Sn+1, can only be Sn+, or Sn. In this way, the stability and the fault-tolerance of a system can be improved.
According to some examples, a method for detecting multiple supply voltages can include, as shown in FIG. 4 (a), dividing all the supply voltages to be identified into the ranges S0, S1 . . . Sn (namely, the state ranges of a state machine), wherein voltage V, is the border between range S and (i=1, 2, . . . n).
The values of R0 (namely, the ratio of a divider resistance) to Rn+, can be determined according to the border voltage V, and the reference voltage Vref output by a reference voltage circuit. As shown in FIG. 4 (b), when the VCC is finally equal to a Vi, a VRi equal to the Vref (i=1,2, . . . n) can be achieved due to a resistor divider, and at the same time, for the sake of protecting this border state, it can be defined that ‘VR0=VCC’ and ‘VRn+1=0’. If the VCC is in a range Si, namely, the VCC is between a Vi and a Vi+1, then the Vref is between a VRi and a VRi+1, by a resistor divider, and as a result, the problem how to determine the voltage range of VCC is converted to the comparison between the VRi and the VRi+1, and the Vref. So it can be seen that there is a significant difference from the existing detection circuit, in which each VRi is corresponding to one comparator, and a voltage range determined by a given logic realized according to the outputs of these comparators.
A threshold selector may select a VH and a VL for comparators according to the current state Sk. For example, VH=VRk, and VL=VRk+i. For instance, if the Vref is higher than the VH (namely, VRk), then it is indicated that the range Sj in which the VCC exists needs to meet ‘j<K’. The state machine first allows ‘j=k−1’, and then continues to search for the correct voltage range of the VCC.
FIG. 6 is an example of a schematic diagram of the state of a supply voltage according to a preferred embodiment of the present invention. As shown in FIG. 6, when the first comparator outputs a low level ‘L’ and the second comparator also outputs a low level ‘L’, the current state Sk of the state machine is stable, and at the moment, the OSC clock of the state machine will be turned off; when the first comparator outputs a high level ‘H’ and the second comparator outputs a low level ‘L’, the state machine will output the next state Sk−1of the current state Sk when a clock edge arrives; and when the first comparator outputs a low level ‘L’ and the second comparator outputs a high level ‘H’, the state machine will output the next state Sk+1 of the current state Sk when a clock edge arrives.
When OSC_EN in FIG. 5 is high, the outputs of the comparators are not (L, L), the OSC and the state machine will be started, and the state machine will determine the next state at each clock edge according to the current state of FIG. 6 and the outputs of the comparators. Since the final stable state is that the outputs of the comparators are (L, L), thus it can be designed that the comparators have the smallest power consumption when the output of the comparators are low levels.
FIG. 7 is a flowchart of an example of a method for detecting multiple supply voltages according to an embodiment of the present invention. As show in FIG. 7, the method comprises the following.
At S702, the current state is Sk.
At S704, it is determined whether or not the OSC_EN shown in FIG. 5 is at a high level according to the outputs of comparators, wherein if the OSC_EN is a high level, S706 is executed, and if the OSC_EN is at a low level, the current state is maintained.
At S706, an OSC and a state machine are started.
At S708, it is determined whether or not the state is in a border range, for example, k=0 or k=n, wherein if the state is in a border range, the current state is maintained, otherwise, S710 is executed.
At S710, it is determined whether or not the Vref is higher than a VH, wherein if the Vref is higher than the VH, a state Sk−1 is entered, otherwise, a state Sk+1 is entered.
The several examples described herein show that multiple supply voltages can be detected by using only two comparators, which reduces the number of comparators and lowers power consumption of the whole circuit system.
Additional Notes and Examples
Example 1 includes subject matter such as a circuit for detecting multiple supply voltages comprising a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider, connected with the threshold divider, is configured to divide a supply voltage VCC into N states SK, and to acquire the border voltages VK and VK+1 corresponding to the SK through a resistor divider, wherein K=1, 2, . . . N; the threshold selector, connected with the supply voltage divider and the state machine, is configured to acquire a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine, and then send the acquired VK as VH to a first comparator in the two comparators, and to acquire a corresponding voltage VK+1 and send the acquired VK+1 as a VL to a second comparator in the two comparators, wherein the VH is greater than the VL, the first comparator is configured to compare a reference voltage Vref from a reference voltage circuit with the VH in magnitude the second comparator is configured to compare the Vref with the VL in magnitude; and the state machine is configured to determine whether or not the VH and the VL outputted by the threshold selector are matched with the current state SK, when each clock period of an oscillator (OSC) arrives, according to the output results of the first comparator and the second comparator, wherein if the VH and the VL are matched with the current state SK, the OSC of the state machine will be turned off, and otherwise, the OSC will be turned on to provide the clock of the state machine to output the next state Sk+1 or Sk−1 of the SK.
In Example 2, the subject matter of Example 1 can optionally include a first comparator optionally configured to output a high level when the Vref is greater than the VH, or to output a low level when the Vref is smaller than the VH, and the second comparator is further configured to output a high level when the VL is greater than the Vref or to output a low level when the VL is smaller than the Vref.
In Example 3, the subject matter of one or any combination of Examples 1 and 2 can optionally include a state machine configured to determine that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator and the second comparator both output a low level.
In Example 4, the subject matter of one or any combination of Examples 1-3 can optionally include a state machine configured to output the next state Sk+1 of the SK when the first comparator outputs a low level and the second comparator outputs a high level, or to output the next state Sk−1 of the SK when the first comparator outputs a high level and the second comparator outputs a low level.
In Example 5, the subject matter of one or any combination of Examples 1-4 can optionally include a first comparator of the two comparators configured to output a high level when the VH is greater than the Vref or to output a low level when the VH is smaller than the Vref, and the second comparator is further configured to output a high level when the VL is greater than the Vref or to output a low level when the VL is smaller than the Vref.
In Example 6, the subject matter of one or any combination of Examples 1-5 can optionally include a state machine configured to determine that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator outputs a high level and the second comparator outputs a low level.
In Example 7, the subject matter of one or any combination of Examples 1-6 can optionally include a state machine configured to output the next state Sk+1 of the SK when the first comparator and the second comparator both output a low level, or to output the next state Sk−1 of the SK when the first comparator and the second comparator both output a high level.
In Example 8, the subject matter of one or any combination of Examples 1-7 can optionally include a threshold selector including a single-pole multi-throw switch.
Example 9 can include subject matter, or can optionally be combined with the subject matter of one or any combination of Examples 1-8 to include subject matter (such as a method, a means for performing acts, or a machine-readable medium including instructions that, when performed by the machine, cause the machine to perform acts) comprising configuring a supply voltage divider which is connected with a threshold selector to divide a supply voltage VCC into N states SK and to acquire the border voltages VK and VK+1 corresponding to the SK through a resistor divider, wherein K=1, 2, . . . N; configuring a threshold selector which is connected with the supply voltage divider and a state machine to acquire a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine, and then send the VK as a VH to a first comparator in the two comparators, and to acquire a corresponding voltage VK+1 and send the acquired VK+1 as a VL to a second comparator in the two comparators, wherein the VH is greater than the VL, configuring the first comparator to compare a reference voltage Vref from a reference voltage circuit with the VH in magnitude, configuring the second comparator to compare the Vref with the VL in magnitude; and configuring the state machine to determine whether or not the VH and the VL outputted by the threshold selector are matched with the current state SK when each clock period of an oscillator (OSC) arrives according to the output results of the first comparator and the second comparator, wherein if the VH and the VL are matched with the current state SK, the OSC of the state machine will be turned off, and otherwise, the OSC will be turned on to provide the clock of the state machine to output the next state Sk+1 or Sk−1of the Sk.
In Example 10, when the High input terminal of the first comparator and the Low input terminal of the second comparator are both connected with the Vref, the step of configuring the state machine of Example 9 can optionally include: the state machine determining that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator and the second comparator both output a low level; and when the Low input terminal of the first comparator and the Low input terminal of the second comparator are both connected with the Vref, the step of configuring the state machine can optionally include: the state machine determining that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator outputs a high level and the second comparator outputs a low level.
Example 11 can include, or can optionally be combined with any portion or combination of any portions of any one or more of Examples 1-20 to include, subject matter that can include means for performing any one or more of the functions of Examples 1-10, or a machine-readable medium including instructions that, when performed by a machine, cause the machine to perform any one or more of the functions of Examples 1-10.
These non-limiting examples can be combined in any permutation or combination.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” In the event of inconsistent usages between this document and documents incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, the code can be tangibly stored on one or more volatile or non-volatile computer-readable media during execution or at other times. These computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAM's), read only memories (ROM's), and the like. In some examples, a carrier medium can carry code implementing the methods. The term “carrier medium” can be used to represent carrier waves on which code is transmitted.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

## Claims

1. A circuit comprising: a supply voltage divider, a state machine, two comparators and a threshold selector, wherein
the supply voltage divider, connected with the threshold selector, is configured to divide a supply voltage VCC into N states SK, and to acquire the border voltages VK and VK+1 corresponding to the SK through a resistor divider, wherein K=1, 2, . . . N;
the threshold selector, connected with the supply voltage divider and the state machine, is configured to acquire a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine, send the acquired VK as VH to a first comparator in the two comparators, and to acquire a corresponding voltage VK+1 and send the acquired VK+1 as VL to a second comparator in the two comparators, wherein the VH is greater than the VL;
the first comparator is configured to compare a reference voltage Vref from a reference voltage circuit with the VH in magnitude; the second comparator is configured to compare the Vref with the VL in magnitude; and
the state machine is configured to determine whether or not the VH and the VL outputted by the threshold selector are matched with the current state SK, when each clock period of an oscillator (OSC) arrives, according to the output results of the first comparator and the second comparator, wherein if the VH and the VL are matched with the current state SK, the OSC of the state machine will be turned off, and otherwise, the OSC will be turned on to provide the clock of the state machine to output the next state Sk+1 or Sk−1 of the SK.

2. The circuit of claim 1, wherein the first comparator is further configured to output a high level when the Vref is greater than the VH, or to output a low level when the Vref is smaller than the VH, and the second comparator is further configured to output a high level when the VL is greater than the Vref, or to output a low level when the VL is smaller than the Vref.

3. The circuit of claim 2, wherein the state machine is further configured to determine that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator and the second comparator both output a low level.

4. The circuit of claim 3, wherein the threshold selector consists of a single-pole multi-throw switch.

5. The circuit of claim 2, wherein the state machine is further configured to output the next state Sk+1 of the SK when the first comparator outputs a low level and the second comparator outputs a high level, or to output the next state Sk−1 of the SK when the first comparator outputs a high level and the second comparator outputs a low level.

6. The circuit of claim 5, wherein the threshold selector consists of a single-pole multi-throw switch.

7. The circuit of claim 2, wherein the threshold selector consists of a single-pole multi-throw switch.

8. The circuit of claim 1, wherein the first comparator is further configured to output a high level when the VH is greater than the Vref or to output a low level when VH is smaller than the Vref, and the second comparator is further configured to output a high level when the VL is greater than the Vref or to output a low level when the VL is smaller than the Vref.

9. The circuit of claim 8, wherein the state machine is further configured to determine that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator outputs a high level and the second comparator output a low level.

10. The circuit of claim 9, wherein the threshold selector consists of a single-pole multi-throw switch.

11. The circuit of claim 8, wherein the state machine is further configured to output the next state Sk+1 of the SK when the first comparator and the second comparator both output a low level, or to output the next state Sk−1 of the SK when the first comparator and the second comparator both output a high level.

12. The circuit of claim 11, wherein the threshold selector consists of a single-pole multi-throw switch.

13. The circuit of claim 8, wherein the threshold selector consists of a single-pole multi-throw switch.

14. The circuit of claim 1, wherein the threshold selector consists of a single-pole multi-throw switch.

15. A method comprising:
configuring a supply voltage divider which is connected with a threshold selector to divide a supply voltage VCC into N states SK and to acquire the border voltages VK and VK+1 corresponding to the SK through a resistor divider, wherein K=1, 2, . . . N;
configuring the threshold selector which is connected with the supply voltage divider and a state machine to acquire a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine, send the acquired VK as VH to a first comparator in the two comparators, and to acquire a corresponding voltage VK+1 and send the acquired VK+1 as VL to a second comparator in the two comparators, wherein the VH is greater than the VL;
configuring the first comparator to compare a reference voltage Vref from a reference voltage circuit with the VH in magnitude; configuring the second comparator to compare the Vref with the VL in magnitude; and
configuring the state machine to determine whether or not the VH and the VL outputted by the threshold selector are matched with the current state SK when each clock period of an oscillator (OSC) arrives, according to the output results of the first comparator and the second comparator, wherein if the VH and the VL are matched with the current state SK, the OSC of the state machine will be turned off, and otherwise, the OSC will be turned on to provide the clock of the state machine to output the next state Sk+1 or Sk−1 of the SK.

16. The method of claim 15, wherein
when the High input terminal of the first comparator and the Low input terminal of the second comparator are both connected with the Vref, the step of configuring the state machine comprises: the state machine determining that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator and the second comparator both output a low level; and
when the Low input terminal of the first comparator and the Low input terminal of the second comparator are both connected with the Vref, the step of configuring the state machine comprises: the state machine determining that the VH and the VL outputted by the threshold selector are matched with the current state SK when the first comparator outputs a high level and the second comparator outputs a low level.