# Patent

## Title
Semiconductor device including first and second semiconductor elements

## Abstract

A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α1 of a breakdown voltage Vbr1 of the first pn junction and a temperature coefficient α2 of a breakdown voltage Vbr2 of the second pn junction have a same algebraic sign and satisfy 0.6×α1<α2<1.1×α1 at T=300 K, wherein Vbr2<Vbr1.

## Background
BACKGROUND
When switching inductive loads at high speed or during electrostatic discharge events, semiconductor components such as power switches or electrostatic discharge devices are required to dissipate energy stored in an inductor or charged element. This requires adjustment of the turn-on behavior of these semiconductor components relative to other semiconductor elements to ensure that the semiconductor element which is designated to dissipate the energy absorbs a respective discharge current and, consequently, to avoid any overstress of semiconductor elements that are not capable of absorbing the energy and to avoid any overstress in a mode that would lead to destruction of devices.
Thus, it is desirable to improve energy dissipation in a semiconductor device when switching off inductive loads at high speed or during electrostatic discharge events.
SUMMARY
According to an embodiment of a semiconductor device, the semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α1 of a breakdown voltage Vbr1 of the first pn junction and a temperature coefficient α2 of a breakdown voltage Vbr2 of the second pn junction have a same algebraic sign and satisfy 0.6×α1<α2<1.1×α1 at T=300K, wherein Vbr2<Vbr1.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and on viewing the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other.
Embodiments are depicted in the drawings and are detailed in the description which follows.
FIG. 1A is a schematic illustration of an equivalent circuit of one embodiment of semiconductor device including a first semiconductor element and a second semiconductor element.
FIG. 1B is one embodiment of a schematic cross-sectional view of the semiconductor device illustrated in FIG. 1A.
FIG. 2 illustrates a schematic cross-sectional view of one embodiment of a semiconductor device including a cell array of a trench n-type field effect transistor (NFET) and a trench sense cell.
FIG. 3 is a schematic illustration of one embodiment of a cross-sectional view of a semiconductor device including a cell array of a trench NFET and a trench sense cell, the trenches of the trench NFET and the trench sense cell having a different depth.
FIG. 4 is a schematic illustration of one embodiment of a cross-sectional view of a superjunction device including a cell array of a superjunction field effect transistor and a superjunction sense cell.
FIG. 5 is a schematic illustration of one embodiment of a circuit diagram of a semiconductor device including a first diode triggering an NFET and a second diode configured to withstand electrostatic discharge currents.
FIG. 6 is one embodiment of a schematic cross-sectional view of a part of the semiconductor device illustrated in FIG. 5.
FIG. 7 is a schematic diagram illustrating embodiments of a lateral p-type impurity profile along lines AA′ and BB′ of the device illustrated in FIG. 6.



DETAILED DESCRIPTION
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, “over”, “above”, “below”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing processes have been designated by the same references in the different drawings if not stated otherwise.
The terms “lateral” and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die.
The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.
As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together—intervening elements may be provided between the “coupled” or “electrically coupled” elements. As an example, none, part or all of the intervening element(s) may be controllable to provide a low-ohmic connection and, at another time, a non-low-ohmic connection between the “coupled” or “electrically coupled” elements. The term “electrically connected” intends to describe a low-ohmic electric connection between the elements electrically connected together, e.g., a connection via a metal and/or highly doped semiconductor.
In this specification, n-doped may refer to a first conductivity type while p-doped is referred to a second conductivity type. It goes without saying that the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Furthermore, some Figures illustrate relative doping concentrations by indicating “−” or “+” next to the doping type. For example, “n−” means a doping concentration which is less than the doping concentration of an “n”-doping region while an “n+”-doping region has a larger doping concentration than the “n”-doping region. Indicating the relative doping concentration does not, however, mean that doping regions of the same relative doping concentration have the same absolute doping concentration unless otherwise stated. For example, two different n+-doped regions can have different absolute doping concentrations. The same applies, for example, to an n+-doped and a p+-doped region.
Specific embodiments described in this specification pertain to, without being limited thereto, power semiconductor devices which are controlled by field-effect and particularly to unipolar devices such as MOSFETs.
The term “field-effect” as used in this specification intends to describe the electric field mediated formation of an “inversion channel” and/or control of conductivity and/or shape of the inversion channel in a semiconductor channel region.
In the context of the present specification, the term “field-effect structure” intends to describe a structure which is formed in a semiconductor substrate or semiconductor body or semiconductor device and has a gate electrode which is insulated at least from the body region by a dielectric region or dielectric layer or part of an insulating structure. Examples of dielectric materials for forming a dielectric region or dielectric layer between the gate electrode and the body region include, without being limited thereto, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxinitride (SiOxNy), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) and hafnium oxide (HfO2) or stacks of these materials.
Above a threshold voltage Vth between the gate electrode and the source electrode, which is typically connected to the body region, an inversion channel is formed and/or controlled due to the field-effect in a channel region of the body region adjoining the dielectric region or dielectric layer. The threshold voltage Vth typically refers to the minimum gate voltage necessary for the onset of a unipolar current flow between the two semiconductor regions of the first conductivity type, which form the source and the drain of a transistor.
In the context of the present specification, the term “MOS” (metal-oxide-semiconductor) should be understood as including the more general term “MIS” (metal-insulator-semiconductor). For example, the term MOSFET (metal-oxide-semiconductor field-effect transistor) should be understood to include FETs having a gate insulator that is not an oxide, i.e., the term MOSFET is used in the more general term meaning IGFET (insulated-gate field-effect transistor) and MISFET, respectively.
Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
FIG. 1A schematically illustrates one embodiment of a circuit diagram of a semiconductor device 100. The semiconductor device 100 includes a first semiconductor element 101 including a first pn junction between a first terminal 102 and a second terminal 103. The semiconductor device 100 further includes a second semiconductor device 104 including a second pn junction between a third terminal 105 and a fourth terminal 106. The first and second semiconductor elements 101, 104 are integrated monolithically in a semiconductor body (not illustrated in FIG. 1A, cf. FIG. 1B). The first and third terminals 102, 105 are electrically coupled to a first device terminal 107. The second and fourth terminals 103, 106 are electrically coupled to a second device terminal 108. A temperature coefficient α1 of a breakdown voltage Vbr1 of the first pn junction of the first semiconductor element 101 and a temperature coefficient α2 of a breakdown voltage Vbr2 of the second pn junction of the semiconductor element 104 have a same algebraic sign and satisfy 0.6×α1<α2<1.1×α1 at T=300K, wherein Vbr2<Vbr1. According to another embodiment, the relation 0.8×α1<α2<α1 at T=300K is valid.
Each one of the first and third terminals 102, 105 may not be directly coupled to the first device terminal 107 but include intervening elements. Likewise, each one of the second and fourth terminals 103, 106 may not be directly coupled to the second device terminal 108 but include one or more intervening elements. As an example, an intervening element 109 between the second terminal 103 and the second device terminal 108 is schematically illustrated. However, more or less intervening elements may be arranged between one or more of the terminals 102, 103, 105, 106 and the corresponding one of the device terminals 107, 108.
In the schematic illustration of the circuit diagram of FIG. 1A, each one of the first and second semiconductor elements 101, 104 is illustrated as a two terminal device such as, e.g., a diode. However, one or both of these elements 101, 104 may include more than two terminals, e.g., three terminals such as two load terminals and one control terminal. As an example, the first and/or the second semiconductor element 101, 104 may include a FET having source, drain, gate and a bipolar transistor having collector, emitter, base, for example.
The device terminals 107, 108 may be, but are not limited to, chip pins including pins such as Ground, Battery, Input, Output and/or voltage taps, for example.
FIG. 1B schematically illustrates one embodiment of a cross-sectional view of the semiconductor device 100 of FIG. 1A. In an area A of a semiconductor body 110, e.g., a semiconductor substrate such as a silicon (Si) substrate or a carrier having a semiconductor layer, e.g., an epitaxial Si layer, formed thereon, the first semiconductor element 101 or a part thereof is formed. In a second area B of the semiconductor body 110, the second semiconductor element 104 or a part thereof is formed. Thus, semiconductor elements 101, 104 are monolithically integrated. The semiconductor elements are interconnected as is illustrated in FIG. 1A (not illustrated in FIG. 1B).
In the schematic cross-sectional view of FIG. 1B, the region A including the first semiconductor element 101 laterally adjoins the second region B including the second semiconductor element 104. According to another embodiment, a lateral distance between the region A and the region B is smaller than 1000 μm, in particular smaller than 100 μm. The region A and the region B may also be arranged directly next to each other. This allows for a favorable thermal coupling between the first and second semiconductor elements 101, 104. This further allows to minimize the impact of process variations which typically increase with increasing distance. Thus, adjustment of these elements is improved. According to another embodiment, region B is surrounded by region A, e.g. region B may include a sense cell that is spread, e.g., spread evenly, over the area A of a transistor cell array, for example.
By setting the temperature coefficients α1, α2 and breakdown voltages Vbr1, Vbr2 as described above, which is achieved by using similar structures and doping profiles, matching of the semiconductor elements 101, 104 can be improved. Hence, reliability of energy dissipation in a designated one of the first and second semiconductor elements 101, 104 during an electrostatic discharge event or during switching off an inductive load can be improved.
FIG. 2 schematically illustrates one embodiment of a cross-sectional view of a semiconductor device 200 including a trench NFET cell array in an area C and a trench sense cell in an area D.
The trench NFET and the trench cell sense cell share an n+-doped semiconductor substrate 201 and a n-doped drift zone 202, e.g. an n-doped epitaxial layer, formed thereon. At a rear side 203 of the n+-doped semiconductor substrate 201 a contact 204, e.g., a metal contact including, e.g., Al, Ti, Ag, Au, Ni, Cu, Tu is formed. The contact 204 constitutes a drain contact of both the trench NFET and the sense cell.
The drift zone 202 in the area C of the trench NFET adjoins a p-doped body region 205. The p-doped body region 205 is electrically coupled to a conductive layer 206 at a front side 207. A p+-doped body contact zone may be provided at an interface between the p-doped body region 205 and the conductive layer 206 (not illustrated in FIG. 2). This body contact zone may establish an ohmic contact between the p-doped body region 205 and the conductive layer 206.
Trenches 207a . . . c extend from the front side 207 through the p-doped body region 205 into the n-doped drift zone 202 of the trench NFET. As an example, the trenches 207a . . . c or some of the trenches 207a . . . c may constitute part of a continuous trench structure. Field electrodes 208a . . . c are arranged in a bottom part of the trenches 207a . . . c and gate electrodes 209a . . . c are arranged in a top part of the trenches 207a . . . c. Insulating structures 210a . . . c are arranged between the field electrodes 208a . . . c and the gate electrodes 209a . . . c. The insulating structures 210a . . . c include gate dielectrics adjoining the body region 205 and also provide an electric insulation between the electrodes 208a . . . c, 209a . . . c and the surrounding drift zone 202/body region 205. In other embodiments, field electrodes can be omitted or can be part of the gate electrodes.
Further, n+-doped source regions 211a . . . e laterally adjoin the trenches 207a . . . c and are electrically coupled to the conductive layer 206. Insulating caps 212a . . . c are arranged on the gate electrodes 209a . . . c and provide an electric insulation between the conductive layer 206 and the gate electrodes 209a . . . c. 
The drift zone 202 in an area D of the trench sense cell adjoins a p-doped body region 205′. In the embodiment illustrated in FIG. 2, the p-doped body region 205′ has a width w2 that is larger than a width w1 of the p-doped body region 205 in the area C of the trench NFET. Further, the p-doped body region 205′ has a depth d2, i.e. a vertical dimension, that is larger than a depth d1 of the p-doped body region 205 in the area C of the trench NFET. These layout and design measures allow the setting of a breakdown voltage Vbr1 of a first pn junction including the p-doped body region 205 and the n-doped drift zone 202 in the area C larger than a breakdown voltage Vbr2 of a second pn junction including the p-doped body region 205′ and the n-doped drift zone 202 in the area D of the trench sense cell.
The p-doped body region 205′ laterally adjoins the insulating structure 210c on one side and an insulating structure 210d on another side opposite to the one side. The insulating structure 210d electrically insulates a field electrode 208d in a trench 207d. The p-doped body region 205′ is electrically coupled to a conductive layer 206′. Similar to the trench NFET in the region C, a p+-doped body contact zone may be provided to establish an ohmic contact between the conductive layer 206′ and the p-doped body region 205′ (not illustrated in FIG. 2). An insulating cap 212d is arranged on top of the field electrode 208c. In the embodiment illustrated in FIG. 2, the trench sense cell lacks any n+-doped source regions. The field electrodes 208a . . . d are typically electrically coupled to the conductive layer 206. In other embodiments the field electrode 208d may be electrically coupled to the conductive layer 206′.
The p-doped body region 205′ is electrically coupled to the gate electrodes 209a . . . b of the trench NFET in the area C via the conductive layer 206′ and optional intervening elements, e.g., a wiring. The optional intervening elements are illustrated in a simplified manner by a line 213. The p-doped body region 205′ is further electrically coupled to a device terminal GND via an intervening element 214. The intervening element 214 may include a resistor, and/or a part of a gate driver circuit, and/or a part of a transformer, for example. As an example, when turning off IGBTs with a negative supply voltage, the electrical coupling may be effected via part of a transformer. The conductive layer 206 is also electrically connected with the device terminal GND. Thus, the interconnection between the trench NFET in the area C and the trench sense cell in the area D is one example of an interconnection as illustrated in the schematic circuit diagram of FIG. 1A. In other words, the trench NFET in the area C is one example of the second semiconductor element 104 illustrated in FIG. 1A and the trench sense cell in the area D is one example of the first semiconductor element 101 illustrated in FIG. 1A.
The design of the first and second pn junctions of the semiconductor device 200 allows the adjustments of a temperature coefficient α1 of the breakdown voltage Vbr1 of the first pn junction and a temperature coefficient α2 of the breakdown voltage Vbr2 of the second pn junction to have a same algebraic sign and to satisfy 0.6×α1<α2<1.1×α1 at T=300K. Thus, when switching off an inductive load via the semiconductor device 200, an increase of a reverse voltage of the pn junctions first triggers an electrical breakdown of the second pn junction of the trench sense cell in the area D while the first pn junction of the trench NFET in the area C remains in a blocking state. A breakdown current, e.g., an avalanche current, generated in the trench sense cell flows to GND via the intervening element 214. A voltage drop across the intervening element 214, e.g., across an internal gate resistor and/or an external gate resistor and/or a internal resistance of a gate driver circuit, leads to a current flowing along the channel between source and drain of the trench NFET in the area C as soon as this voltage drop exceeds the threshold voltage of the trench NFET 200. Thus, when switching off an inductive load via the semiconductor device 200, dissipation of energy stored in the inductor occurs within the trench NFET in the area C triggered by electrical breakdown in the trench sense cell in the area D. Since the current within the trench NFET in the area C between the conductive layer 206 and the drift zone 202 is a channel current, avalanche generation within the trench NFET 200 can be reduced by several orders of magnitude. Hence, trapping of hot carriers within the insulating structures 210a . . . b which would occur during avalanche breakdown of the trench NFET can be significantly reduced. This leads to an improved reliability of the semiconductor device 200.
According to one embodiment, a difference between the first breakdown voltage Vbr1 of the first pn junction and the second breakdown voltage Vbr2 of the second pn junction is in a range between 50% to 600%, even 50% to 300%, of a threshold voltage of the trench NFET in the area C. A difference Vbr1−Vbr2 may be within a range of 2V to 10V, for example.
The semiconductor device 200 illustrated in FIG. 2 is one example of a device design having a breakdown voltage Vbr2 in a trench sense cell that is smaller than the breakdown voltage Vbr1 in the trench NFET 200 such that a temperature coefficient of breakdown voltages α1 of the first pn junction and a temperature coefficient of breakdown voltage α2 of the second pn junction have a same algebraic sign and satisfy 0.6×α1<α2<1.1×α1 at T=300K.
However, apart from the design of the semiconductor device 200 illustrated in FIG. 2, other design measures may also allow the setting of the breakdown voltage Vbr2 of the trench sense cell of the area D smaller than the breakdown voltage Vbr1 of the trench NFET in the area C. A further example of such a design is illustrated in simplified manner in the schematic cross-sectional view of a FIG. 3. In FIG. 3, a reduction of the breakdown voltage of the trench sense cell in the area D compared with the breakdown voltage of the trench NFET in the area C is effected by setting a depth dT2 of the trenches of the trench sense cell smaller than a depth dT1 of the trenches of the trench NFET. In the case of trench FETs including field electrodes effecting charge compensation in the drift zone, this may be achieved by setting a width wT2 of the trenches of the trench sense cell D smaller than a width wT1 of trenches of the trench NFET, for example.
According to another embodiment, the trenches of the trench sense cell D may be completely filled with an insulating material, e.g., SiO2.
According to yet another embodiment, an optional shielding region of the first conductivity type is arranged within the drift zone and adjoins a bottom side of the trenches of the trench sense cell. The shielding region is schematically illustrated in FIG. 3 by a dashed line and may include a dose of p-type impurities in a range of 1×1012 cm−2 to 1×1013 cm−2, for example.
Yet another example of a design of a semiconductor device 400 is illustrated in simplified manner in the schematic cross-sectional view of FIG. 4. In FIG. 4, the semiconductor device 400 includes a cell array of a superjunction FET in a first area C and a superjunction sense cell in a second area D. The superjunction FET includes first p-doped compensation regions 431a, 431b formed within an n-doped drift zone 432. First p-doped body regions 433a, 433b adjoin a first side 435 and the first p-doped compensation regions 431a, 431b. First n+-type source regions 436a, 436b are arranged within the first p-doped body regions 433a, 433b and adjoin the first side 435. A first gate structure 434 is arranged on the first side 435.
The superjunction sense cell in the area D includes second p-doped compensation regions 441a, 441b formed within the n-doped drift zone 432. Second p-doped body regions 443a, 443b adjoin the first side 435 and the second p-doped compensation regions 441a, 441b. Second n+-type source regions 446a, 446b are arranged within the second p-doped body regions 443a, 443b and adjoin the first side 435. A gate structure 444 may be arranged on the first side 435.
A reduction of a breakdown voltage Vbr1 of the superjunction sense cell in the second area D compared with a breakdown voltage Vbr2 of the superjunction FET in the first area C may be achieved by adjusting lateral dimensions wp1, wn1, wp2, wn2 of the compensation regions and drift zones in the superjunction NFET and superjunction sense cell, for example. As an example, in a p-loaded superjunction FET wp1<wp2 or wn1>wn2 may be set. As a further example, in an n-loaded superjunction FET wp1>wp2 or wn1<wn2 may be set. As a further example for reducing a breakdown voltage Vbr1 of the superjunction sense cell in the second area D compared with a breakdown voltage Vbr2 of the superjunction FET in the first area C, a depth of the second p-doped compensation regions 441a, 441b may be set smaller than the depth of the p-doped compensation regions 431a, 431b. 
Although the specific embodiments described above included NFETs, the above-described teaching may also be applied to other semiconductor devices including planar DMOSFETs (Double-diffused MOSFETs) including non-compensated drift zones, lateral DMOSFETs and IGBTs. The FETs may also be formed as drain-up FETs.
FIG. 5 schematically illustrates one embodiment of a circuit diagram of a semiconductor device 500. The semiconductor device 500 includes a first semiconductor diode 501 including a first pn junction between a first cathode 502 and a first anode 503. The semiconductor device 500 further includes a second semiconductor diode 504 including a second pn junction between a second cathode 505 and a second anode 506.
The first and second semiconductor diodes 501, 504 are integrated monolithically in a semiconductor body (not illustrated in FIG. 5, cf. FIG. 6). The first and second cathodes 502, 505 are electrically coupled to a first device terminal 507. The first and second anodes 503, 506 are electrically coupled to a second device terminal 508. The second anode 506 is electrically coupled to the second device terminal 508 via an intervening element 509. A temperature coefficient α1 of a breakdown voltage Vbr1 of the first pn junction of the first semiconductor diode 501 and a temperature coefficient α2 of a breakdown voltage Vbr2 of the second pn junction of the second semiconductor diode 504 have a same algebraic sign and satisfy 0.6×α1<α2<1.1×α1 at T=300K, wherein Vbr2<Vbr1.
The semiconductor device 500 further includes an NFET 530. A drain of the NFET 530 is electrically coupled to the first device terminal 507. A source of the NFET is electrically coupled to the second device terminal 508. A gate of the NFET is electrically coupled to the anode 506 of the second diode 504.
When switching off an inductive load via NFET 530, an increase of a voltage between the first and second device terminals 507, 508 leads to a breakdown of the second semiconductor diode 504. The second semiconductor diode 504 may clamp the voltage between the first and second device terminals 507, 508 by acting as a voltage divider together with the intervening element in such a way that the NFET 530 is turned on to dissipate energy stored in the inductor that is switched off.
During electrostatic discharge between the first and second device terminal, the first semiconductor diode 501 absorbs most of the discharge current due to constraints in area and inner resistance of NFET 530. Thus, a voltage between device terminals 507 and 508 rises until the first semiconductor diode 501 absorbs the discharge current. Since the first and second semiconductor diodes 501, 504 are closely correlated with regard to their temperature coefficients α1, α2 and their breakdown voltages Vbr1 and Vbr2, a so-called ESD window, i.e. voltage range of operation of ESD protection element, can be increased while providing a safe operation of the device over an overall operation temperature range and/or an area consumption can be reduced.
FIG. 6 illustrates one embodiment of a cross-sectional view of the first and second semiconductor diodes 501, 504 of the semiconductor device 500 illustrated in FIG. 5. With regard to an interconnection between the first and second semiconductor diodes 501, 504, reference is made to the circuit diagram illustrated in FIG. 5.
The first semiconductor diode 501 includes an n+-doped buried layer 533a that is electrically coupled to a first cathode contact 534a at a front side 535 via an n+-doped sinker 537a. The n+-doped sinker 537a and the n+-doped buried layer 533a encompass an n−-doped layer 539a that may be a part of an epitaxial layer. The n−doped layer 539a encompasses a p-doped anode region 541a. The p-doped anode region 541a adjoins the front side 535 and is electrically coupled to an anode contact 536a. According to one embodiment, the p-doped anode region 541a includes a profile of p-type impurities having a sufficient concentration at the front side 535 that allows the forming of an ohmic contact to the anode contact 536a. Alternatively or in addition, a p+-doped anode contact zone may be provided within the p-doped anode region 541a at the front side 535.
Similar to the first diode 501, also the second diode includes an n+-doped buried layer 533b, an n+-doped sinker 537b, an n−-doped layer 539b, a p-doped anode region 541b, a second cathode contact 534b and a second anode contact 536b. The corresponding elements in the first and second diode are manufactured using the same process steps.
A breakdown voltage Vbr1 of the first diode 501 is set larger than a breakdown voltage Vbr2 of the second diode 504 by choosing different doses of p-type impurities in the p-doped anode regions 541a, 541b. According to one embodiment, an average sheet concentration of p-type impurities in the p-doped anode regions 541a, 541b may be set differently by using different mask apertures or arrays of different mask apertures when implanting these impurities in the respective regions. As an example, outdiffusion of impurities implanted through neighboring mask openings leads to an overlap impurity profiles. Enhanced outdiffusion will homogenize the profile along a lateral direction.
Although the first and second diodes 501, 504 illustrated in the example of FIG. 6 include the n+-doped buried layers 533a, 533b and the n+-doped sinkers 537a, 537b, the n+-doped sinkers 537a, 537b may also be omitted, e.g., in a lateral pn junction diode. Further, the n+-doped sinkers 537a, 537b may also be replaced by trenches that are at least partially filled with n+-doped semiconductor material, e.g. n+-doped polysilicon adjoining sidewalls of the trenches.
Since the first and second semiconductor diodes 501, 504 are closely correlated with regard to their breakdown voltages Vbr1, Vbr2 and temperature coefficients α1, α2 due to similar or same processing of the anode and cathode semiconductor regions, the so-called ESD window may be increased while providing a safe operation of the device over an overall operation temperature range.
Examples of p-type impurity profiles are illustrated in FIG. 7.
Referring to the schematic diagram illustrated in FIG. 7, according to a first example, a profile of concentration cp1 along a lateral direction x of line BB′ in the anode region 541b of the second diode 504 illustrated in FIG. 6 is constant, and a profile of concentration cp2 along the lateral direction x of line AA′ in the anode region 541a of the first diode 501 is corrugated and includes minima and maxima. The corrugated profile cp2 may be formed by implanting the p-type impurities via a mask having apertures above the anode regions 541b to be formed. The apertures may be arranged as a regular pattern of openings such as squares leading to a corresponding regular pattern of maxima in the profile cp2. The pattern of maxima is in an area parallel to the front side 535.
According to another example, a profile cp3 along the lateral direction x of line BB′ in the anode region 541b of the second diode 504 is corrugated and includes minima and maxima. In this example, cp3>cp2 holds to set Vbr1>Vbr2.
According to yet another example, Vbr1>Vbr2 may also be set by implanting a first p-type impurity dose into both the first and second anode regions and a second p-type impurity dose into only the second anode region or a smaller n-type impurity dose only into the first anode region.
Examples of setting Vbr1>Vbr2 in the device illustrated in FIG. 5 were explained above. Further examples include setting different doses of p- or n-type impurities not only in the anode region but in the anode region and cathode region or merely in the cathode region.
As an example, these doses may be set accordingly such that the relation 0<(Vbr1−Vbr2)/Vbr1<0.2 holds.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

## Claims

1. A semiconductor device, comprising:
a first semiconductor element including a first pn junction between a first terminal and a second terminal;
a second semiconductor element including a second pn junction between a third terminal and a fourth terminal;
a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated; and wherein
the first and third terminals are electrically coupled to a first device terminal;
the second and fourth terminals are electrically coupled to a second device terminal; and
a temperature coefficient α1 of a breakdown voltage Vbr1 of the first pn junction and a temperature coefficient α2 of a breakdown voltage Vbr2 of the second pn junction have a same algebraic sign and satisfy 0.6×α1<α2<1.1×α1 at T=300K, wherein Vbr2<Vbr1.

2. The semiconductor device of claim 1, wherein
the first semiconductor element is a trench field effect transistor cell and the first pn junction includes a first body region of a first conductivity type and a first drift region of a second conductivity type different from the first conductivity type;
the first body region adjoins a first trench structure at a first side of the first body region and the first body region adjoins a second trench structure at a second side of the first body region opposite to the first side;
the second semiconductor element is a sense cell and the second pn junction includes a second body region of the first conductivity type and a second drift region of the second conductivity type; and
the second body region adjoins a third trench structure at a first side of the second body region and the second body region adjoins a fourth trench structure at a second side of the second body region opposite to the first side.

3. The semiconductor device of claim 2, wherein the second body region is electrically coupled to a gate electrode of at least one of the first and second trench structures.

4. The semiconductor device of claim 2, wherein a difference between the first breakdown voltage Vbr1 of the first pn junction and the second breakdown voltage Vbr2 of the second pn junction is in a range between 50% to 600% of a threshold voltage of the trench field effect transistor.

5. The semiconductor device of claim 2, wherein each one of the first and second trench structures includes a trench that is filled with an insulating material.

6. The semiconductor device of claim 2, wherein a width of the first body region is larger than the width of the second body region.

7. The semiconductor device of claim 2, wherein a width of the first body region is smaller than the width of the second body region.

8. The semiconductor device of claim 2, wherein a depth of each one of the first and second trench structures is smaller than a depth of each one of the third and fourth trench structures.

9. The semiconductor device of claim 2, wherein a width of each one of the first and second trench structures is smaller than a width of each one of the third and fourth trench structures.

10. The semiconductor device of claim 2, wherein a depth of each one of the first and second trench structures is larger than a depth of each one of the third and fourth trench structures.

11. The semiconductor device of claim 2, wherein a width of each one of the first and second trench structures is larger than a width of each one of the third and fourth trench structures.

12. The semiconductor device of claim 2, further comprising a shielding region of the first conductivity type that is arranged within the drift region and adjoins a bottom side of each one of the third and fourth trench structures.

13. The semiconductor device of claim 2, wherein a first distance between a bottom side of the first body region to a top side of the first body region at a surface of a semiconductor body of the first and second semiconductor elements is smaller than a second distance between a bottom side of the second body region to a top side of the second body region at the surface of the semiconductor body.

14. The semiconductor device of claim 2, wherein
a trench field effect transistor cell array includes a first plurality of the field effect transistor cells;
a second plurality of the sense cells is spread over an area of the trench field effect transistor cell array; and
the first plurality is larger than the second plurality.

15. The semiconductor device of claim 2, wherein
each one of the first and second trench structures includes a gate electrode and at least one field electrode that is arranged below the gate electrode; and further comprising
an electric insulator between the gate electrode and the at least one field electrode.

16. The semiconductor device of claim 1, wherein
the first semiconductor element is a superjunction array cell and the first pn junction includes a first p-type pillar region and a first n-type pillar region;
the second semiconductor element is a superjunction sense cell and the second pn junction includes a second p-type pillar region and a second n-type pillar region; and wherein
the first and the second semiconductor elements differ in at least one of a lateral dimension of their p-type pillar region and their n-type pillar region.

17. The semiconductor device of claim 1, wherein
the first semiconductor element is a transistor cell and the first pn junction includes a first body region of a first conductivity type and a first drift region of a second conductivity type different from the first conductivity type;
the second semiconductor element is a sense cell and the second pn junction includes a second body region of the first conductivity type and a second drift region of the second conductivity type; and wherein
a first distance between a bottom side of the first body region to a top side of the first body region at a surface of a semiconductor body of the first and second semiconductor elements is smaller than a second distance between a bottom side of the second body region to a top side of the second body region at the surface of the semiconductor body.

18. The semiconductor device of claim 1, wherein
the first semiconductor element is a transistor cell and the first pn junction includes a first body region of a first conductivity type and a first drift region of a second conductivity type different from the first conductivity type;
the second semiconductor element is a sense cell and the second pn junction includes a second body region of the first conductivity type and a second drift region of the second conductivity type; and wherein
a width of the first body region differs from a width of the second body region.

19. The semiconductor device of claim 1, wherein
the first semiconductor element is a first diode and the first pn junction includes a first anode region of a first conductivity type and a first cathode region of a second conductivity type different from the first conductivity type; and
the second semiconductor element is a second diode and the second pn junction includes a second anode region of the first conductivity type and a second cathode region of the second conductivity type.

20. The semiconductor device of claim 19, further comprising
a transistor including a first load terminal, a second load terminal and a control terminal; and wherein
the first and second load terminals of the transistor and the first semiconductor element are connected in parallel.

21. The semiconductor device of claim 20, wherein
the transistor is an n-type field effect transistor;
the first load terminal is a drain;
the second load terminal is a source;
the control terminal is a gate; and
the second anode region is electrically coupled to the gate.

22. The semiconductor device of claim 19, wherein the first breakdown voltage Vbr1 of the first pn junction and the second breakdown voltage Vbr2 of the second pn junction satisfy 0<(Vbr1−Vbr2)/Vbr1<0.2.

23. The semiconductor device of claim 19, wherein
the first anode region includes a first p-type impurity and the second anode region includes the first p-type impurity; and
the first cathode region includes a first n-type impurity and the second cathode region includes the first n-type impurity; and wherein
a lateral concentration profile of at least one of the first p-type impurity in the first anode region, the first p-type impurity in the second anode region, the first n-type impurity in the first cathode region, and the first n-type impurity in the second cathode region is corrugated and includes maxima and minima.

24. The semiconductor device of claim 19, wherein
the second semiconductor diode includes at least one of
a second p-type impurity in the second anode region that is absent in the first anode region, or
a second n-type impurity in the second cathode region that is absent in the first cathode region.

25. The semiconductor device of claim 19, wherein
the first diode is an electrostatic discharge protection device including an anode area of at least 4000 μm2.