Janis M. Niedra

QSS Group, Inc., Cleveland, Ohio

Junction-to-Case Thermal Resistance of a Silicon

Carbide Bipolar Junction Transistor Measured

NASA/CR—2006-214258

November 2006
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NASA/CR—2006-214258

November 2006

National Aeronautics and

Space Administration

Glenn Research Center

Cleveland, Ohio 44135

Prepared under Contract NAS3–00145

Janis M. Niedra

QSS Group, Inc., Cleveland, Ohio

Junction-to-Case Thermal Resistance of a Silicon

Carbide Bipolar Junction Transistor Measured
Acknowledgments

This work was sponsored by the NASA Glenn Research Center under NAS3–00145,

with G.E. Schwarze as the Project Manager.

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Level of Review: This material has been technically reviewed by expert reviewer(s).
NASA/CR—2006-214258 1

Junction-to-Case Thermal Resistance of a Silicon 

Carbide Bipolar Junction Transistor Measured 

Janis M. Niedra 

QSS Group, Inc. 

Cleveland, Ohio 44135 

Abstract 

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by 

using the base-emitter voltage (VBE) characteristic for thermometry. The VBE was measured as a function 

of the base current (IB) at selected temperatures (T), all at a fixed collector current (IC) and under very low 

duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be 

the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat 

the chip, but same IC pulse height, the chip temperature was identified by matching the VBE to the 

thermometry curves. From the measured average power, the chip-to-case thermal resistance could be 

estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing 

temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut 

analysis, however, does not support this. 

Source of the Problem 

Intelligent use of a transistor in power management applications requires control of its junction 

temperature to some specified limits. The commonly specified thermal conductivity, junction to case, is 

not always available for packaged experimental or prototype devices obtained from R&D laboratories. 

Packaging obviously prevents the direct observation of the semiconductor chip. The sole recourse then is 

to find a terminal electrical property that can be exploited for thermometry. This paper reports an attempt 

to estimate the thermal resistance of a packaged SiC based BJT, from observations of electrical 

characteristics under low and high duty cycle power switching. 

Procedure Explained 

The regulation or switching of collector current, IC, to a load is the most direct way of setting the 

temperature rise of the chip above its case. And the case is assumed mounted to a temperature-controlled 

heat sink. The base-to-emitter junction voltage, VBE, depends on the base current, IB, and the junction 

temperature T. And so VBE(IB, T) and IC are two elements on which the temperature rise thermometry can 

be based. But of course there are complications. 

A key realization is that external measurements at the base and emitter leads include bulk voltage 

drops in the chip added to the junction voltage. Ohmic drops due to the flow of IC can be both significant 

as compared to the junction VBE as well as temperature dependent in doped SiC. In SiC, usually the 

dopant atoms are not fully ionized at room temperature, leading to a significant temperature dependence 

of bulk electrical resistivity as the temperature is raised. And there may be other temperature 

dependencies. Therefore our VBE thermometer must be calibrated taking IC into account. And this IC must 

have the same pulse height as will be finally used in a higher duty cycle mode to heat the chip internally. 

At room and selected higher case temperatures, as set by an external heater, the external VBE is plotted 

against IB, in a very low duty cycle pulse mode. The IC is set to a fixed pulse height that is representative 

of practical application of the particular BJT, by say a resistive load and a dc power supply. And the IB
NASA/CR—2006-214258 2

pulses should be kept sufficiently high to ensure saturated switching of the BJT and just long enough to 

get steady VBE and IB readings. If properly done, internal heating of the chip then should be negligible. 

The so generated thermometry curves can be used to obtain an estimate of the junction-to-case 

thermal resistance. The duty cycle now has to be substantially increased to get a measurable increase of 

the steady state chip temperature above that of the heat-sunk case, while maintaining the same IC pulse 

height. Comparison of the VBE pulse height with that of the calibration curves then gives the temperature. 

The thermal resistance then follows from the known case temperature and the average power loss in the 

chip shown by the displayed waveforms. 

Basic Experiment 

All thermometry work was done with variations of the circuit shown in figure 1. This circuit was built 

primarily for establishing a turn-off transient that is as rapid as the turn-on transient, but modifications 

worked well also for thermometry. 

Figure 1.—This switching speed test circuit was used for 

thermometry calibration work. In the higher duty cycle, chip 

heating case, the negative pulser and its 50 Ω load resistor 

were simply replaced by a dc power supply. Also at higher 

duty cycle, other resistors were varied to reduce their 

dissipation. The positive pulser provides the constant pulse 

height IB. 

BNC 555 

delay

generator 

Ch. B 

HV-1000N 

neg. pulser 

50 Ω

240 Ω

(~6 V)

1N5819 

40 V, 1 A Schottky

HV-1000 

pos. pulser 

470 Ω

Ch. A 50 Ω

 + 

100 Ω

+

IC

IB

+ VB

BJT
NASA/CR—2006-214258 3

Temperature calibration data are shown in figure 2 below for a 4 A, 600 V rated SiC BJT made by 

United Silicon Carbide, Inc., and labeled P2. The decrease of VBE with increasing T at constant IB is 

equivalent to the usual shifting to the left of the I vs. V curves for say silicon P-N junction diodes, with 

the I-axis drawn vertically. But the curve bunching seen in figure 2 is not usual. However, in SiC devices 

the dopants are usually not fully ionized at room temperature. Hence as the temperature is raised, the 

degree of ionization increases and the body resistance drops. And the terminally measured VBE includes 

the resistive drop due to IC, which thus decreases with increasing temperature until the dopants are fully 

ionized. The degree of ionization also plays a more subtle effect through the complicated physics of the 

so-called reverse saturation current I0 in the diode equation. In fact, the simple diode equation, when 

solved for the junction voltage in the form 

 V = (κ T/q) ln[(I/I0) + 1], (1) 

can be misleading as to temperature effects, because the complicated T-dependence of I0 is not manifest. 

Being an aside, details of the mechanism that can (and usually do) generate a negative ∂V/∂T in the diode 

equation are ferreted out in appendix A. The bunching of the curves seen in figure 2 is not, however, 

predicted there. This bunching is in any case undesirable, as it reduces temperature resolution and here 

especially in the region of interest around 200 °C. 

The P2 device was next mounted to a temperature controlled heat sink plate and set up to switch a 

pulsed 3 A current into a 100 Ω non-inductive load resistor that was also mounted to the same heat sink. 

Pulses of about 640 ns were spaced 5 μs, making a duty cycle of 0.13. The combined heat from the load 

200 250 300 350 400

I

b (mA)

5

6

7

8

9

10

11

Vbe (V)

T = 23 C

T = 100 C

T = 150 C

T = 200 C

USC SiC BJT, P2

Ic = 3.0 A

Figure 2.—Temperature dependence of the VBE versus IB curves. The duty cycle here is 

sufficiently low such that the chip and case temperatures are practically identical. 
NASA/CR—2006-214258 4

resistor and the transistor caused the temperature of the heat sink to slowly rise. When the VBE pulse 

height matched the VBE of the 100 °C calibration curve (see fig. 2), waveforms were recorded, plate 

temperature (80 °C) was noted and operation ceased. Hence the case-to-chip temperature rise was then 

20 °C. 

Various scope measurements could then be done on the recorded traces. The exponential rise-time for 

the IC was τon = 68.3 ns and the linearly approximated fall-time was τoff = 134 ns. The formulas giving the 

energy loss in these approximations are 

 Eon = (1/2) V0 I0 τon (exponential approximation) 

and 

 Eoff = (1/6) V0 I0 τoff (linear approximation), 

where V0 and I0 (= IC) are the switched voltage and current. The arithmetic then gives Eon = 3.16×10−5 J 

and Eoff = 2.07x10−5

 J. According to the scope measurement, the on-state VCE was only 0.4 V, whereas 

according to the static characteristics of the P2, about 4 V was expected at 100 °C and 3 A. Using the 

scope measurement, the conduction loss is only 7.6×10−7

 J, which is quite small compared to the 

switching loss. The base-drive energy was also small, being about 0.15×10−5

 J. Finally, adding all losses 

and dividing by the 5 μs period gives an average power of 11 W into the chip. 

The junction-to-case thermal resistance RθJC is thus about 20/11 = 1.8 °C/W. This is somewhat lower 

than that of a roughly comparable silicon BJT, such as the planar BUH50 (50 W, 800 V, 4 A). But such a 

comparison can only be very rough, because the P2 has no given power rating. Nevertheless, the value of 

the thermal resistance obtained appears to be reasonable and gives some confidence in the method. 

Final Remarks 

The initial experimental evidence supports the feasibility of the presented method of temperature rise 

thermometry. But it also points out the problem of curve bunching and consequent loss of temperature 

resolution seen in figure 2. The root cause in the described experiment appears to be the increase in body 

conductivity as more dopants in SiC (especially the acceptors) become ionized with increasing 

temperature. This problem may be a characteristic of a material, such as SiC, whose commonly used 

dopant atoms are not fully ionized at room temperature. However, a workaround may be possible by 

using pulse control methods.. 

Alternative Schemes 

In a modified procedure, consider generating the low duty cycle, calibration curve set (fig. 2.) with 

the collector lead open. Making IC = 0 hopefully should reduce the nonlinear bunching with increasing T 

of the VBE versus IB curves, if dopant ionization is at the heart of the matter. The general idea is to use 

higher duty cycle pulses of IC to substantially heat the chip, but measure a steady VBE and IB while IC = 0. 

For example, after a sufficient number of base drive pulses to cause a substantial temperature rise of the 

chip, the collector power supply could be effectively disconnected, for the duration of one base pulse or 

one period. This would be a matter of pulse control logic. A scheme might utilize a commercially 

available high voltage pulser for the collector supply, with base drive applied continuously or pulsed in a 

synchronism. Values of VBE and IB could be measured during the IC dead time. In all such schemes, a fastrecovery diode (GaAs, Schottky) is needed in the collector lead to block current flow in the base-tocollector direction. 
NASA/CR—2006-214258 5

Conduction and Switching Losses 

Occasionally the concern has been voiced that higher on-state conduction losses in a SiC based, as 

compared to a Si based, BJTs would be seriously adverse to their application as switches. The present 

example of the P2 device, however, shows that this is circumstantial and not always so. Therefore, let us 

look a little closer at the comparison of conduction losses to switching losses expected for a waveform of 

essentially square pulses of width w, repeated with a period τ. The duty cycle D then is D = w/τ. Let the 

switched voltage and current be V0 and I0. 

Approximating both turn-on and turn-off by the same exponential function, the total switching loss in 

one period then is 

 ES = V0 I0 τs , 

where the exponential switching time constant τs is related to the usual scope measured 10 to 90 percent 

switching time τs,10-90 by τs = τs,10-90/ln 9. The conduction loss in one period is simply 

 EC = I0

2

 RCE,on w , 

where RCE,on is the collector-to emitter on-resistance, mimicking MOSFET terminology. Division of ES

and EC by τ then gives the average switching and conduction loss powers PS and PC. The ratio of these 

powers thus is 

 PC/PS = EC/ES = I0 RCE,on w/(V0 τs) . 

To get a numerical feel, assume a switching frequency of 200 kHz and a duty cycle of 0.5, giving 

w = 2.5 μs. The τs,10-90 is not likely to be significantly less than 50 ns even for SiC power BJTs, giving τ

s = 23 ns. At least for the P2 device, the RCE,on was observed to be about 1.5 Ω at room temperature on a 

static curve tracer, but appeared to be less under fast pulse conditions. 3 A is about the rated current for 

this device, but operation at 300 V is at about 1⁄2 of the rated voltage. With these values, PC/PS = 1.6. But 

operation at higher frequency (smaller w) and higher voltage is clearly possible for this device and 

τs,10-90 = 50 ns is likely to be on the short side. Hence the evidence shown here does not support the claim 

of necessarily unacceptably high conduction losses in SiC based BJTs. 

NASA/CR—2006-214258 7

Appendix A 

Temperature Dependences in the Diode Equation Applied to SiC 

The usual observed decrease of V with increasing T at constant I means that in the simplest p-n 

junction diode modeling equation, i.e., Eq. (1), the so-called reverse saturation current I0 must have a 

T-dependence of at least exponential order. We shall review here this dependence, pointing out the source 

of the usually negative (∂V/∂T)|I and the effect of dopant degree of ionization. A caveat is that Eq. (1) 

may be inadequate if there is significant recombination in the depletion region, in which case additional 

terms are required. 

A standard form for I0, written in terms of the electron and hole diffusion constants, minority carrier 

diffusion lengths, intrinsic carrier density and the ionized dopant densities, is 

⎥

⎥

⎦

⎤

⎢

⎢

⎣

⎡ = + − + P D

2

P i

N A

2

N i

0 L N

D n

L N

D n

I (A1) q A

The above I0 can be put in more fundamental terms such as the temperature, electron and hole 

mobilities, densities and effective masses, and minority carrier lifetimes and the band gap energy. Use is 

made of the Einstein relation and standard textbook formulas [1] for ni, etc., to finally give 

( ) ( ) ( ) κT

E

7/2

1/2

p

p 1

1/2

n

3/2 1 n n p

1/2 6 3

0

g

κT e

τ

μ

n

τ

μ I 4Aq h 2π m m p − − ∗ ∗ − −

⎥

⎥

⎦

⎤

⎢

⎢

⎣

⎡

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

+ ⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛ = , (A2) 

where A is the junction area, q is the magnitude of the electronic charge, − p and = NA + = ND n . In the case 

of an NPN transistor, the emitter region will be more heavily doped than the base and so the n−1

 in the 

bracket can be neglected. 

Some of the terms in the above expressions can vary widely, even in Si. The lifetimes are sensitive to 

temperature and the presence of recombination centers. The mobilities vary as T−α, where 2<α<2.5. The 

effective masses are not particularly temperature sensitive. Unlike in Si, the dopants used in SiC are far 

from being fully ionized at room temperature and hence their degree of ionization must be calculated 

from their positions in the bandgap and the temperature. The following values have been suggested [2]: 

mn* = 0.5 m0 τn = 100 ns μn = 900 cm2

V−1s

−1

 NA ≈ 3×1017 cm−3

mp* = 0.3 m0 τp = 100 ns μp = 90 cm2

V−1s

−1

 J ≈ 500 A/cm2

EC – ED = 0.05 eV EA – EV = 0.25 eV 

In spite of uncertainties, a rough estimate for SiC of the terms in Eq. (A1) or Eq. (A2) can be obtained. 

Let us write I0 in the form 

( ) κT

E

0

g

I Af T e

− = , (A3) 

where the function f is defined by 
NASA/CR—2006-214258 8

() ( ) ( ) ( )7 / 2

1/ 2

p

p 1

1/ 2

n

3/ 2 1 n n p

1/ 2 6 3 f T 4q h 2 m m p n κT ⎥

⎥

⎦

⎤

⎢

⎢

⎣

⎡

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

τ

μ

+ ⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

τ

μ = π − ∗ ∗ − − . (A4) 

and the mobilities, lifetimes and carrier densities are functions of T. 

The most temperature-sensitive terms in Eq. (A4) are assumed to be the p and n, as the degree of 

ionization involves an exponential dependence on T. Finding only the p is sufficient here, since the 

emitter is assumed to be heavily doped and the donors sit much shallower in energy. The ionization 

formula is developed in reference 3, the result for acceptors being 

⎥

⎥

⎦

⎤

⎢

⎢

⎣

⎡

− ⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛ = +

ζ

ζ 1 N

4 N 1

2

N

p

1/ 2

A , (A5) 

where 

( ) T

E

3 / 2 2

p D

A

2 m T / h e

g

2 N κ

Δ− ∗ ζ = π κ , (A6) 

and the degeneracy factor gD is usually set to 2. If NA>>Nζ, such when nearing carrier freeze-out, then 

p ≈ (NA Nζ)

1/2 is a good approximation. Thus at 300 K, where Nζ = 1.39×1014, only p = 6.46×1015 cm−3

out of the 3×1017 cm−3

 acceptors are ionized, compared to p = 5.80×1016 cm−3 at 500 K. The 

corresponding change in body resistivity is obviously quite large. 

For any reasonable forward current, the “1” in Eq. (1) can be neglected and hence Eq. (1) can be 

written in the form 

 qV = Eg + κ T ln[J/f(T)] , (A7) 

where J = I/A is the current density and Eg is the band gap (about 3 eV in SiC). From this follows the 

sensitivity 

 (∂V/∂T)|J = (κ/q) [ln(J/f) − (T/f) (df/dT)] , (A8) 

of the junction voltage to temperature. 

A rough estimate in SiC shows that at room temperature, the value of J/f(T) is considerably below 

unity, making ln[J/f(T)] negative. Indeed, f(300) ≈ 1.4×107

A/cm2, giving (κ/q)ln(J/f) ≈ −8.8×10−4 V/K, 

which is much below the roughly –1.3×10−2

 V/K observed. Moreover, the uncertainties in mobilities, 

lifetimes and ionized dopant densities seem insufficient to correct for this discrepancy. 

Let us ferret out more systematically the main T-dependences hidden in the function f and 

contributing via the df/dT. The simplest such in Eq. (A4) is some power of T. Besides the manifest T7/2, 

the mobilities too have been modeled as proportional to T−2.3. The contribution to (∂V/∂T)|J in Eq. (A8) 

from total power law Tα

 proportionality in f is 

8.61x10 (V / K) q ) T

(T )

(T )

f ( q f

T

α=− 5α κ = − ∂

∂

∂

κ ∂ − − α

α . (A9) 
NASA/CR—2006-214258 9

But from Eq. (A4) and the above remarks, α ~ 1 and surely below 10. Hence this contribution is rather 

small and constant. 

The exponential T-dependence of p seems likely to contribute more. Its complications are best ironed 

out step by step. After some tedious algebra, one finds that 

⎥

⎥

⎥

⎥

⎥

⎥

⎦

⎤

⎢

⎢

⎢

⎢

⎢

⎢

⎣

⎡

−

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

+

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

+

∂

∂ = ∂

∂

ζ

ζ ζ 1

N

N 1 4

N

N 1 2

T

N

2

1

T

p

1/ 2

A

A

 (A10) 

and also that 

ζ ζ ⎟

⎠

⎞ ⎜

⎝

⎛

κ

Δ = + ∂

∂

N T

E

2

3

T

1

T

N A , (A11) 

where ΔEA ≡ EA – EV. Again in the case of NA>>Nζ, which is applicable here at 300 K, 

( ) ⎟

⎠

⎞ ⎜

⎝

⎛

κ

Δ ⎟ ≈ + ⎠

⎞ ⎜

⎝

⎛

κ

Δ ≈ +

∂

∂

ζ T

E

2

3

2T

p N N T

E

2

3

2T

1

T

p 1/ 2 A

A

A . (A12) 

Using the above results, the contribution to (∂V/∂T)|J arising from ∂p/∂T is found to be 

⎟

⎠

⎞ ⎜

⎝

⎛

κ

Δ + κ ≈⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

∂

∂ ⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛ κ =⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

∂

∂

∂

κ ∂ − T

E

2

3

T 2q

p

p

f

q f

T

T

p

p

f

qf

T A , (A13) 

within the approximation based on NA>>Nζ. At 300 K, the value of this positive contribution is 4.79×10−4

V/K. 

For general interest, the above contributions can be totaled. Omitting considerable algebra, the final 

form is 

( ) ⎪⎭

⎪

⎬

⎫

⎪⎩

⎪

⎨

⎧

⎥

⎥

⎦

⎤

⎢

⎢

⎣

⎡

κ −α+ κ ⎟ = ⎠

⎞ ⎜

⎝

⎛

∂

∂

11/ 4

J C0 T

J ln 43

T q

V , (A14) 

where 

()()

1/ 2

n

3 / 4 n p3 / 2

n 1/ 2

A

1/ 2 9 / 2 D 9 / 4 C0 2(2 ) g q h N m m ⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

τ

μ ≡ π − − ∗ ∗ . (A15) 

For the given numerical values (and gD = 2), C0 = 1.28×1065 A m−2 (Joule)−11/4. At K = 300, and 

J = 500 A/cm2

, (∂V/∂T)|J = 8.61×10−5 [3/4 − α +ln(4.36×10−3)] V/K = 8.61×10−5 (3/4 − α −5.44) V/K. 

This diode equation based analysis applied to SiC predicts that (∂V/∂T)|J is, with high confidence, 

negative and increasing in magnitude with increasing temperature at room temperature. It provides no 

support for the curve bunching seen in figure 2. 
NASA/CR—2006-214258 10

Worth a passing note is the absence of ΔEA in Eq. (A14). This is actually apparent from the outset 

from Eqs. (A7), (A4) and (A6), whenever p ≈ (NA Nζ)

1/2 is a valid approximation. The κTln operation in 

Eq.(A7) then reduces the 2 T

EA

e κ

Δ− factor, arising from Eq.(A6), to −ΔEA/2, which contributes zero to 

(∂V/∂T)|J. The band gap factor T

Eg

e κ

− appearing in Eq.(A2) suffers a similar fate. The fact that Eg and ΔEA

may themselves have a temperature dependence was simply ignored here. 
NASA/CR—2006-214258 11

References 

1. G.W. Neudeck, The PN Junction Diode, Modular Series on Solid State Devices, vol. II, G.W. 

Neudeck and R.F. Pierret, editors, Addison-Wesley, 1983. 

2. Dr. Philip G. Neudeck, NASA Glenn Research Center, private communication. 

3. R.F. Pierret, Advanced Semiconductor Fundamentals, Modular Series on Solid State 

Devices, vol. VI, G.W. Neudeck and R.F. Pierret, editors, Addison-Wesley, 1983. 
This publication is available from the NASA Center for AeroSpace Information, 301–621–0390.

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16

Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction

Transistor Measured

Janis M. Niedra

SiC bipolar junction transistor; Junction temperature; VBE thermometry; Switching losses;

Pulse techniques

Unclassified -Unlimited

Subject Category: 33

QSS Group, Inc.

21000 Brookpark Road

Cleveland, Ohio 44135

Project Manager, Gene E. Schwarze, Power and Propulsion Division, NASA Glenn Research Center, organization

code RPE, 216–433–6117.

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter

voltage (VBE) characteristic for thermometry. The VBE was measured as a function of the base current (IB) at selected

temperatures (T), all at a fixed collector current (IC) and under very low duty cycle pulse conditions. Under such

conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At

increased duty cycle such as to substantially heat the chip, but same IC pulse height, the chip temperature was identified

by matching the VBE to the thermometry curves. From the measured average power, the chip-to-case thermal resistance

could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing

temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however,

does not support this.