# Patent

## Title
Digital-to-analog converter, data driver and display device using same

## Abstract

A digital-to-analog converter including includes a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n−1:2n−2: . . . :20, from an output terminal.

## Background
FIELD OF THE INVENTION
This invention relates to a digital-to-analog converter and to a data driver and display device that employ this converter.
BACKGROUND OF THE INVENTION
Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that rely upon active matrix drive and are capable of presenting a high-definition display are being utilized as these liquid crystal display devices. The typical structure of an active-matrix liquid crystal display device will be described with reference to FIG. 37. The principal components connected to one pixel of a liquid crystal display unit are illustrated schematically by equivalent circuits in FIG. 37.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 966 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other.
The TFT 963, which has a switching function, is turned on and off under the control of a scan signal. When the TFT 963 turns on, a grayscale voltage that corresponds to a video signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes owing to a potential difference between each pixel electrode 964 and opposing-substrate electrode 966. This potential difference is held by capacitance 965 of the liquid crystal, as a result of which an image is displayed.
A data line 962 that sends a plurality of level voltages (grayscale voltages) applied to each pixel electrode 964 and a scan line 961 that sends the scan signal are wired on the semiconductor substrate in the form of a grid (the data lines are 1280×3 in number and the scan lines are 1024 in number in the case of the above-mentioned color SXGA panel). The scan line 961 and data line 962 constitute a large capacitive load owing to the capacitance produced at the intersection of these lines and capacitance, etc., of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scan signal is supplied to the scan line 961 by a gate driver 970, and that the supply of grayscale voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), data is selected successively every pixel row (every line) by each scan line, and a grayscale voltage is supplied from each data line within the selection interval.
Although the gate driver 970 need only supply at least a bi-level scan signal, it is required that the data driver 980 drive the data lines by grayscale voltages of multiple levels that conform to the number of gray levels. To this end, a buffer in the data driver 980 employs a differential amplifier that is capable of outputting highly precise voltages.
With the progress that has been made in raising image quality (increasing the number of colors) in liquid crystal display devices, there is now growing demand for at least 260,000 colors (video data of six bits per each of the colors R, G, B) and preferably 16,770,000 colors (video data of six bits per each of the colors R, G, B) or more.
For this reason, a data driver that outputs a grayscale voltage corresponding to multiple-bit video data requires an output voltage of very high precision. Moreover, there is an increase in the number of elements in the circuitry that processes the video data and an increase in the chip area of the data-driver LSI chip. These invite an increase in cost. This problem will be elaborated below.
FIG. 38 is a diagram illustrating an example of the configuration of the data driver 980 shown in FIG. 37. Here the main portions of the data driver 980 are depicted as blocks. As shown in FIG. 38, the data driver 980 includes a latch address selector 981, a latch 982, a grayscale voltage generating circuit 983, decoders 984 and buffer circuits 985.
The latch address selector 981 decides data latch timing based upon a clock signal CLK. The latch 982 latches video digital data based upon the data latch timing and outputs data to each of the decoders 984 all at once in response to an STB (strobe) signal. The grayscale voltage generating circuit 983 generates grayscale voltages the number of levels whereof corresponds to the video data. The decoders 984 each select and output one grayscale voltage that corresponds to the data input thereto, and the buffer circuits 985, to which the grayscale voltages output from the decoders 984 are applied, subject these voltages to current amplification and output the results as output voltage Vout.
By way of example, if 6-bit video data is input, the number of levels is 64 and the grayscale voltage generating circuit 983 generates grayscale voltages having 64 levels. The decoders 984 select one grayscale voltage from these grayscale voltages of 64 levels.
If 8-bit video data is input, on the other hand, then the number of levels is 256, the grayscale voltage generating circuit 983 generates grayscale voltages having 256 levels and the decoders select one grayscale voltage from these grayscale voltages of 256 levels.
Thus, an increase in the number of bits of video data is accompanied by an increase in the scale of the circuitry of the grayscale voltage generating circuit 983 and decoders 984. For example, if the number of bits is increased from six to eight, the scale of the circuitry increases by four times or more. Accordingly, an increase in the number of bits of video data increases the chip area of the data driver LSI chip and raises cost.
A charge redistribution DAC (digital-analog converter) of the kind shown in FIG. 39 (see Yoshiyuki Takeishi, Edited by Hisashi Hara, “Foundations of MOS Integrated Circuits”, Ultra LSI Introduction Series 5, p. 164, FIG. 5-39, Kindai Kagakusha, May 30, 2002) Non-Patent Document 1) is known as an example of technology for suppressing an increase in the chip area of a data driver LSI chip even if the number of bits is increased. As shown in FIG. 39, the DAC (which is a DAC of the type having a capacitor array and a resistor string) comprises a resistor string; switches S01a to S16a and S01b to S16b that select voltages, which have been extracted from the taps of the resistor string, by higher-order bits (D4 to D7) and supplying the selected voltages to terminals Na and Nb; a switch Sinit that initializes the voltage at a non-inverting input (+) of a voltage follower; and a switch SLSB that selects any one of the voltages that have been supplied to the terminals Na and Nb by lower-order bits (D0 to D3) and supplies selected voltages to four capacitors C/8, C/4, C/2 and C.
In terms of operation of the DAC, two mutually adjacent voltages are selected from among voltages V000, V016, . . . , and V256 of the resistor string by the higher-order bits (D4 to D7) and are supplied to the terminals Na and Nb. By turning on the switch Sinit and connecting switches Sse10 to Sse13 to the Na side, the voltage at a node (Nc) of the non-inverting input side of the voltage follower is initialized to the voltage at terminal Na and the respective terminal voltages across the four capacitors C/8, C/4, C/2 and C are reset.
Next, when the voltages at the terminals Na and Nb are selectively supplied to the four capacitors C/8, C/4, C/2 and C by the lower-order bits (D0 to D3), redistribution of electric charge occurs, a voltage that is the result of the voltage between the voltage at terminal Na and the voltage at terminal Nb being divided by 16 is supplied to the node Nc and a voltage that is the same as that at node Nc is output by the voltage follower. Accordingly, owing to the selection of two mutually adjacent voltages by the higher-order bits and division by 16 by means of the lower-order bits, outputs having 16×16=256 levels can be obtained.
In accordance with the conventional art, the number of reference voltages from the resistor string can be reduced in comparison with the number of output voltage levels. More specifically, if we let m represent the number of reference voltages and n the number of capacitors, then (m−1)×2n outputs can be obtained.
By applying this technique to the grayscale voltage generating circuit 983, decoders 984 and amplifiers 985, therefore, the area of the data driver can be reduced and a reduction in cost achieved.
[Non-Patent Document 1]
Yoshiyuki Takeishi, Edited by Hisashi Hara, “Foundations of MOS Integrated Circuits”, Ultra LSI Introduction Series 5, p. 164, FIG. 5-39, Kindai Kagakusha, May 30, 2002
SUMMARY OF THE DISCLOSURE
In accordance with the conventional art described above with reference to FIG. 39, the more the value of n, i.e., the number of capacitors, is increased, the larger the number of outputs that can be obtained with respect to a small number of reference voltages. In this example of the conventional art, however, the capacitors for performing charge redistribution require twice the capacitance value as the order of the bits rises. For example, if n=4, holds, an eight-fold (23=8) capacitance value is required for C/8, C/4, C/2 and C. If n is increased, therefore, the area occupied by the capacitors becomes very large and the effect of reducing area diminishes.
Accordingly, an object of the present invention is to provide a digital-to-analog converter that is equipped with an amplifier that outputs mn multivalued voltage levels with respect to m input voltages, thereby reducing the number of input voltages required while keeping the area occupied by an amplifier small, and reducing the number of transistors.
Another object of the present invention is to provide a small-area, low-cost data driver and a display device that includes this data driver by using the digital-to-analog converter described above.
According to one aspect of the present invention, the foregoing objects are attained by providing a digital-to-analog converter comprising: a reference voltage generating circuit for outputting m (m>=4) reference voltages having voltage values that differ from one another; a decoder, which receives a digital signal and the m reference voltages, and selects and outputs n (n>=3) identical or different reference voltages from among the m reference voltages on the basis of the digital signal; and an amplifying circuit, which receives the selected n voltages, and outputs to an output terminal a voltage obtained by taking the weighted mean of the input n voltages at a ratio of 2n−1:2n−2: . . . :20; wherein a maximum of mn voltage levels that differ from one another can be output to the output terminal in accordance with the input digital signal.
In a digital-to-analog converter according to another aspect of the present invention, the m (m=2K, where K is an integer and K>=2 holds) reference voltages may be set to a {1+(2n−1)×Σj=1K[αj×2(j−1)n]}th level (where α1, α2, . . . , and αK are 0 or 1) from among equally spaced mn voltage levels.
In a digital-to-analog converter according to another aspect of the present invention, the decoder receives an n×k-bit (where k is an integer and k>=2 holds) digital signal and the m (=2k) reference voltages as inputs and includes n selected-voltage output terminals and n sub-decoders; the sub-decoders each receiving the m reference voltages as inputs and outputting one voltage from among the m reference voltages based upon one group of digital signals from among bit groups obtained by dividing the digital signal into n groups of k digital signals each; n outputs of the sub-decoders being connected to respective ones of the n selected-voltage output terminals; the decoder selecting, and outputting to the n selected-voltage output terminals, the n (n>=3) identical or different voltages from among the m reference voltages based upon the digital signal; the amplifying circuit receiving as inputs the n voltages selected at the n selected-voltage output terminals and outputting, from the output terminal, the voltage obtained by taking the weighted mean of the input n voltages at the ratio of 2n−1:2n−2: . . . :20.
In a digital-to-analog converter according to another aspect of the present invention, the amplifying circuit includes: a differential amplifying circuit having a non-inverting input terminal to which a reference voltage is supplied and an output end connected to the output terminal; first to nth switches (a first switch group) each having a first end connected to a respective one of the n selected-voltage output terminals; n−1 switches (a second switch group) each connected between a second end of an xth switch of the first switch group and a second end of an (x+1)th switch of the first switch group (where 1<=x<=n−1 holds); a switch connected between an nth switch of the first switch group and the output end of the differential amplifying circuit; a switch connected between the output end of the differential amplifying circuit and an inverting input terminal of the differential amplifying circuit; and n capacitors connected between second ends of respective ones of the first to nth switches of the first switch group and the inverting input terminal of the differential amplifying circuit.
In a digital-to-analog converter according to another aspect of the present invention, the decoder receives an (n×k)-bit (where k is an integer and k>=2 holds) digital signal and the m (=2k) reference voltages as inputs and includes one selected-voltage output terminal, a bit-group selecting circuit and a sub-decoder; the bit-group selecting circuit successively selecting and outputting a total of n bit groups one group at a time from bit groups obtained by dividing the digital signal into n groups of k bits each; the sub-decoder receiving the m reference voltages as inputs and outputting one voltage from among the m reference voltages based upon the digital signal of the bit group selected by the bit-group selecting circuit; the single output of the sub-decoder being connected to the single selected-voltage output terminal; the decoder selecting, on a time-division basis, the n (n>=3) identical or different voltages from among the m reference voltages based upon the digital signal and successively supplying these voltages to the single selected-voltage output terminal; the amplifying circuit receiving as inputs the n voltages successively supplied to the single selected-voltage output terminal and outputting, from the output terminal, the voltage obtained by taking the weighted mean of the input n voltages at the ratio of 2n−1:2n−2: . . . :20.
In a digital-to-analog converter according to another aspect of the present invention, the amplifying circuit includes: a differential amplifying circuit having a non-inverting input terminal to which a reference voltage is supplied and an output end connected to the output terminal; first to nth switches (a first switch group) each having a first end connected to the single selected-voltage output terminal; n−1 switches (a second switch group) each connected between a second end of an xth switch of the first switch group and a second end of an (x+1)th switch of the first switch group (where 1<=x<=n−1 holds); a switch connected between an nth switch of the first switch group and the output end of the differential amplifying circuit; a switch connected between the output end of the differential amplifying circuit and an inverting input terminal of the differential amplifying circuit; and n capacitors connected between second ends of respective ones of the first to nth switches of the first switch group and the inverting input terminal of the differential amplifying circuit.
In a digital-to-analog converter according to another aspect of the present invention, the decoder receives an (n×k)-bit (where k is an integer and k>=2 holds) digital signal and the m (=2k) reference voltages as inputs and includes r (1<r<n) selected-voltage output terminals, r bit-group selecting circuits and r sub-decoders; the bit-group selecting circuits each successively selecting and outputting bit groups one group at a time from (n/r) bit groups among bit groups obtained by dividing the digital signal into n groups of k bits each; the sub-decoders each receiving the m reference voltages as inputs and outputting one voltage from among the m reference voltages based upon the digital signal of the bit group selected by the bit-group selecting circuit; r outputs of the sub-decoders being connected to respective ones of the r selected-voltage output terminals; the decoder selecting, on a time-division basis, the n (n>=3) identical or different voltages from among the m reference voltages based upon the digital signal and successively supplying these voltages to the r selected-voltage output terminals; the amplifying circuit receiving as inputs the n voltages successively supplied to the r selected-voltage output terminals and outputting, from the output terminal, the voltage obtained by taking the weighted mean of the input n voltages at the ratio of 2n−1:2n−2: . . . :20.
In a digital-to-analog converter according to another aspect of the present invention, the amplifying circuit includes: a differential amplifying circuit having a non-inverting input terminal to which a reference voltage is supplied and an output end connected to the output terminal; a total of n switches (a first switch group) in which first ends of n/r switches each are connected to a respective one of the r selected-voltage output terminals; n−1 switches (a second switch group) each connected between a second end of an xth switch of the first switch group and a second end of an (x+1)th switch of the first switch group (where 1<=x<=n−1 holds); a switch connected between an nth switch of the first switch group and the output end of the differential amplifying circuit; a switch connected between the output end of the differential amplifying circuit and an inverting input terminal of the differential amplifying circuit; and n capacitors connected between second ends of the first to nth switches of the first switch group and the inverting input terminal of the differential amplifying circuit.
In a digital-to-analog converter according to another aspect of the present invention, the sub-decoder receives the m reference voltages and a bit group comprising k digital signals as inputs thereto; wherein digital signals of the bit group are represented by B0, B1, . . . , and B(k−1), complementary signals of the digital signals of the bit group are represented by B0B, B1B, . . . , and B(k−1)B, and SigN(D,p,q) is a function that returns DB (the complementary signal of D) when the remainder of p−1 divided by 2(q+1) is less than 2q, and returns D otherwise; w, y are integers (where 1<=w<=m, 0<=y<=k−1 hold); with regard to m paths connecting the m reference voltages and a single output terminal of the sub-decoder, a wth reference voltage and the single output terminal are connected via k switches controlled by respective ones of k control signals sigN[B(0),w,0], sigN[B(1),w,1], . . . , sigN[B(y),w,y], . . . , sigN[B(k−1),w,k−1]; and one of the m reference voltages is selected and output by a k-bit digital signal of the bit group.
In a digital-to-analog converter according to another aspect of the present invention, the sub-decoder receives the m reference voltages and a bit group comprising k digital signals as inputs thereto and includes a single output terminal; a switch circuit for selecting one of the m reference voltages; and a switch control circuit for outputting a control signal that controls the switch circuit, which selects one of the m reference voltages, by a k-bit digital signal of the bit group; one of the m reference voltages being selected and output by the k-bit digital signal of the bit group.
In a digital-to-analog converter according to another aspect of the present invention, the switch control circuit receives a k-bit digital signal of the bit group and includes 2k logic circuits that differ from one another in terms of the logic of input signals applied thereto, each logic circuit receiving a digital signal or a complementary signal thereof per bit of the bit group and turning a switch ON only in a case where the input k signals are all “1”s or all “0”s. The switch circuit is such that m paths connecting the m reference voltages and the output of the sub-decoder are connected via switches that change over ON/OFF of the connection of the reference voltages to the output, and the switches are controlled by respective ones of switch control signals that have been output by the switch control circuit.
A display device according to another aspect of the present invention has the above-described digital-to-analog converter as a driver for driving data lines.
The meritorious effects of the present invention are summarized as follows.
The present invention is such that in a DAC using a differential amplifier having n input voltages and capable of outputting a voltage obtained by taking the weighted mean of these voltages at a ratio of 2n−1:2n−2: . . . :20, an advantage is that a maximum of mn voltage levels can be output with respect to the number m of voltages received by the DAC.
In accordance with the present invention, the effect of reducing area is significant and cost can be reduced in fields where there is a very large number of bits, as in the data driver of a liquid crystal display device, etc.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating the structure of a digital-to-analog converter according to a first embodiment of the present invention;
FIG. 2 is a diagram illustrating an example of the structure of a reference voltage generating circuit;
FIG. 3 is a diagram illustrating another example of the structure of a reference voltage generating circuit;
FIG. 4A is a diagram illustrating an example of the structure of an amplifying circuit according to a second embodiment of the present invention, and
FIG. 4B is a timing chart illustrating ON/OFF control of switches in FIG. 4A;
FIG. 5A is a diagram illustrating another example of the structure of an amplifying circuit according to the second embodiment of the present invention, and
FIG. 5B is a timing chart illustrating ON/OFF control of switches in FIG. 4A;
FIG. 6 is a diagram illustrating an example of the structure of a decoder according to the second embodiment;
FIG. 7 is a diagram illustrating an example of the structure of a sub-decoder according to the present invention;
FIG. 8 is a diagram illustrating another example of the structure of a sub-decoder according to the present invention;
FIG. 9 is a diagram illustrating a further example of the structure of a sub-decoder according to the present invention;
FIG. 10 is a diagram illustrating an example of the structures of a switch control circuit and switch circuit according to the present invention;
FIG. 11 is a diagram illustrating another example of the structures of a switch control circuit and switch circuit according to the present invention;
FIG. 12 is a diagram illustrating another example of the structures of a switch control circuit and switch circuit according to the present invention;
FIG. 13 is a diagram illustrating another example of the structures of a switch control circuit and switch circuit according to the present invention;
FIG. 14 is a diagram illustrating another example of the structures of a switch control circuit and switch circuit according to the present invention;
FIG. 15 is a diagram illustrating another example of the structures of a switch control circuit and switch circuit according to the present invention;
FIG. 16 is a diagram illustrating a specific example of a switch in the switch circuit according to the present invention;
FIG. 17 is a diagram illustrating another specific example of a switch in the switch circuit according to the present invention;
FIG. 18 is a diagram illustrating a further specific example of a switch in the switch circuit according to the present invention;
FIG. 19A is a diagram illustrating an example of the structure of an amplifying circuit according to a third embodiment of the present invention, and
FIG. 19B is a timing chart illustrating ON/OFF control of switches in FIG. 19A;
FIG. 20A is a diagram illustrating another example of the structure of an amplifying circuit according to the third embodiment of the present invention, and
FIG. 20B is a timing chart illustrating ON/OFF control of switches in FIG. 20A;
FIG. 21 is a diagram illustrating an example of the structure of a decoder according to the third embodiment;
FIG. 22 is a diagram illustrating an example of the structure of bit-group selecting circuit according to the third embodiment;
FIG. 23 is a timing chart of the bit-group selecting circuit according to the third embodiment;
FIG. 24A is a diagram illustrating an example of the structure of an amplifying circuit according to a fourth embodiment of the present invention, and
FIG. 24B is a timing chart illustrating ON/OFF control of switches in FIG. 24A;
FIG. 25A is a diagram illustrating another example of the structure of the amplifying circuit according to the fourth embodiment of the present invention, and
FIG. 25B is a timing chart illustrating ON/OFF control of switches in FIG. 25A;
FIG. 26 is a diagram illustrating an example of the structure of a decoder according to the fourth embodiment;
FIG. 27 is a diagram illustrating an example of the structure of bit-group selecting circuit according to the fourth embodiment;
FIG. 28 is a timing chart of the bit-group selecting circuit according to the fourth embodiment;
FIG. 29 is a diagram illustrating the structure of a data driver according to a fifth embodiment of the present invention;
FIG. 30 is a diagram illustrating the structure of an active-matrix liquid crystal display device according to the fifth embodiment;
FIG. 31 is a diagram illustrating the relationship between reference voltages and output voltages in a case where m=4, n=3 holds in the present invention;
FIG. 32 is a diagram illustrating the relationship between reference voltages and output voltages in a case where m=4, n=3 holds in the present invention;
FIG. 33 is a diagram illustrating an example of an arrangement in a case where m=4 holds in a sub-decoder according to the present invention;
FIG. 34 is a diagram illustrating an example of an arrangement in a case where m=8 holds in a sub-decoder according to the present invention;
FIG. 35 is a diagram illustrating an example of the structure of a decoder in a case where m=4, n=3 holds in the present invention;
FIG. 36 is a diagram illustrating an example of division of a bit group according to the present invention;
FIG. 37 is a diagram illustrating the configuration of an active-matrix liquid crystal display device;
FIG. 38 is a diagram illustrating the configuration of a data driver according to the conventional art;
FIG. 39 is a diagram illustrating the configuration of a DAC having a capacitor array and a resistor string described in Non-Patent Document 1;
FIG. 40 is a diagram illustrating another example of the configuration of an amplifying circuit according to an embodiment of the present invention;
FIG. 41 is a diagram illustrating an example of the configuration of an amplifying circuit according to an embodiment of the present invention;
FIG. 42 is a diagram illustrating an example of the configuration of a differential amplifying circuit in FIG. 40;
FIG. 43A is a diagram illustrating another example of the configuration of an amplifying circuit according to an embodiment of the present invention, and
FIG. 43B is a timing chart illustrating ON/OFF control of switches in FIG. 43A;
FIG. 44A is a diagram illustrating another example of the configuration of an amplifying circuit according to an embodiment of the present invention, and
FIG. 44B is a timing chart illustrating ON/OFF control of switches in FIG. 44A;
FIG. 45A is a diagram illustrating another example of the configuration of an amplifying circuit according to an embodiment of the present invention, and
FIG. 45B is a timing chart illustrating ON/OFF control of switches in FIG. 45A; and
FIG. 46A is a diagram illustrating another example of the configuration of an amplifying circuit according to an embodiment of the present invention, and
FIG. 46B is a timing chart illustrating ON/OFF control of switches in FIG. 46A.



DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described with reference to the accompanying drawings.
Referring to FIG. 1, an output circuit (DAC) 11 according to an exemplary embodiment of the present invention includes a decoder (selecting circuit) 12, which receives a plurality (m) of reference voltages from a reference voltage generating circuit that generates m (m>=4) reference voltages having voltage values that differ from one another, and selects and outputs n identical or different reference voltages based upon a selecting signal; and an amplifying circuit 13, which receives n reference voltages that are output from the decoder 12, and outputs a voltage, that is obtained by taking the weighted mean of the input n voltages at a ratio of 2n−1:2n−2: . . . :20, from an output terminal. This circuit is used as a digital-to-analog converter in which a digital data signal is employed as the selecting signal, and which outputs a voltage the level whereof conforms to the digital data signal.
In the case of the arrangement shown in FIG. 39, doubling the number of reference voltages without changing the configuration of the amplifier results in only a two-fold increase in the number of output voltage levels. By contrast, in the present invention, doubling the number of reference voltages without changing the configuration of the amplifier results in (2 m)n=2n×mn output voltage levels. In other words, it will be understood that the number of output voltage levels is increased by a factor of 2n.
Conversely, this can be interpreted to mean that an increase in the number of reference voltages when the number of bits is increased can be kept small and an increase in the size of the circuitry can be reduced in comparison with the arrangement of FIG. 39. In particular, if the present invention is applied to fields where there is a very large number of bits, as in the data driver of a liquid crystal display device, the effect of reducing area is significant and cost can be reduced.
In accordance with the present invention, the amplifying circuit 13 can take on any form so long as it outputs a voltage obtained by taking the weighted mean of the input n voltages at a ratio of 2n−1:2n−2: . . . :20.
For the sake of simplicity, assume that the decoder 12 has n selected-voltage output terminals T1, T2, . . . , and Tn, and that the n voltages that are output from the decoder 12 are output to respective ones of the output terminals T1 to Tn. In one example of the amplifying circuit 13, the latter can be implemented by an arrangement that includes a differential amplifying circuit having an output end and an inverting input terminal (−) connected to the output of the decoder 12; n switches (a first switch group) having first ends connected to respective ones of the n selected-voltage output terminals T1, T2, . . . , and Tn; n switches (a second switch group) connected between second ends of respective ones of the n switches and a non-inverting input terminal (+) of the differential amplifying circuit; and n capacitors connected between respective ones of nodes of the first and second switch groups and a power supply.
In accordance with an embodiment, the decoder 12 receives m reference voltages of mutually different voltage values as inputs thereto, supplies the n output terminals T1 to Tn with a group of n voltages, inclusive of voltages that may be identical, from among the m reference voltages, i.e., supplies the n output terminals T1 to Tn with any one group of n voltages, based upon a selecting signal, from among mn voltage groups, and is capable of outputting a maximum of mn voltage levels that differ from one another.
When the input m (m=2k, where k is an integer and k>=2 holds) reference voltages are set to a {1+(2n−1)×Σj=1K[αj×2(j−1)n]}th level (where α1, α2, . . . , and αk are 0 or 1) from among equally spaced mn voltage levels, the voltage levels that are output from the amplifying circuit 13 are all equally spaced.
The decoder 12 receives an (n×k)-bit (where k is an integer and k>=2 holds) digital signal and the m (=2k) reference voltages as inputs and includes n selected-voltage output terminals and n sub-decoders 121 (see FIG. 6). The sub-decoders each receive the m reference voltages as inputs and output one voltage from among the m reference voltages based upon one group of digital signals from among bit groups obtained by dividing the digital signal into n groups of k digital signals each. The n outputs of the sub-decoders are connected to respective ones of the n-number of selected-voltage terminals T1 to Tn. On the basis of the digital signal, the decoder selects, and outputs to the n selected-voltage output terminals T1 to Tn, the n (n>=3) identical or different voltages from among the m reference voltages. The amplifying circuit 13 receives as inputs the n voltages selected at the n selected-voltage output terminals T1 to Tn and outputs, from the output terminal, the voltage obtained by taking the weighted mean of the input n voltages at the ratio of 2n−1:2n−2: . . . :20. A maximum of mn mutually different voltage levels can be output to the output terminal in accordance with the input digital signal.
The sub-decoder 121 may be constructed as follows: The sub-decoder 121 receives m reference voltages and a bit group comprising k digital signals as inputs thereto. Let the digital signals of the bit group be represented by B0, B1, . . . , and B(k−1), and let the complementary signals of the digital signals of the bit group be represented by B0B, B1B, . . . , and B(k−1)B.
SigN(D,p,q) is a function that returns DB (a signal obtained by inverting D) when the remainder of p−1 divided by 2(q+1) is less than 2q and returns D otherwise.
Let w, y represent integers (where 1<=w<=m, 0<=y<=k−1 hold). With regard to m paths connecting the m reference voltages and a single output terminal of the sub-decoder 121, a wth reference voltage and the output terminal are connected via k switches controlled by respective ones of k control signals sigN[B(0),w,0], sigN[B(1),w,1], . . . , sigN[B(y),w,y], . . . , and sigN[B(k−1),w,k−1]. One of the m reference voltages is selected and output by a k-bit digital signal of the bit group.
NMOS transistors can be used as the switches. Each NMOS transistor has a gate to which the digital signal is input, and a drain and source one of which forms a input end of the switch and the other of which forms an output end of the switch.
Alternatively, the sub-decoder 121 may be constructed as follows: The sub-decoder 121 receives m reference voltages and a bit group comprising k digital signals as inputs thereto. Let the digital signals of the bit group be represented by B0, B1, . . . , and B(k−1), and let the complementary (inverted) signals of the digital signals of the bit group be represented by B0B, B1B, . . . , and B(k−1)B.
SigP(D,p,q) is a function that returns D when the remainder of p−1 divided by 2(q+1) is less than 2q and returns DB (a signal obtained by inverting D) otherwise.
Let w, y represent integers (where 1<=w<=m, 0<=y<=k−1 hold). With regard to m paths connecting the m reference voltages and a single output terminal of the sub-decoder 121, a wth reference voltage and the output terminal are connected via k switches controlled by respective ones of k control signals sigP[B(0),w,0], sigP[B(1),w,1], . . . , sigP[B(y),w,y], . . . , and sigP[B(k−1),w,k−1]. One of the m reference voltages is selected and output by a k-bit digital signal of the bit group.
PMOS transistors can be used as the switches. Each PMOS transistor has a gate to which the digital signal is input, and a drain and source one of which forms an input end of the switch and the other of which forms an output end of the switch.
Referring to FIG. 9, in another exemplary embodiment of the present invention, the sub-decoder 121 receives m reference voltages and a bit group comprising k digital signals as inputs thereto. The sub-decoder 121 includes a single output terminal; a switch circuit 1212 for selecting one of the m reference voltages; and a switch control circuit 1211 for outputting a signal that controls the switch circuit 1212, which selects one of the m reference voltages, by the k-bit digital signal of the bit group. One of the m reference voltages is selected and output by the k-bit digital signal of the bit group.
In this embodiment of the invention, the switch control circuit 1211 receives a k-bit digital signal of the bit group and includes 2k logic circuits that differ from one another in terms of the logic of input signals applied thereto, each logic circuit receiving a digital signal or a complementary signal thereof per bit of the bit group and turning a switch ON only in a case where the input k signals are all “1”s or all “0”s. The switch circuit 1212 is such that m paths connecting the m reference voltages and the output of the sub-decoder 121 are connected via switches that change over ON/OFF of the connection of the reference voltages to the output. The switches are controlled by respective ones of switch control signals that have been output by the switch control circuit 1211.
In this embodiment of the invention, the input k digital signals are divided into U sub-bit groups each of which includes two or more digital signals. Each logic circuit of the switch control circuit 1211 can be replaced by U logic circuits each of which receives a respective one of the sub-bit groups as an input and outputs a signal that turns a switch ON only in a case where the input signals of the sub-bit group are all “1”s or all “0”s. Further, each of the switches in the switch circuit that change over ON/OFF of the connection of the reference voltages to the output can be replaced by a group of U switches serially arrayed. The U switches are controlled by respective ones of switch control signals that have been output by the U logic circuits.
Further, in an embodiment of a display device according to the present invention, the decoder 12 receives a plurality of voltage levels from a grayscale voltage generating circuit for generating a plurality of voltage levels as the plurality of reference voltages, and received digital video data as the selecting signals, and the amplifying circuit 13 constructs a driving circuit for receiving the outputs of the decoder 12 and driving the data lines.
The embodiments of the invention will be described in greater detail.
FIG. 1 is a diagram useful in describing the configuration of a digital-to-analog converter (DAC) 11 according to an embodiment of the present invention. As shown in FIG. 1, the DAC 11 receives as inputs m mutually different reference voltages generated by a reference voltage generating circuit 14, makes it possible to output a maximum of mn voltage levels based upon a digital signal and outputs voltages selected from among these voltage levels.
The DAC 11 has a decoder 12 and an amplifying circuit 13. The decoder 12 receives m mutually different reference voltages as inputs and is capable of outputting a maximum of mn-number of voltages. The amplifying circuit 13 outputs a voltage obtained by taking the weighted mean of the input n voltages, which have been output by the decoder 12, at a ratio of 2n−1:2n−2: . . . :20.
The reference voltage generating circuit 14 is capable of using a resistor string, etc., shown in FIG. 2 or 3. As shown in FIG. 2, voltages VrefH and VrefL are supplied to respective ends of a resistor string 141, and reference voltages are output from taps between resistors. In the arrangement of FIG. 3, a buffer (voltage follower) 142 is added to each tap in such a manner that reference voltages can be extracted at a high driving capability.
If the m (m=2k, where k is an integer and k>=2 holds) reference voltages are set to a {1+(2n−1)×Σj=1K[αj×2(j−1)n]}th level (where α1, α2, . . . , and αk are 0 or 1) from among equally spaced mn voltage levels, then the mn voltage levels that are output from the amplifying circuit 13 will all be equally spaced.
First, if we let v represent the spacing of mn (=2kn) mutually adjacent equal voltages having an equal spacing, then a reference voltage Vref will be expressed by the Equation (1) below.




  
    
      
        
          
            v
            nf
          
          ⁡
          
            (
            
              
                α
                1
              
              ,
              
                α
                2
              
              ,
              
                α
                3
              
              ,
              ...
              ⁢
              
                
              
              ,
              
                α
                k
              
            
            )
          
        
        =
        
          
            {
            
              1
              +
              
                
                  (
                  
                    
                      2
                      ′′
                    
                    -
                    1
                  
                  )
                
                ⁢
                
                  
                    ∑
                    
                      j
                      =
                      1
                    
                    k
                  
                  ⁢
                  
                    
                      α
                      j
                    
                    ·
                    
                      2
                      
                        
                          (
                          
                            j
                            -
                            1
                          
                          )
                        
                        ⁢
                        n
                      
                    
                  
                
              
            
            }
          
          ⁢
          v
        
      
    
    
      
        (
        1
        )
      
    
  




where α1, α2, α3, . . . , and αk take on a value of 0 or 1.

In order to indicate that the outputs will all be equally spaced, it will suffice if an output voltage Vout(i) of the amplifying circuit 13 at any gray level i (1<=i<=2kn) is expressed by a linear relationship with respect to the gray level i, i.e., by Equation (2) below.

Vout(i)=i·v  (2)

In a case where a voltage at the gray level i is output, voltages Vsel1(i) to Vsel(n)(i) selected by the decoder 12 are expressed by Equation (3) below using Equation (1) and digital signals D0 to D(kn−1).




   
  
    
      
        
          {
          
            
              
                
                  
                    
                      V
                      
                        sel
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    ⁡
                    
                      (
                      i
                      )
                    
                  
                  =
                  
                    
                      V
                      ref
                    
                    ⁡
                    
                      (
                      
                        
                          D
                          
                            n
                            -
                            1
                          
                        
                        ,
                        
                          D
                          
                            
                              2
                              ⁢
                              
                                
                              
                              ⁢
                              n
                            
                            -
                            1
                          
                        
                        ,
                        
                          D
                          
                            
                              3
                              ⁢
                              
                                
                              
                              ⁢
                              n
                            
                            -
                            1
                          
                        
                        ,
                        ...
                        ⁢
                        
                          
                        
                        ,
                        
                          D
                          
                            kn
                            -
                            1
                          
                        
                      
                      )
                    
                  
                
              
            
            
              
                
                  
                    
                      V
                      
                        sel
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    ⁡
                    
                      (
                      i
                      )
                    
                  
                  =
                  
                    
                      V
                      ref
                    
                    ⁡
                    
                      (
                      
                        
                          D
                          
                            n
                            -
                            2
                          
                        
                        ,
                        
                          D
                          
                            
                              2
                              ⁢
                              
                                
                              
                              ⁢
                              n
                            
                            -
                            2
                          
                        
                        ,
                        
                          D
                          
                            
                              3
                              ⁢
                              
                                
                              
                              ⁢
                              n
                            
                            -
                            2
                          
                        
                        ,
                        ...
                        ⁢
                        
                          
                        
                        ,
                        
                          D
                          
                            kn
                            -
                            2
                          
                        
                      
                      )
                    
                  
                
              
            
            
              
                
                  
                    
                  
                  ⁢
                  
                    ⋮
                    ⁢
                    
                      
                    
                    ⁢
                    ⋮
                    ⁢
                    
                      
                    
                    ⁢
                    ⋮
                    ⁢
                    
                      
                    
                    ⁢
                    ⋮
                    ⁢
                    
                      
                    
                    ⁢
                    ⋮
                    ⁢
                    
                      
                    
                    ⁢
                    ⋱
                    ⁢
                    
                      
                    
                    ⁢
                    ⋮
                  
                
              
            
            
              
                
                  
                    
                      V
                      
                        sel
                        ⁡
                        
                          (
                          
                            n
                            -
                            1
                          
                          )
                        
                      
                    
                    ⁡
                    
                      (
                      i
                      )
                    
                  
                  =
                  
                    
                      V
                      ref
                    
                    ⁡
                    
                      (
                      
                        
                          D
                          1
                        
                        ,
                        
                          D
                          
                            n
                            +
                            1
                          
                        
                        ,
                        
                          D
                          
                            
                              2
                              ⁢
                              
                                
                              
                              ⁢
                              n
                            
                            +
                            1
                          
                        
                        ,
                        ...
                        ⁢
                        
                          
                        
                        ,
                        
                          D
                          
                            
                              
                                (
                                
                                  k
                                  -
                                  1
                                
                                )
                              
                              ⁢
                              n
                            
                            +
                            1
                          
                        
                      
                      )
                    
                  
                
              
            
            
              
                
                  
                    
                      V
                      
                        sel
                        ⁡
                        
                          (
                          n
                          )
                        
                      
                    
                    ⁡
                    
                      (
                      i
                      )
                    
                  
                  =
                  
                    
                      V
                      ref
                    
                    ⁡
                    
                      (
                      
                        
                          D
                          0
                        
                        ,
                        
                          D
                          n
                        
                        ,
                        
                          D
                          
                            2
                            ⁢
                            
                              
                            
                            ⁢
                            n
                          
                        
                        ,
                        
                          ...
                          ⁢
                          
                            
                          
                          ⁢
                          
                            D
                            
                              
                                (
                                
                                  k
                                  -
                                  1
                                
                                )
                              
                              ⁢
                              n
                            
                          
                        
                      
                      )
                    
                  
                
              
            
          
        
      
      
        
          (
          3
          )
        
      
    
  




Further, the gray level i is expressed by Equation (4) below similarly using the digital signals D0 to D(kn−1).




  
    
      
        i
        =
        
          1
          +
          
            
              ∑
              
                j
                =
                0
              
              
                kn
                -
                1
              
            
            ⁢
            
              
                D
                j
              
              ·
              
                2
                j
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Since the amplifying circuit 13 outputs a voltage obtained by taking the weighted mean of the voltages Vsel1(i) to Vsel(n)(i), the output voltage Vout(i) of the amplifying circuit 13 is expressed by Equation (5) below.




  
    
      
        
          
            V
            out
          
          ⁡
          
            (
            i
            )
          
        
        =
        
          
            
              
                2
                
                  n
                  -
                  1
                
              
              ⁢
              
                
                  V
                  
                    sel
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁡
                
                  (
                  i
                  )
                
              
            
            +
            
              
                2
                
                  n
                  -
                  2
                
              
              ⁢
              
                
                  V
                  
                    sel
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                ⁡
                
                  (
                  i
                  )
                
              
            
            +
            ...
            +
            
              
                2
                1
              
              ⁢
              
                
                  V
                  
                    sel
                    ⁡
                    
                      (
                      
                        n
                        -
                        1
                      
                      )
                    
                  
                
                ⁡
                
                  (
                  i
                  )
                
              
            
            +
            
              
                2
                0
              
              ⁢
              
                
                  V
                  
                    sel
                    ⁡
                    
                      (
                      n
                      )
                    
                  
                
                ⁡
                
                  (
                  i
                  )
                
              
            
          
          
            
              2
              n
            
            -
            1
          
        
      
    
    
      
        (
        5
        )
      
    
  




If Equation (3) is substituted into Vsel1(i) to Vsel(n)(i) of Equation (5), then the numerator of Equation (5) becomes as follows:




  
    
      
        
          
            
              
                
                  Numerator
                  ⁢
                  
                    
                  
                  ⁢
                  of
                
                ⁢
                
                  
                
              
            
          
          
            
              
                Equation
                ⁢
                
                  
                
                ⁢
                
                  (
                  5
                  )
                
              
            
          
        
        =
        
        ⁢
        
          
            
              2
              0
            
            ⁢
            v
          
          +
          
            
              
                (
                
                  
                    2
                    n
                  
                  -
                  1
                
                )
              
              ·
              
                2
                0
              
            
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  
                    D
                    0
                  
                  ·
                  
                    2
                    0
                  
                
                +
                
                  
                    D
                    n
                  
                  ·
                  
                    2
                    n
                  
                
                +
                
                  
                    D
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                  
                  ·
                  
                    2
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                  
                
                +
                ...
                +
                
                  
                    D
                    
                      
                        (
                        
                          k
                          -
                          1
                        
                        )
                      
                      ⁢
                      n
                    
                  
                  ·
                  
                    2
                    
                      
                        (
                        
                          k
                          -
                          1
                        
                        )
                      
                      ⁢
                      n
                    
                  
                
              
              )
            
            ⁢
            v
          
          +
        
      
    
  
  
    
      
        
        ⁢
        
          
            
              2
              1
            
            ⁢
            v
          
          +
          
            
              
                (
                
                  
                    2
                    n
                  
                  -
                  1
                
                )
              
              ·
              
                2
                1
              
            
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  
                    D
                    1
                  
                  ·
                  
                    2
                    0
                  
                
                +
                
                  
                    D
                    
                      n
                      +
                      1
                    
                  
                  ·
                  
                    2
                    n
                  
                
                +
                
                  
                    D
                    
                      
                        2
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                      +
                      1
                    
                  
                  ·
                  
                    2
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                  
                
                +
                ...
                +
                
                  
                    D
                    
                      
                        
                          (
                          
                            k
                            -
                            1
                          
                          )
                        
                        ⁢
                        n
                      
                      +
                      1
                    
                  
                  ·
                  
                    2
                    
                      
                        (
                        
                          k
                          -
                          1
                        
                        )
                      
                      ⁢
                      n
                    
                  
                
              
              )
            
            ⁢
            v
          
          +
        
      
    
  
  
    
      
        
        ⁢
        
          
            ⋯
            ⁢
            
              
            
            ⁢
            ⋮
            ⁢
            
              
            
            ⁢
            ⋮
            ⁢
            
              
            
            ⁢
            ⋮
            ⁢
            
              
            
            ⁢
            ⋱
            ⁢
            
              
            
            ⁢
            ⋮
          
          +
        
      
    
  
  
    
      
        
        ⁢
        
          
            
              2
              
                n
                -
                2
              
            
            ⁢
            v
          
          +
          
            
              
                (
                
                  
                    2
                    n
                  
                  -
                  1
                
                )
              
              ·
              
                2
                
                  n
                  -
                  2
                
              
            
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  
                    D
                    
                      n
                      -
                      2
                    
                  
                  ·
                  
                    2
                    0
                  
                
                +
                
                  
                    D
                    
                      
                        2
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                      -
                      2
                    
                  
                  ·
                  
                    2
                    n
                  
                
                +
                
                  
                    D
                    
                      
                        3
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                      -
                      2
                    
                  
                  ·
                  
                    2
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                  
                
                +
                ...
                +
                
                  
                    D
                    
                      kn
                      -
                      2
                    
                  
                  ·
                  
                    2
                    
                      
                        (
                        
                          k
                          -
                          1
                        
                        )
                      
                      ⁢
                      n
                    
                  
                
              
              )
            
            ⁢
            v
          
          +
        
      
    
  
  
    
      
        
        ⁢
        
          
            
              2
              
                n
                -
                1
              
            
            ⁢
            v
          
          +
          
            
              
                (
                
                  
                    2
                    n
                  
                  -
                  1
                
                )
              
              ·
              
                2
                
                  n
                  -
                  1
                
              
            
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  
                    D
                    
                      n
                      -
                      1
                    
                  
                  ·
                  
                    2
                    0
                  
                
                +
                
                  
                    D
                    
                      
                        2
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                      -
                      1
                    
                  
                  ·
                  
                    2
                    n
                  
                
                +
                
                  
                    D
                    
                      
                        3
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                      -
                      1
                    
                  
                  ·
                  
                    2
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                  
                
                +
                ...
                +
                
                  
                    D
                    
                      kn
                      -
                      1
                    
                  
                  ·
                  
                    2
                    
                      
                        (
                        
                          k
                          -
                          1
                        
                        )
                      
                      ⁢
                      n
                    
                  
                
              
              )
            
            ⁢
            v
          
        
      
    
  
  
    
      
        =
        
        ⁢
        
          
            
              (
              
                
                  2
                  0
                
                +
                
                  2
                  1
                
                +
                ...
                +
                
                  2
                  
                    n
                    -
                    1
                  
                
              
              )
            
            ⁢
            v
          
          +
          
            
              (
              
                
                  2
                  n
                
                -
                1
              
              )
            
            ⁢
            
              v
              ·
              
                
                  ∑
                  
                    j
                    =
                    0
                  
                  
                    kn
                    -
                    1
                  
                
                ⁢
                
                  
                    D
                    j
                  
                  ·
                  
                    2
                    j
                  
                
              
            
          
        
      
    
  
  
    
      
        =
        
        ⁢
        
          
            (
            
              
                2
                n
              
              -
              1
            
            )
          
          ⁢
          
            (
            
              1
              +
              
                
                  ∑
                  
                    j
                    =
                    0
                  
                  
                    kn
                    -
                    1
                  
                
                ⁢
                
                  
                    D
                    j
                  
                  ·
                  
                    2
                    j
                  
                
              
            
            )
          
          ⁢
          v
        
      
    
  




Accordingly, output voltage Vout(i) of amplifying circuit 13 is expressed by Equation (6) below.




  
    
      
        
          
            V
            out
          
          ⁡
          
            (
            i
            )
          
        
        =
        
          
            
              
                (
                
                  
                    2
                    n
                  
                  -
                  1
                
                )
              
              ⁢
              
                (
                
                  1
                  +
                  
                    
                      ∑
                      
                        j
                        =
                        0
                      
                      
                        kn
                        -
                        1
                      
                    
                    ⁢
                    
                      
                        D
                        j
                      
                      ·
                      
                        2
                        j
                      
                    
                  
                
                )
              
              ⁢
              v
            
            
              
                2
                n
              
              -
              1
            
          
          =
          
            
              (
              
                1
                +
                
                  
                    ∑
                    
                      j
                      =
                      0
                    
                    
                      kn
                      -
                      1
                    
                  
                  ⁢
                  
                    
                      D
                      j
                    
                    ·
                    
                      2
                      j
                    
                  
                
              
              )
            
            ⁢
            v
          
        
      
    
    
      
        (
        6
        )
      
    
  




Substituting Equation (4) into Equation (6) gives the following:

Vout(i)=iv 

This indicates Equation (2).

Thus, it is indicated that by setting the reference voltages to a {1+(2n−1)×Σj=1K[αj×2(j−1)n]}th level (where α1, α2, . . . , and αk are 0 or 1) from among equally spaced mn voltage levels, mn output voltages of the amplifying circuit 13 are all equally spaced.
Next, a case where the decoder 12 of FIG. 1 has n output terminals (i.e., where the amplifying circuit 13 has n input terminals) will be described as a second embodiment of the present invention. That is, the decoder 12 receives m reference voltages that differ from one another, selects n voltages, inclusive of voltages that may be identical, from among the m reference voltages based upon a selecting signal, and supplies the selected voltages to n output terminals T1, T2, . . . , Tn.
Further, the amplifying circuit 13 outputs a voltage obtained by taking the weighted mean of the n voltages, which have been supplied to the terminals T1 to Tn, at a ratio of 2n−1:2n−2: . . . :20. Let VQ1, VQ2, . . . , and VQn represent the n voltages supplied to the terminals T1 to Tn.
A case where there are four reference voltages and three output terminals T1, T2 and T3 of the decoder 12, namely a case where m=4, n=3 holds, will now be described as an example. FIG. 31 is a diagram illustrating the relationship among reference voltages, selected voltages of the decoder 12 and output voltages of the amplifying circuit 13. In the example depicted in FIG. 31, 43=64 equally spaced voltages can be output with respect to four reference voltages. With reference to Equation (1), the four reference voltages (A, B, C, D) are the 1st, 8th, 57th and 64th voltages, respectively.
The amplifying circuit 13 outputs a voltage obtained by taking the weighted mean of the voltages VQ1, VQ2 and VQ3, which are supplied respectively to the terminals T1, T2 and T3, at the ratio 4:2:1. That is, the amplifying circuit 13 outputs the following:

Vout=(4VQ1+2VQ2+1VQ3)/7

Accordingly, by setting voltages V(T1), V(T2) and V(T3) at terminals T1, T2 and T3 in the manner illustrated in FIG. 31, 64 equally spaced voltages are obtained.
A case where there are four reference voltages and four output terminals T1, T2, T3 and T4 of the decoder 12, namely a case where m=4, n=4 holds, will now be described as another example.
FIG. 32 is a diagram illustrating the relationship among reference voltages, selected voltages of the decoder 12 and output voltages of the amplifying circuit 13. In the example depicted in FIG. 32, 44=256 equally spaced voltages can be output with respect to the four reference voltages. With reference to Equation (1), the four reference voltages (A, B, C, D) are the 1st, 16th, 241st and 256th voltages, respectively.
The amplifying circuit 13 outputs a voltage obtained by taking the weighted mean of the voltages VQ1, VQ2, VQ3 and VQ4 which are supplied respectively to the terminals T1, T2, T3 and T4 at the ratio 8:4:2:1. That is, the amplifying circuit 13 outputs the following:

Vout=(8VQ1+4VQ1+2VQ2+1VQ3)/15

Accordingly, by setting voltages V(T1), V(T2), V(T3) and V(T4) at terminals T1, T2, T3 and T4 in the manner illustrated in FIG. 32, 256 equally spaced voltages are obtained.
A specific example of the amplifying circuit 13 will be described next. FIG. 4A is a diagram illustrating an example of the configuration of the amplifying circuit 13 in this embodiment, and FIG. 4B is a timing chart illustrating switching control of the amplifying circuit 13 shown in FIG. 4A. As shown in FIG. 4A, the amplifying circuit 13 includes a voltage-follower differential amplifying circuit A1 having its output end and its inverting input terminal (−) connected to the output terminal of the circuit; a first switch group comprising n switches SA1 to SAn having first ends thereof connected to n selected-voltage terminals T1 to Tn, respectively; a second switch group comprising n switches SB1 to SBn connected between respective ones of second ends of the first switch group and the non-inverting input terminal (+) of the differential amplifying circuit A1; and n capacitors C1 to Cn connected between respective ones of nodes of the first and second switch groups and ground.
As shown in FIGS. 4A and 4B, first, in time period ta, if switches SB1 to SBn are turned OFF and switches SA1 to SAn are turned ON, voltages VQ1 to VQn supplied to input terminals T1 to Tn are stored in capacitors C1 to Cn, respectively, via the ON switches SA1 to SAn. If switches SA1 to SAn are turned OFF and switches SB1 to SBn are turned ON in the next time period tb, then charge is redistributed among the capacitors C1 to Cn. By setting the capacitance ratio of the capacitors C1 to Cn to the ratio 2n−1:2n−2: . . . :20 beforehand, the non-inverting input voltage of the voltage follower A1 becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20. Accordingly, the output voltage of the voltage follower A1 also becomes a voltage that is the result of taking the weighted mean of the voltages VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
FIG. 5A is a diagram illustrating another example of the configuration of the amplifying circuit 13 in this embodiment, and FIG. 5B is a timing chart illustrating switching control of the amplifying circuit 13 shown in FIG. 5A. The arrangement shown in FIG. 5A is capable of canceling any offset that might be produced by a voltage follower A2 due to element variance, etc. As shown in FIG. 5A, the amplifying circuit 13 includes a voltage-follower differential amplifying circuit A2 having a non-inverting input terminal (+) that receives a reference voltage Vref—oc as an input, and an output end connected to output terminal Vout; a first switch group comprising first to nth switches SC1 to SCn having first ends thereof connected to n selected-voltage terminals T1 to Tn, respectively; a second switch group comprising n−1 switches SE1 to SEn−1 each connected between a second end of an xth switch Scx of the first switch group and a second end of an (x+1)th switch Scx+1 of the first switch group (where 1<=x<=n−1 holds); a switch SEn connected between a second end of the nth switch SCn of the first switch group and the output end of the differential amplifying circuit; a switch SD connected between the output end of the differential amplifying circuit and the inverting input terminal (−) of the differential amplifying circuit; and n capacitors C1 to Cn capacitors connected between second ends of the switches of the first switch group and the inverting input terminal of the differential amplifying circuit.
As shown in FIGS. 5A and 5B, first, in time period ta, if switches SE1 to SEn are turned OFF and switches SC1 to SCn and switch SD are turned ON, voltages VQ1 to VQn supplied to input terminals T1 to Tn are supplied to first ends of capacitors C1 to Cn, respectively, via the switches SC1 to SCn.
On the other hand, if we let dV represent offset of the voltage follower A2, then the output of the voltage follower will be Vref-oc+dV and this is supplied to the second ends of the capacitors C1 to Cn via the switch SD. Consequently, voltages [VQ1−(Vref+dV)], . . . [VQn−(Vref+dV)] are stored in the capacitors C1 to Cn, respectively.
If switches SC1 to SCn and switch SD are turned OFF and switches SE1 to SEn are turned ON in the next time period tb, then charge is redistributed among the capacitors C1 to Cn. At the same time, the output of the voltage follower and the inverting input terminal (−) are connected via the capacitors C1 to Cn. As a result, the offset dV is cancelled and the output of the voltage follower A2 becomes as follows:

[(C1×VQ1+C2×VQ2+ . . . +Cn×VQn)/(C1+C2+ . . . +Cn)

By setting the capacitance ratio of the capacitors C1 to Cn to the ratio 2n−1:2n−2: . . . :20 beforehand, the output voltage of the voltage follower A2 becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
FIG. 40 is a diagram illustrating another example of the configuration of the amplifying circuit 13. As shown in FIG. 40, the amplifying circuit comprises a differential amplifying circuit 131 that includes at least first to nth input terminals Vin—1 to Vin—n; an output terminal Vout; first to nth differential pairs 132A to 132C; ith (where i is an integer and 1<=i<=n holds) current sources 133A to 133C that supply ith differential pairs with current; a load circuit 134 connected together in common with output pairs of the first to nth differential pairs. In an ith differential pair (where i is an integer and 1<=I<=n holds), one of the input pairs is connected to an ith input terminal and the other is connected to the output terminal. One of output pairs of the first to nth differential pairs are connected together in common, and the other output pairs of the first to nth differential pairs are connected together in common. The differential amplifying circuit further includes an amplifier stage 135 having an input end that is connected to a node at which the one output pairs of the first to nth differential pairs are connected together in common, and an output end connected to the output terminal. The load circuit is connected to a node at which the one output pairs of the first to nth differential pairs are connected together in common, and to a node at which the other output pairs of the first to nth differential pairs are connected together in common. In the example illustrated in FIG. 40, each differential pair is constructed by a pair of NMOS transistors whose sources are connected in common. The amplifier stage 135 may be constructed by a differential amplifier obtained by connecting a differential input pair to nodes at which the load circuit 134 and output pairs of n differential pairs are connected.
In the differential amplifying circuit 131, the sizes of the differential pairs 132A to 132C are set to 2n−1:2n−2: . . . :20, respectively, and the values of the currents that flow into the current sources 133A to 133C are set to 2n−1:2n−2: . . . :20, whereby the output Vout of the differential amplifying circuit 131 becomes a voltage obtained by taking the weighted mean of n voltages Vin—1 Vin13 n, which are supplied to the differential amplifying circuit 131, at the ratio 2n−1:2n−2: . . . :20.
As illustrated in FIG. 41, the differential amplifying circuit 131 can be used in the amplifying circuit 13 of this embodiment. That is, the differential amplifying circuit 131 is capable of outputting a voltage obtained by taking the weighted mean of the n voltages VQ1 to VQn, which have been output from the decoder 12, at the ratio 2n−1:2n−2: . . . :20.
It should be noted that in addition to the arrangement in which sizes of the differential pairs are set to the ratio 2n−1:2n−2: . . . :20, the differential pairs 132A to 132C in the differential amplifying circuit 131 may each be constructed by arraying a plurality of transistors of identical size in parallel, as illustrated in FIG. 42. More specifically, as shown in FIG. 42, the differential pair 132A (which corresponds to the differential pair 132A in FIG. 40) includes 2n−1 NMOS transistors having drains connected in common and connected to a node at which a first end of the load circuit 134 (see FIG. 40) and the input end of the amplifier stage 135 (see FIG. 40) are connected, and gates to which the input voltage Vin—1 is input, and 2n−1 NMOS transistors having drains connected in common and connected to the second end of the load circuit 134 (see FIG. 40), and gates to which the output signal Vout is input. The sources of these 2n−1 pairs of NMOS transistor pairs are connected in common and are connected to the current source 133A (current value=2n−1×i). In the differential pair 132A, the size of the differential pair 132A is essentially 2n−1×W, where W represents the channel width of one NMOS transistor. Similarly, the differential pair 132B includes 2n−2 NMOS transistors having drains connected in common and connected to a node at which the first end of the load circuit 134 (see FIG. 40) and the input end of the amplifier stage 135 (see FIG. 40) are connected, and gates to which the input signal Vin—2 is input, and 2n−2 NMOS transistors having drains connected in common and connected to the second end of the load circuit 134 (see FIG. 40), and gates to which the output signal Vout is input. The sources of these 2n−2 pairs of NMOS transistor pairs are connected in common and are connected to the current source 133B (current value=2n−2×i). The size of the transistor pair 132B is essentially 2n−2×W. The differential pair 133C includes one NMOS transistor having a drain connected to the node at which the first end of the load circuit 134 (FIG. 40) and the input end of the amplifier stage 135 (FIG. 40) are connected, and a gate to which the input signal Vin—n is input, and one NMOS transistor having a drain connected to the second end of the load circuit 134 (FIG. 40) and a gate to which the output signal Vout is input. The sources of the NMOS transistor pair of this pair (=20 pair) are connected in common and are connected to current source 133C (current value=20×i. The size of this differential pair 132C is essentially 20×W. In this case, the transistors constructing the differential pairs 132A to 132C are all of the same size and therefore the precision of the weighted mean can be somewhat improved.
It should be noted that the amplifying circuit 13 is not limited to the example of structure described above. Any structure will suffice so long as it is possible to output a voltage obtained by taking the weighted mean of the voltages VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
Next, an example of the configuration of the decoder 12 will be described. FIG. 6 is a diagram illustrating a specific example of the configuration of the decoder 12 according to this embodiment. As illustrated in FIG. 6, the decoder 12 receives an (n×k)-bit (where k is an integer and k>=2 holds) digital signal and the m (=2k) reference voltages as inputs and includes n selected-voltage output terminals and n sub-decoders 121. The sub-decoders each receive the m reference voltages as inputs and output one voltage from among the m reference voltages based upon one group of digital signals from among bit groups BG1 to BGn obtained by dividing the digital signal into n groups of k digital signals each. Further, n outputs of the sub-decoders 121 are connected to respective ones of the n selected-voltage output terminals T1 to Tn. The decoder selects, and outputs to the n selected-voltage output terminals T1 to Tn, the n (n>=3) identical or different voltages from among the m reference voltages based upon the digital signal.
Division into the bit groups may be performed as illustrated in FIG. 36 by way of example.
The configuration of the sub-decoders 121 will be described next. FIG. 7 is a diagram illustrating a specific example of the sub-decoder 121. As shown in FIG. 7, the sub-decoder 121 receives m reference voltages Vref1 to Vrefm and a bit group comprising k digital signals [B0 to B(k−1)] and has one output terminal T. Signals obtained by inverting the digital signals of the bit groups will be expressed by B0B, B1B, . . . , B(k−1)B below.
In order to describe the connection relationship of the decoder 12, the symbols and functions set forth below are introduced. That is, let w, y be integers (where 1<=w<=m, 0<=y<=k−1 hold), and let SigN(D,p,q) be a function that returns DB (the complementary signal of D) when the remainder of p−1 divided by 2(q+1) is less than 2q, and returns D otherwise.
With regard to m paths connecting the m reference voltages Vref1 to Vrefm input to the sub-decoder 121 and the single output terminal T that outputs the selected voltage, a wth reference voltage Vrefw and the output terminal T are connected via k switches controlled by respective ones of k control signals sigN[B(0),w,0], sigN[B(1),w,1], . . . , sigN[B(y),w,y], . . . , sigN[B(k−1),w,k−1].
FIGS. 33 and 34 illustrate examples of the configuration of the sub-decoder 121 in a case where there are four reference voltages (m=4) and eight reference voltages (m=8), respectively. FIGS. 33 and 34 illustrate decoders of 2-bit and 3-bit tournament types, respectively. In the example shown in FIG. 33, the decoder has two path transistors NM1, NM2 provided between the terminal T and voltage Vref1 and turned ON and OFF by B0B and B1B, respectively; a path transistor NM3 provided between the connection node of path transistors NM1, NM2 and Vref2 and turned ON and OFF by B0; two path transistors NM4, NM5 provided between the terminal T and Vref3 and turned ON and OFF by B0B and B1, respectively; and a path transistor NM6 provided between the connection node of path transistors NM3, NM4 and Vref4 and turned ON and OFF by B0.
The path transistors NM1 to NM14 in FIGS. 33 and 34 are all constituted by NMOS transistors.
PMOS transistors may also be used as the path transistors that construct the sub-decoder. In this case, the logic of the input k-bit digital signal would be the opposite of the logic in the case where NMOS transistors are used. For instance, taking FIG. 33 as an example, B0 and B0B would be reversed, and B1 and B1B would be reversed.
Further, FIG. 35 illustrates an example of the configuration of decoder 12 in a case where the arrangement of FIG. 33 is applied to the sub-decoder 121 for a case where there are four reference voltages and the decoder 12 has three output terminals T1, T2 and T3, i.e., in a case where m=4, n=3 holds. In this example, 6-bit data (D0 to D5) is input and three sub-decoders 121 are provided in view of the face that n=3 holds.
Further, if the 6-bit data is divided into bit groups in accordance with FIG. 36, then the three groups will be as follows:

BG1=[D2,D5];

BG2=[D1,D4]; and

BG3=[D0,D3].

If these bit groups are input to respective ones of the three sub-decoders 121, then 64 voltages, inclusive of voltages that may be identical, are selected from the four reference voltages Vref1 to Vref4) in accordance with the 6-bit data, and the selected voltages are supplied to the three output terminals T1, T2 and T3.
The arrangements shown in FIG. 7 and in FIGS. 33 to 35 are examples, and any arrangement may be adopted so long as the connection relationship illustrated above holds. Although tournament-type decoders are illustrated in FIG. 7 and in FIGS. 33 to 35, it is permissible to adopt an arrangement (of ROM type) in which the connections between the m reference voltages and output terminal are all made independent paths. However, the arrangement of FIG. 8 has a greater number of switches than the arrangement shown in FIG. 7.
Another example of the configuration of the sub-decoder 121 will be described. FIG. 9 is a diagram illustrating a specific example of the configuration of the sub-decoders 121 shown in FIG. 6. As shown in FIG. 9, the sub-decoder 121 receives m reference voltages and a bit group comprising a k-bit digital signal as inputs thereto, and has a single output terminal T. The sub-decoder 121 further includes a switch circuit 1212 for selecting one of the m reference voltages, and a switch control circuit 1211 for outputting a signal that controls the switch circuit 1212 in accordance with the k-bit digital signal. One of the m reference voltages is selected and output by the k-bit digital signal of the bit group.
The switch control circuit 1211 and switch circuit 1212 of FIG. 9 will be described in greater detail. FIG. 10 is a diagram illustrating a specific example of the structures of the switch control circuit 1211 and switch circuit 1212 shown in FIG. 9. For the sake of simplicity, FIG. 10 illustrates an arrangement in which k=4 holds and the number of input reference voltages is m=2k=16 (Vref0 to Vref15).
As shown in FIG. 10, the switch control circuit 1211 receives the k-bit digital signal of the bit group as an input and includes 2k (16) logic circuits 1211a. Each logic circuit receives a digital signal B× or a complementary signal B×B thereof (0<=x<=k−1) per bit of the bit group and turns a switch (a PMOS switch) ON only in a case where the input k signals are all HIGH. The 2k logic circuits 1211a differ from one another in terms of the combination of logic of the signals that are input thereto.
In the example of FIG. 4, k=4 holds. Accordingly, a 4-bit digital signal (B0 to B3) is input. With regard to each of the bits of B0 to B3, either B× or the complementary signal B×B thereof (0<=x<=3) is supplied to the 24=16 logic circuits (NAND gates). With regard to B0 to B3, combinations of bit signal B× or the complementary signal B×B thereof are 16 in total, and the setup is such that the digital signals that are input to each of the logic circuits 1211a will form combinations that differ from one another.
If NAND gates are used as the logic circuits 1211a, as illustrated in FIG. 10, then, with respect to certain input bit data, only one among the 2k NAND gates will deliver an output of LOW level. Accordingly, a signal that selects one of the m (=2k) reference voltages can be output by k-bit data.
Further, as shown in FIG. 10, the switch circuit 1212 is such that m paths connecting the m reference voltages and the output T of the sub-decoder are connected via switches that change over ON/OFF of the connection of the reference voltages to the output, and the switches are controlled by respective ones of switch control signals that have been output by the switch control circuit 1211.
By way of example, if the bit data of the bit group is (B0, B1, B2, B3)=(1, 0, 0, 1) in FIG. 10, then only the output of the logic circuit (logic circuit A in FIG. 10) whose inputs are B0, the complementary signal (B1B) of B1, the complementary signal (B2B) of B2 and B3 will take on the LOW level, and the outputs of the remaining logic circuits will take on the HIGH level.
In the example illustrated in FIG. 10, PMOS transistors are used as the switches of the switch circuit 1212. When the gate voltage of the PMOS transistor is at the LOW level, the switch is ON, and when the gate voltage is at the HIGH level, the switch is OFF. Accordingly, among the 16 switches, only the switch (switch A of FIG. 10) to which Vref9 is connected turns ON, and the remaining switches turn OFF. The output of the sub-decoder 121 (the potential at terminal T), therefore, is Vref9.
Next, another example of the structures of switch control circuit 1211 and switch circuit 1212 will be described. In the example of FIG. 10, NAND gates are employed as the logic circuits. In general, however, if the number of NAND gates increases, driving capability declines. This makes it necessary to enlarge transistor size. Accordingly, it is possible to adopt an arrangement in which the k-bit signal that is supplied to the logic circuits is further divided into U sub-bit groups each containing two or more bits, and a logic circuit is provided for every sub-bit group. In the example depicted in FIG. 10, the four signals B0 to B3 are input to each NAND gate. In FIG. 11, however, the signals B0 to B3 are divided into (B0,B1) and (B2,B3), and each NAND gate is divided into a NAND gate 1211b to which (B0,B1) are input and a NAND gate 1211c to which (B2,B3) are input.
It should be noted that in FIG. 11, only the first three reference voltages Vref0 to Vref3 of the 16 reference voltages are shown, and the remaining reference voltage are not illustrated. The circuit arrangement is similar with regard to the remaining reference voltages Vref4 to Vref15.
Further, in the example illustrated in FIG. 10, the outputs of the logic circuits 1211a are connected to respective ones of the single switches. If each of these logic circuits is divided into the two NAND gates, namely the NAND gate 1211b to which B0, B1 are input and the NAND gate 1211c to which B2, B3 are input, as illustrated in FIG. 11, then each switch also is divided into two switches and these are connected in series.
If (B0, B1, B2, B3)=(0, 1, 0, 0), for example, holds in FIG. 11, then the outputs C, E, F, G and H take on the LOW level and the remaining outputs take on the HIGH level among the logic circuits A to H in FIG. 11.
In FIG. 11, therefore, switches c, e, f, g and h among the switches a to h turn ON. A path, in which two serially connected switches turn ON, from a reference voltage to the output terminal T of the sub-decoder is solely the path through switches c and g, namely the path of reference voltage Vref2. Accordingly, the output of the sub-decoder 121 is Vref2.
With regard to a plurality of logic circuits for which input sub-bit groups, inclusive of logic (B0 and B0B, etc.), are identical within the same sub-decoder, these may be eliminated with the exception of at least one, and the switches connected to the outputs of the deleted logic circuits may be connected to the output of a logic circuit that is not eliminated.
For example, in FIG. 11, logic circuits E, F, G, H among the logic circuits A to H all receive B2B and B3B as inputs and their outputs are always the same. This means that these logic circuits can be eliminated with the exception of one, as illustrated in FIG. 12. The output of a logic circuit I in FIG. 12 in such case is connected in common with the switches e, f, g. Adopting this expedient makes it possible to reduce the number of elements in the switch control circuit 1211.
Furthermore, in FIG. 12, the arrangement is such that switches e, f, g and h have either ends thereof, namely either their entrance or exit ports (either their sources or drains) connected in common and have their switch control ends (the gates of the transistors) connected in common. In this case the other ends of the four switches, namely the other of the entrance or exit ports, (the terminals not connected in common) can be made common to thereby form one switch.
FIG. 13 illustrates the structure obtained by making the switches e, f, g and h of FIG. 11 a single switch i by common connection. Adopting this expedient also makes it possible to reduce the number of elements of the switch circuit.
FIG. 14 is a diagram in which the operation described earlier in the specification is applied to all of the reference voltages Vref0 to Vref15.
The following will be understood from FIG. 14:
the inputs of logic circuits J1, K1, L1 and M1 are all B0B and B1B;
the inputs of logic circuits J2, K2, L2 and M2 are all B0 and B1B;
the inputs of logic circuits J3, K3, L3 and M3 are all B0B and B1; and
the inputs of logic circuits J4, K4, L4 and M4 are all B0 and B1.
Accordingly, as described earlier in the specification, these logic circuits can be eliminated with the exception of one and can be unified to logic circuits J, K, L and M, respectively, in FIG. 15 by common connection. The logic circuit J of FIG. 15 is the result of unifying logic circuits J1, K1, L1 and M1 of FIG. 14 by common connection, the logic circuit K of FIG. 15 is the result of unifying logic circuits J2, K2, L2 and M2 of FIG. 14 by common connection, logic circuit L of FIG. 15 is the result of unifying logic circuits J3, K3, L3 and M3 of FIG. 14 by common connection, and logic circuit M of FIG. 15 is the result of unifying logic circuits J4, K4, L4 and M4 of FIG. 14 by common connection. Adopting this expedient makes it possible to reduce the number of elements in the switch control circuit.
Although FIGS. 10 to 15 illustrate examples in which NAND gates are used as the logic circuits and PMOS transistors as the switches, arrangements other than these may be adopted for the logic circuits and switches.
FIG. 16 illustrates an example in which NOR gates are used as logic circuits and NMOS transistors as switches. In a case where NOR gates are used as the logic circuits, the output of the NOR gate is H if the bit signals input to the NOR gate are all L. Accordingly, only one among k2 NOR gates will output the HIGH level with respect to certain input bit data, and therefore only one NMOS transistor of the switch circuit will turn ON.
FIG. 17 illustrates an example in which NAND gates are used as logic circuits and CMOS switches, which include a PMOS transistor and an NMOS transistor, are used as switches. Each logic circuit (NAND gate) in the example of FIG. 17 outputs the LOW level if the bit signals input thereto are all at the HIGH level. Accordingly, only one among k2 NAND gates will output the LOW level with respect to certain input bit data.
Accordingly, if the output of the NAND gate is connected to the PMOS transistor of the switch circuit and a signal obtained by inverting the signal from the NAND gate is connected to the NMOS transistor, only one CMOS switch will turn ON.
FIG. 18 illustrates an example in which NOR gates are used as logic circuits and CMOS switches as switches. Each logic circuit (NOR gate) in FIG. 18 outputs the HIGH level if the bit signals input thereto are all at the LOW level. Accordingly, only one among k2 NOR gates will output the HIGH level with respect to certain input bit data. If the output of the NOR gate is connected to the NMOS transistor of the switch circuit and a signal obtained by inverting the signal from the NOR gate is connected to the PMOS transistor, therefore, only one CMOS switch will turn ON.
Next, a case where the decoder 12 in FIG. 1 has a single output terminal (the amplifying circuit 13 has a single input terminal) will be described as a third embodiment of the present invention. That is, the decoder 12 receives as inputs the m reference voltages that differ from one another, selects n voltages, inclusive of voltages that may be identical, from among the m reference voltages based upon a selecting signal, and successively outputs the selected voltages to a single output terminal. Further, the amplifying circuit 13 successively receives as inputs the n voltages selected at the single output terminal and outputs voltages obtained by taking the weighted mean of the entered n voltages at the ratio 2n−1:2n−2: . . . :20. The single output terminal will be expressed by T0 below, and the n voltages successively supplied to the terminal T0 will be denoted by VQ1, VQ2, . . . , and VQn.
FIG. 19A is a diagram illustrating an example of the configuration of the amplifying circuit 13 according to this embodiment, and FIG. 19B is a timing chart illustrating the operation of the switches of FIG. 19A. With reference to FIGS. 19A and 19B, assume that switches SG1 to SGn are turned OFF in time periods ta1 to tan, and assume the following with regard to switches SF1 to SFn:
only switch SF1 is turned on in time period ta1;
only switch SF2 is turned on in time period ta2;
. . . .
only switch SFn is turned on in time period tan.
In such case, the n voltages VQ1, VQ2, . . . , and VQn successively supplied to the input terminal T0 are stored in capacitors C1 to Cn via switches SF1 to SFn, respectively.
If switches SF1 to SFn are all turned OFF and switches SG1 to SGn are all turned ON in the next time period tb, then charge is redistributed among the capacitors C1 to Cn. By setting the capacitance ratio of the capacitors C1 to Cn to the ratio 2n−1:2n−2: . . . :20 beforehand, the non-inverting input voltage of voltage follower A3 becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
Accordingly, the output voltage of the voltage follower A3 also becomes a voltage that is the result of taking the weighted mean of the voltages VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
FIG. 20A is a diagram illustrating another example of the configuration of the amplifying circuit 13 in this embodiment, and FIG. 20B is a timing chart for describing the operation of switches in FIG. 20A. In a manner similar to that of the arrangement shown in FIG. 5A, the example shown in FIG. 20A is such that offset in voltage follower A4 can be cancelled.
In accordance with FIGS. 20A and 20B, assume that switches SJ1 to SJn are turned OFF and switch S1 is turned ON in time periods ta1 to tan, and assume the following with regard to switches SH1 to SHn:
only switch SH1 is turned on in time period ta1;
only switch SH2 is turned on in time period ta2;
. . . .
only switch SHn is turned on in time period tan.
In such case, the n voltages VQ1, VQ2, . . . , VQn successively supplied to input terminal T1 are stored in capacitors C1 to Cn via switches SH1 to SHn, respectively.
On the other hand, if we let dV represent offset of voltage follower A4, then the output of the voltage follower will be Vref+dV and this is supplied to the other ends of the capacitors C1 to Cn via the switch SD. Consequently, voltages [VQ1−(Vref+dV)], . . . [VQn−(Vref+dV)] are stored in the capacitors C1 to Cn, respectively.
If switches SH1 to SHn and switch S1 are turned OFF and switches SJ1 to SJn are turned ON in the next time period tb, then charge is redistributed among the capacitors C1 to Cn. At the same time, the output of the voltage follower and the inverting input terminal (−) are connected via the capacitors C1 to Cn. As a result, the offset dV is cancelled and the output of the voltage follower A4 becomes as follows:

[(C1×VQ1+C2×VQ2+ . . . +Cn×VQn)/(C1+C2+ . . . +Cn)

By setting the capacitance ratio of the capacitors C1 to Cn to the ratio 2n−1:2n−2: . . . :20 beforehand, the output voltage of the voltage follower A4 becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
FIG. 43A is a diagram illustrating a further example of the configuration of the amplifying circuit 13. As shown in FIG. 43A, the amplifying circuit 13 includes the differential amplifying circuit 131 having the plurality of differential pairs described above with reference to FIG. 40; a plurality (n) of switches SP1 to SPn having first ends connected in common with the terminal T0 and second ends connected to respective ones of the plurality (n) of input terminals Vin—1 to Vin—n of the differential amplifying circuit 131; and n voltage-holding capacitors Chld connected between the second ends of the n switches SP1 to SPn and ground. FIG. 43B is a timing chart illustrating the operation of the switches shown in FIG. 43A. With reference to FIGS. 43A and 43B, first assume that the following holds:
only switch SP1, is turned on in time period ta1;
only switch SP2 is turned on in time period ta2;
. . . .
only switch SPn is turned on in time period tan.
In such case, the n voltages VQ1, VQ2, . . . , VQn successively supplied to input terminal T0 are stored in the corresponding voltage-holding capacitors Chld via respective ones of the switches SP1 to SPn, respectively.
If switches SP1, to SPn are all turned OFF in the next time period tb, then a state is obtained in which the voltages VQ1 to VQn are supplied to the n input terminals Vin—1 to Vin—n of the differential amplifying circuit 131 and the output voltage Vout becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
In FIG. 44A, which is another example of the configuration of an amplifying circuit, the switch SPn and the voltage-holding capacitor corresponding to the switch SPn in FIG. 43A have been removed, and the nth input terminal Vin—1 of the amplifying circuit 13 is connected directly to the terminal T0. FIG. 44B is a timing chart illustrating the operation of the switches in FIG. 44A. With reference to FIGS. 44A and 44B, first assume that the following holds:
only switch SQ1 is turned on in time period ta1;
only switch SQ2 is turned on in time period ta2;
. . . .
only switch SQn−1 is turned on in time period tan−1.
In such case, the n voltages VQ1, VQ2, . . . , VQn−1 successively supplied to input terminal T0 are stored in the corresponding voltage-holding capacitors Chld via respective ones of the switches SQ1 to SQn−1, respectively.
In the succeeding time periods tan and tb, a state is obtained in which the voltages VQ1 to VQn are supplied to the n differential pairs of the differential amplifying circuit 131, and the output voltage Vout becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
If the configuration of FIG. 44A is compared with that of FIG. 43A, it will be understood that the number of switches and number of voltage-holding capacitors can be reduced.
It should be noted that the amplifying circuit 13 is not limited to the examples of structure described above. Any structure will suffice so long as it is capable of outputting a voltage obtained by taking the weighted mean of VQ1 to VQn, which are successively input from the terminal T0, at the ratio 2n−1:2n−2: . . . :20.
An example of the configuration of the decoder 12 will be described next. FIG. 21 is a diagram illustrating a specific example of the decoder 12. As shown in FIG. 21, the decoder 12 receives an (n×k)-bit (where k is an integer and k>=2 holds) digital signal and the m (=2k) reference voltages as inputs and includes one selected-voltage output terminal T1; one bit-group selecting circuit 122 for successively selecting and outputting a total of n bit groups one group at a time from bit groups BG1 to BGn obtained by dividing the digital signal into n groups of k bits each; and a single sub-decoder 121 for receiving the m reference voltages as inputs and outputting one voltage from among the m reference voltages based upon the digital signal of the bit group selected by the bit-group selecting circuit 122. The single output of the sub-decoder 121 is connected to the single selected-voltage output terminal. The sub-decoder 121 selects n (n>=3) identical or different voltages from among the m reference voltages based upon the digital signal and successively supplies these voltages to the single selected-voltage output terminal T1.
One example of the configuration of the bit-group selecting circuit 122 in FIG. 21 will now be described. FIG. 22 is a diagram illustrating a specific example of the bit-group selecting circuit 122 according to this embodiment. As shown in FIG. 22, bit-group selecting signals Ctl1 to Ctln for selecting one group from bit group 1 (BG1) to bit group n (BGn) are input to the bit-group selecting circuit 122.
FIG. 23 is a timing chart illustrating the timing operation of the bit-group selecting signals Ctl1 to Ctln. Time periods ta1 to tan in FIG. 23 are synchronized to switches SF1 to SFn and switches SH1 to SHn of the amplifier 13 described earlier in the specification.
In accordance with FIG. 23, bit groups are selected as follows:
bit group 1 (BG1) is selected in time period ta1;
bit group 2 (BG2) is selected in time period ta2;
. . . ,
bit group n (BGn) is selected in time period tan.
With regard to time period tb, this is the output time period of the amplifying circuit 13 and, hence, no bit group is selected.
Various structures described earlier in the specification and in FIGS. 6 to 18 can be used with regard to the sub-decoder 121.
In accordance with this embodiment, reference voltages are selected from among the m reference voltages as follows:
one reference voltage conforming to the bit group 1 (BG1) is selected in time period ta1;
one reference voltage conforming to the bit group 2 (BG2) is selected in time period ta2;
. . . , and
one reference voltage conforming to the bit group n (BGn) is selected in time period tan.
Thus, n reference voltages, inclusive of reference voltages that may be identical, are successively selected and output to the output terminal T1, of decoder 12 in the period from ta1 to tan.
By operating the amplifier 13 in sync with the time periods ta1 to tan, a maximum of mn mutually different voltage levels can be output in accordance with the digital signal of k×n bits applied thereto.
Next, a case where the decoder 12 of FIG. 1 has r (2<=r<=n−1) output terminals (the amplifying circuit 13 has r input terminals) will be described as a fourth embodiment of the present invention. That is, the decoder 12 receives as inputs the m reference voltages that differ from one another, selects n voltages, inclusive of voltages that may be identical, from among the m reference voltages based upon a selecting signal, and successively outputs the selected voltages to r output terminals.
Further, the amplifying circuit 13 successively receives as inputs the n voltages selected at the r output terminals and outputs voltages obtained by taking the weighted mean of the entered n voltages at the ratio 2−1:2n−2: . . . :20. The r output terminals will be expressed by T0 to Tr below, and the n voltages successively supplied to the terminals T0 to Tr will be denoted by VQ1, VQ2, . . . , and VQn, respectively.
FIG. 24A is a diagram illustrating an example of the configuration of the amplifying circuit 13 according to this embodiment, and FIG. 24B is a timing chart for describing ON/OFF control of switches in FIG. 24A. The definition J=N/r will hold in the description that follows.
In accordance with FIGS. 24A and 24B, switches SL1 to SLn are turned OFF in time periods ta1 to ta(J).
If r switches SK1, SK(J+1), . . . , and SK[(r−1)J+1] among switches SK1 to SKn are turned ON in time period ta1, then r voltages VQ1, VQ(J+1), . . . , and VQ[(r−1)J+1] supplied to input terminals T1 to Tr are stored up in capacitors CK1, CK(J+1), . . . , and CK[(r−1)J+1], respectively.
Next, in time period ta2, if r switches SK2, SK(J+2), . . . , and SK[(r−1)J+2] are turned ON, then r voltages VQ2, VQ(J+2), . . . , and VQ[(r−1)J+2] supplied to input terminals T1 to Tr are stored up in capacitors CK2, CK(J+2), . . . , and CK[(r−1)J+2], respectively.
By repeating a similar operation up to time period ta(J), the n voltages VQ1, VQ2, . . . , and VQn selected in the decoder 12 are stored in the capacitors C1 to Cn, respectively.
If switches SK1 to SKn are turned OFF and switches SL1 to SLn are turned ON in the next time period tb, then charge is redistributed among the capacitors C1 to Cn. By setting the capacitance ratio of the capacitors C1 to Cn to the ratio 2n−1:2n−2: . . . :20 beforehand, the non-inverting input voltage of voltage follower A5 becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20. Accordingly, the output voltage of the voltage follower A5 also becomes a voltage that is the result of taking the weighted mean of the voltages VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
FIG. 25A is a diagram illustrating another example of the configuration of the amplifying circuit 13 in this embodiment, and FIG. 25B is a timing chart illustrating ON/OFF control of switches in FIG. 25A. The example shown in FIG. 25 is capable of canceling offset in voltage follower A6 in a manner similar to that of the example illustrated in FIG. 3.
In accordance with FIGS. 25A and 25B, switches SO1 to SOn are turned OFF and switch SN is turned ON in time periods ta1 to ta(J).
If r switches SM1, SM(J+1), . . . , and SM[(r−1)J+1] among switches SM1 to SMn are turned ON in time period ta1, then r voltages VQ1, VQ(J+1), . . . , and VQ[(r−1)J+1] supplied to input terminals T1 to Tr are stored up in capacitors CM1, CM(J+1), . . . , and CM[(r−1)J+1], respectively.
Next, in time period ta2, if r switches SM2, SM(J+2), . . . , and SM[(r−1)J+2] are turned ON, then r voltages VQ2, VQ(J+2), . . . , and VQ[(r−1)J+2] supplied to input terminals T1 to Tr are stored up in capacitors CK2, CK(J+2), . . . , and CK[(r−1)J+2], respectively.
By repeating a similar operation up to time period ta(J), the n voltages VQ1, VQ2, . . . , and VQn selected in the decoder 12 are supplied to first ends of the capacitors C1 to Cn, respectively.
On the other hand, if we let dV represent offset of voltage follower A6, then the output of the voltage follower A6 will be Vref-oc+dV and this is supplied to the second ends of the capacitors C1 to Cn via the switch SD. Consequently, voltages [VQ1−(Vref+dV)], . . . [VQn−(Vref+dV)] are stored in the capacitors C1 to Cn, respectively.
If switches SM1 to SMn and switch SD are turned OFF and switches SO1 to SOn are turned ON in the next time period tb, then charge is redistributed among the capacitors C1 to Cn. At the same time, the output terminal of the voltage follower A6 and the inverting input terminal (−) are connected via the capacitors C1 to Cn. As a result, the offset dV is cancelled. Accordingly, the output of the voltage follower A6 becomes as follows:

[(C1×VQ1+C2×VQ2+ . . . +Cn×VQn)/(C1+C2+ . . . +Cn)

By setting the capacitance ratio of the capacitors C1 to Cn to the ratio 2n−1:2n−2: . . . :20 beforehand, the output voltage of the voltage follower A6 becomes as follows:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the output voltage Vout of the voltage follower A6 is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
FIG. 45A is a diagram illustrating another example of the configuration of the amplifying circuit 13. As shown in FIG. 45A, the amplifying circuit 13 includes the differential amplifying circuit 131 having the plurality of differential pairs described above with reference to FIG. 40; n switches SR1 to SRn and voltage-holding capacitors Chld corresponding to respective ones of the n switches SR1 to SRn. More specifically, first ends of J switches (where J=n/r holds) SR1 to SR(J) are connected in common with input terminal T1, and first ends of J switches SR(J+1) to SR(J2) are connected in common with input terminal T2. Similarly, first ends of J switches SR[(r−1)×J+1] to SRn are connected in common with input terminal Tr. The second end of each switch is connected to the corresponding input terminal of the amplifying circuit 13, and the voltage-holding capacitors Chld are connected between second ends of the switches and ground. FIG. 45B is a timing chart illustrating the operation of the switches shown in FIG. 45A. With reference to FIGS. 45A and 45B, if r switches SR1, SR(J+1), . . . , SR[(r−1)J+1] among switches SR1 to SRn are turned ON in time period ta1, then r voltages VQ1, VQ(J+1), . . . , and VQ[(r−1)J+1] supplied to input terminals T1 to Tr are stored up in respective ones of the charge-holding capacitors Chld.
Next, in time period ta2, if r switches SR2, SR(J+2), . . . , and SR[(r−1)J+2] are turned ON, then r voltages VQ2, VQ(J+2), . . . , and VQ[(r−1)J+2] supplied to input terminals T1 to Tr are stored up in respective ones of the capacitors Chld.
By repeating a similar operation up to time period ta(J), the n voltages VQ1, VQ2, . . . , and VQn selected in the decoder 12 are stored in the charge-holding capacitors Chld.
If switches SR1 to SRn are all turned OFF in the next time period tb, then a state is obtained in which the voltages VQ1 to VQn are supplied to the n differential pairs of the differential amplifying circuit 131, and the output voltage Vout is given by the following:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the voltage is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
The arrangement shown in FIG. 46A is obtained by eliminating the switches SR(J), SR(2J), . . . , and SRn and the voltage-holding capacitors between the switches SR(J), SR(2J), . . . , and SRn and the differential amplifying circuit 131 in FIG. 45A. First ends of J−1 (where J=n/r holds) switches SS1 to SS(J−1) are connected in common with the input terminal T1, switch SR(J) in FIG. 45A is eliminated and the input terminal T1 is connected directly to the corresponding input terminal of the amplifying circuit 13. First ends of J−1 switches SS(J+1) to SS(2J−1) are connected in common with the input terminal T2, switch SR(2J) in FIG. 45A is eliminated and the input terminal T2 is connected directly to the corresponding input terminal of the amplifying circuit 13. Similarly, first ends of J−1 switches Ss[(r−1)×j+1] to SS(n−1) are connected in common with the input terminal Tr, switch SR(n) in FIG. 45A is eliminated and the input terminal Tr is connected directly to the corresponding input terminal of the amplifying circuit 13. FIG. 46B is a timing chart illustrating the operation of the switches shown in FIG. 46A. With reference to FIGS. 46A and 46B, if r switches SS1, SS(J+1), . . . , and SS[(r−1)J+1] among switches SS1 to SSn are turned ON in time period ta1, then r voltages VQ1, VQ(J+1), . . . , and VQ[(r−1)J+1] supplied to input terminals T1 to Tr are stored up in respective ones of the charge-holding capacitors Chld.
Next, in time period ta2, if r switches SS2, SS(J+2), . . . , and SS[(r−1)J+2] are turned ON, then r voltages VQ2, VQ(J+2), . . . , and VQ[(r−1)J+2] supplied to input terminals T1 to Tr are stored up in respective ones of the charge-holding capacitors Chld.
By repeating a similar operation up to the time period ta(J−1), a state is obtained in which the voltages VQ1 to VQn are supplied to the n differential pairs of the differential amplifying circuit 131, and the output voltage Vout becomes as follows in the succeeding time periods ta(J) and tb:

(2n−1×VQ1+2n−2×VQ2+ . . . +20×VQn)/(2n−1+2n−2+ . . . +20)

That is, the output voltage Vout is the result of taking the weighted mean of VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
The structure shown in FIG. 46A makes it possible to somewhat reduce (by r) the number of switches and number of voltage-holding capacitors in comparison with the structure shown in FIG. 45A.
It should be noted that the configuration of the amplifying circuit 13 is not limited to the example. Any structure will suffice so long as it is possible to output a voltage obtained by taking the weighted mean of the successively input voltages VQ1 to VQn at the ratio 2n−1:2n−2: . . . :20.
FIG. 26 is a diagram illustrating a specific example of the configuration of decoder 12 according to this embodiment. As shown in FIG. 26, the decoder 12 receives an (n×k)-bit (where k is an integer and k>=2 holds) digital signal and the m (=2k) reference voltages as inputs and includes r selected-voltage output terminals (T1 to Tr); r bit-group selecting circuits 123 each for successively selecting and outputting a total of J bit groups one group at a time from J groups of bit groups among bit groups obtained by dividing the digital signal into n groups of k bits each; and r sub-decoders 121 each for receiving the m reference voltages as inputs and outputting one voltage from among the m reference voltages based upon the digital signal of the bit group selected by the respective one of the bit-group selecting circuits 123. The r outputs of the sub-decoders 121 are connected to respective ones of the r selected-voltage output terminals. The decoder 12 selects n identical or different voltages from among the m reference voltages based upon the digital signal and successively outputs these voltages to the r selected-voltage output terminals T1 to Tr.
The structure of the bit-group selecting circuits 123 of FIG. 26 will be described next. FIG. 27 is a diagram illustrating a specific example of the bit-group selecting circuit 123 according to this embodiment. As shown in FIG. 27, bit-group selecting signals Ctl1 to Ctlj for selecting one group from J groups of bit groups (BG1 to BGJ in FIG. 27) are input to the bit-group selecting circuit 123. FIG. 28 is a timing chart illustrating the timing operation of the bit-group selecting signals Ctl1 to Ctlj. Time periods ta1 to taJ in FIG. 28 are synchronized to switches SK1 to SKn and switches SM1 to SMn of the amplifier 13 described earlier in the specification above.
In accordance with FIGS. 27 and 28, bit groups are selected as follows:
r bit groups BG1, BGJ+1, . . . , and BGN−J+1 are selected in time period ta1;
r bit groups BG2, BGJ+2, . . . , and BGn−J+2 are selected in time period ta2;
. . . ,
r bit groups BGJ, BG2J, . . . , and BGn are selected in time period ta1.
With regard to time period tb, this is the output time period of the amplifying circuit 13 and, hence, no bit group is selected.
The structures described earlier in the specification and in FIGS. 6 to 18 can be used with regard to the sub-decoder 121.
In accordance with this embodiment, reference voltages are selected from among the m reference voltages as follows:
r reference voltages conforming to BG1, BGJ+1, . . . , and BGn−J+1 are selected in time period ta1;
r reference voltages conforming to BG2, BGJ+2, . . . , and BGn−J+2 are selected in time period ta2;
. . . , and
r reference voltages conforming to BGJ, BGJ2, . . . , and BGn are selected in time period ta1.
Thus, n reference voltages, inclusive of reference voltages that may be identical, are successively selected and output to the r outputs terminal T1 to Tr of decoder 12 in the period from ta1 to taJ.
By operating the amplifier 13 in sync with the time periods ta1 to taJ, a maximum of mn mutually different voltage levels can be output in accordance with the digital signal of k×n bits applied thereto.
A fifth embodiment of the present invention will now be described. FIG. 29 illustrates an arrangement in which the present invention has been applied to the data driver of a display device such as a liquid crystal display device. As shown in FIG. 29, a digital-to-analog converter (DAC) 11 is constituted by any of first to fourth embodiments. Circuit blocks such as a latch address selector and latch are similar to those of FIG. 38. The reference voltage (grayscale voltage) generating circuit 14 generates and outputs m reference voltages with respect to mn output levels and is shared by the plurality of DACs 11. If the m reference voltages are set according to Equation (1), then mn output levels of the DACs will be linear.
It should be noted that each DAC 11 of FIG. 29 may be constituted by a plurality of blocks, wherein mn output levels serve as one block. In this case, the reference voltage generating circuit 14 also would be so adapted that m reference voltages are provided in the equivalent number of blocks, and the circuit also would be constructed in accordance with the number of blocks.
Further, in FIG. 29, the decoders 12 and amplifying circuits 13 are such that the power-supply voltages thereof are decided by the voltage (grayscale voltage) generated by the reference voltage generating circuit 14. On the other hand, the power-supply voltage can be set separately for latch address selector 921 and latch 922, and for the purpose of reducing size and conserving power, this can be set to a power-supply voltage lower than the power-supply voltage of the reference (grayscale) voltage generating circuit, decoders and amplifying circuits.
In such case a level shifting circuit would be provided. If such an arrangement is applied to the present invention, the level shifting circuit would preferably be provided between the latch 922 and decoders 12.
FIG. 30 illustrates a case where the present invention has been applied to a display device. The data driver 980 in FIG. 30 is the data driver comprising the arrangement of FIG. 29. Here a linear output is obtained in response to an input of data of n×k bits. In a case where a linear-output data driver is used, grayscale voltages that conform to the gamma characteristic of the display device [liquid crystal or organic electroluminescent (EL) element] can be output by assigning grayscale voltages that conform to the display-device gamma characteristic from among a multiplicity of linear output levels. The data driver therefore has a number of linear levels that is greater than the number of display tones. In FIG. 30, the device includes a data conversion table 991 for converting L-bit data that corresponds to display tones to (n×k)-bit data (L<n×k) that corresponds to linear levels, and a data converting circuit 990 for performing a data conversion based upon the data conversion table 991. The data conversion table 991 ideally is one made to conform to the gamma curve of a liquid crystal or to the characteristics of each of R, G, B of liquid crystal or organic EL device, by way of example. It will suffice if the data conversion table 991 and data converting circuit 990 are such that (n×k)-bit data is supplied to the data driver 980, and it is simple to provide these in linkage with the display controller 940, as illustrated in FIG. 30.
By applying the DAC according to this embodiment to any data driver of such a display device, inclusive of systems other than those mentioned, the cost of the display device can be reduced and a reduction in frame width is possible. For example, it goes without saying that a differential amplifier according to the present invention is applicable, in a manner similar to that of a liquid crystal display device, to a display device such as an active-matrix drive organic EL display that presents a display by outputting multiple-level voltage signals to data lines.
The DAC described in the foregoing embodiments comprises MOS transistors. In the drive circuit of a liquid crystal display device, use may be made of MOS transistors (TFTs) comprising polycrystalline silicon. Further, although examples in which the invention is applied to an integrated circuit have been illustrated in the foregoing embodiments, the invention naturally is applicable to discrete elements as well.
Though the present invention has been described in accordance with the foregoing embodiments, the invention is not limited to this embodiment and it goes without saying that the invention covers various modifications and changes that would be obvious to those skilled in the art within the scope of the claims.
It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.
Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.

## Claims

1. A digital-to-analog converter comprising:
a reference voltage generating circuit that outputs m (where m is an integer greater than or equal to 4) reference voltages having voltage values which differ from one another;
a decoder that receives a digital signal and the m reference voltages, and selects and outputs n (where n is an integer greater than or equal to 3) identical or different reference voltages from among the m reference voltages on the basis of the received digital signal; and
an amplifying circuit that receives the selected n voltages and outputs to an output terminal, a voltage obtained by taking a weighted mean of the received n voltages at a ratio of 2n−1:2n−2: . . . :20;
wherein a maximum of mm voltage levels that differ from one another are allowed to be output to the output terminal in accordance with the received digital signal.

2. The digital-to-analog converter according to claim 1, wherein the m (where m is equal to 2K, where K is an integer greater than or equal to 2) reference voltages are set to a {1+(2n−1)×Σj=1K[αj×2(j−1)n]}th level (where α1, α2, . . . , and αK are 0 or 1) from among equally spaced mn voltage levels.

3. The digital-to-analog converter according to claim 1, wherein said decoder receives the digital signal, of n×k bits (where k is an integer greater than or equal to 2), as an input; and
the n×k bits of the digital signal are represented by D0, D1, . . . , and Dnk−1;
the digital signal is divided into n bit groups of k bits each;
an ith (where i is an integer which is greater than or equal to 1 and less than or equal to n) bit group comprises a digital signal of k bits [Di−1, Di−1+n, Di−130 2n, . . . , Di−1+(k−1)n]; and
n voltages are selected, for every bit group, from the m reference voltages in accordance with values of the bits of the bit group.

4. The digital-to-analog converter according to claim 1, wherein said decoder receives an (n×k)-bit (where k is an integer greater than or equal to 2) digital signal and the m (where m is equal to 2k) reference voltages as inputs and includes:
n selected-voltage output terminals; and
n sub-decoders, each of which receives the m reference voltages as inputs and outputs one voltage from among the m reference voltages based upon one bit group of digital signals from among bit groups obtained by dividing the digital signal into n groups of k digital signals each;
outputs of the n sub-decoders being connected to respective ones of said n selected-voltage output terminals;
said decoder selecting, and outputting to said n selected-voltage output terminals, the n (where n is an integer greater than or equal to 3) identical or different voltages from among the m reference voltages based upon the (n×k)-bit digital signal; and
said amplifying circuit that receives as inputs the n voltages selected at said n selected-voltage output terminals and outputs, from the output terminal, the voltage obtained by taking the weighted mean of the input n voltages at the ratio of 2n−1:2n−2: . . . :20.

5. The digital-to-analog converter according to claim 4, wherein said amplifying circuit includes:
a differential amplifying circuit having an output end and an inverting input terminal connected to the output terminal;
a first switch group comprising n switches each having a first end connected to a respective one of said n selected-voltage output terminals;
a second switch group comprising n switches connected between second ends of respective ones of the switches of said first switch group and a non-inverting input terminal of said differential amplifying circuit; and
n capacitors connected between respective ones of nodes of said first and second switch groups and a power supply.

6. The digital-to-analog converter according to claim 4, wherein said amplifying circuit includes:
a differential amplifying circuit having a non-inverting input terminal to which a reference voltage is supplied and an output end connected to the output terminal;
a first switch group comprising first to nth switches each having a first end connected to a respective one of said n selected-voltage output terminals;
a second switch group comprising n−1 switches each connected between a second end of an xth switch (where x is an integer which is greater than or equal to 1 and which is less than or equal to n−1) of said first switch group and a second end of an (x+1)th switch of said first switch group;
a switch connected between a second end of an nth switch of said first switch group and the output end of said differential amplifying circuit;
a switch connected between the output end of said differential amplifying circuit and an inverting input terminal of said differential amplifying circuit; and
n capacitors connected between second ends of respective ones of the first to nth switches of said first switch group and the inverting input terminal of said differential amplifying circuit.

7. The digital-to-analog converter according to claim 1, wherein said decoder receives an (n×k)-bit (where k is an integer greater than or equal to 2) digital signal and the m (where m is equal to 2k) reference voltages as inputs and includes:
and a single selected-voltage output terminal;
a bit-group selecting circuit; and
a sub-decoder;
said bit-group selecting circuit successively selecting and outputting a total of n bit groups one group at a time from bit groups obtained by dividing the digital signal into n groups of k bits each;
said sub-decoder receiving the m reference voltages as inputs and outputting one voltage from among the m reference voltages based upon the digital signal of the bit group selected by said bit-group selecting circuit;
the single output of said sub-decoder being connected to the single selected-voltage output terminal;
said decoder selecting, on a time-division basis, the n (n>=3) identical or different voltages from among the m reference voltages based upon the digital signal and successively supplying these voltages to the single selected-voltage output terminal;
said amplifying circuit receiving as inputs the n voltages successively supplied to the single selected-voltage output terminal and outputting, from the output terminal, the voltage obtained by taking the weighted mean of the input n voltages at the ratio of 2n−1:2n−2: . . . :20.

8. The digital-to-analog converter according to claim 7, wherein said amplifying circuit includes:
a differential amplifying circuit having an output end and an inverting input terminal connected to the output terminal;
a first switch group comprising n switches each having a first end connected to the single selected-voltage output terminal;
a second switch group comprising n switches connected between second ends of respective ones of the n switches of said first switch group and a non-inverting input terminal of said differential amplifying circuit; and
n capacitors connected between respective ones of nodes of said first and second switch groups and a power supply.

9. The digital-to-analog converter according to claim 7, wherein said amplifying circuit includes:
a differential amplifying circuit having a non-inverting input terminal to which a reference voltage is supplied and an output end connected to the output terminal;
a first switch group comprising first to nth switches each having a first end connected to the single selected-voltage output terminal;
a second switch group comprising n−1 switches each connected between a second end of an xth switch (where x is an integer which is greater than or equal to 1 and which is less than or equal to n−1) of said first switch group and a second end of an (x+1)th switch of said first switch group;
a switch connected between a second end of an nth switch of said first switch group and the output end of the differential amplifying circuit;
a switch connected between the output end of said differential amplifying circuit and an inverting input terminal of said differential amplifying circuit; and
n capacitors connected between second ends of respective ones of the first to nth switches of said first switch group and the inverting input terminal of the differential amplifying circuit.

10. The digital-to-analog converter according to claim 1, wherein said decoder receives an (n×k)-bit (where k is an integer greater than or equal to 2 and n is an integer greater than or equal to 3) digital signal and the m (where m is equal to 2k) reference voltages as inputs and includes:
r (where r is an integer which is greater than 1 and less than n) selected-voltage output terminals;
r bit-group selecting circuits; and
r sub-decoders;
said bit-group selecting circuits each successively selecting and outputting bit groups one group at a time from (n/r) bit groups among bit groups obtained by dividing the digital signal into n groups of k bits each;
said sub-decoders each receiving the m reference voltages as inputs and outputting one voltage from among the m reference voltages based upon the digital signal of the bit group selected by said bit-group selecting circuit;
r outputs of said sub-decoders being connected to respective ones of said r selected-voltage output terminals;
said decoder selecting, on a time-division basis, the n identical or different voltages from among the m reference voltages based upon the digital signal and successively supplying these voltages to said r selected-voltage output terminals;
said amplifying circuit receiving as inputs the n voltages successively supplied to said r selected-voltage output terminals and outputting, from the output terminal, the voltage obtained by taking the weighted mean of the input n voltages at the ratio of 2n−1:2n−2: . . . :20.

11. The digital-to-analog converter according to claim 10, wherein said amplifying circuit includes:
a differential amplifying circuit having an output end and an inverting input terminal connected to the output terminal;
a first switch group comprising a total of n switches in which first ends of n/r switches each are connected to a respective one of said r selected-voltage output terminals;
a second switch group comprising a total of n switches connected between second ends of respective ones of said n switches of said first switch group and a non-inverting input terminal of said differential amplifying circuit; and
n capacitors connected between respective ones of nodes of said first and second switch groups and a power supply.

12. The digital-to-analog converter according to claim 10, wherein said amplifying circuit includes:
a differential amplifying circuit having a non-inverting input terminal to which a reference voltage is supplied and an output end connected to the output terminal;
a first switch group comprising a total of n switches in which first ends of n/r switches each are connected to a respective one of said r selected-voltage output terminals;
a second switch group comprising n−1 switches each connected between a second end of an xth switch (where x is an integer which is greater than or equal to 1 and which is less than or equal to n−1) of said first switch group and a second end of an (x+1)th switch of said first switch group;
a switch connected between a second end of an nth switch of said first switch group and the output end of said differential amplifying circuit;
a switch connected between the output end of said differential amplifying circuit and an inverting input terminal of said differential amplifying circuit; and
n capacitors connected between second ends of respective ones of the first to nth switches of said first switch group and the inverting input terminal of said differential amplifying circuit.

13. The digital-to-analog converter according to claim 4, wherein said sub-decoder receives the m reference voltages and a bit group comprising k digital signals as inputs thereto;
the k digital signals of the bit group are represented by B0, B1, . . . , and B(k−1);
complementary signals of the k digital signals of the bit group are represented by B0B, B1B, . . . , and B(k−1)B;
SigN(D,p,q) is a function that returns DB (the complementary signal of D) when the remainder of p−1 divided by 2(q+1) is less than 2q, and returns D otherwise;
w, y are integers where w is greater than or equal to 1 and less than or equal to m and y is greater than or equal to 0 and less than or equal to k−1;
with regard to m paths connecting the m reference voltages and a single output terminal of said sub-decoder, a wth reference voltage and the single output terminal are connected via k switches controlled by respective ones of k control signals sigN[B(0),w,0], sigN[B(1),w,1], . . . , sigN[B(y),w,y], . . . , and sigN[B(k−1),w,k−1]; and
one of the m reference voltages is selected and output by the k bit digital signals of the bit group.

14. The digital-to-analog converter according to claim 13, wherein said switch includes an NMOS transistor having a gate to which the digital signal is input, and a drain and source one of which forms a input end of said switch and the other of which forms an output end of said switch.

15. The digital-to-analog converter according to claim 4, wherein said sub-decoder receives the m reference voltages and a bit group comprising k digital signals as inputs thereto;
the k digital signals of the bit group are represented by B0, B1, . . . , and B(k−1);
complementary signals of the digital signals of the bit group are represented by B0B, B1B, . . . , and B(k−1)B;
SigP(D,p,q) is a function that returns D when the remainder of p−1 divided by 2(q+1) is less than 2q, and returns DB (where DB is the complementary signal of D) otherwise;
w, y are integers where w is greater than or equal to 1 and less than or equal to m and y is greater than or equal to 0 and less than or equal to k−1;
with regard to m paths connecting the m reference voltages and a single output terminal of said sub-decoder, a wth reference voltage and the single output terminal are connected via k switches controlled by respective ones of k control signals sigP[B(0),w,0], sigP[B(1),w,1], . . . , sigP[B(y),w,y], . . . , and sigP[B(k−1),w,k−1]; and
one of the m reference voltages is selected and output by the k digital signal of the bit group.

16. The digital-to-analog converter according to claim 15, wherein said switch includes a PMOS transistor having a gate to which the digital signal is supplied, and a drain and source one of which forms an input end of said switch and the other of which forms an output end of said switch.

17. The digital-to-analog converter according to claim 4, wherein said sub-decoder receives the m reference voltages and a bit group comprising k digital signals as inputs thereto and includes:
a single output terminal;
a switch circuit that selects one of the m reference voltages;
a switch control circuit that outputs a signal for controlling said switch circuit, which selects one of the m reference voltages, by the k digital signals of the bit group;
said sub-decoder that selects and outputs one of the m reference voltages by the k-bit digital signal of the bit group.

18. The digital-to-analog converter according to claim 17, wherein said switch control circuit receives the k digital signal of the bit group as an input and includes 2k logic circuits that differ from one another in terms of the logic of input signals applied thereto, each of said logic circuit receiving a digital signal or a complementary signal thereof per bit of the bit group and turning a switch ON only in a case where the input k digital signals are all “1”s or all “0”s.

19. The digital-to-analog converter according to claim 18, wherein the input k digital signals are divided into U sub-bit groups each of which includes two or more digital signals;
U logic circuits are provided as the logic circuits of said switch control circuit and each receives a respective one of the sub-bit groups as an input and outputs a signal that turns a switch ON only in a case where the input signals of the sub-bit group are all “1”s or all “0”s;
each of the switches in the switch circuit that change over ON/OFF of the connection of the reference voltages to the output is constructed by a group of U switches serially arrayed; and
said U switches are ON/OFF-controlled by respective ones of switch control signals that have been output by said U logic circuits.

20. The digital-to-analog converter according to claim 7, wherein said amplifying circuit includes:
a differential amplifying circuit for outputting from the output terminal a voltage obtained by taking the weighted mean of n voltages, which are supplied to respective ones of first to nth input terminals, at a ratio of 21−1:2n−2: . . . :20;
first to nth switches having first ends connected in common with the single selected-voltage output terminal and having second ends connected to respective ones of the first to nth input terminals; and
first to nth capacitors connected between second ends of respective ones of the first to nth switches and a low-potential power supply.

21. The digital-to-analog converter according to claim 7, wherein said amplifying circuit includes:
a differential amplifying circuit that outputs from the output terminal a voltage obtained by taking the weighted mean of n voltages, which are supplied to respective ones of first to nth input terminals, at a ratio of 2n−1:2n−2: . . . :20;
first to (n−1)th switches having first ends connected in common with the single selected-voltage output terminal and having second ends connected to respective ones of the first to (n−1)th input terminals; and
first to (n−1)th capacitors connected between second ends of respective ones of the first to (n−1)th switches and a low-potential power supply;
the nth terminal of said differential amplifying circuit being connected to said selected-voltage output terminal.

22. The digital-to-analog converter according to claim 10, wherein said amplifying circuit includes:
a differential amplifying circuit that outputs from the output terminal a voltage obtained by taking the weighted mean of n voltages, which are supplied to respective ones of first to nth input terminals, at a ratio of 2n−1:2n−2: . . . :20;
with regard to each selected-voltage output terminal of said r selected-voltage output terminals,
J (where J=n/r holds) switches having first ends connected in common with said selected-voltage output terminal and having second ends connected to corresponding input terminals of said differential amplifying circuit; and
capacitors connected between second ends of respective ones of said switches and a low-potential power supply.

23. The digital-to-analog converter according to claim 10, wherein said amplifying circuit includes:
a differential amplifying circuit that outputs from the output terminal a voltage obtained by taking the weighted mean of n voltages, which are supplied to respective ones of first to nth input terminals, at a ratio of 2n−1:2n−2: . . . :20;
with regard to each selected-voltage output terminal of said r selected-voltage output terminals,
J−1 (where J=n/r holds) switches having first ends connected in common with said selected-voltage output terminal and having second ends connected to corresponding input terminals of said differential amplifying circuit; and
capacitors connected between second ends of respective ones of said J−1 switches, whose first ends are connected to said selected-voltage output terminal, and a low-potential power supply;

with regard to each selected-voltage output terminal of said r selected-voltage output terminals, no Jth switch is provided and said selected-voltage output terminal is connected directly to a corresponding input terminal of said differential amplifying circuit.

24. The digital-to-analog converter according to claim 20, wherein said amplifying circuit comprises a differential amplifying circuit that includes:
first to nth input terminals;
an output terminal;
first to nth differential pairs;
first to nth current sources which supply said first to nth differential pairs with current, respectively; and
a load circuit connected in common with output pairs of said first to nth differential pairs;
in an ith differential pair (where i is an integer which is greater than or equal to 1 and is less than or equal to n), one input pair is connected to an ith input terminal and the other input pair is connected to said output terminal;
one output pairs of said first to nth differential pairs are connected together in common, and the other output pairs of said first to nth differential pairs are connected together in common;
said differential amplifying circuit further including an amplifier stage having an input end that is connected to a node at which the one output pairs of said first to nth differential pairs are connected together in common, and an output end connected to said output terminal;
said load circuit being connected to a node at which the one output pairs of said first to nth differential pairs are connected together in common, and to a node at which the other output pairs of said first to nth differential pairs are connected together in common.

25. The digital-to-analog converter according to claim 24, wherein a ratio of the sizes of transistors of said first to nth differential pairs is set to 2n−1:2n−2: . . . :20;
a ratio of values of currents that flow into said first to nth current sources is set to 2n−1:2n−2: . . . :20; and
said output terminal of said differential amplifying circuit outputs a voltage obtained by taking the weighted mean of n voltages, which are supplied to said first to nth input terminals of said differential amplifying circuit, at the ratio 2n−1:2n−2: . . . :20.

26. The digital-to-analog converter according to claim 24, wherein each of said first to nth differential pairs comprises a plurality of transistors all of the same size, and a ratio of numbers of transistor pairs constituting said first to nth differential pairs is set to 2n−1:2n−2: . . . :20;
a differential pair that, which includes a plurality of transistor pairs, among said first to nth differential pairs includes a plurality of transistors connected in parallel between respective ones of output pairs of said differential pair and a current source corresponding to said differential pair;
a ratio of values of currents that flow into said first to nth current sources is set to 2n−1:2n−2: . . . :20; and
said output terminal of said differential amplifying circuit outputs a voltage obtained by taking the weighted mean of n voltages, which are supplied to said first to nth input terminals of said differential amplifying circuit, at the ratio 2n−1:2n−2: . . . :22.

27. The digital-to-analog converter according to claim 19, wherein with regard to a plurality of logic circuits for which input sub-bit groups, inclusive of logic, are identical within the same sub-decoder, the logic circuits are eliminated with the exception of at least one; and
switches connected to the outputs of said eliminated logic circuits are connected to the output of a logic circuit that is not eliminated.

28. The digital-to-analog converter according to claim 17, wherein at least one logic circuit included in said switch control circuit is a NAND gate, which receives a plurality of digital signals of an input bit group or sub-bit group, and which outputs the switch control signal; and
at least one of said switches included in said switch circuit is a PMOS switch having a gate to which the switch control signal is connected, and a source and drain one of which is connected to a terminal to which the reference voltage is supplied or to a switch connected in series with said switch, and the other of which is connected to one terminal among said n output terminals or to a switch connected in series with said switch; or
a CMOS switch comprising:
a PMOS transistor having a gate to which the switch control signal is connected, and having a source and drain one of which is connected to a terminal to which the reference voltage is supplied or to a switch connected in series with said switch, and the other of which is connected to one terminal among said n output terminals or to a switch connected in series with said switch, and
an NMOS transistor having a gate to which a complementary signal of the switch control signal is connected, and having one of a source and drain one of which is connected to a terminal to which the reference voltage is supplied or to a switch connected in series with said switch, and the other of which is connected to one terminal among said n output terminals or to a switch connected in series with said switch.

29. The digital-to-analog converter according to claim 17, wherein at least one logic circuit included in said switch control circuit is a NOR gate, which receives a plurality of digital signals of an input bit group or sub-bit group, and which outputs the switch control signal; and
at least one of said switches included in said switch circuit is a PMOS switch having a gate to which the switch control signal is connected, and a source and drain one of which is connected to a terminal to which the reference voltage is supplied or to a switch connected in series with said switch, and the other of which is connected to one terminal among said n output terminals or to a switch connected in series with said switch; or
a CMOS switch comprising:
a PMOS transistor having a gate to which the switch control signal is connected, and a source and drain one of which is connected to a terminal to which the reference voltage is supplied or to a switch connected in series with said switch, and the other of which is connected to one terminal among said n output terminals or to a switch connected in series with said switch, and
an NMOS transistor having a gate to which a complementary signal of the switch control signal is connected, and a source and drain one of which is connected to a terminal to which the reference voltage is supplied or to a switch connected in series with said switch, and the other of which is connected to one terminal among said n output terminals or to a switch connected in series with said switch.

30. A data driver for a display device, said data driver comprising:
a grayscale voltage generating circuit that generates a plurality of voltage levels;
a decoder circuit that outputs at least two voltages, which have been selected from said plurality of voltage levels, based upon video data;
an amplifying circuit, which receives as inputs the voltages output from said decoder circuit, and outputs to an output terminal a voltage corresponding to the video data; and
the digital-to-analog converter set forth in claim 1;
said decoder comprising said decoder of said digital-to-analog converter and receiving the plurality of voltage levels from said grayscale voltage generating circuit as the plurality of reference voltages and receiving the video data as the selecting signal; and
said amplifying circuit, which outputs the voltage corresponding to the video data from the output terminal, comprising the amplifying circuit of said digital-to-analog converter.

31. A display device comprising:
a plurality of data lines extending in parallel with one another along a first direction;
a plurality of scan lines extending in parallel with one another in a direction perpendicular to the first direction;
a plurality of pixel electrodes arranged in matrix form at intersections of said plurality of data lines and said plurality of scan lines;
a plurality of transistors corresponding to respective ones of said plurality of pixel electrodes, each transistor having a drain and a source one of which is connected to the corresponding pixel electrode and the other of which is connected to a corresponding data line, and a gate connected to a corresponding scan line;
a gate driver for supplying scan signals to respective ones of said plurality of scan lines; and
a data driver for supplying grayscale signals, which correspond to input data, to respective ones of said plurality of data lines;
said data driver comprising the data driver for said display device set forth in claim 30.

32. The display device according to claim 31, further comprising:
a data conversion table for making Z-bit video data correspond to m-bit (where Z is less than m) video data for each of colors R, G and B; and
a data converting circuit, to which the Z-bit video data is input, for converting the Z-bit video data to the m-bit video data by referring to said data conversion table, and outputting the m-bit video data to said data driver.

33. A digital-to-analog converter comprising:
a decoder, which receives m (where m is an integer greater than or equal to 4) reference voltages having voltage values that differ from one another and an input digital signal, and selects and outputs n (where n is an integer greater than or equal to 3) identical or different voltages from among the input m reference voltages based upon the digital signal; and
an amplifying circuit, which receives the selected n reference voltages, and outputs a voltage, obtained as a result of taking the weighted mean of the input n voltages at a prescribed weighting, from an output terminal.

34. The digital-to-analog converter according to claim 33, wherein said amplifying circuit outputs from the output terminal a voltage obtained by taking the weighted mean of the input n voltages at a weighing proportional to n powers of 2 that differ from one another.

35. The digital-to-analog converter according to claim 34, wherein m of the m reference voltages that are supplied to said converter is made 2K (where K is an integer greater than or equal to 2); and
the reference voltages are set to a {1+(2n−1)×Σj=1K[αj×2(j−1)n]}th level (where α1, α2, . . . , and αK are 0 or 1) from among equally spaced first to (mn)th voltage levels.

36. The digital-to-analog converter according to claim 33, wherein said decoder outputs n of the selected n voltages in parallel or outputs the selected n voltages one or a plurality at a time sequentially.