# Patent

## Title
Overlay measurement target

## Abstract

In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy.

## Background
This Application is a divisional application of U.S. patent application Ser. No. 11/035,652 filed Jan. 13, 2005, which claims priority to U.S. Patent Application Ser. No. 60/651,475 filed Oct. 18, 2004. Both of these applications are incorporated herein by reference in their entirety.


BACKGROUND OF INVENTION
Modern semiconductor devices, such as integrated circuits, are typically fabricated from wafers of semiconductor material. The wafers are fabricated by a succession of patterned layers of semiconductor material. Circuit patterns are fabricated using a variety of long established techniques, for example, lithographic techniques. Precise positioning and alignment during fabrication is important in manufacturing accurate patterns. For example, alignment control of the stepper tool is important in ensuring a consistent process. Statistical stepper alignment methodologies are established, in which statistical techniques are used to determine the alignment of a reticle with a pattern created by or in association with the stepper to facilitate alignment of the stepper. The technique typically uses images generated within the stepper optics, or projected onto the wafer by the stepper optics. Similar statistical methods have been employed to align for example an exposure tool during pattern fabrication.
Although such alignment technology has performed well, and is important in device fabrication, it relates to alignment of fabrication tooling only. This can be a limitation with semiconductor structures having a succession of pattern layers of semiconductor material, where it is desirable to be able to determine the misregistration between fabricated layers themselves.
Overlay metrology in semiconductor device fabrication is used to determine how well one printed layer is overlaid on a previously printed layer. Close alignment of each layer at all points within the device is important for reaching the design goals and hence the required quality and performance of the manufactured device. It is consequently important for the efficiency of the manufacturing process that any alignment error between two patterned layers on a wafer can be measured quickly and accurately. It is similarly important to be able to measure any alignment error between successive exposures in the same layer. Discussion here of two layers applies as well to two exposures in the same layer.
Misregistration between layers is referred to as overlay error. Overlay metrology tools are used to measure the overlay error. This information may be fed into a closed loop system to correct the overlay error.
Current overlay metrology uses optically readable target marks or patterns printed onto layers of a semiconductor wafer during fabrication. The relative displacement of two successive layers is measured by imaging the patterns at high magnification, digitizing the images, and processing the image data using various known image analysis algorithms to quantify the overlay error. Overlay metrology techniques thus involve the direct measurement of misregistration between patterns provided in direct association with each of the layers. In particular, target marks or patterns are developed in or on the surface of each of the layers, rather than being latent images, or images generated within or projected from the optics of an imaging instrument.
The pattern of the target mark may be applied to the wafer by any suitable method. The mark is often preferably printed onto the wafer layers, for example using photolithographic methods. Typically, the same technique is used to apply overlay target marks on each of two or more wafer layers to be tested to enable alignment information representative of the alignment of the layers to be measured. Accuracy of layer alignment should correspond to accuracy of circuit pattern alignment within the fabricated wafer.
Current overlay metrology is normally practiced by printing targets with rectangular symmetry. For each measurement, two targets are printed, one in the current layer and one in a previous layer, or one in association with each pattern in a common layer. The choice of which previous layer to use is determined by process tolerances. The two targets usually have a nominally common center, but are printed with different sizes so that they can be differentiated. Normally, but not always, the target printed in the current layer is the smaller of the two targets. An overlay measurement in such a system is the actual measured displacement of the centers of the two targets.
The size of the targets is currently often designed so that both targets can be imaged simultaneously by a bright-field microscope. Due to imaging considerations, the larger of the two targets is typically about 25 μm square on the outside. This arrangement permits capture of all of the necessary data for the performance of the measurement from a single image. Measurements at a rate of one in every second or less are possible using current technology.
This procedure generally requires that the target and the target image be symmetric, since otherwise there is no uniquely defined center point. Without symmetry, there is an uncertainty in the measurement, which may be more than can be tolerated. Preferred sizes and shapes of current designs of targets to be measured are generally well known. The targets are positioned in the scribe area at the edge of the fabricated circuit.
It is generally highly desirable that the measurement targets maintain axial symmetry about the optical axis of the measurement tool, since accurate measurement requires very close control of image aberrations. In current practice, this can only be achieved for images at or centered about the system axis. In most known systems, measurements are therefore made from the targets by computing a center line for each different target. The overlay measurement is the difference in the center lines. Most of the target designs in general use permit measurement of the vertical and horizontal overlay displacement from a single image.
Measurement errors must be controlled to a very small amount. These errors can be classified as random errors, characterized by determination of measurement precision; and systematic errors, characterized by tool induced errors, tool-to-tool measurement differences and errors introduced by asymmetry in the targets being measured. Successful application of overlay metrology to semiconductor process control generally requires that these errors (combined) be less than 10% of the process control budget. The process control budget is approximately one third of the smallest dimension patterned by the process. The smallest feature sizes being printed in semiconductor device manufacture is currently 65 nm. These features will become progressively even smaller. The overlay measurement error budget is therefore now 3 nm or less, and will become yet smaller in the foreseeable future.
Measurement precision is easily determined by analysis of the variations of repeated measurements. Different forms of precision may be determined by well known appropriate methods, allowing determination of the static, short-term and long-term components of precision.
Determining the contribution of the measurement tool alone to errors is achieved by comparing measurements made with the target in its normal presentation, with a measurement made after rotating the target by 180° with respect to the imaging system. Ideally the measurement will simply change sign. The average of the measurements at 0° and 180° is called Tool Induced Shift (TIS), as is well known to those skilled in the art. TIS is widely accepted as a measure of the tool's systematic error contribution. Measurements of TIS differ from tool to tool and with process layer Subtraction of the estimated TIS error from the measurements allows removal of the TIS error from the measurements, but at the expense of the additional time taken to measure the target twice.
Different tools, even when of the same type, will make slightly different measurements, even after allowing for precision and TIS errors. The magnitude of this error can be determined experimentally by comparing the averages of repeated measurements at 0° and 180° on two or more tools.
The contributions of precision, TIS variation and tool-to-tool differences are normally combined through a root-sum-square product, or alternative appropriate method, to determine the total measurement uncertainty due to the measurement process. The total measurement uncertainty should be less than 10% of the overall overlay budget for the process if the metrology is to have value. Existing measurement tools and procedures achieve a total uncertainty sufficient for current manufacturing techniques but insufficient for the future requirements of smaller feature sizes.
Overlay metrology today is performed almost exclusively by bright-field microscopy. Patterns are fabricated at the edge of the imaged field, in the scribe-line area of the device, specifically for the purpose of metrology. Currently, some device features are smaller than the wavelength of visible light. As a result, the targets generally are significantly larger than these very small features (approximately 25 μm outside dimensions are normal as shown in FIG. 1). The current standard target is large so that the elements are effectively isolated.
There are three sources of error to be considered. The first source of error is imperfection in the manufacture of the target which leads to an uncertainty in its location. An example of this is physical asymmetry of the target, caused perhaps by uneven deposition of a metal film. A second source of error is the difference in the displacement of the two layers at the measurement target and the genuine overlay of the same layers in the device being manufactured. These can arise from errors in the design and manufacture of the reticles used to create the patterns on the wafer, proximity effects in the printing process and distortion of the films after printing by other process steps. A third source of error is shift in the apparent relative position of the two layers due to proximity effects when the measured image is formed. These measurement errors represent a practical limitation of the current state of the art and can cause serious problems in the application of overlay metrology to semiconductor process control.
Error from imperfection in manufacture of the target can sometimes be reduced by fabricating the features in the measured targets from much smaller objects, such as lines or holes. These smaller features are printed at the design rule for the process, currently in the range 0.1-0.2 μm, and are grouped close together. They are too small to be individually resolved by optical microscopes used in overlay metrology tools. The small features are grouped into larger shapes in the pattern of traditional overlay targets. The use of small features avoids some of the mechanisms causing imperfections in the shape of the manufactured targets, in part by taking advantage of the optimization of the manufacturing process for objects of this size and shape.
If the various parts of the measurement target are brought too close together then they will interact during formation of the image in the measurement tool (R Silver et al, SPIE 5038, p. 428). These interactions will introduce an error into the measurement (Smith, Nigel P.; Goelzer, Gary R.; Hanna, Michael; Troccolo, Patrick M., “Minimizing overlay measurement errors”, August 1993, Proceedings of SPIE Volume: 1926 Integrated Circuit Metrology, Inspection, and Process Control VII, Editor(s): Postek, Michael T). The effect can be reduced to some extent by enhancing the resolution of the imaging system, for example by increasing the numerical aperture (NA) of the imaging system. But such an increase would also increase the system aberration and hence the magnitude of tool created measurement errors (particularly TIS) to unacceptable levels. In order to maintain acceptable measurement error levels, some prior art systems use microscopes with NA limited to 0.5. Hence the separation of features in the target must be kept at more than 5 μm if proximity effects in the image are to be ignored. The prior art systems do not correct for these proximity effects.
High speed is one of the key advantages of existing overlay metrology practice. Hence, use of repeated measurements is undesirable, unless they can be made without requiring significantly more time. There remains a need for alternative overlay patterns and/or analysis methods which reduce errors and improve accuracy, and without substantial loss of throughput speed.
In order to achieve the very accurate and precise measurement of overlay required as, design rules shrink to 65 nm and below, all of these issues are considered. While in some cases the prior-art method employing measurement of large targets in the scribe line area may be sufficient for process control in the future, the area of applicability will be process dependent and is most likely to occur in the front end of processes where the device stack, and hence the image formation process, is simpler.
BRIEF STATEMENT OF THE INVENTION
In a first aspect, a novel target design occupies only a few square microns of space. The target is located close to or in the active device area. In-chip target design reduces WIS (wafer or process induced measurement error) and tends to increase measurement accuracy. It has strong correlation of measuring overlay result from optical distortions and process variations between the location of the actual overlay target and the active area. Furthermore, it reduces the difference in the relative dimensions of the overlay targets and actual targets in the active area since the error sets often vary with the size of the features.
Reduction in the size of the measurement targets is desirable. Smaller targets use less of the imaging field of view. Consequently, there is less difference in aberration coefficients at different parts of the image and hence less measurement error due to those aberrations. The width of scribe lines is being reduced at the same time that a greater reliance on metrology is increasing demand for space within them. E-beam tools are replacing photolithography systems for some patterning applications. These tools are unable to create patterns larger than 10 μm in linear dimension. The marks and mark components described here can be made via lithography, photolithography, via e-beam tools, by nano-imprinting (e.g., as described in U.S. Patent Publication No. 2004/0168586, incorporated herein by reference) or in other ways. Any attempt to reduce target size below the (e.g., 25 μm) dimensions in common use by prior art systems, will require treatment of imaging proximity effects if measurement error levels are to be maintained.
In another aspect, measurement error introduced by the placement of the measurement targets within the scribe lines can be removed by placing them within the active area of the wafer. Since this intrudes on the productive portion of the semiconductor device, the size of such patterns is reduced to a target size of about 1 μm square, or smaller.
Very small measurement targets—about 1 μm square or smaller—are also capable of reducing errors due to process induced shape changes, which will effect objects similar in size to the device patterns less than they will affect larger areas. One well-known example of this effect is that chemical-mechanical polishing used to achieve surface flatness prior to lithography steps will cause surface height modification (called “dishing”) in large (>1 μm) objects while no such damage is caused to smaller ones.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a top view of a prior art target.
FIGS. 2, 7, 8 and 9 show novel targets.
FIGS. 3, 4, 5 and 6 are side or section views of targets and FIG. 10 illustrates a plan view of targets in an active circuit area and in a scribe line.



DETAILED DESCRIPTION OF THE DRAWINGS
An overlay metrology mark for determining the relative position between two or more layers of a semiconductor structure or between two or more separately generated patterns on a single layer of a semiconductor structure includes a first mark portion 20 associated with a first layer or pattern and a second mark portion 30 associated with a second layer or pattern. As shown in FIG. 2, in plan view, the first mark portion 20 comprises an unfilled rectangle or square of width W and height H and line width W1 (on all sides). The second mark portion 30 is a cross of width W2 which is contained within the rectangle. By design the center of the square 20 and the center of the cross 30 are coincident. Any difference is the overlay error that is to be measured.
One of the two mark portions may or may not be buried beneath one or more layers of semi-transparent or transparent material, as shown by the cross-sections taken along lines A-A′ and B-B′ of FIG. 2 illustrated in FIGS. 3 and 4, respectively. In the preferred embodiment the first mark portion, comprising the rectangle pattern, is buried while the second mark portion, the cross, is patterned in photoresist material and lies on top.
A small gap (G) may be located between the cross and rectangle if required by the manufacturing process for the target, but is not required. As shown in FIG. 5, one instance where a gap may be required is when there is no material covering either layer. In other situations, no gap is required, for example when one layer is buried beneath a film which is then polished flat, as shown in FIG. 6. Where a gap is used, the gap is advantageously located within the outer rectangle instead of between the rectangle and the cross, as shown in FIG. 7.
In the preferred embodiment of the invention the width, W, and height, H, of the surrounding rectangle are the same, as are the lengths of the arms of the enclosed cross (W-2G, H-2G).
The cross 30 need not be joined at the center. it can be composed of four bars or rectangles 40 arranged on a cross pattern 50, as shown in FIGS. 8 and 9. This arrangement avoids rounding that occurs at the junction of the intersections of the two arms of a completed cross. This is an important refinement if the width W2 of the cross pieces are close to or at the design limits of the lithography process.
The target designs described above retain the central symmetry characteristic of target designs used in the prior art systems. This axial symmetry favors the optical systems used to form images of the targets during measurement. This minimizes the errors arising in the measurement from optical distortion of the image. However, the central group of four bars (or a box) used in the measurement targets of the prior art is collapsed to a cross, facilitating reduction in size of the target.
Although the design may be used to create targets of similar size to those of the prior art (W=H≈25 μm, and W1≈W2≈2 μm), this pattern may be reduced in size to allow its use within the circuit area 102 (W=H≈1 μm, and W1≈W2≈0.1 μm), as illustrated in FIG. 10 with a first layer with a first circuit pattern 101 and a second layer with a second circuit pattern 103 that include the active area 102 and a scribe line area 104. A reduced sized target 100 following this design may still be used to improve measurement accuracy even if it is placed within the scribe line region 104. When used in either the scribe region 104 or the active area 102 of the wafer, the novel targets described above avoid the problems discussed above by using design-rule size features distributed over a small area to avoid damage from process steps such as CMP which are optimized for object patterns smaller than 1 μm.
These novel overlay targets can be used in or near the active area. These targets permit measurement from the current to most critical previous layer. In the event of excessive measurement uncertainty, alternative layers may be measured and back-up targets used.
Ideally, measurements within the device area are made using the circuit pattern 106 itself. However, the circuit pattern is designed to achieve the function of the device being manufactured and not to benefit metrology. When imaged in plan view (FIG. 10), most relevant sections of the active device area 102 will be patterned in many layers at the same point, and not just the two layer patterns used for overlay measurement. In the general case, the resultant image is too complicated for the available analysis methods for measurements of acceptable quality to be made. It is therefore usually necessary to provide special measurement targets 100 where the image complexity can be controlled so as to permit the measurement tool to extract accurate measurement data.
Suitable small measurement targets have been proposed and demonstrated with the measurements made using a scanning electron microscope (SEM). See Eric P. Solecky, J. Morillo (IBM) SPIE5375-06, 2004, US Patent Publication No. 2003/0071997. A SEM has much better resolution than the optical tools used in prior art overlay measurement systems. Hence the image proximity errors discussed above are less of a concern or even irrelevant. However, SEMs have the disadvantage of not being able to image through buried layers. Hence many required overlay measurements cannot be made using this method. Additionally, SEM tools are both more expensive and slower than optical systems, resulting in an undesirable increase in cost per measurement. An advantage of the novel targets described here, is that they enable measurement of suitable overlay targets, including those where one of the layers is buried, with the speed and cost advantages of existing optical measurement equipment.
In order for designers to accept placement of measurement targets within the device area, the new targets must offer improved measurement quality that cannot be obtained in any other way, and the area occupied by these targets must be kept to a minimum. There is no specific upper limit to the acceptable size of any targets used. Targets of 1 μm outer dimension will be more viable than larger ones of 10 μm or more. On the other hand, a 25 μm target as used in prior art systems would not be acceptable within the device area. Hence, any pattern placed within the device area must be much smaller than those in use before. Interaction effects must also be considered within the algorithms used to perform the measurement if the desired measurement accuracy is to be reached.
The terms in the claims, including the terms rectangle, cross, frame, center line, circle, square, and other similar terms of geometry do not have their usual mathematical dictionary definitions. Rather, they are defined here to have their usual meanings as understood in semiconductor manufacturing metrology. Accordingly, the term rectangle as used here, for example, includes shapes that are not mathematically perfect rectangles, due to manufacturing process or measurement limitations.

## Claims

1. An integrated circuit structure comprising:
a first layer including an active circuit area and a scribe line area;
a first optical metrology target in the active circuit area of the first layer;
a second layer including an active circuit area and a scribe line area; and
a second optical metrology target in the active circuit area of the second layer, the second optical metrology target overlies the first optical metrology target forming an overlay metrology mark that is 1 square micron or smaller;
wherein the first optical metrology target comprises one of a rectangle-shaped frame and four rectangles positioned in a cross shape and the second optical metrology target comprises the other of the frame and the cross shape, wherein the cross shape is nominally positioned to be bounded by the frame, the four rectangles radiating from a central point of the cross shape.

2. The integrated circuit structure of claim 1, wherein rectangle-shaped frame has a width and a height that are substantially the same and the cross shape has a width and a height that are substantially the same.

3. The integrated circuit structure of claim 1, wherein there is a gap between the rectangles at the central point of the cross shape.

4. The integrated circuit structure of claim 1, wherein each of the rectangles in the cross shape has a width and a length, the length being greater than the width, wherein a first pair of rectangles are collinear along their lengths and a second pair of rectangles are collinear along their lengths and the first pair of rectangles and second pair of rectangles are orthogonal to each other.

5. The integrated circuit structure of claim 1, wherein the dimensions of the first optical metrology target and the second optical metrology target are at or near the design rule of a microlithography process used to form the active circuit area of the first layer and the active circuit area of the second layer.

6. The integrated circuit structure of claim 1, wherein centers of the first optical metrology target and the second optical metrology target are nominally coincident.

7. The integrated circuit structure of claim 1, where the horizontal and vertical dimensions of the first optical metrology target are substantially the same and the horizontal and vertical dimensions of the second optical metrology target mark are substantially the same.

8. The integrated circuit structure of claim 1, wherein either or both of the first optical metrology target and the second optical metrology target are formed by sub-elements patterned at or near the design rule of a microlithography process used to form the active circuit area of the first layer and the active circuit area of the second layer.

9. The integrated circuit structure of claim 8, wherein at least one of the sub-elements is shaped substantially as at least one of circles, squares, and lines.

10. An integrated circuit structure comprising:
a first circuit pattern on a layer, with the first circuit pattern having an active circuit area;
a first optical metrology target in the active area of the first pattern;
a second circuit pattern on the layer, with the second circuit pattern having an active circuit area; and
a second optical metrology target in the active area of the second circuit pattern, the second optical metrology target and the first optical metrology target are aligned forming an overlay metrology mark that is 1 square micron or smaller;
wherein the first optical metrology target comprises one of a rectangle-shaped frame and four rectangles positioned in a cross shape and the second optical metrology target comprises the other of the frame and the cross shape, wherein the cross shape is nominally positioned to be bounded by the frame, the four rectangles radiating from a central point of the cross shape.

11. The integrated circuit structure of claim 10, wherein rectangle-shaped frame has a width and a height that are substantially the same and the cross shape has a width and a height that are substantially the same.

12. The integrated circuit structure of claim 10, wherein there is a gap between the rectangles at the central point of the cross shape.

13. The integrated circuit structure of claim 10, wherein each of the rectangles in the cross shape has a width and a length, the length being greater than the width, wherein a first pair of rectangles are collinear along their lengths and a second pair of rectangles are collinear along their lengths and the first pair of rectangles and second pair of rectangles are orthogonal to each other.

14. The integrated circuit structure of claim 10, wherein there are gaps between the cross shape and the frame in the rectangle-shaped frame.

15. The integrated circuit structure of claim 14, wherein the gaps are in the rectangle-shaped frame.

16. An integrated circuit structure comprising:
a first layer including an active circuit area and a scribe line area;
a first optical metrology target in the active circuit area of the first layer, the first optical metrology target comprises one of a rectangle-shaped frame and four rectangles positioned in a cross shape, the four rectangles radiating from a central point of the cross shape;
a second layer including an active circuit area and a scribe line area; and
a second optical metrology target in the active circuit area of the second layer, the second optical metrology target comprises the other of the frame and the cross shape, wherein the cross shape is nominally positioned to be bounded by the frame.

17. The integrated circuit structure of claim 16, wherein the largest dimension of the frame and the cross shape is 1 square micron or smaller.

18. The integrated circuit structure of claim 16, wherein there is a gap between the rectangles at the central point of the cross shape.

19. The integrated circuit structure of claim 16, wherein each of the rectangles in the cross shape has a width and a length, the length being greater than the width, wherein a first pair of rectangles are collinear along their lengths and a second pair of rectangles are collinear along their lengths and the first pair of rectangles and second pair of rectangles are orthogonal to each other.

20. The integrated circuit structure of claim 16, wherein the widths of the frame and the cross shape are at or near the design rule of a microlithography process used to form the active circuit area of the first layer and the active circuit area of the second layer.

21. The integrated circuit structure of claim 16, wherein centers of the frame and the cross shape are nominally coincident.

22. The integrated circuit structure of claim 16, wherein rectangle-shaped frame has a width and a height that are substantially the same and the cross shape has a width and a height that are substantially the same.

23. The integrated circuit structure of claim 16, wherein either or both of the frame and the rectangles positioned in the cross shape are formed by sub-elements patterned at or near the design rule of a microlithography process used to form the active circuit area of the first layer and the active circuit area of the second layer.

24. The integrated circuit structure of claim 23, wherein at least one of the sub-elements is shaped substantially as at least one of circles, squares, and lines.