# Patent

## Title
Semiconductor device and method for driving the same

## Abstract

An image sensor is provided which is capable of holding data for one frame period or longer and conducting a difference operation with a small number of elements. A photosensor is provided in each of a plurality of pixels arranged in a matrix, each pixel accumulates electric charge in a data holding portion for one frame period or longer, and an output of the photosensor changes in accordance with the electric charge accumulated in the data holding portion. As a writing switch element for the data holding portion, a transistor with small leakage current (sufficiently smaller than 1×10−14 A) is used. As an example of the transistor with small leakage current, there is a transistor having a channel formed in an oxide semiconductor layer.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for driving the semiconductor device. Specifically, the present invention relates to an image sensor provided with a photosensor in each of a plurality of pixels, and a method for driving the image sensor. The present invention further relates to an electronic device including the image sensor.
Note that a semiconductor device refers to a semiconductor element itself or a device including a semiconductor element. As an example of such a semiconductor element, for example, a thin film transistor can be given. Therefore, the semiconductor device includes a liquid crystal display device, a memory device, and the like.
A photosensor refers to one element provided in a pixel, and an image sensor refers to a device including a plurality of pixels each provided with a photosensor.
2. Description of the Related Art
Image sensors are widely used these days. Image sensors are required to have high resolution, and with an increase in the resolution of image sensors, data processing speed also continues to increase.
In addition, image sensors are required to have a wider dynamic range. One of proposed methods for widening the dynamic range of an image sensor is to provide a difference arithmetic circuit in each pixel (e.g., Patent Document 1).
REFERENCE


    [Patent Document 1] Japanese Published Patent Application No. H08-223490


SUMMARY OF THE INVENTION
A capacitor is used to store data of a previous frame in a pixel of a display device. If the leakage current of a switch element for writing data to the capacitor is large, the data written is lost. Note that leakage current refers to a current flowing between a source and a drain when a transistor is turned off.
For example, the leakage current of a transistor having a channel formed in a silicon semiconductor layer is large. Therefore, in the case where the transistor having a channel formed in a silicon semiconductor layer is used as a switch element and a moving image is taken at 60 fps (frames per second), data can be held for about one frame period ( 1/60 seconds) at the longest, and data rewriting is required every frame.
On the other hand, in order to hold data for at least one frame period, the capacitor needs to have a large capacitance. One possible method for increasing the capacitance of the capacitor is to enlarge the area of the capacitor. However, the enlargement of the area of the capacitor inhibits an increase in resolution and furthermore results in a decrease in aperture ratio.
On the other hand, one method for conducting a difference operation is to use a current mirror circuit. However, providing each pixel with a current mirror circuit leads to an increase in the number of elements included in a pixel circuit and inhibits an increase in resolution. It also leads to a decrease in aperture ratio.
It is an object of one embodiment of the present invention to provide an image sensor capable of holding data for one frame period (at least 1/60 seconds in the case of 60 fps) or longer. It is another object to provide an image sensor capable of conducting a difference operation with a small number of elements, without using a current mirror circuit or the like and without increasing the number of elements included in a pixel circuit.
One embodiment of the present invention is a semiconductor device including a photosensor in each of a plurality of pixels arranged in a matrix. Each pixel accumulates electric charge in a data holding portion for one frame period or longer, and an output of the photosensor changes in accordance with the electric charge accumulated in the data holding portion. As a writing switch element for a data holding portion, a transistor with small leakage current is used. As an example of the transistor with small leakage current, there is a transistor having a channel formed in an oxide semiconductor layer.
One embodiment of the present invention is a semiconductor device including a plurality of pixels arranged in a matrix. Each pixel electrically connected to first to seventh wirings includes a photodiode, first and second capacitors, first to third transistors, and a data holding portion. A cathode of the photodiode is electrically connected to the first wiring. An anode of the photodiode is electrically connected to a first electrode of the first capacitor. A first electrode of the second capacitor is electrically connected to the third wiring. One of a source and a drain of the first transistor is electrically connected to the second wiring. A gate of the first transistor is electrically connected to the sixth wiring. One of a source and a drain of the second transistor is electrically connected to the fourth wiring. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor. The other of the source and the drain of the third transistor is electrically connected to the seventh wiring. A gate of the third transistor is electrically connected to the fifth wiring. The data holding portion is configured by electrically connecting a second electrode of the first capacitor, a second electrode of the second capacitor, the other of the source and the drain of the first transistor, and a gate of the second transistor. Leakage current of the first transistor is small.
One embodiment of the present invention is a semiconductor device including a plurality of pixels arranged in a matrix. Each pixel electrically connected to first to eighth wirings includes a photodiode, first and second capacitors, first to fourth transistors, and a data holding portion. A cathode of the photodiode is electrically connected to the first wiring. An anode of the photodiode is electrically connected to one of a source and a drain of the fourth transistor. A gate of the fourth transistor is electrically connected to the eighth wiring. The other of the source and the drain of the fourth transistor is electrically connected to a first electrode of the first capacitor. A first electrode of the second capacitor is electrically connected to the third wiring. One of a source and a drain of the first transistor is electrically connected to the second wiring. A gate of the first transistor is electrically connected to the sixth wiring. One of a source and a drain of the second transistor is electrically connected to the fourth wiring. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor. The other of the source and the drain of the third transistor is electrically connected to the seventh wiring. A gate of the third transistor is electrically connected to the fifth wiring. The data holding portion is configured by electrically connecting a second electrode of the first capacitor, a second electrode of the second capacitor, the other of the source and the drain of the first transistor, and a gate of the second transistor. Leakage current of the first transistor is small.
Note that the first wiring may be a wiring to which a reset signal is supplied. The second wiring may be a wiring which can be set at a constant potential as a reference potential. The third wiring may be a wiring capable of setting one electrode of a capacitor at a constant potential. The fourth wiring may be a wiring to which a reference potential for a source follower circuit including the second transistor is supplied. The fifth wiring may be a wiring capable of selecting a pixel where an output signal is detected. The sixth wiring may be a wiring capable of supplying a signal for controlling a transistor serving as a switch element for the data holding portion. The seventh wiring may be a wiring for transmitting an output signal. The eighth wiring may be a wiring capable of supplying a signal for controlling light exposure of a pixel (such a signal is referred to as a shutter signal).
The leakage current of the first transistor in the above configuration is preferably smaller than 1×10−14 A.
The first transistor in the above configuration is preferably a transistor having a channel formed in an oxide semiconductor layer.
One embodiment of the present invention is a method for driving a semiconductor device including a plurality of pixels arranged in a matrix, each of which includes at least a photodiode and a data holding portion. An operation of reading the data holding portion of the photodiode includes at least first to third operations. In the first operation, a potential of a first current generated by first light reception by the photodiode is read. In the second operation, the potential of the first current from the photodiode is stored in the data holding portion. In the third operation, a combined potential of a potential of a second current generated by second light reception by the photodiode and an output potential based on the potential of the first current stored through the second operation is read.
Note that a transistor is turned on when a gate voltage (a potential difference obtained by subtracting the potential of the source from that of the gate) is higher than or equal to a threshold voltage of the transistor, and the transistor is turned off when the gate voltage is lower than the threshold voltage of the transistor.
According to one embodiment of the present invention, an image sensor with a wide dynamic range can be provided. In addition, an image sensor with less data due to a difference operation can be provided.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an example of a configuration of an image sensor according to one embodiment of the present invention.
FIG. 2 illustrates an example of a circuit configuration of a pixel of an image sensor according to one embodiment of the present invention.
FIG. 3 is a timing chart illustrating an example of a reading operation of a photosensor provided in an image sensor according to one embodiment of the present invention.
FIG. 4 illustrates an example of a circuit configuration of a pixel of an image sensor according to one embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view of a transistor which can be used.
FIGS. 6A to 6D illustrate a method for manufacturing the transistor illustrated in FIG. 5.
FIGS. 7A to 7E each illustrate a structure of an oxide semiconductor which can be applied to a transistor.
FIGS. 8A to 8C illustrate a structure of an oxide semiconductor which can be applied to a transistor.
FIGS. 9A to 9C illustrate a structure of an oxide semiconductor which can be applied to a transistor.
FIG. 10 shows gate voltage dependence of mobility obtained by calculation.
FIGS. 11A to 11C each show gate voltage dependence of drain current and mobility obtained by calculation.
FIGS. 12A to 12C each show gate voltage dependence of drain current and mobility obtained by calculation.
FIGS. 13A to 13C each show gate voltage dependence of drain current and mobility obtained by calculation.
FIGS. 14A and 14B illustrate cross-sectional structures of transistors used for calculation.
FIGS. 15A to 15C each show characteristics of a transistor formed using an oxide semiconductor film.
FIGS. 16A and 16B each show Vg-Id characteristics of a transistor of Sample 1 after a BT test.
FIGS. 17A and 17B each show Vg-Id characteristics of a transistor of Sample 2 after a BT test.
FIG. 18 shows Vg dependence of Id and field-effect mobility.
FIG. 19A shows a relation between substrate temperature and threshold voltage, and FIG. 19B shows a relation between substrate temperature and field-effect mobility.
FIG. 20 shows XRD spectra of Sample A and Sample B.
FIG. 21 shows a relation between off-state current of a transistor and substrate temperature in measurement.



DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail below with reference to drawings. Note that the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments. Note that in the drawings used for the description below, the same portions or portions having a similar function are denoted by the same reference numerals, and the repeated description thereof is omitted.
Note that ordinal numbers in the description below are used for convenience, and a first wiring may be referred to as a second wiring, and a second wiring may be referred to as a first wiring. The same applies to other wirings.
Embodiment 1
In this embodiment, a circuit configuration of an image sensor according to one embodiment of the present invention and a method for driving the image sensor are described with reference to FIGS. 1 to 3.
FIG. 1 illustrates an example of a configuration of an image sensor according to this embodiment. An image sensor 100 includes a first shift register 102, a second shift register 104, a reading circuit 106, and a pixel array 108. The first shift register 102 is electrically connected to the pixel array 108 through the reading circuit 106. The second shift register 104 is electrically connected to the pixel array 108. The pixel array 108 includes a plurality of pixels 110. The pixels 110 are arranged in a matrix in the pixel array 108. Data which is output from the pixel array 108 is output to an external circuit of the image sensor 100 through the reading circuit 106.
FIG. 2 illustrates an example of a circuit configuration of the pixel 110. A circuit of the pixel 110 in FIG. 2 includes a photodiode 200, a first capacitor 202, a second capacitor 204, a first transistor 206, a second transistor 208, and a third transistor 210. Note that the second capacitor 204 may be formed with a parasitic capacitance.
A cathode of the photodiode 200 is electrically connected to a first wiring 220. An anode of the photodiode 200 is electrically connected to one electrode of the first capacitor 202. The first wiring 220 is electrically connected to the second shift register 104. The other electrode of the first capacitor 202 is electrically connected to a data holding portion 212. One electrode of the second capacitor 204 is electrically connected to the data holding portion 212. The other electrode of the second capacitor 204 is electrically connected to a third wiring 224 which is held at a constant potential. The third wiring 224 is electrically connected to the second shift register 104. Alternatively, the third wiring 224 may be electrically connected to an external circuit through the second shift register 104. A drain of the first transistor 206 is electrically connected to the data holding portion 212. A source of the first transistor 206 is electrically connected to a second wiring 222. A gate of the first transistor 206 is electrically connected to a sixth wiring 230. The second wiring 222 is electrically connected to the second shift register 104. Alternatively, the second wiring 222 may be electrically connected to an external circuit through the second shift register 104. The sixth wiring 230 is electrically connected to the second shift register 104. A gate of the second transistor 208 is electrically connected to the data holding portion 212. A source of the second transistor 208 is electrically connected to a fourth wiring 226. A drain of the second transistor 208 is electrically connected to a source of the third transistor 210. The fourth wiring 226 is electrically connected to the second shift register 104. A gate of the third transistor 210 is electrically connected to a fifth wiring 228. A drain of the third transistor 210 is electrically connected to a seventh wiring 232. The fifth wiring 228 is electrically connected to the second shift register 104. The seventh wiring 232 is electrically connected to the reading circuit 106.
Note that the first transistor 206 is a transistor with small leakage current. As an example of the transistor with small leakage current, there is a transistor having a channel formed in an oxide semiconductor layer.
Herein, the transistor with small leakage current refers to a transistor with a small off-state current of 10 aA/μm (1×10−17 A/μm) or less per micrometer of channel width at room temperature, preferably 1 aA/μm (1×10−18 A/μm) or less, further preferably 1 zA/μm (1×10−21 A/μm) or less, still further preferably 1 yA/μm (1×10−24 A/μm) or less. In particular, as described below, the leakage current of the first transistor 206 is sufficiently smaller than 10−14 A. Thus, the size of the first transistor 206 is preferably small.
Note that the second transistor 208 and the third transistor 210 are transistors each having a channel formed in a silicon semiconductor layer. However, without being limited thereto, the second transistor 208 and the third transistor 210 may be transistors each having a channel formed in an oxide semiconductor layer.
Note that the anode and the cathode of the photodiode 200 may be reversed. That is, the anode of the photodiode 200 may be electrically connected to the first wiring 220, and the cathode thereof may be electrically connected to the one electrode of the first capacitor 202. In that case, it should be noted that there is a need to adjust the relationship of operation voltages. The source and the drain of each transistor may be reversed depending on the operation voltage.
When the first transistor 206 is turned off, a current flowing between the source and the drain of the first transistor 206 is smaller than 10−14 A, and when the first transistor 206 is turned on, the current flowing between the source and the drain of the first transistor 206 is larger than 10−14 A.
The second transistor 208 is included in a source follower circuit whose source or drain is electrically connected to the fourth wiring 226 and which changes the amount of current flowing between the source and the drain in accordance with the potential of a gate. The source of the second transistor 208 is electrically connected to the fourth wiring 226. The third transistor 210 is used to select one pixel from a plurality of pixels sharing the seventh wiring 232. Note that the connection relationship between the second transistor 208 and the third transistor 210 is not limited to the configuration in FIG. 2, and the drain of the second transistor 208 may be electrically connected to the fourth wiring 226, and the source of the third transistor 210 may be electrically connected to the seventh wiring 232.
Note that the first wiring may be a wiring to which a reset signal is supplied. The second wiring may be a wiring which can be set at a constant potential as a reference potential. The third wiring may be a wiring capable of setting one electrode of a capacitor at a constant potential. The fourth wiring may be a wiring to which a reference potential for the source follower circuit including the second transistor is supplied. The fifth wiring may be a wiring capable of selecting a pixel where an output signal is detected. The sixth wiring may be a wiring capable of supplying a signal for controlling a transistor serving as a switch element for the data holding portion. The seventh wiring may be a wiring for transmitting an output signal. Note that although not illustrated, an eighth wiring may be provided. The eighth wiring may be a wiring capable of supplying a signal for controlling light exposure of a pixel (such a signal is referred to as a shutter signal).
Next, a reading operation of the circuit in FIG. 2 will be described with reference to FIG. 3. FIG. 3 is an example of a timing chart illustrating the reading operation of the circuit in FIG. 2. The vertical axis represents potential, and the horizontal axis represents time. Vres denotes the potential of the first wiring 220. V04g denotes the potential of the gate of the first transistor 206. Vano denotes the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202. V213 denotes the potential of the data holding portion 212. Note that these potentials depend on the light sensitivity of the photodiode 200 or the like and are therefore preferably adjusted by an external circuit of the image sensor 100.
The reading operation of the photosensor can be divided into the following three operations. A first operation is to directly read an output potential of the photodiode 200, that is, the potential of a current generated by light reception by the photodiode 200 (periods 311 and 312). A second operation is to store the output potential of the photodiode 200 (periods 313 and 314). A third operation is to read a combined potential of an output potential of the photodiode 200 and the potential stored in the second operation (periods 315 and 316). Note that light received by the photosensor is not limited to visible light.
The first operation will be described. When the potential of the first wiring 220 in the period 311 is set lower than the potential of the first wiring 220 in the period 312, the photodiode 200 is in the forward mode, and the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is substantially equal to the potential of the first wiring 220. When the potential of the first wiring 220 in the period 312 is set higher than the potential of the first wiring 220 in the period 311, the photodiode 200 is in the reverse mode, and the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is rapidly increased if the intensity of light received by the photodiode 200 is high, and is gradually increased if the intensity of light received by the photodiode 200 is low.
In the period 311, the first transistor 206 is turned on so that the potential of the data holding portion 212 becomes substantially equal to the potential of the second wiring 222. Then, in the period 312, the first transistor 206 is turned off, and the potential of the data holding portion 212 changes in accordance with the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202.
When the third transistor 210 is turned on in the period 312, a current based on the potential of the data holding portion 212 flows between the source and the drain of the second transistor 208. The potential of the data holding portion 212 changes in accordance with the intensity of light received by the photodiode 200, and the current that flows between the source and the drain of the second transistor 208 changes in accordance with the potential of the data holding portion 212. Thus, the intensity of light received by the photodiode 200 can be determined by measurement of the current that flows between the source and the drain of the second transistor 208.
Next, the second operation will be described. In the periods 313 and 314, the first transistor 206 is turned on. When the first transistor 206 is turned on, the potential of the data holding portion 212 is substantially equal to the potential of the second wiring 222. That is, the potential of the data holding portion 212 does not change.
When the potential of the first wiring 220 in the period 313 is set lower than the potential of the first wiring 220 in the period 314, the photodiode 200 is in the forward mode, and the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is substantially equal to the potential of the first wiring 220. When the potential of the first wiring 220 in the period 314 is set higher than the potential of the first wiring 220 in the period 313, the photodiode 200 is in the reverse mode, and the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is rapidly increased if the intensity of light received by the photodiode 200 is high, and is gradually increased if the intensity of light received by the photodiode 200 is low. Since the potential of the data holding portion 212 is fixed, an increase in the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is smaller than that in the period 312 even when the intensity of light received is substantially equal to that in the period 312.
When the first transistor 206 is turned off at the end of the period 314, the potential (charge) of the data holding portion 212 is held.
When the potential of the first wiring 220 in the period 315 is set lower than the potential of the first wiring 220 in the period 314 while the potential (charge) of the data holding portion 212 is being held, the photodiode 200 is in the forward mode, and the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is reset with a reset signal. The potential of the data holding portion 212 changes in accordance with the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202.
In the case where the intensity of light received by the photodiode 200 is high, there is a large change in the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202, the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 becomes high at the end of the period 314, and there is a larger decrease in the potential of the data holding portion 212 than in the case where there is a small change in the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202.
When the potential of the first wiring 220 in the period 316 is set higher than the potential of the first wiring 220 in the period 315, the photodiode 200 is in the reverse mode. The potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is rapidly increased if the intensity of light received by the photodiode 200 is high, and is gradually increased if the intensity of light received by the photodiode 200 is low. The potential of the data holding portion 212 changes in accordance with the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202.
Early in the period 316, unlike in the period 312, the potential of the data holding portion 212 differs according to the intensity of light received by the photodiode 200. In the case where the intensity of light received by the photodiode 200 in the period 314 is substantially equal to that in the period 316, the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is close at the end of the period 316. The potential of the data holding portion 212 when the intensity of light received is high is close to the potential of the data holding portion 212 when the intensity of light received is low. The potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is rapidly increased if the intensity of light received by the photodiode 200 is high, and is gradually increased if the intensity of light received by the photodiode 200 is low.
In the case where the intensity of light received by the photodiode 200 in the period 316 is higher than the intensity of light received by the photodiode 200 in the period 314, the potential of the data holding portion 212 is higher than in the case where the intensity of light received by the photodiode 200 in the period 314 is substantially equal to that in the period 316. In the case where the intensity of light received by the photodiode 200 in the period 316 is lower than the intensity of light received by the photodiode 200 in the period 314, the potential of the data holding portion 212 is lower. When a plurality of pixels is compared at a given time and the intensities of light received by the photodiodes 200 differ in the period 314 even when the intensities of light received by the photodiodes 200 are equal in the period 316, the potentials of the data holding portions 212 differ at the end of the period 316.
In other words, in the case where the intensity of light received by the photodiode 200 in the period 314 is lower than the intensity of light received by the photodiode 200 in the period 316, the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is higher than in the case where the intensity of light received by the photodiode 200 in the period 314 is equal to that in the period 316. In the case where the intensity of light received by the photodiode 200 in the period 314 is higher than the intensity of light received by the photodiode 200 in the period 316, the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 is lower.
Even when data directly read through the first operation has a value smaller than the lower limit of reading by the source follower circuit including the second transistor 208 or by the reading circuit 106, the data can be read by storing the data through the second operation and obtaining a difference through the third operation. That is, the operating range (dynamic range) can be widened.
The third operation can be repeated successively. That is, not only a difference from the previous frame but also a difference from the frame stored through the second operation can be continuously obtained. The potential (charge) of the data holding portion 212 is held as long as the first transistor 206 is off. When the intensity of light received by the photodiode 200 is drastically changed, data can be read again through the first operation and stored through the second operation.
For example, in the case where the leakage current of the first transistor 206 is 10−14 A and the capacitance of the second capacitor 204 is 100 fF, the length of the period in which a change in the potential of the data holding portion 212 is 1 mV or less is about 10 msec if the potentials of wirings except the data holding portion 212 are constant. This means that only one frame can be stored when a moving image is taken at 60 fps. However, in the case where the leakage current of the first transistor 206 is sufficiently smaller than 10−14 A as described above, a difference from not only the previous frame but also the further previous frame can be obtained.
In the case of taking a moving image with a small change in brightness over time, data (the amount of change) obtained through the third operation is small; thus, the number of bits per digital output can be reduced and AD conversion can be performed.
The configuration and operation of the image sensor in this embodiment can be applied to a touch panel or the like without limitation to an imaging device used only for the purpose of taking a moving image.
Note that only the first transistor 206 is a transistor with small leakage current in this embodiment, but the present invention is not limited thereto and the other transistors may be transistors with small leakage current.
This embodiment can be implemented in combination with any of the other embodiments and examples.
Embodiment 2
In one embodiment of the present invention, a global shutter method may be employed. In this embodiment, a circuit configuration of a global shutter image sensor which is one embodiment of the present invention will be described with reference to FIG. 4.
An image sensor illustrated in FIG. 4 has a configuration in which a fourth transistor 400 is provided between the anode of the photodiode 200 and the one electrode of the first capacitor 202 in FIG. 2.
The anode of the photodiode 200 is electrically connected to a source of the fourth transistor 400. A gate of the fourth transistor 400 is electrically connected to an eighth wiring 234. The eighth wiring 234 is electrically connected to the second shift register 104. A drain of the fourth transistor 400 is electrically connected to the one electrode of the first capacitor 202. The other connections are similar to those in FIG. 2. Note that the source and the drain of the fourth transistor 400 may be interchanged with each other.
Next, a reading operation of the circuit in FIG. 4 will be described with reference to FIG. 3. In the periods 311, 313, and 315 in FIG. 3, the potential of the eighth wiring 234 is set high so that the fourth transistor 400 is turned on.
When the fourth transistor 400 is on, the potential between the anode of the photodiode 200 and the source of the fourth transistor 400 and the potential between the drain of the fourth transistor 400 and the one electrode of the first capacitor 202 are roughly equal to the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 in FIG. 3.
Early in the periods 312, 314, and 316 in FIG. 3, the potential of the eighth wiring 234 is set high so that the fourth transistor 400 is turned on. When the fourth transistor 400 is on, the potential between the anode of the photodiode 200 and the source of the fourth transistor 400 and the potential between the drain of the fourth transistor 400 and the one electrode of the first capacitor 202 are roughly equal to the potential between the anode of the photodiode 200 and the one electrode of the first capacitor 202 in FIG. 3.
After that, the potential of the eighth wiring 234 is lowered so that the fourth transistor 400 is turned off. When the fourth transistor 400 is turned off, the potential between the drain of the fourth transistor 400 and the one electrode of the first capacitor 202 does not change. In addition, the potential of the data holding portion 212 does not change.
In each of the periods 312, 314, and 316, a period during which the fourth transistor 400 is turned on is a light exposure period. In the light exposure period, a portion between the drain of the fourth transistor 400 and the one electrode of the first capacitor 202 functions in a manner similar to a portion between the anode of the photodiode 200 and the one electrode of the first capacitor 202 in FIG. 2; thus, operation as a global shutter image sensor which is one embodiment of the present invention can be achieved.
Embodiment 3
A transistor having a channel formed in an oxide semiconductor layer is preferably used as the first transistor 206 in Embodiment 1 and Embodiment 2.
Note that in the present invention, the transistors other than the first transistor 206 are not limited to those having specific structures and may have various structures. Thus, the transistors may be formed using polycrystalline silicon or may be formed using a silicon-on-insulator (SOI) substrate. Alternatively, the transistors may be formed using a compound semiconductor substrate such as a GaAs substrate.
Although the transistors in the above description are n-channel transistors, the present invention is not limited thereto and p-channel transistors may be used as appropriate.
Next, a transistor with small off-state current which can be used in the present invention will be described. As an example of the transistor with small off-state current, there is a transistor containing a metal oxide which has semiconductor characteristics in a channel formation region. As an example of a transistor other than the transistor with small off-state current, there is a transistor formed using a semiconductor substrate.
FIG. 5 illustrates examples of schematic cross-sectional structures of transistors which can be used in the present invention. In FIG. 5, a transistor with small off-state current is formed over a transistor formed using a semiconductor substrate. As the transistor formed using the semiconductor substrate, both a p-channel transistor and an n-channel transistor may be provided, or only either one may be provided.
The p-channel transistor and the n-channel transistor may be formed using the semiconductor substrate by a known method. After the p-channel transistor and the n-channel transistor are formed using the semiconductor substrate, the transistor with small off-state current is formed thereover. In other words, the transistor with small off-state current is formed over a semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor. As an example of the transistor with small off-state current, there is a transistor having a channel formation region in an oxide semiconductor layer.
Note that the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor includes high-concentration impurity regions 501 serving as a source region and a drain region, low-concentration impurity regions 502, a gate insulating film 503, a gate electrode 504, and an interlayer insulating film 505 (FIG. 5).
A transistor 510 having a channel formation region in an oxide semiconductor layer includes an oxide semiconductor layer 511 over the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor, a source electrode 512a and a drain electrode 512b which are apart from each other and in contact with the oxide semiconductor layer 511, a gate insulating film 513 over at least a channel formation region of the oxide semiconductor layer 511, and a gate electrode 514b over the gate insulating film 513 so as to overlap with the oxide semiconductor layer 511 (FIG. 6D).
The interlayer insulating film 505 also functions as a base insulating film for the oxide semiconductor layer 511.
The interlayer insulating film 505 contains oxygen at least on its surface and may be formed using an insulating oxide from which part of oxygen is released by heat treatment. As the insulating oxide from which part of oxygen is released by heat treatment, an insulating oxide containing a large amount of oxygen exceeding the stoichiometry is preferably used. This is because oxygen can be supplied to an oxide semiconductor film in contact with the interlayer insulating film 505 by the heat treatment.
As an example of the insulating oxide containing a large amount of oxygen exceeding the stoichiometry, silicon oxide represented by SiOx where x>2 can be given. However, one embodiment of the present invention is not limited thereto, and the interlayer insulating film 505 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxynitride, gallium oxide, hafnium oxide, yttrium oxide, or the like.
Note that the interlayer insulating film 505 may be formed by stacking a plurality of films. The interlayer insulating film 505 may have a stacked structure in which a silicon oxide film is formed over a silicon nitride film, for example.
From the insulating oxide containing a large amount of oxygen exceeding the stoichiometry, part of oxygen is easily released by heat treatment. The amount of released oxygen (the value converted into the number of oxygen atoms) obtained by TDS analysis when part of oxygen is easily released by heat treatment is greater than or equal to 1.0×1018 atoms/cm3, preferably greater than or equal to 1.0×1020 atoms/cm3, more preferably greater than or equal to 3.0×1020 atoms/cm3.
Here, a method for the TDS analysis is described. The amount of a gas released in the TDS analysis is proportional to a time integral value of ion intensity. Thus, the amount of a released gas can be calculated from the time integral value of the ion intensity of an oxide and a reference value of a standard sample. The reference value of a standard sample refers to the ratio of the density of atoms of a predetermined element contained in the sample (standard sample) to the time integral value of its spectrum.
For example, the number of oxygen molecules (O2) released from an oxide (NO2) can be found according to the formula, NO2=NH2/SH2×SO2×α, from the time integral value of the ion intensity of a silicon wafer containing hydrogen at a predetermined density (standard sample) and the time integral value of the ion intensity of the oxide.
NH2 is the value obtained by conversion of the number of hydrogen molecules (H2) released from the standard sample into density. SH2 is the time integral value of the ion intensity of hydrogen molecules (H2) of the standard sample. In other words, the reference value of the standard sample is NH2/SH2. SO2 is the time integral value of the ion intensity of oxygen molecules (O2) of the insulating oxide. α is a coefficient which influences the ion intensity. Refer to Japanese Published Patent Application No. H06-275697 for details of the above equation.
Note that the amount of oxygen released in the TDS analysis (the value converted into the number of oxygen atoms) is measured with a thermal desorption spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W, using a silicon wafer containing hydrogen atoms at 1×1016 atoms/cm3 as the standard sample.
Note that, in the TDS analysis, oxygen is partly detected as oxygen atoms. The ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of the oxygen molecules. Note that, since the above coefficient α includes the ionization rate of oxygen molecules, the number of the released oxygen atoms can also be calculated through the evaluation of the number of the released oxygen molecules.
Note that NO2 is the number of released oxygen molecules (O2). Therefore, the amount of released oxygen converted into the number of oxygen atoms is twice the number of the released oxygen molecules (O2).
The interlayer insulating film 505 may be formed by a sputtering method, a CVD method, or the like and is preferably formed by a sputtering method. In the case where a silicon oxide film is formed as the interlayer insulating film 505, a quartz (preferably synthetic quartz) target may be used as a target, and an argon gas may be used as a sputtering gas. Alternatively, a silicon target may be used as a target, and a gas containing oxygen may be used as a sputtering gas. Note that the gas containing oxygen may be a mixed gas of an argon gas and an oxygen gas or may be an oxygen gas alone.
Between the formation of the interlayer insulating film 505 and the formation of an oxide semiconductor film to be the oxide semiconductor layer 511, first heat treatment is performed. The first heat treatment is performed to remove water and hydrogen contained in the interlayer insulating film 505. The temperature of the first heat treatment may be set higher than or equal to a temperature at which water and hydrogen contained in the interlayer insulating film 505 are released (a temperature at which the release amount peaks) and lower than a temperature at which the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor alters or deforms, and is preferably set higher than or equal to 400° C. and lower than or equal to 750° C., and lower than a temperature of second heat treatment performed in a later step.
Then, the second heat treatment is performed after the oxide semiconductor film is formed. The second heat treatment is performed to supply oxygen to the oxide semiconductor film from the interlayer insulating film 505 which serves as a source of oxygen. Note that the timing of the second heat treatment is not limited thereto, and the second heat treatment may be performed after the oxide semiconductor film is processed into the oxide semiconductor layer 511.
Note that it is preferable that the second heat treatment be performed in a nitrogen gas atmosphere or a rare gas atmosphere including helium, neon, argon, or the like and the atmosphere do not contain hydrogen, water, a hydroxyl group, hydride, and the like. Alternatively, the purity of a nitrogen gas or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is preferably set to 6N (99.9999%) or more, more preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).
In some cases, the oxide semiconductor film or the oxide semiconductor layer 511 may be crystallized into a microcrystalline oxide semiconductor layer or a polycrystalline oxide semiconductor layer, depending on the conditions of the second heat treatment or the material of the oxide semiconductor film or the oxide semiconductor layer 511. For example, the oxide semiconductor film or the oxide semiconductor layer 511 may be crystallized into a microcrystalline oxide semiconductor layer having a degree of crystallization of greater than or equal to 90%, or greater than or equal to 80%. Further, the oxide semiconductor film or the oxide semiconductor layer 511 may be an amorphous oxide semiconductor layer without containing a crystalline component, depending on the conditions of the second heat treatment or the material of the oxide semiconductor film or the oxide semiconductor layer 511. Furthermore, the oxide semiconductor film or the oxide semiconductor layer 511 may be an amorphous oxide semiconductor layer containing microcrystals (having a crystal grain size of 1 nm to 20 nm).
Note that in the second heat treatment, the interlayer insulating film 505 serves as a source of oxygen.
Note that the interlayer insulating film 505 over which the oxide semiconductor film is formed preferably has an average surface roughness (Ra) of greater than or equal to 0.1 nm and less than 0.5 nm. This is because crystal orientations can be aligned when the oxide semiconductor film is a crystalline oxide semiconductor film.
Note that the average surface roughness (Ra) is obtained by expanding the arithmetic means surface roughness (Ra) that is defined by JIS B 0601:2001 (ISO 4287:1997) into three dimensions so as to be able to be applied to a curved surface. The average surface roughness (Ra) is expressed as an average value of the absolute values of deviations from a reference surface to a specific surface.
Here, the arithmetic means surface roughness (Ra) is shown by the following formula (1) assuming that a portion having a measurement length L is picked up from a roughness curve in the direction of the center line of the roughness curve, the direction of the center line of the roughness curve of the picked portion is represented by an X-axis, the direction of longitudinal magnification (direction perpendicular to the X-axis) is represented by a Y-axis, and the roughness curve is expressed as Y=F(X).




  
    
      
        
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When the specific surface which is a surface represented by measurement data is expressed as Z=F(X,Y), the average surface roughness (Ra) is an average value of the absolute values of deviations from the reference surface to the specific surface and is shown by the following formula (2).




  
    
      
        
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Here, the specific surface is a surface which is a target of roughness measurement, and is a quadrilateral region which is specified by four points represented by the coordinates (X1, Y1, F(X1,Y1)), (X1, Y2, F(X1,Y2)), (X2, Y1, F(X2,Y1)), and (X2, Y2, F(X2,Y2)).
S0 represents the area of a rectangle which is obtained by projecting the specific surface on the XY plane, and Z0 represents the height of the reference surface (the average height of the specific surface).
Chemical mechanical polishing (CMP) treatment may be performed so that the average surface roughness of the interlayer insulating film 505 can be greater than or equal to 0.1 nm and less than 0.5 nm. The CMP treatment may be performed before formation of the oxide semiconductor film, preferably before the first heat treatment.
The CMP treatment may be performed at least once. When the CMP treatment is performed plural times, it is preferable that first polishing be performed at a high polishing rate and final polishing be performed at a low polishing rate.
Instead of the CMP treatment, dry etching or the like may be performed in order to planarize the interlayer insulating film 505. As the etching gas, a chlorine-based gas such as a chlorine gas, a boron chloride gas, a silicon chloride gas, or a carbon tetrachloride gas, a fluorine-based gas such as a carbon tetrafluoride gas, a sulfur fluoride gas, or a nitrogen fluoride gas, or the like may be used.
Instead of the CMP treatment, plasma treatment or the like may be performed in order to planarize the interlayer insulating film 505. The plasma treatment may be performed here using a rare gas. In the plasma treatment, the surface to be processed is irradiated with ions of an inert gas and is planarized by a sputtering effect through removal of minute projections and depressions on the surface. Such plasma treatment is also referred to as “reverse sputtering”.
Note that any of the above treatments may be employed in order to planarize the interlayer insulating film 505. For example, only reverse sputtering may be performed, or dry etching may be performed after CMP treatment is performed. Note that dry etching or reverse sputtering is preferably used so that water and the like can be prevented from entering the interlayer insulating film 505 over which the oxide semiconductor film is to be formed. In particular, in the case where the planarization treatment is performed after the first heat treatment, dry etching or reverse sputtering is preferably used.
The oxide semiconductor layer 511 may be selectively formed in such a manner that an oxide semiconductor film is formed, an etching mask is formed over the oxide semiconductor film, and etching is performed. Alternatively, an ink jet method or the like may be used.
The oxide semiconductor film preferably contains at least indium (In) or zinc (Zn). In particular, both In and Zn are preferably contained. In addition, gallium (Ga) is preferably contained. When gallium (Ga) is contained, variation in the transistor characteristics can be reduced. Such an element capable of reducing variation in the transistor characteristics is referred to as a stabilizer. As a stabilizer, tin (Sn), hafnium (Hf), or aluminum (Al) can be given.
As another stabilizer, a lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) can be given. One or a plurality of these elements can be used.
As the oxide semiconductor, for example, an indium oxide, a tin oxide, a zinc oxide, a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zb-based oxide, an Al—Zb-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide, a three-component metal oxide such as a Sn—Ga—Zb-based oxide, an Al—Ga—Zb-based oxide, a Sn—Al—Zb-based oxide, an In—Ga—Zb-based oxide (also referred to as IGZO), an In—Al—Zb-based oxide, an In—Sn—Zb-based oxide, an In—Hf—Zb-based oxide, an In—La—Zb-based oxide, an In—Ce—Zb-based oxide, an In—Pr—Zb-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, an In—Lu—Zn-based oxide, or an In—Zr—Zn-based oxide, a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used.
Note that here, for example, an “In—Ga—Zn-based oxide” means an oxide containing In, Ga, and Zn as main components and there is no limitation on the ratio of In:Ga:Zn. Further, a metal element in addition to In, Ga, and Zn may be contained.
For example, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or an oxide with an atomic ratio close to the above atomic ratios can be used. Alternatively, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or an oxide with an atomic ratio close to the above atomic ratios may be used.
However, the oxide semiconductor film which can be used in one embodiment of the present invention is not limited to those described above, and an oxide semiconductor film having an appropriate composition may be used depending on needed semiconductor characteristics (mobility, threshold voltage, variation, and the like). In accordance with needed transistor characteristics (semiconductor characteristics), the carrier density, the impurity concentration, the defect density, the atomic ratio between a metal element and oxygen, the interatomic distance, the density, and the like may be appropriately adjusted.
For example, with the In—Sn—Zn-based oxide, a relatively high mobility can be obtained. However, mobility can be increased by reducing the defect density in the bulk also in the case of using the In—Ga—Zn-based oxide.
The oxide semiconductor may be either single crystal or non-single-crystal. In the case where the oxide semiconductor is non-single-crystal, the oxide semiconductor may be either amorphous or polycrystalline. Further, the oxide semiconductor may have a structure including a crystalline portion in an amorphous portion. Moreover, the oxide semiconductor may be non-amorphous.
Note that the metal oxide preferably contains oxygen in excess of the stoichiometry. When excess oxygen is contained, generation of carriers due to oxygen deficiency in the oxide semiconductor film to be formed can be prevented.
Note that for example, in the case where the oxide semiconductor film is formed using an In—Zn-based metal oxide, a target has a composition ratio where In/Zn is 1 to 100, preferably 1 to 20, more preferably 1 to 10 in atomic ratio. When the atomic ratio of Zn is in the above preferred range, field-effect mobility can be improved. Here, when the atomic ratio of the metal oxide is In:Zn:O=X:Y:Z, it is preferable to satisfy the relation of Z>1.5X+Y so that excess oxygen is contained.
Note that the filling factor of the target is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% and less than or equal to 99.9%. With a high filling factor, a dense oxide semiconductor film can be formed.
Note that the energy gap of a metal oxide which can be applied to the oxide semiconductor film is preferably 2 eV or more, more preferably 2.5 eV or more, still more preferably 3 eV or more. In this manner, the off-state current of a transistor can be reduced by using a metal oxide having a wide band gap.
Note that the oxide semiconductor film contains hydrogen. As hydrogen, a hydrogen atom, a hydrogen molecule, water, a hydroxyl group, or hydride may be contained in the oxide semiconductor film. It is preferable that hydrogen contained in the oxide semiconductor film be as little as possible.
Note that the concentrations of an alkali metal and an alkaline earth metal in the oxide semiconductor film are preferably low, and these concentrations are preferably 1×1018 atoms/cm3 or lower, more preferably 2×1016 atoms/cm3 or lower. This is because an alkali metal and an alkaline earth metal may be bonded to an oxide semiconductor to generate carriers, in which case the off-state current of the transistor is increased.
Note that there is no particular limitation on the formation method and the thickness of the oxide semiconductor film, which can be determined in consideration of the size or the like of a transistor to be manufactured. As an example of a method for forming the oxide semiconductor film, a sputtering method, a molecular beam epitaxy method, a coating method, a printing method, a pulsed laser deposition method, or the like can be given. The thickness of the oxide semiconductor film may be greater than or equal to 3 nm and less than or equal to 50 nm. This is because the transistor might be normally on when the oxide semiconductor film has a large thickness of more than 50 nm. In a transistor having a channel length of 30 μm, when the oxide semiconductor film has a thickness of 5 nm or less, a short-channel effect can be suppressed.
Here, as a preferable example, the oxide semiconductor film is formed by a sputtering method using an In—Ga—Zn-based metal oxide target. A rare gas (for example, an argon gas), an oxygen gas, or a mixed gas of a rare gas and an oxygen gas may be used as a sputtering gas.
It is preferable that a high-purity gas in which hydrogen, water, a hydroxyl group, or hydride is reduced be used as the sputtering gas for the formation of the oxide semiconductor film. In order to keep the high purity of a sputtering gas, a gas attached to the inner wall of a treatment chamber or the like is removed, and the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor may be subjected to heat treatment before the oxide semiconductor film is formed. In addition, a high-purity sputtering gas may be introduced into the treatment chamber, which may be an argon gas having a purity of 9N (99.9999999%) or more, a dew point of −121° C. or less, a water content of 0.1 ppb or less, and a hydrogen content of 0.5 ppb or less or may be an oxygen gas having a purity of 8N (99.999999%) or more, a dew point of −112° C. or less, a water content of 1 ppb or less, and a hydrogen content of 1 ppb or less. When the oxide semiconductor film is formed while the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor is being heated and kept at a high temperature, the concentration of impurities such as water contained in the oxide semiconductor film can be reduced. Furthermore, damage to the oxide semiconductor film by use of a sputtering method can be reduced. Here, the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor may be kept at a temperature of higher than or equal to 100° C. and lower than or equal to 600° C., preferably higher than or equal to 200° C. and lower than or equal to 400° C.
In addition, oxygen may be supplied by ion implantation so that the oxide semiconductor film contains excess oxygen.
Note that the oxide semiconductor film may have an amorphous structure or a crystalline structure. In one embodiment in the case of having a crystalline structure, the oxide semiconductor film is preferably a c-axis aligned crystalline oxide semiconductor (C-Axis Aligned Crystalline Oxide Semiconductor: CAAC-OS) film. When the oxide semiconductor film is a CAAC-OS film, the reliability of the transistor can be increased.
Note that the CAAC-OS film means an oxide semiconductor film including a crystal which has c-axis alignment and a triangular or hexagonal atomic arrangement when seen from the direction of an a-b plane, a surface, or an interface. In the crystal, metal atoms are arranged in a layered manner, or metal atoms and oxygen atoms are arranged in a layered manner along the c-axis, and the direction of the a-axis or the b-axis is varied in the a-b plane (or the surface, or at the interface) (the crystal rotates around the c-axis).
Note that the CAAC-OS film means, in a broad sense, a non-single-crystal oxide semiconductor film including a phase which has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from the direction perpendicular to the a-b plane and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.
Note that the CAAC-OS film is not single crystal, but this does not mean that the CAAC-OS film is composed of only an amorphous component. Although the CAAC-OS film includes a crystallized portion (crystalline portion), a boundary between one crystalline portion and another crystalline portion is not clear in some cases.
Part of oxygen included in the CAAC-OS film may be substituted with nitrogen. The c-axes of individual crystalline portions included in the CAAC-OS film may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate over which the CAAC-OS film is formed, a surface of the CAAC-OS film, or an interface of the CAAC-OS film). Alternatively, normals of the a-b planes of individual crystalline portions included in the CAAC-OS film may be aligned in one direction (e.g., a direction perpendicular to the surface of the substrate over which the CAAC-OS film is formed, the surface of the CAAC-OS film, or the interface of the CAAC-OS film).
Note that the CAAC-OS film may be a conductor, a semiconductor, or an insulator depending on its composition or the like. The CAAC-OS film transmits or does not transmit visible light depending on its composition or the like.
An example of such a CAAC-OS film is a film formed using a material which has a triangular or hexagonal atomic arrangement when observed from the direction perpendicular to a surface of the film, a surface of a substrate, or an interface and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner when a cross section of the film is observed.
Examples of crystal structures included in such a CAAC-OS film will be described in detail with reference to FIGS. 7A to 7E, FIGS. 8A to 8C, and FIGS. 9A to 9C. In FIGS. 7A to 7E, FIGS. 8A to 8C, and FIGS. 9A to 9C, the vertical direction basically corresponds to the c-axis direction and a plane perpendicular to the c-axis direction basically corresponds to the a-b plane. When the expression “an upper half” or “a lower half” is simply used, the boundary is the a-b plane. Furthermore, in FIGS. 7A to 7E, O surrounded by a circle represents a tetracoordinate O atom and O surrounded by a double circle represents a tricoordinate O atom.
FIG. 7A illustrates a structure including one hexacoordinate indium (hereinafter referred to as In) atom and six tetracoordinate oxygen (hereinafter referred to as tetracoordinate O) atoms proximate to the In atom. A structure in which one In atom and oxygen atoms proximate to the In atom are only illustrated is called a subunit here. The structure in FIG. 7A is actually an octahedral structure, but is illustrated as a planar structure for simplicity. Note that three tetracoordinate O atoms exist in each of an upper half and a lower half in FIG. 7A. In the subunit illustrated in FIG. 7A, electric charge is 0.
FIG. 7B illustrates a structure including one pentacoordinate gallium (hereinafter referred to as Ga) atom, three tricoordinate oxygen (hereinafter referred to as tricoordinate O) atoms proximate to the Ga atom, and two tetracoordinate O atoms proximate to the Ga atom. All the tricoordinate O atoms exist on the a-b plane. One tetracoordinate O atom exists in each of an upper half and a lower half in FIG. 7B. An In atom can also have the structure illustrated in FIG. 7B because an In atom can have five ligands. In the subunit illustrated in FIG. 7B, electric charge is 0.
FIG. 7C illustrates a structure including one tetracoordinate zinc (hereinafter referred to as Zn) atom and four tetracoordinate O atoms proximate to the Zn atom. In FIG. 7C, one tetracoordinate O atom exists in an upper half and three tetracoordinate O atoms exist in a lower half. Alternatively, three tetracoordinate O atoms may exist in the upper half and one tetracoordinate O atom may exist in the lower half in FIG. 7C. In the subunit illustrated in FIG. 7C, electric charge is 0.
FIG. 7D illustrates a structure including one hexacoordinate tin (hereinafter referred to as Sn) atom and six tetracoordinate O atoms proximate to the Sn atom. In FIG. 7D, three tetracoordinate O atoms exist in each of an upper half and a lower half. In the subunit illustrated in FIG. 7D, electric charge is +1.
FIG. 7E illustrates a subunit including two Zn atoms. In FIG. 7E, one tetracoordinate O atom exists in each of an upper half and a lower half. In the subunit illustrated in FIG. 7E, electric charge is −1.
Here, a plurality of subunits forms one group, and a plurality of groups forms one cycle which is called a unit.
Now, a rule of bonding between the subunits will be described. The three O atoms in the upper half with respect to the hexacoordinate In atom in FIG. 7A each have three proximate In atoms in the downward direction, and the three O atoms in the lower half each have three proximate In atoms in the upward direction. The one O atom in the upper half with respect to the pentacoordinate Ga atom in FIG. 7B has one proximate Ga atom in the downward direction, and the one O atom in the lower half has one proximate Ga atom in the upward direction. The one O atom in the upper half with respect to the tetracoordinate Zn atom in FIG. 7C has one proximate Zn atom in the downward direction, and the three O atoms in the lower half each have three proximate Zn atoms in the upward direction. In this manner, the number of the tetracoordinate O atoms above the metal atom is equal to the number of the metal atoms proximate to and below each of the tetracoordinate O atoms. Similarly, the number of the tetracoordinate O atoms below the metal atom is equal to the number of the metal atoms proximate to and above each of the tetracoordinate O atoms. Since the coordination number of the tetracoordinate O atom is 4, the sum of the number of the metal atoms proximate to and below the O atom and the number of the metal atoms proximate to and above the O atom is 4. Accordingly, when the sum of the number of tetracoordinate O atoms above a metal atom and the number of tetracoordinate O atoms below another metal atom is 4, the two kinds of subunits including the metal atoms can be bonded. For example, in the case where the hexacoordinate metal (In or Sn) atom is bonded through three tetracoordinate O atoms in the lower half, it is bonded to the pentacoordinate metal (Ga or In) atom or the tetracoordinate metal (Zn) atom.
A metal atom whose coordination number is 4, 5, or 6 is bonded to another metal atom through a tetracoordinate O atom in the c-axis direction. In addition to the above, one group can be formed in a different manner by combining a plurality of subunits so that the total electric charge of the layered structure is 0.
FIG. 8A illustrates a model of one group included in a layered structure of an In—Sn—Zn-based metal oxide. FIG. 8B illustrates a unit including three groups. Note that FIG. 8C illustrates an atomic arrangement in the case where the layered structure in FIG. 8B is observed from the c-axis direction.
In FIG. 8A, a tricoordinate O atom is omitted for simplicity, and a tetracoordinate O atom is illustrated by a circle; the number in the circle shows the number of tetracoordinate O atoms. For example, three tetracoordinate O atoms existing in each of an upper half and a lower half with respect to a Sn atom are denoted by circled 3. Similarly, in FIG. 8A, one tetracoordinate O atom existing in each of an upper half and a lower half with respect to an In atom is denoted by circled 1. Similarly, FIG. 8A also illustrates a Zn atom proximate to one tetracoordinate O atom in a lower half and three tetracoordinate O atoms in an upper half, and a Zn atom proximate to one tetracoordinate O atom in an upper half and three tetracoordinate O atoms in a lower half.
In the group included in the layered structure of the In—Sn—Zn-based metal oxide in FIG. 8A, in the order starting from the top, a Sn atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to an In atom proximate to one tetracoordinate O atom in each of an upper half and a lower half, the In atom is bonded to a Zn atom proximate to three tetracoordinate O atoms in an upper half, the Zn atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Zn atom, the In atom is bonded to a subunit that includes two Zn atoms and is proximate to one tetracoordinate O atom in an upper half, and the subunit is bonded to a Sn atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the subunit. A plurality of such groups is bonded to form one unit that corresponds to one cycle.
Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively. For example, electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4, respectively. Thus, electric charge of a subunit including a Sn atom is +1. Accordingly, electric charge of −1, which cancels +1, is needed to form a layered structure including a Sn atom. As a structure having electric charge of −1, the subunit including two Zn atoms as illustrated in FIG. 7E can be given. For example, with one subunit including two Zn atoms, electric charge of one subunit including a Sn atom can be cancelled, so that the total electric charge of the layered structure can be 0.
An In atom can have either five ligands or six ligands. Specifically, using the unit illustrated in FIG. 8B, In—Sn—Zn-based metal oxide crystal (In2SnZn3O8) can be obtained. Note that a layered structure of the obtained In—Sn—Zn-based metal oxide crystal can be expressed by a composition formula, In2SnZn2O7(ZnO)m (m is 0 or a natural number).
The above-described rule also applies to other metal oxides. As an example, FIG. 9A illustrates a model of a group included in a layered structure of In—Ga—Zn-based metal oxide crystal.
In the group included in the layered structure of the In—Ga—Zn-based metal oxide crystal in FIG. 9A, in the order starting from the top, an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to one tetracoordinate O atom in an upper half of a Zn atom, the Zn atom is bonded to a Ga atom proximate to one tetracoordinate O atom in each of an upper half and a lower half through three tetracoordinate O atoms in a lower half with respect to the Zn atom, and the Ga atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Ga atom. A plurality of such groups is bonded to form a unit that corresponds to one cycle.
FIG. 9B illustrates a unit including three groups. Note that FIG. 9C illustrates an arrangement of atoms in the case where the layered structure in FIG. 9B is observed from the c-axis direction.
Here, since electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate) Ga atom are +3, +2, and +3, respectively, electric charge of a subunit including any of an In atom, a Zn atom, and a Ga atom is 0. As a result, the total electric charge of a group having a combination of such subunits is always 0.
Note that the group included in the layered structure of the In—Ga—Zn-based metal oxide crystal is not limited to the group illustrated in FIG. 9A.
Here, a method for forming the CAAC-OS film is described.
First, an oxide semiconductor film is formed by a sputtering method or the like. Note that by forming the oxide semiconductor film while keeping the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor at high temperature, the ratio of a crystalline portion to an amorphous portion can be high. At this time, the temperature of the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor may be, for example, higher than or equal to 150° C. and lower than or equal to 450° C., preferably higher than or equal to 200° C. and lower than or equal to 350° C.
Here, the formed oxide semiconductor film may be subjected to a heat treatment. By the heat treatment, the ratio of a crystalline portion to an amorphous portion can be high. In the heat treatment, the temperature of the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor is, for example, higher than or equal to 200° C. and lower than a temperature at which the semiconductor substrate 500 provided with the p-channel transistor and the n-channel transistor alters or deforms, preferably higher than or equal to 250° C. and lower than or equal to 450° C. The heat treatment may be performed for 3 minutes or longer, and preferably 24 hours or shorter. This is because the productivity is decreased when the heat treatment is performed for a long time, although the ratio of a crystalline portion to an amorphous portion can be high. Note that the heat treatment may be performed in an oxidizing atmosphere or an inert atmosphere; however, there is no limitation thereon. This heat treatment may be performed under a reduced pressure.
The oxidizing atmosphere is an atmosphere containing an oxidizing gas. As examples of the oxidizing gas, oxygen, ozone, nitrous oxide, and the like can be given. It is preferable that components (e.g., water and hydrogen) which are not preferably contained in the oxide semiconductor film be removed from the oxidizing atmosphere as much as possible. For example, the purity of oxygen, ozone, or nitrous oxide may be higher than or equal to 8N (99.999999%), more preferably higher than or equal to 9N (99.9999999%).
The oxidizing atmosphere may contain an inert gas such as a rare gas. Note that the oxidizing atmosphere contains an oxidizing gas at a concentration of higher than or equal to 10 ppm. An inert atmosphere contains an inert gas (a nitrogen gas, a rare gas, or the like) and contains a reactive gas such as an oxidizing gas at a concentration of lower than 10 ppm.
Note that a rapid thermal annealing (RTA) apparatus may be used for all the heat treatments. With the use of the RTA apparatus, the heat treatment can be performed at high temperature if the heating time is short. Thus, the oxide semiconductor film having a high ratio of a crystalline portion to an amorphous portion can be formed, and a decrease in productivity can be suppressed.
However, the apparatus used for all the heat treatments is not limited to an RTA apparatus; for example, an apparatus provided with a unit that heats an object to be processed by thermal conduction or thermal radiation from a resistance heater or the like may be used. For example, an electric furnace or a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be given as the heat treatment apparatus used for all the heat treatments. Note that an LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for heating an object to be processed using a high-temperature gas as a heat medium. Here, the temperature of the high-temperature gas is preferably higher than the heat temperature of the object to be processed.
With the use of an In—Ga—Zn-based metal oxide in which the nitrogen concentration is higher than or equal to 1×1017 atoms/cm3 and lower than or equal to 5×1019 atoms/cm3, a metal oxide film having a c-axis-aligned hexagonal crystal structure is formed and one or more layers containing Ga and Zn are provided between two layers of the In—O crystal planes (crystal planes containing indium and oxygen).
For example, the CAAC-OS film is formed by a sputtering method with a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target may be separated from the target along an a-b plane; in other words, a sputtered particle having a plane parallel to an a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) may flake off from the sputtering target. In that case, the flat-plate-like sputtered particle reaches a substrate while maintaining their crystal state, whereby the CAAC-OS film can be formed.
For the deposition of the CAAC-OS film, the following conditions are preferably used.
By reducing the amount of impurities entering the CAAC-OS film during the deposition, the crystal state can be prevented from being broken by the impurities. For example, the concentration of impurities (e.g., hydrogen, water, carbon dioxide, or nitrogen) which exist in the deposition chamber may be reduced. Furthermore, the concentration of impurities in a deposition gas may be reduced. Specifically, a deposition gas whose dew point is −80° C. or lower, preferably −100° C. or lower is used.
By increasing the substrate heating temperature during the deposition, migration of a sputtered particle is likely to occur after the sputtered particle reaches a substrate surface. Specifically, the substrate heating temperature during the deposition is higher than or equal to 100° C. and lower than or equal to 740° C., preferably higher than or equal to 200° C. and lower than or equal to 500° C. By increasing the substrate heating temperature during the deposition, when the flat-plate-like sputtered particle reaches the substrate, migration occurs on the substrate surface, so that a flat plane of the flat-plate-like sputtered particle is attached to the substrate.
Furthermore, it is preferable that the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition. The proportion of oxygen in the deposition gas is 30 vol % or higher, preferably 100 vol %.
As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.
The In—Ga—Zn—O compound target, which is polycrystalline, is made by mixing InOX powder, GaOY powder, and ZnOZ powder in a predetermined molar ratio, applying pressure, and performing heat treatment at a temperature higher than or equal to 1000° C. and lower than or equal to 1500° C. Note that X, Y and Z are given positive numbers. Here, the predetermined molar ratio of InOX powder to GaOY powder and ZnOZ powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The kinds of powder and the molar ratio for mixing powder may be determined as appropriate depending on the desired sputtering target.
In order to form an In—Sn—Zn-based metal oxide, a target of In:Sn:Zn=1:2:2, 2:1:3, 1:1:1, or 20:45:35 in atomic ratio may be used, for example.
As described above, the CAAC-OS film can be formed.
The CAAC-OS film has high orderliness of a bond between metal and oxygen as compared to an oxide semiconductor film having an amorphous structure. In other words, in the case of an oxide semiconductor film having an amorphous structure, the number of oxygen atoms coordinated around an adjacent metal atom varies according to the kind of the adjacent metal. In contrast, in the case of the CAAC-OS film, the number of oxygen atoms coordinated around an adjacent metal atom is substantially the same. Therefore, oxygen deficiency is hardly observed even at a microscopic level, and charge transfer and instability of electric conductivity due to hydrogen atoms (including hydrogen ions), alkali metal atoms, or the like can be suppressed.
Therefore, when a transistor has a CAAC-OS film used for a channel formation region, it is possible to suppress the shift of the threshold voltage of the transistor which occurs through light irradiation or a bias-temperature stress (BT) test on the transistor, so that the transistor can have stable electrical characteristics.
Next, an etching mask is formed over the oxide semiconductor film and etching is performed, whereby the oxide semiconductor layer 511 is formed (FIG. 6A).
Then, the source electrode 512a and the drain electrode 512b which are apart from each other are formed in contact with the oxide semiconductor layer 511 (FIG. 6B).
The source electrode 512a and the drain electrode 512b may be selectively formed in such a manner that, for example, a conductive film (e.g., a metal film or a silicon film to which an impurity element imparting one conductivity type is added) is formed by a sputtering method, an etching mask is formed over the conductive film, and etching is performed. Alternatively, an ink jet method may be used. Note that the conductive film to be the source electrode 512a and the drain electrode 512b may be formed by using a single layer or by stacking a plurality of layers. For example, the conductive film may be formed to have a three-layer structure in which an Al layer is sandwiched between Ti layers. Note that a layer serving as the source electrode 512a and the drain electrode 512b also functions as a signal line.
Next, the gate insulating film 513 is formed over at least the channel formation region of the oxide semiconductor layer 511, and after the gate insulating film 513 is formed, an opening is formed (FIG. 6C). The opening is formed so as to overlap with the gate electrode 504.
As the gate insulating film 513, for example, a film of an insulating material (for example, silicon nitride, silicon nitride oxide, silicon oxynitride, silicon oxide, or the like) may be formed using a sputtering method. Note that the gate insulating film 513 may be formed by using a single layer or by stacking a plurality of layers. Here, the gate insulating film 513 is formed to have a two-layer structure in which a silicon oxynitride layer is stacked over a silicon nitride layer, for example. Note that in the case where the gate insulating film 513 is formed by a sputtering method, hydrogen and moisture can be prevented from entering the oxide semiconductor layer 511. In addition, the gate insulating film 513 is preferably an insulating oxide film because oxygen can be supplied to fill oxygen vacancies.
Note that “silicon nitride oxide” contains more nitrogen than oxygen. Further, “silicon oxynitride” contains more oxygen than nitrogen.
Here, the oxide semiconductor film may be processed by dry etching. For example, a chlorine gas or a mixed gas of a boron trichloride gas and a chlorine gas may be used as an etching gas used for the dry etching. However, there is no limitation thereon; wet etching may be used or another method capable of processing the oxide semiconductor film may be used.
The gate insulating film 513 contains oxygen at least in a portion in contact with the oxide semiconductor layer 511 and is preferably formed using an insulating oxide from which part of oxygen is released by heating. In other words, the materials given as examples of the material of the interlayer insulating film 505 are preferably used. When the portion of the gate insulating film 513 which is in contact with the oxide semiconductor layer 511 is formed using silicon oxide, oxygen can be diffused into the oxide semiconductor layer 511 and a reduction in the resistance of the transistor can be prevented.
Note that the gate insulating film 513 may be formed using a high-k material such as hafnium silicate (HfSiOx), hafnium silicate to which nitrogen is added (HfSixOyNz), hafnium aluminate to which nitrogen is added (HfAlxOyNz), hafnium oxide, yttrium oxide, or lanthanum oxide so that gate leakage current can be reduced. Here, gate leakage current refers to leakage current which flows between a gate electrode and a source or drain electrode. Further, a layer formed using the high-k material and a layer formed using silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, or gallium oxide may be stacked. Note that even in the case where the gate insulating film 513 has a stacked structure, the portion in contact with the oxide semiconductor layer 511 is preferably formed using an insulating oxide.
The gate insulating film 513 may be formed by a sputtering method. The thickness of the gate insulating film 513 may be greater than or equal to 1 nm and less than or equal to 300 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm. When the thickness of the gate insulating film 513 is greater than or equal to 5 nm, gate leakage current can be particularly reduced.
In addition, third heat treatment (preferably at a temperature of higher than or equal to 200° C. and lower than or equal to 400° C., for example, at a temperature of higher than or equal to 250° C. and lower than or equal to 350° C.) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. By the third heat treatment, hydrogen or moisture remaining in the oxide semiconductor layer 511 can be diffused into the gate insulating film. Furthermore, by the third heat treatment, oxygen can be supplied to the oxide semiconductor layer 511 from the gate insulating film 513 which serves as a source of oxygen.
The third heat treatment is performed after the gate insulating film 513 is formed over the oxide semiconductor layer 511 here, but the timing is not limited thereto. The third heat treatment may be performed after the electrode 514a and the gate electrode 514b are formed or a conductive film to be the electrode 514a and the gate electrode 514b is formed.
Note that the concentration of hydrogen in the oxide semiconductor layer 511 is preferably 5.0×1019 atoms/cm3 or lower, more preferably 5.0×1018 atoms/cm3 or lower. When the concentration of hydrogen is low as mentioned above, the threshold voltage of the transistor can be prevented from shifting in the negative direction.
Note that the oxide semiconductor layer 511 preferably has a low carrier concentration of lower than 1.0×1014/cm3. When the carrier concentration is low, off-state current can be low.
Next, a conductive film is formed over the gate insulating film 513, an etching mask is formed over the conductive film, and etching is performed, whereby the electrode 514a and the gate electrode 514b are formed (FIG. 6D). Note that a layer serving as the gate electrode 514b also functions at least as a scan line.
The electrode 514a and the gate electrode 514b may be formed using a material and a method which are similar to those for the source electrode 512a and the drain electrode 512b. 
Although not illustrated, it is preferable that a dopant be added to the oxide semiconductor layer 511 using the gate electrode 514b as a mask to form a source region and a drain region in the oxide semiconductor layer 511.
Note that here, the dopant may be added by an ion implantation method or an ion doping method. Alternatively, the dopant may be added by performing plasma treatment in an atmosphere of a gas containing the dopant. As the dopant, nitrogen, phosphorus, boron, or the like may be added.
In the above-described manner, an oxide semiconductor transistor can be manufactured over a transistor formed using a semiconductor substrate as illustrated in FIG. 5.
As described above, an oxide semiconductor is preferably used for the oxide semiconductor transistor. A transistor including an oxide semiconductor can have high field-effect mobility.
Note that the actual field-effect mobility of the transistor including an oxide semiconductor can be lower than its original mobility. One of the causes for the lower mobility is a defect inside a semiconductor or a defect at an interface between the semiconductor and an insulating film. When a Levinson model is used, the field-effect mobility on the assumption that no defect exists inside the semiconductor can be calculated theoretically.
Assuming that the original mobility and the measured field-effect mobility of a semiconductor are μ0 and μ, respectively, and a potential barrier (such as a grain boundary) exists in the semiconductor, the measured field-effect mobility can be expressed by the following formula (3).




  
    
      
        
          [
          
            Formula
            ⁢
            
              
            
            ⁢
            3
          
          ]
        
        ⁢
        
          
        
      
    
    
      
        
      
    
  
  
    
      
        μ
        =
        
          
            μ
            0
          
          ⁢
          
            exp
            ⁡
            
              (
              
                -
                
                  E
                  kT
                
              
              )
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




Here, E represents the height of the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature. When the potential barrier is assumed to be attributed to a defect, the height of the potential barrier can be expressed by the following formula (4) according to the Levinson model.




  
    
      
        
          [
          
            Formula
            ⁢
            
              
            
            ⁢
            4
          
          ]
        
        ⁢
        
          
        
      
    
    
      
        
      
    
  
  
    
      
        E
        =
        
          
            
              
                e
                2
              
              ⁢
              
                N
                2
              
            
            
              8
              ⁢
              ɛ
              ⁢
              
                
              
              ⁢
              n
            
          
          =
          
            
              
                e
                3
              
              ⁢
              
                N
                2
              
              ⁢
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              8
              ⁢
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              ⁢
              
                
              
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                C
                ox
              
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                g
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Here, e represents the elementary charge, N represents the average defect density per unit area in a channel, ∈ represents the dielectric constant of the semiconductor, n represents the number of carriers per unit area in the channel, Cox represents the capacitance per unit area, Vg represents the gate voltage, and t represents the thickness of the channel. In the case where the thickness of the semiconductor layer is less than or equal to 30 nm, the thickness of the channel may be regarded as being the same as the thickness of the semiconductor layer.
The drain current Id in a linear region can be expressed by the following formula (5).




  
    
      
        
          [
          
            Formula
            ⁢
            
              
            
            ⁢
            5
          
          ]
        
        ⁢
        
          
        
      
    
    
      
        
      
    
  
  
    
      
        
          I
          d
        
        =
        
          
            
              W
              ⁢
              
                
              
              ⁢
              μ
              ⁢
              
                
              
              ⁢
              
                V
                g
              
              ⁢
              
                V
                d
              
              ⁢
              
                C
                ox
              
            
            L
          
          ⁢
          
            exp
            ⁡
            
              (
              
                -
                
                  E
                  kT
                
              
              )
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




Here, L represents the channel length and W represents the channel width, and L and W are each 10 μm. In addition, Vd represents the drain voltage. When dividing both sides of the formula (5) by Vg and then taking logarithms of both sides, the following formula (6) can be obtained.




  
    
      
        
          [
          
            Formula
            ⁢
            
              
            
            ⁢
            6
          
          ]
        
        ⁢
        
          
        
      
    
    
      
        
      
    
  
  
    
      
        
          ln
          ⁡
          
            (
            
              
                I
                d
              
              
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                g
              
            
            )
          
        
        =
        
          
            
              ln
              ⁡
              
                (
                
                  
                    W
                    ⁢
                    
                      
                    
                    ⁢
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                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      d
                    
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                  L
                
                )
              
            
            -
            
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              kT
            
          
          =
          
            
              ln
              ⁡
              
                (
                
                  
                    W
                    ⁢
                    
                      
                    
                    ⁢
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                    ⁢
                    
                      
                    
                    ⁢
                    
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                      d
                    
                    ⁢
                    
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                      ox
                    
                  
                  L
                
                )
              
            
            -
            
              
                
                  e
                  3
                
                ⁢
                
                  N
                  2
                
                ⁢
                t
              
              
                8
                ⁢
                k
                ⁢
                
                  
                
                ⁢
                T
                ⁢
                
                  
                
                ⁢
                ɛ
                ⁢
                
                  
                
                ⁢
                
                  C
                  ox
                
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                  V
                  g
                
              
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




The right side of the formula (6) is a function of Vg. From the formula (6), it is found that the defect density N can be obtained from the slope of a line in a graph which is obtained by plotting actual measured values with ln(Id/Vg) as the ordinate and 1/Vg as the abscissa. That is, the defect density can be evaluated from the Id-Vg characteristics of the transistor. The defect density N of an oxide semiconductor in which the ratio of indium (In) to tin (Sn) and zinc (Zn) is 1:1:1 is approximately 1×1012/cm2.
On the basis of the defect density obtained in this manner, or the like, μ0 can be calculated to be 120 cm2/Vs from the formula (3) and the formula (4). The measured mobility of an In—Sn—Zn oxide including a defect is approximately 40 cm2/Vs. However, assuming that no defect exists inside the semiconductor and at the interface between the semiconductor and an insulating film, it is found from the above results that the mobility μ0 of the oxide semiconductor is 120 cm2/Vs.
Note that even when no defect exists inside a semiconductor, scattering at an interface between a channel and a gate insulating film affects the transport property of the transistor. In other words, the mobility μ1 at a position that is distance x away from the interface between the channel and the gate insulating film can be expressed by the following formula (7).




  
    
      
        
          [
          
            Formula
            ⁢
            
              
            
            ⁢
            7
          
          ]
        
        ⁢
        
          
        
      
    
    
      
        
      
    
  
  
    
      
        
          1
          
            μ
            1
          
        
        =
        
          
            1
            
              μ
              0
            
          
          +
          
            
              D
              B
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  -
                  
                    x
                    l
                  
                
                )
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




Here, D represents the electric field in the gate direction, and B and/are constants. B and/can be obtained from actual measurement results; according to the above measurement results, B is 4.75×107 cm/s and l is 10 nm (the depth to which the influence of interface scattering reaches). When D is increased (i.e., when the gate voltage is increased), the second term of the formula (7) is increased and accordingly the mobility μ1 is decreased.
Calculation results of the mobility μ2 of a transistor whose channel includes an ideal oxide semiconductor without a defect inside the semiconductor are shown in FIG. 10. For the calculation, device simulation software Sentaurus Device (manufactured by Synopsys, Inc.) was used, and the bandgap, the electron affinity, the relative permittivity, and the thickness of the oxide semiconductor were assumed to be 2.8 eV, 4.7 eV, 15, and 15 nm, respectively. Further, the work functions of a gate, a source, and a drain were assumed to be 5.5 eV, 4.6 eV, and 4.6 eV, respectively. The thickness of a gate insulating film was assumed to be 100 nm, and the relative permittivity thereof was assumed to be 4.1. The channel length and the channel width were each assumed to be 10 μm, and the drain voltage Vd was assumed to be 0.1 V.
As shown in FIG. 10, the mobility has a peak of more than or equal to 100 cm2/Vs at a gate voltage that is a little over 1 V and is decreased as the gate voltage becomes higher because the influence of interface scattering is increased. Note that in order to reduce interface scattering, it is preferable that a surface of the semiconductor layer be flat at the atomic level (atomic layer flatness), as described with the above formula (1) and the like.
Calculation results of characteristics of minute transistors which are manufactured using an oxide semiconductor having such a mobility are shown in FIGS. 11A to 11C, FIGS. 12A to 12C, and FIGS. 13A to 13C. FIGS. 14A and 14B illustrate cross-sectional structures of the transistors used for the calculation. The transistors illustrated in FIGS. 14A and 14B each include a semiconductor region 603a and a semiconductor region 603c which have n+-type conductivity in an oxide semiconductor layer. In the calculation, the resistivity of the semiconductor region 603a and the semiconductor region 603c was assumed to be 2×10−3 Ωcm.
The transistor illustrated in FIG. 14A includes a base insulating film 601, an embedded insulating film 602 which is embedded in the base insulating film 601 and formed of aluminum oxide, the semiconductor region 603a, the semiconductor region 603c, an intrinsic semiconductor region 603b serving as a channel formation region therebetween, and a gate 605. In the calculation, the width of the gate 605 was assumed to be 33 nm.
A gate insulating film 604 is formed between the gate 605 and the semiconductor region 603b. In addition, a sidewall insulator 606a and a sidewall insulator 606b are formed on both side surfaces of the gate 605, and an insulating film 607 is formed over the gate 605 so as to prevent a short circuit between the gate 605 and another wiring. The width of the sidewall insulator was assumed to be 5 nm. A source 608a and a drain 608b are provided in contact with the semiconductor region 603a and the semiconductor region 603c, respectively. Note that the channel width of this transistor is 40 nm.
The transistor illustrated in FIG. 14B includes the base insulating film 601, the embedded insulating film 602 formed of aluminum oxide, the semiconductor region 603a, the semiconductor region 603c, the intrinsic semiconductor region 603b serving as a channel formation region therebetween, the gate insulating film 604, the gate 605, the sidewall insulator 606a and the sidewall insulator 606b, the insulating film 607, the source 608a, and the drain 608b. 
The transistor illustrated in FIG. 14A is different from the transistor illustrated in FIG. 14B in the conductivity type of semiconductor regions directly below the sidewall insulator 606a and the sidewall insulator 606b. The semiconductor regions directly below the sidewall insulator 606a and the sidewall insulator 606b are regions having n+-type conductivity in the transistor illustrated in FIG. 14A, and are intrinsic semiconductor regions in the transistor illustrated in FIG. 14B. In other words, in the transistor illustrated in FIG. 14B, a region which overlaps with neither the semiconductor region 603a (the semiconductor region 603c) nor the gate 605 has a longer width by Loff. This region is called an offset region, and the width Loff is called an offset length. The offset length is equal to the width of the sidewall insulator 606a (the sidewall insulator 606b).
The other parameters used in calculation are as described above. For the calculation, device simulation software Sentaurus Device manufactured by Synopsys, Inc. was used. FIGS. 11A to 11C show the gate voltage (Vg: a potential difference obtained by subtracting the potential of the source from that of the gate) dependence of the drain current (Id, a solid line) and the mobility (μ, a dotted line) of the transistor having the structure illustrated in FIG. 14A. The drain current Id is obtained by calculation under the assumption that the drain voltage (Vd: a potential difference obtained by subtracting the potential of the source from that of the drain) is +1 V and the mobility μ is obtained by calculation under the assumption that the drain voltage is +0.1 V.
The thickness of the gate insulating film is 15 nm in FIG. 11A, 10 nm in FIG. 11B, and 5 nm in FIG. 11C. As the gate insulating film is thinner, the drain current Id (off-state current) particularly in an off state is significantly decreased. In contrast, there is no noticeable change in the peak value of the mobility μ and the drain current Id (on-state current) in an on state.
FIGS. 12A to 12C show the gate voltage Vg dependence of the drain current Id (a solid line) and the mobility μ (a dotted line) of the transistor illustrated in FIG. 14B where the offset length Loff is 5 nm. The drain current Id is obtained by calculation under the assumption that the drain voltage is +1 V and the mobility μ is obtained by calculation under the assumption that the drain voltage is +0.1 V. The thickness of the gate insulating film is 15 nm in FIG. 12A, 10 nm in FIG. 12B, and 5 nm in FIG. 12C.
FIGS. 13A to 13C show the gate voltage Vg dependence of the drain current Id (a solid line) and the mobility μ (a dotted line) of the transistor illustrated in FIG. 14B where the offset length Loff is 15 nm. The drain current Id is obtained by calculation under the assumption that the drain voltage is +1 V and the field-effect mobility μ is obtained by calculation under the assumption that the drain voltage is +0.1 V. The thickness of the gate insulating film is 15 nm in FIG. 13A, 10 nm in FIG. 13B, and 5 nm in FIG. 13C.
In either of the structures, as the gate insulating film is thinner, the off-state current is significantly decreased, whereas no noticeable change arises in the peak value of the mobility μ and the on-state current.
Note that the peak of the mobility μ is approximately 80 cm2/Vs in FIGS. 11A to 11C, approximately 60 cm2/Vs in FIGS. 12A to 12C, and approximately 40 cm2/Vs in FIGS. 13A to 13C; thus, the peak of the mobility μ is decreased as the offset length Loff is increased. Further, the same applies to the off-state current. The on-state current is also decreased as the offset length Loff is increased; however, the decrease in the on-state current is much more gradual than the decrease in the off-state current.
As described above, the oxide semiconductor transistor including an oxide semiconductor can have significantly high mobility.
Note that the transistor described in this embodiment as an oxide semiconductor transistor is a mere example, and without limitation thereto, various modes can be employed for the oxide semiconductor transistor.
A transistor in which an oxide semiconductor containing In, Sn, and Zn as main components is used as a channel formation region can have favorable characteristics by depositing the oxide semiconductor while heating a substrate or by performing heat treatment after forming an oxide semiconductor film. Note that a main component refers to an element included in a composition at 5 atomic % or more.
By intentionally heating the substrate after formation of the oxide semiconductor film containing In, Sn, and Zn as main components, the field-effect mobility of the transistor can be improved. Further, the threshold voltage of the transistor can be positively shifted to make the transistor normally off.
As an example, FIGS. 15A to 15C are graphs each showing characteristics of a transistor in which an oxide semiconductor film containing In, Sn, and Zn as main components and having a channel length L of 3 μm and a channel width W of 10 μm, and a gate insulating film with a thickness of 100 nm are used. Note that Vd was set to 10 V.
FIG. 15A shows characteristics of a transistor whose oxide semiconductor film containing In, Sn, and Zn as main components was formed by a sputtering method without heating a substrate intentionally. The field-effect mobility of the transistor is 18.8 cm2/Vsec. On the other hand, when the oxide semiconductor film containing In, Sn, and Zn as main components is formed while heating the substrate intentionally, the field-effect mobility can be improved. FIG. 15B shows characteristics of a transistor whose oxide semiconductor film containing In, Sn, and Zn as main components was formed while heating a substrate at 200° C. The field-effect mobility of the transistor is 32.2 cm2/Vsec.
The field-effect mobility can be further improved by performing heat treatment after formation of the oxide semiconductor film containing In, Sn, and Zn as main components. FIG. 15C shows characteristics of a transistor whose oxide semiconductor film containing In, Sn, and Zn as main components was formed by sputtering at 200° C. and then subjected to heat treatment at 650° C. The field-effect mobility of the transistor is 34.5 cm2/Vsec.
The intentional heating of the substrate is expected to have an effect of reducing moisture taken into the oxide semiconductor film during the formation by sputtering. Further, the heat treatment after film formation enables hydrogen, a hydroxyl group, or moisture to be released and removed from the oxide semiconductor film. In this manner, the field-effect mobility can be improved. Such an improvement in field-effect mobility is presumed to be achieved not only by removal of impurities by dehydration or dehydrogenation but also by a reduction in interatomic distance due to an increase in density. In addition, the oxide semiconductor can be crystallized by being highly purified by removal of impurities from the oxide semiconductor. In the case of using such a purified non-single-crystal oxide semiconductor, ideally, a field-effect mobility exceeding 100 cm2/Vsec is expected to be achieved.
The oxide semiconductor containing In, Sn, and Zn as main components may be crystallized in the following manner: oxygen ions are implanted into the oxide semiconductor, hydrogen, a hydroxyl group, or moisture included in the oxide semiconductor is released by heat treatment, and the oxide semiconductor is crystallized through the heat treatment or by another heat treatment performed later. By such crystallization treatment or recrystallization treatment, a non-single-crystal oxide semiconductor having favorable crystallinity can be obtained.
The intentional heating of the substrate during film formation and/or the heat treatment after the film formation contributes not only to improving field-effect mobility but also to making the transistor normally off. In a transistor in which an oxide semiconductor film that contains In, Sn, and Zn as main components and is formed without heating a substrate intentionally is used as a channel formation region, the threshold voltage tends to be shifted negatively. In contrast, when the oxide semiconductor film formed while heating the substrate intentionally is used, the problem of the negative shift of the threshold voltage can be solved. That is, the threshold voltage is shifted so that the transistor becomes normally off; this tendency can be confirmed by comparison between FIGS. 15A and 15B.
Note that the threshold voltage can also be controlled by changing the ratio of In to Sn and Zn; when the composition ratio of In to Sn and Zn is 2:1:3, a normally-off transistor is expected to be formed. In addition, an oxide semiconductor film having high crystallinity can be obtained by setting the composition ratio of a target as follows: In:Sn:Zn=2:1:3.
The temperature of the intentional heating of the substrate or the temperature of the heat treatment is 150° C. or higher, preferably 200° C. or higher, further preferably 400° C. or higher. When film formation or heat treatment is performed at high temperature, the transistor can be normally off.
By intentionally heating the substrate during film formation and/or by performing heat treatment after the film formation, the stability against a gate-bias stress can be increased. For example, when a gate bias is applied with an intensity of 2 MV/cm at 150° C. for one hour, drift of the threshold voltage can be less than ±1.5 V, preferably less than ±1.0 V.
A BT test was performed on the following two transistors: Sample 1 on which heat treatment was not performed after formation of an oxide semiconductor film, and Sample 2 on which heat treatment at 650° C. was performed after formation of an oxide semiconductor film.
First, Vg-Id characteristics of the transistors were measured at a substrate temperature of 25° C. and Vd of 10 V. Then, the substrate temperature was set to 150° C. and Vd was set to 0.1 V. After that, Vg of 20 V was applied so that the intensity of an electric field applied to gate insulating films was 2 MV/cm, and the condition was kept for one hour. Next, Vg was set to 0 V. Then, Vg-Id characteristics of the transistors were measured at a substrate temperature of 25° C. and Vd of 10 V. This process is called a positive BT test.
In a similar manner, first, Vg-Id characteristics of the transistors were measured at a substrate temperature of 25° C. and Vd of 10 V. Then, the substrate temperature was set at 150° C. and Vd was set to 0.1 V. After that, Vg of −20 V was applied so that the intensity of an electric field applied to the gate insulating films was −2 MV/cm, and the condition was kept for one hour. Next, Vg was set to 0 V. Then, Vg-Id characteristics of the transistors were measured at a substrate temperature of 25° C. and Vd of 10 V. This process is called a negative BT test.
FIGS. 16A and 16B show results of the positive BT test and the negative BT test, respectively, of Sample 1. FIGS. 17A and 17B show results of the positive BT test and the negative BT test, respectively, of Sample 2.
The amount of shift in the threshold voltage of Sample 1 due to the positive BT test and that due to the negative BT test were 1.80 V and −0.42 V, respectively. The amount of shift in the threshold voltage of Sample 2 due to the positive BT test and that due to the negative BT test were 0.79 V and 0.76 V, respectively. It is found that, in each of Sample 1 and Sample 2, the amount of shift in the threshold voltage between before and after the BT tests is small and the reliability is high.
The heat treatment can be performed in an oxygen atmosphere; alternatively, the heat treatment may be performed first in an atmosphere of nitrogen or an inert gas or under reduced pressure, and then in an atmosphere including oxygen. Oxygen is supplied to the oxide semiconductor after dehydration or dehydrogenation, whereby the effect of the heat treatment can be further increased. As a method for supplying oxygen after dehydration or dehydrogenation, a method in which oxygen ions are accelerated by an electric field and implanted into the oxide semiconductor film may be employed.
A defect due to oxygen vacancy is easily caused in the oxide semiconductor or at an interface between the oxide semiconductor and a film stacked over the oxide semiconductor; when excess oxygen is included in the oxide semiconductor by the heat treatment, oxygen vacancy caused constantly can be compensated for with excess oxygen. The excess oxygen is mainly oxygen existing between lattices. When the concentration of oxygen is set in the range of 1×1016 atoms/cm3 to 2×1020 atoms/cm3, excess oxygen can be included in the oxide semiconductor without causing crystal distortion or the like.
When heat treatment is performed so that at least part of the oxide semiconductor includes crystal, a more stable oxide semiconductor film can be obtained. For example, when an oxide semiconductor film that is formed by sputtering using a target having a composition ratio of In:Sn:Zn=1:1:1 without heating a substrate intentionally is analyzed by X-ray diffraction (XRD), a halo pattern is observed. The formed oxide semiconductor film can be crystallized by being subjected to heat treatment. The temperature of the heat treatment can be set as appropriate; when the heat treatment is performed at 650° C., for example, a clear diffraction peak can be observed with X-ray diffraction.
An XRD analysis of an In—Sn—Zn—O film was conducted. The XRD analysis was conducted using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS, and measurement was performed by an out-of-plane method.
Sample A and Sample B were prepared and the XRD analysis was performed thereon. A method for forming Sample A and Sample B will be described below.
An In—Sn—Zn—O film with a thickness of 100 nm was formed over a quartz substrate that had been subjected to dehydrogenation treatment.
The In—Sn—Zn—O film was formed with a sputtering apparatus with a power of 100 W (DC) in an oxygen atmosphere. An In—Sn—Zn—O target having an atomic ratio of In:Sn:Zn=1:1:1 was used as a target. Note that the substrate heating temperature in film formation was set at 200° C. A sample formed in this manner was used as Sample A.
Next, a sample formed by a method similar to that of Sample A was subjected to heat treatment at 650° C. As the heat treatment, heat treatment in a nitrogen atmosphere was performed first for one hour and heat treatment in an oxygen atmosphere was further performed for one hour without lowering the temperature. A sample formed in this manner was used as Sample B.
FIG. 20 shows XRD spectra of Sample A and Sample B. No peak derived from crystal was observed in Sample A, whereas peaks derived from crystal were observed when 2θ was around 35 deg. and at 37 deg. to 38 deg. in Sample B.
As described above, by intentionally heating a substrate during deposition of an oxide semiconductor containing In, Sn, and Zn as main components and/or by performing heat treatment after the deposition, characteristics of a transistor can be improved.
These substrate heating and heat treatment have an effect of preventing hydrogen and a hydroxyl group, which are unfavorable impurities for an oxide semiconductor, from being contained in the film or an effect of removing hydrogen and a hydroxyl group from the film. That is, an oxide semiconductor can be purified by removing hydrogen serving as a donor impurity from the oxide semiconductor, whereby a normally-off transistor can be obtained. The purification of an oxide semiconductor enables the off-state current of the transistor to be 1 aA/μm or lower. Here, the unit of the off-state current represents current per micrometer of a channel width.
FIG. 21 shows a relation between the off-state current of a transistor and the inverse of substrate temperature (absolute temperature) at measurement. Here, for simplicity, the horizontal axis represents a value (1000/T) obtained by multiplying an inverse of substrate temperature at measurement by 1000.
Specifically, as shown in FIG. 21, the off-state current was 0.1 aA/μm (1×10−19 A/μm) or smaller and 10 zA/μm (1×10−20 A/μm) or smaller when the substrate temperature was 125° C. and 85° C., respectively. The proportional relation between the logarithm of the off-state current and the inverse of the temperature suggests that the off-state current at room temperature (27° C.) is 0.1 zA/μm (1×10−22 A/μm) or smaller. Hence, the off-state current can be 1 aA/μm (1×10−18 A/μm) or smaller, 100 zA/μm (1×10−19 A/μm) or smaller, and 1 zA/μm (1×10−21 A/μm) or smaller at 125° C., 85° C., and room temperature, respectively.
Note that in order to prevent hydrogen and moisture from being contained in the oxide semiconductor film during formation of the film, it is preferable to increase the purity of a sputtering gas by sufficiently suppressing leakage from the outside of a deposition chamber and degasification from an inner wall of the deposition chamber. For example, a gas with a dew point of −70° C. or lower is preferably used as the sputtering gas in order to prevent moisture from being contained in the film. In addition, it is preferable to use a target that is purified so as not to contain impurities such as hydrogen and moisture. Although it is possible to remove moisture from a film of an oxide semiconductor containing In, Sn, and Zn as main components by heat treatment, a film that does not contain moisture originally is preferably formed because moisture is released from the oxide semiconductor containing In, Sn, and Zn as main components at a higher temperature than from an oxide semiconductor containing In, Ga, and Zn as main components.
The relation between the substrate temperature and electrical characteristics of the transistor of the sample, on which heat treatment at 650° C. was performed after formation of the oxide semiconductor film, was evaluated.
The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, Lov of 0 μm, and dW of 0 μm. Note that Vd was set to 10 V. Note that the substrate temperatures were −40° C., −25° C., 25° C., 75° C., 125° C., and 150° C. Here, in the transistor, the width of a portion where a gate electrode overlaps with one of a pair of electrodes is referred to as Lov, and the width of a portion of the pair of electrodes, which does not overlap with an oxide semiconductor film, is referred to as dW.
FIG. 18 shows the Vg dependence of Id (a solid line) and field-effect mobility (a dotted line). FIG. 19A shows a relation between the substrate temperature and the threshold voltage, and FIG. 19B shows a relation between the substrate temperature and the field-effect mobility.
From FIG. 19A, it is found that the threshold voltage gets lower as the substrate temperature increases. Note that the threshold voltage is decreased from 1.09 V to −0.23 V in the range from −40° C. to 150° C.
From FIG. 19B, it is found that the field-effect mobility gets lower as the substrate temperature increases. Note that the field-effect mobility is decreased from 36 cm2/Vs to 32 cm2/Vs in the range from −40° C. to 150° C. Thus, it is found that variation in electrical characteristics is small in the above temperature range.
In a transistor in which such an oxide semiconductor containing In, Sn, and Zn as main components is used as a channel formation region, a field-effect mobility of 30 cm2/Vsec or higher, preferably 40 cm2/Vsec or higher, further preferably 60 cm2/Vsec or higher can be obtained with the off-state current maintained at 1 aA/μm or lower, which can achieve on-state current needed for an LSI. For example, in an FET where L/W is 33 nm/40 nm, an on-state current of 12 μA or higher can flow when the gate voltage is 2.7 V and the drain voltage is 1.0 V. In addition, sufficient electrical characteristics can be ensured in a temperature range needed for operation of a transistor.
This application is based on Japanese Patent Application serial no. 2011-156229 filed with Japan Patent Office on Jul. 15, 2011, the entire contents of which are hereby incorporated by reference.

## Claims

1. A semiconductor device comprising:
a plurality of pixels arranged in a matrix, each of the plurality of pixels being electrically connected to first to seventh wirings and comprising:
a photodiode;
a first capacitor;
a second capacitor;
a first transistor;
a second transistor;
a third transistor; and
a data holding portion,

wherein a cathode of the photodiode is electrically connected to the first wiring,
wherein an anode of the photodiode is electrically connected to a first electrode of the first capacitor,
wherein a first electrode of the second capacitor is electrically connected to the third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein a gate of the first transistor is electrically connected to the sixth wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the seventh wiring,
wherein a gate of the third transistor is electrically connected to the fifth wiring, and
wherein the data holding portion is configured by electrically connecting a second electrode of the first capacitor, a second electrode of the second capacitor, the other of the source and the drain of the first transistor, and a gate of the second transistor.

2. A semiconductor device comprising:
a plurality of pixels arranged in a matrix, each of the plurality of pixels being electrically connected to first to eighth wirings and comprising:
a photodiode;
a first capacitor;
a second capacitor;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor; and
a data holding portion,

wherein a cathode of the photodiode is electrically connected to the first wiring,
wherein an anode of the photodiode is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fourth transistor is electrically connected to the eighth wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a first electrode of the first capacitor,
wherein a first electrode of the second capacitor is electrically connected to the third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein a gate of the first transistor is electrically connected to the sixth wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the seventh wiring,
wherein a gate of the third transistor is electrically connected to the fifth wiring, and
wherein the data holding portion is configured by electrically connecting a second electrode of the first capacitor, a second electrode of the second capacitor, the other of the source and the drain of the first transistor, and a gate of the second transistor.

3. The semiconductor device according to claim 1, wherein a leakage current of the first transistor is smaller than 1×10−14 A.

4. The semiconductor device according to claim 1, wherein the first transistor comprises a channel formed in an oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein the first wiring is a wiring to which a reset signal is supplied.

6. The semiconductor device according to claim 1, wherein the second wiring is a wiring which is set at a constant potential as a reference potential.

7. The semiconductor device according to claim 1, wherein the third wiring is a wiring capable of setting the first electrode of the second capacitor at a constant potential.

8. The semiconductor device according to claim 1, wherein the fourth wiring is a wiring to which a reference potential for a source follower circuit including the second transistor is supplied.

9. The semiconductor device according to claim 1, wherein the fifth wiring is a wiring capable of selecting a pixel where an output signal is detected.

10. The semiconductor device according to claim 1, wherein the sixth wiring is a wiring capable of supplying a signal for controlling the first transistor.

11. The semiconductor device according to claim 1, wherein the seventh wiring is a wiring for transmitting an output signal.

12. The semiconductor device according to claim 2, wherein a leakage current of the first transistor is smaller than 1×10−14 A.

13. The semiconductor device according to claim 2, wherein the first transistor comprises a channel formed in an oxide semiconductor layer.

14. The semiconductor device according to claim 2, wherein the first wiring is a wiring to which a reset signal is supplied.

15. The semiconductor device according to claim 2, wherein the second wiring is a wiring which is set at a constant potential as a reference potential.

16. The semiconductor device according to claim 2, wherein the third wiring is a wiring capable of setting the first electrode of the second capacitor at a constant potential.

17. The semiconductor device according to claim 2, wherein the fourth wiring is a wiring to which a reference potential for a source follower circuit including the second transistor is supplied.

18. The semiconductor device according to claim 2, wherein the fifth wiring is a wiring capable of selecting a pixel where an output signal is detected.

19. The semiconductor device according to claim 2, wherein the sixth wiring is a wiring capable of supplying a signal for controlling the first transistor.

20. The semiconductor device according to claim 2, wherein the seventh wiring is a wiring for transmitting an output signal.

21. The semiconductor device according to claim 2, wherein the eighth wiring is a wiring capable of supplying a signal for controlling light exposure of a pixel.

22. A method for driving a semiconductor device comprising:
at least first to third operations in an operation of reading a data holding portion of a photodiode in a pixel,
wherein a potential of a first current generated by first light reception by the photodiode is read in the first operation,
wherein the potential of the first current from the photodiode is stored in the data holding portion in the second operation, and
wherein a combined potential of a potential of a second current generated by second light reception by the photodiode and an output potential based on the potential of the first current stored through the second operation is read in the third operation.

23. The method for driving the semiconductor device according to claim 22, wherein a transistor with small leakage current is used as a writing switch element for the data holding portion.

24. The method for driving the semiconductor device according to claim 23, wherein the leakage current of the transistor is smaller than 1×10−14 A.

25. The method for driving the semiconductor device according to claim 23, wherein the transistor comprises a channel formed in an oxide semiconductor layer.