# Patent

## Title
System and method for process, voltage, temperature (PVT) stable differential amplifier transfer function

## Abstract

A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a Divisional Application of and claims priority to U.S. patent application Ser. No. 13/014,567, filed on Jan. 26, 2011, titled “SYSTEM AND METHOD FOR PROCESS, VOLTAGE, TEMPERATURE (PVT) STABLE DIFFERENTIAL AMPLIFIER TRANSFER FUNCTION,” by Cohen, which is herein incorporated by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to communication receivers and, more particularly, to a receiver calibration process that minimizes susceptibility to PVT variations.
2. Description of the Related Art
A typical receiver must be capable of capturing a signal with an unknown signal-to-noise ratio (SNR) and an unknown amplitude. As a result, the receiver must be capable of amplification and automatic gain control (AGC)—to set the gain to a specific amplitude. In a digital system, the receiver must also be capable of limiting—amplifying the received signal and converting it to a digital bit stream.
FIG. 1 is a schematic diagram of a conventional differential signal receiver (prior art). The first stage provides gain and improves SNR. The second stage provides frequency response conditioning. The third stage provides gain to enhance the signal amplitude.
Assuming that all transistors have the same small signal gain gm, all load resistors have the same resistance Rd (RD), and the source capacitance Cs is set to “0”, the low frequency gain of the receiver can be calculated to be:




  ADC
  =
  
    
      2
      ⁢
      gmRd
    
    +
    
      gmRd
      
        1
        +
        gmRs
      
    
  




Based on the models provided by the transistor manufacturer for their 40 nanometer (nm) process, the variation of the process parameters (min to max over process and temperature) is: gm 30%, R (Rd and Rs): 56%. Thus, the gm*R product varies by approximately 2× over process and temperature.
In applications where a limiting function is desired, the output of the receiver feeds a slicer, which converts the signal to a rail-to-rail digital bit stream. Therefore, there is a minimum DC gain requirement. Typically, the limiting receiver is designed to have a very high gain, in order to meet the minimum gain requirement over PVT variations.
Looking at the first stage, the output load forms a pole at:




  
    fp
    ⁢
    
      
    
    ⁢
    1
  
  =
  
    1
    
      2
      ⁢
      π
      *
      RD
      *
      CL
      ⁢
      
        
      
      ⁢
      1
    
  




Looking at the second stage, the RsCs degeneration forms a zero and a pole at:




  
    
      fz
      ⁢
      
        
      
      ⁢
      2
    
    =
    
      1
      
        2
        ⁢
        π
        *
        Rs
        *
        Cs
      
    
  
  ,
  
    
      fp
      ⁢
      
        
      
      ⁢
      2
    
    =
    
      
        1
        +
        
          gm
          ⁢
          
            Rs
            2
          
        
      
      
        2
        ⁢
        π
        *
        Rs
        *
        Cs
      
    
  




And another pole at:




  
    fp
    ⁢
    
      
    
    ⁢
    3
  
  =
  
    1
    
      2
      ⁢
      π
      *
      RD
      *
      CL
      ⁢
      
        
      
      ⁢
      2
    
  




Looking at the third stage, the output load is forms a pole at:




  
    fp
    ⁢
    
      
    
    ⁢
    4
  
  =
  
    1
    
      2
      ⁢
      π
      *
      RD
      *
      CL
      ⁢
      
        
      
      ⁢
      3
    
  




CL is a combination of the gate capacitance of the nmos switch (Cgg) and the parasitic metal capacitance of the routing (Cp). Over process and temperature, Cgg can vary by 14% and Cp can vary by 50% (min to max).
Assuming that CL consists of 50% Cgg and 50% Cp, the location of the fp1, fp3, and fp4 poles can vary by up to 30%.
fz2 and fp2 are responsible for the frequency response shaping and are controlled by adjusting Cs. fz2 sets the amount of high frequency gain, while, if properly designed, fp2 is high enough not to interfere with the high frequency peaking. Its variation is not critical as long as it is placed at a very high frequency.
In summary, the variation of the poles and zero(s) of the receive filter make the frequency response unpredictable.
It would be advantageous if a receiver could be calibrated in a manner so as to make the transfer function stable, regardless of variations in process and temperature.
SUMMARY OF THE INVENTION
Accordingly, a method for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The method provides a differential amplifier including a first field effect transistor (FET), a second FET, a first variable resistance gain resistor between the drain (D) of the first FET and a first dc supply voltage, and a second variable resistance gain resistor between the drain of the second FET and the first dc supply voltage. A variable resistance degeneration resistor is located between the source (S) of the first FET and the source of the second FET, a variable capacitance degeneration capacitor is located between the source of the first FET and the source of the second FET, a first current source is connected between the source of the first FET and a second dc supply voltage, and a second current source is connected between the source of the second FET and the second dc supply voltage. After disconnecting the degeneration capacitor, a differential input signal is supplied to the first and second FET gates in a first frequency band having a low frequency (fL) and a high frequency (fH). The first gain resistor, second gain resistor, and the degeneration resistor values are selectively adjusted until a differential output signal is measured with a flat amplitude transfer function in the first frequency band, responsive to the differential input signal and adjusted values.
After calibration, the degeneration capacitor is connected between the first and second FET sources. Then the degeneration capacitor is selectively tuned until a differential output signal with a first peaked amplitude transfer function is measured, having a first gain at FL and a second gain at FH. This first peaked amplitude transfer function can be measured despite variations in PVT.
As an alternative, the degeneration capacitor is connected during calibration. Then, the first gain resistor, second gain resistor, the degeneration resistor, and the degeneration capacitor values are selectively adjusted until a differential output signal is measured, with a first peaked amplitude transfer function having a first gain at FL and a second gain at FH. The first peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.
Additional details of the above-described methods and a clock and data recovery (CDR) device with a PVT stable receiver are described below.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a conventional differential signal receiver (prior art).
FIG. 2 is a flowchart illustrating a method for process, voltage, temperature (PVT) stable transfer function calibration of a differential amplifier.
FIG. 3 is a schematic diagram of a differential amplifier chain provided in support of FIGS. 2 and 5.
FIG. 4 is a graph depicting an exemplary peaked amplitude transfer function, where the gain at FH is greater than the gain at FL.
FIG. 5 is a flowchart illustrating an alternative method for PVT stable transfer function calibration in a differential amplifier.
FIG. 6 is a schematic block diagram depicting a clock and data recovery (CDR) device with a PVT stable receiver.
FIGS. 7A and 7B are a flowchart illustrating the calibration method of FIG. 2 in greater detail.
FIG. 8 is a schematic diagram depicting the addition of a degeneration resistor to a non-peaking gain stage, for the purpose of AGC control.



DETAILED DESCRIPTION
FIG. 2 is a flowchart illustrating a method for process, voltage, temperature (PVT) stable transfer function calibration of a differential amplifier. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. Generally however, the method follows the numeric order of the depicted steps.
FIG. 3 is a schematic diagram of a differential amplifier chain provided in support of FIGS. 2 and 5.
The method of FIG. 2 starts at Step 200. Step 202 provides a differential amplifier 300 including a first field effect transistor (FET) 302, a second FET 304, a first variable resistance gain resistor 306 between the drain (D) of the first FET and a first dc supply voltage, a second variable resistance gain resistor 308 between the drain of the second FET and the first dc supply voltage, a variable resistance degeneration resistor 310 between the source (S) of the first FET and the source of the second FET, and a variable capacitance degeneration capacitor 312 between the source of the first FET and the source of the second FET (see FIG. 3). A first current source 314 is connected between the source of the first FET and a second dc supply voltage, and a second current source 316 is connected between the source of the second FET and the second dc supply voltage.
Step 204 disconnects the degeneration capacitor (sets the capacitance value to zero). Step 206 supplies a differential input signal to the first and second FET gates in a first frequency band having a low frequency (fL) and a high frequency (fH). Step 208 selectively adjusts values for the first gain resistor, second gain resistor, and the degeneration resistor. In one aspect, all the gain resistors are set to the same value. Step 210 measures a differential output signal with a flat amplitude transfer function in the first frequency band, responsive to the differential input signal and adjusted values. Alternately stated, values are adjusted in Step 208 until a flat bandpass response is obtained in Step 210.
Step 212 connects the degeneration capacitor between the first and second FET sources. In response to selectively tuning the degeneration capacitor, Step 214 measures the differential output signal with a first peaked amplitude transfer function having a first gain at FL and a second gain at FH. Step 216 measures the first peaked amplitude transfer function in response to variations in PVT. That is, adjustments are made to the degeneration capacitor in Step 212 until the first peaked amplitude transfer function is obtained in Step 214. Due to the calibration performed in Steps 204 to 210, the transfer function remains relatively stable (constant) despite variations in PVT.
FIG. 4 is a graph depicting an exemplary peaked amplitude transfer function, where the gain at FH is greater than the gain at FL.
In another aspect, Step 202 provides a differential preamplifier 317 including a third FET 318 (see FIG. 3) with a gate to accept an input signal, a fourth FET 320 with a gate to accept a differential input signal, a third variable resistance gain resistor 322 between the drain of the third FET and the first dc supply voltage, a fourth variable resistance gain resistor 324 between the drain of the fourth FET and the first dc supply voltage, and a third current source 326 connected between the source of the third and fourth FETs and the second dc supply voltage. The gate of the first FET 302 is connected to the third FET 318 drain and the gate of the second FET 304 is connected to a drain of the fourth FET 320. Then, selectively adjusting values in Step 208 additionally includes selectively adjusting values for the third and fourth gain resistors. In one aspect, all the gain resistors are set to the same value.
In another aspect, Step 202 provides a differential post-amplifier 328 including a fifth FET 330 with a gate connected to the drain of the first FET 302, a sixth FET 332 with a gate connected to the drain of the second FET 304, a fifth variable resistance gain resistor 334 between the drain of the fifth FET 330 and the first dc supply voltage, a sixth variable resistance gain resistor 336 between the drain of the sixth FET 332 and the first dc supply voltage, and a fourth current source 338 connected between the source of the fifth and sixth FETs and the second dc supply voltage. Then, selectively adjusting values in Step 208 additionally includes selectively adjusting values for the fifth and sixth gain resistors. Alternately stated, all three amplifiers 317, 300, and 328 are connected exactly as shown in the figure. Note: the method is not limited to any particular number of amplifier stages, types of amplifier stages (frequency compensating and non-frequency compensating), or the order of amplifier stages. In one aspect, all the gain resistors are set to the same value.
In one aspect, Step 202 provides FETs all having a first small signal gain. Then, measuring the first peaked amplitude transfer function in response to PVT variations includes measuring an amplitude transfer function across the first frequency band that is constant within 1.3 decibels (dB), in the range from −40 to +130 degrees C.
FIG. 5 is a flowchart illustrating an alternative method for PVT stable transfer function calibration in a differential amplifier. The method begins at Step 500. Step 502 provides the differential amplifier 300 described above in Step 202 and shown in FIG. 3. Step 504 supplies a differential input signal to the first and second FET gates in a first frequency band having a low frequency (fL) and a high frequency (fH). Step 506 selectively adjusts values for the first gain resistor, second gain resistor, the degeneration resistor, and the degeneration capacitor. Step 508 measures a differential output signal, with a first peaked amplitude transfer function having a first gain at FL and a second gain at FH. Alternately stated, values are adjusted in Step 506 until the first peaked amplitude response is obtained in Step 508.
In one aspect, Step 502 provides a differential preamplifier 317 as described above and shown in FIG. 3. Then, selectively adjusting values in Step 506 additionally includes selectively adjusting values for the third and fourth gain resistors. Likewise, if Step 502 provides a differential post-amplifier 328 as described above and shown in FIG. 3, selectively adjusting values in Step 506 additionally includes selectively adjusting values for the fifth and sixth gain resistors. Note: the method is not limited to any particular number of amplifier stages, types of amplifier stages (frequency compensating and non-frequency compensating), or the order of amplifier stages.
In one aspect, Step 510 measures the first peaked amplitude transfer function in response to variations in PVT. More explicitly, when Step 502 provides FETs all having a common, first, small signal gain, Step 510 measures an amplitude transfer function across the first frequency band that is constant within 0.1 decibels (dB) in response to variations in PVT, in the range from −40 to +130 degrees C.
FIG. 6 is a schematic block diagram depicting a clock and data recovery (CDR) device with a PVT stable receiver. The CDR device 600 comprises a receiver 602 including differential amplifier 300. As in FIG. 3, the differential amplifier 300 includes a first field effect transistor (FET) 302, a second FET 304, a first variable resistance gain resistor 306 between the drain (D) of the first FET and a first dc supply voltage, a second variable resistance gain resistor 308 between the drain of the second FET and the first dc supply voltage, a variable resistance degeneration resistor 310 between the source (S) of the first FET and the source of the second FET, and a variable capacitance degeneration capacitor 312 between the source of the first FET and the source of the second FET (see FIG. 3). A first current source 314 is connected between the source of the first FET and a second dc supply voltage, and a second current source 316 is connected between the source of the second FET and the second dc supply voltage.
A phase-locked loop (PLL) 604 includes a phase/frequency detector (PFD) 606 having an input on line 608 to accept a conditioned signal from the receiver 602, an input on line 610 to accept a clock signal, and an output on line 612 to supply a control voltage responsive to the difference between the data and clock signals. A frequency synthesizer 614 has an input on line 612 to accept the control voltage and an output on line 616 to supply a synthesizer signal with a frequency responsive to the control voltage. Conventionally, a loop filter or loop filter/charge pump combination 618 is used to condition the control voltage to the frequency synthesizer. A voltage controlled oscillator (VCO) is an example of a frequency synthesizer.
A feedback divider 620 has an input on line 616 to accept the synthesizer signal and an input on line 622 to accept a divisor. The feedback divider 620 divides the synthesizer signal frequency by the divisor and supplies the clock signal on line 610.
A multiplexer (MUX) 624 has an input on line 616 to accept the synthesizer signal, an input on line 626 to accept a data signal, an input on line 628 to accept a switch signal, and an output on line 630 to supply an input signal to the receiver 602 responsive to the switch signal. A peak amplitude detector 631 has an input to accept the conditioned signal from the receiver on line 608 and an output on line 632 to supply an amplitude measurement.
An initialization module 634 has an input on line 632 to accept the amplitude measurement, and input on line 636 to accept a start-up signal, an output on line 622 to supply the divisor, an output on line 628 to supply the switch signal, and outputs on line 638 to select the first gain resistor, second gain resistor, degeneration resistor, and degeneration capacitor values. In response to the start-up signal, the initialization module 634 supplies a switch signal such that the MUX 624 supplies the synthesized signal as an input to the receiver 602. The initialization module 634 disconnects the degeneration capacitor 312 and supplies divisor values to the feedback divider 620 such that the frequency synthesizer 614 supplies a synthesizer signal in a first frequency band having a low frequency (fL) and a high frequency (fH). The initialization module 634 selectively adjusting values for the first gain resistor 306, second gain resistor 308, and the degeneration resistor 310, using signals on line 638, such that the peak detector 631 measures a flat amplitude transfer function in the first frequency band. In one aspect, all the gain resistors are set to the same value.
The input signals to the receiver 602 on line 630, and the output signals from the receiver on line 608 are shown as a single line. In one aspect, in the interest of simplifying the drawing, the single lines 630 and 608, as well as the PLL signals, are intended to represent differential signals. Alternatively, the single lines represent single-ended signals that are converted to and from differential signals.
Although the receiver 602 is shown as being comprised of amplifiers 317, 300, and 328, it should be noted that in one aspect of the system, as described above, the MUX output on line 630 is directly connected to the gates of the differential amplifier 300 (bypassing preamplifier 317). Likewise, the output of the differential amplifier 300 is connected directly to line 608, bypassing post amplifiers 328.
After calibration, the initialization module 634 connects the degeneration capacitor 312 between the first FET 302 and second FET 304 sources and supplies a degeneration capacitor value such that the peak detector 631 measures a conditioned signal on line 608 with a first peaked transfer function having a first gain at FL and a second gain at FH. The peak detector 631 measures the first peaked transfer function in response to variations in PVT.
In another aspect, the receiver includes the differential preamplifier 317. The MUX output on line 630 is connected to the third FET 318 gate and the fourth FET 320 gate. The third FET 318 drain is connected to a gate of the first FET 302 and the fourth FET 320 drain is connected to a gate of the second FET 304. In this aspect, the output of the differential amplifier 300 is connected to line 608, bypassing post-amplifiers 328. The initialization module 634 selectively adjusts the third 322 and fourth gain resistor 324 values, using signals on line 638, in response to the start-up signal on line 636. In one aspect, all the gain resistors are set to the same value.
In another aspect, the receiver 602 includes the differential post-amplifier 328, so that the gates of FETs 302 and 304 are connected to line 630. The drain of the fifth FET 330 supplies a conditioned signal and the drain of the sixth FET 332 supplies a differential conditioned signal on line 608. The initialization module 634 has an output on line 638 to selectively adjust the fifth and sixth gain resistor values in response to the start-up signal. In one aspect, all the gain resistors are set to the same value.
In another aspect, the receiver includes all three amplifiers 317, 300, and 328 connected as exactly as shown. Note: the method is not limited to any particular number of amplifier stages, types of amplifier stages (frequency compensating and non-frequency compensating), or the order of amplifier stages. If all the FETs have the same small signal gain, the peak detector 631 is able to measure a first peaked amplitude transfer function across the first frequency band that is constant within 1.3 decibels (dB) in response to variations in PVT.
In another variation, an initialization module 634 initially selects the first gain resistor 306, second gain resistor 308, degeneration resistor 310, and degeneration capacitor 312 values in response to the start-up signal (the degeneration capacitor is not disconnected in this variation). The initialization module selectively adjusts values for the first gain resistor, second gain resistor, degeneration capacitor, and the degeneration resistor such that the peak detector 631 measures a first peaked amplitude transfer function having a first gain at FL and a second gain at FH, which remains constant despite variations in PVT.
As in the example above, the receiver may include the combination of the pre-amplifier 317 and the differential amplifier 300, and the initialization module 634 additionally adjusts third gain resistor 322 and fourth gain resistor 324 values in response to the start-up signal. Also, as in the example above, the receiver 602 may include a differential post-amplifier, with the gates of the first FET 302 and second FET 304 connected to line 630. The fifth FET 330 has a gate connected to the first FET drain and the sixth FET 332 has a gate connected to the second FET drain. The drain of the fifth FET 330 supplies a conditioned signal on line 608 and the drain of the sixth FET 332 supplies a differential conditioned signal. The initialization module 634 additionally adjusts the fifth gain resistor 334 and the sixth gain resistor 336 values in response to the start-up signal.
In another aspect, the receiver includes all three amplifiers 317, 300, and 328 connected as exactly as shown. Note: the method is not limited to any particular number of amplifier stages, types of amplifier stages (frequency compensating and non-frequency compensating), or the order of amplifier stages. Considering a receiver where amplifiers 300, 317, and 328 are used, and if all the FETs have the same small signal gain, first peaked amplitude transfer function across the first frequency band is constant within 0.1 decibels (dB), despite variations in PVT.
Functional Description
One approach to deal with the PT variation is to calibrate gain resistors so as to present a fixed resistance value response. Fixed resistance means that the resistors are calibrated to have an arbitrary nominal value (for example, 1K ohms for load resistors and 500 ohms for the degeneration resistor). The resistor calibration compensates for process variation of the resistor value by comparing its nominal resistance value with an external, accurate resistor. That method does not require any wideband measurement and is done at DC. By doing that, the gm*R variation drops to 30% and RC variation drops to 32%. However, in some high performance applications, this might not be sufficient in order to maintain good performance at extreme PT conditions. Another approach is to directly measure the transfer function of the receiver and calibrate it to achieve a specific (e.g., peaked) response.
FIGS. 7A and 7B are a flowchart illustrating the calibration method of FIG. 2 in greater detail. The method starts at Step 700. In Step 702 the switch signal supplies the synthesizer signal to the receiver from the MUX (see FIG. 6). The gain resistors are set to a maximum value and the degeneration capacitor is set to zero. In Step 704 the divisor is selected to supply frequency FH, and in Step 706 the amplitude is measured. In Step 708 the divisor is selected to supply frequency FL, and in Step 710 the amplitude is measured. Amplitude flatness tolerance is measured in Step 712. If the amplitude measurements are out of tolerance, Step 714 determines if the gain resistors are set to a minimum value. If so, an error is asserted in Step 716. If not, the gain resistor values are decremented in Step 718 and the method returns to Step 704.
If the amplitude flatness is in tolerance, Step 720 determines if a peaked amplitude is required. If not, the process ends at Step 722. If peaking is required, Step 724 increments the degeneration capacitor value. In Step 726 the divisor is selected to supply frequency FH, and in Step 728 the amplitude is measured. In Step 730 the divisor is selected to supply frequency FL, and in Step 732 the amplitude is measured. If Step 732 determines that the peaking is sufficient, the process ends. Otherwise, Step 734 determines if the degeneration capacitor value is at the maximum limit. If so, an error is asserted in Step 738. Otherwise, Step 736 decrements the gain resistor values, and process returns to Step 724.
Note: for AGC applications, gain can be controlled by adjusting Rs (resistor 310). Rs is adjusted after the first stage of calibration.
A receiver can consist of any number of gain stages, and any number of frequency response shaping circuits. Also, degeneration resistors (Rs) can be added to the gain stages (pre and post-amplifiers) to provide more gain control for AGC applications. The algorithm can be used to calibrate other types of receivers or filters, and not limited to the example shown in this document. The algorithm can also measure the entire transfer function of a receiver, by injecting a range of frequencies to the input and measure the output response.
For a fast calibration, the calibration algorithm can be reduced to the first stage only, meaning that only the flat response is calibrated. To the first order, the algorithm fixes the RC time constant. In that case, Rs (degeneration resistor) should also be calibrated together with Rd (gain resistors). The AGC control, if needed, is performed on a non-peaking stage as shown in the example below.
FIG. 8 is a schematic diagram depicting the addition of a degeneration resistor to a non-peaking gain stage, for the purpose of AGC control.
A simulation was performed on the circuit of FIG. 3 using all three amplifier stages. The amplitude response was designed to peak at 5 gigahertz (GHz). The gain resistors were set to provide −1 dB attenuation at 5 GHz, with degeneration capacitor 312 (Cs)=0, The simulation results are shown in Table 1, where “cold” is −40 and “hot” is +130 degrees C.












TABLE 1










Max Peaking




Min peaking
Max peaking
variation



Corner
(dB)
(dB)
(dB)




















No calibration
Slow, cold
−1.82
8.9
2.7



Fast, hot
−0.48
6.2


Fixed R
Slow, cold
−1.34
8.4
1.3


calibration
Fast, hot
−0.72
7.1


Time constant
Slow, cold
−1
7.75
0.13


calibration
Fast, hot
−1
7.88









A CDR device with a stable receiver and a corresponding receiver calibration process have been provided. Examples of structures and process flows have been presented to illustrate the invention. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.

## Claims

1. A clock and data recovery (CDR) device comprising:
a receiver comprising a differential amplifier, wherein the differential amplifier comprises a plurality of variable gain resistors, a variable degeneration resistor, and a variable degeneration capacitor, and wherein the receiver is operable to generate an output signal; and
an initialization module operable to disconnect the variable regeneration capacitor in response to receiving a start-up signal, and wherein the initialization module is further operable to selectively adjust values for the plurality of variable gain resistors and the variable degeneration resistor until the output signal of the differential amplifier comprises a first frequency band with a flat transfer function.

2. The CDR device of claim 1, wherein the differential amplifier further comprises a first field effect transistor (FET) and a second FET, wherein a first variable gain resistor is coupled to the first FET and a second variable gain resistor is coupled to the second FET, and wherein the variable degeneration resistor is coupled between the first FET and the second FET.

3. The CDR device of claim 2 further comprising a phase-locked loop (PLL) coupled to the receiver, wherein the PLL is operable to generate a synthesized signal to be received by the receiver, and wherein the PLL comprises:
a phase/frequency detector operable to generate a control voltage responsive to a difference between the output signal from the receiver and a received clock signal;
a frequency synthesizer operable to generate the synthesized signal with a frequency responsive to the control voltage received from the phase/frequency detector; and
a feedback divider operable to generate the clock signal by dividing the synthesized signal received from the frequency synthesizer by a divisor value; and
wherein the initialization module is further operable to supply divisor values to the feedback divider responsive to the start-up signal, such that the first frequency band of the synthesized signal comprises a low frequency (FL) and a high frequency (FH).

4. The CDR device of claim 3 further comprising a multiplexer (MUX) operable to supply one of the synthesized signal and a data signal to the receiver responsive to a switch signal, wherein the initialization module is further operable to generate the switch signal responsive to the start-up signal.

5. The CDR device of claim 4 further comprising:
a peak detector operable to measure an amplitude of the synthesized signal;
wherein the initialization module is further operable to reconnect the degeneration capacitor, and further yet operable to supply a degeneration capacitor value until the synthesized signal, as determined by the peak detector, comprises a peaked transfer function having a first gain at FL and a second gain at FH, and wherein the peak detector measures the peaked transfer function in response to variations in process, voltage, and temperature (PVT).

6. The CDR device of claim 5, wherein the receiver further comprises:
a differential preamplifier comprising a third FET operable to accept an input from the MUX, a fourth FET operable to accept a differential input signal from the MUX, a third variable gain resistor coupled to the third FET, and a fourth variable gain resistor coupled to the fourth FET, wherein the third FET is connected to the first FET and the fourth FET is connected to the second FET, and wherein the initialization module is further operable to adjust the third and fourth variable gain resistor values in response to the start-up signal.

7. The CDR device of claim 6, wherein the receiver further comprises:
a differential post-amplifier comprising a fifth FET connected to the first FET, a sixth FET connected to the second FET, a fifth variable gain resistor coupled to the fifth FET, and a sixth variable gain resistor coupled to the sixth FET, wherein the fifth FET is operable to supply a conditioned signal and the sixth FET is operable to supply a differential conditioned signal, and wherein the initialization module is further yet operable to selectively adjust the fifth and sixth variable gain resistor values in response to the start-up signal.

8. The CDR device of claim 7, wherein all the FETs have a small signal gain, and wherein the peak detector measures a peaked amplitude transfer function across the first frequency band that is constant within 1.3 decibels (dB) in response to variations in PVT.

9. A clock and data recovery (CDR) device, the CDR device comprising:
a receiver comprising a differential amplifier, wherein the differential amplifier comprises a plurality of variable gain resistors, a variable degeneration resistor, and a variable degeneration capacitor, and wherein the receiver is operable to generate an output signal; and
an initialization module operable to, in response to receiving a start-up signal, selectively adjust values for the plurality of variable gain resistors, the variable degeneration resistor, and the variable degeneration capacitor until the output signal of the differential amplifier comprises a first frequency band with a peaked amplitude transfer function having a first gain at a low frequency (FL) and a second gain at a high frequency (FH).

10. The CDR device of claim 9, wherein the differential amplifier further comprises a first field effect transistor (FET) and a second FET, wherein a first variable gain resistor is coupled to the first FET and a second variable gain resistor is coupled to the second FET, and wherein the variable degeneration resistor is coupled between the first FET and the second FET.

11. The CDR device of claim 10 further comprising a phase-locked loop (PLL) coupled to the receiver, wherein the PLL is operable to generate a synthesized signal to be received by the receiver, and wherein the PLL comprises:
a phase/frequency detector operable to generate a control voltage responsive to a difference between the output signal from the receiver and a received clock signal;
a frequency synthesizer operable to generate the synthesized signal with a frequency responsive to the control voltage received from the phase/frequency detector; and
a feedback divider operable to generate the clock signal by dividing the synthesized signal received from the frequency synthesizer by a divisor value; and
wherein the initialization module is further operable to supply divisor values to the feedback divider responsive to the start-up signal, such that the first frequency band of the synthesized signal comprises the low frequency (FL) and the high frequency (FH).

12. The CDR device of claim 11 further comprising a multiplexer (MUX) operable to supply one of the synthesized signal and a data signal to the receiver responsive to a switch signal, wherein the initialization module is further operable to generate the switch signal responsive to the start-up signal.

13. The CDR device of claim 12 further comprising a peak detector operable to measure the peaked amplitude transfer function in response to variations in process, voltage, and temperature (PVT).

14. The CDR device of claim 13, wherein the receiver further comprises:
a differential preamplifier comprising a third FET operable to accept an input from the MUX, a fourth FET operable to accept a differential input signal from the MUX, a third variable gain resistor coupled to the third FET, and a fourth variable gain resistor coupled to the fourth FET, wherein the third FET is connected to the first FET and the fourth FET is connected to the second FET, and wherein the initialization module is further operable to adjust the third and fourth variable gain resistor values in response to the start-up signal.

15. The CDR device of claim 14, wherein the receiver further comprises:
a differential post-amplifier comprising a fifth FET connected to the first FET, a sixth FET connected to the second FET, a fifth variable gain resistor coupled to the fifth FET, and a sixth variable gain resistor coupled to the sixth FET, wherein the fifth FET is operable to supply a conditioned signal and the sixth FET is operable to supply a differential conditioned signal, and wherein the initialization module is further yet operable to selectively adjust the fifth and sixth variable gain resistor values in response to the start-up signal.

16. The CDR device of claim 15, wherein all the FETs have a small signal gain, and wherein the peak detector measures a peaked amplitude transfer function across the first frequency band that is constant within 0.1 decibels (dB) in response to variations in PVT.