# Patent

## Title
Controller compensation for frequency jitter

## Abstract

A controller for use in a power supply includes a drive signal generator, a jitter signal generator, a compensator signal generator, and an arithmetic operator. The drive signal generator is coupled to output a drive signal in response to an input signal. The jitter signal generator is coupled to provide a jitter signal that is representative of a first percentage amount to modulate a switching period of the drive signal. The compensator signal generator is coupled to provide a compensator signal responsive to the jitter signal, where the compensator signal is representative of a second percentage amount to change a duty ratio of the drive signal. The arithmetic operator adjusts the input signal of the controller in response to the compensator signal to provide a compensated input signal, where the duty ratio of the drive signal is adjusted by the second percentage amount in response to the compensated input signal.

## Background
REFERENCE TO PRIOR APPLICATION
This application is a continuation of U.S. patent application Ser. No. 12/615,962, filed Nov. 10, 2009, now pending. U.S. patent application Ser. No. 12/615,962 is hereby incorporated by reference.


TECHNICAL FIELD
The present invention relates generally to power supplies, and more specifically, the present invention relates to controllers for switched mode power supplies.
BACKGROUND INFORMATION
Electronic devices use power to operate. Switched mode power supplies are commonly used due to their high efficiency, small size and low weight to power many of today's electronics. Conventional wall sockets provide a high voltage alternating current. In a switching power supply a high voltage alternating current (ac) input is converted to provide a well regulated direct current (dc) output through an energy transfer element. The switched mode power supply control circuit usually provides output regulation by sensing the output and controlling it in a closed loop. In operation, a switch is utilized to provide the desired output by regulating the duty cycle (typically the ratio of the on time of the switch to the total switching period) of the switch in a switched mode power supply.
Due to regulatory requirements, the electromagnetic interference (EMI) emissions of a power supply can not exceed a suitable level. The EMI emissions of the power supply are partly due to the switching noise and the switching frequency of the power supply. Various techniques may be utilized to reduce the EMI emissions of the power supply, particularly the magnitude of the EMI emissions of the power supply. In one example, the EMI can be reduced with snubbers and input filters. In another example, frequency jittering is utilized to spread the energy in the harmonics of the switching frequency to reduce the magnitude of some types of EMI emissions. However, in power supplies operating in discontinuous conduction mode (DCM), the frequency jittering creates an undesirable ripple at the output of the power supply.



BRIEF DESCRIPTION OF THE DRAWINGS
Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
FIG. 1 is a functional block diagram illustrating an example switching power supply utilizing a controller in accordance with an embodiment of the present invention.
FIG. 2A is a diagram illustrating an example switching current waveform of a switching power supply operating in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) in accordance with an embodiment of the present invention.
FIG. 2B is a diagram illustrating an example switching current waveform of a switching power supply utilizing pulse width modulation (PWM) duty ratio programmed control and operating in DCM in accordance with an embodiment of the present invention.
FIG. 2C is a diagram illustrating an example switching current waveform of a switching power supply utilizing pulse width modulation (PWM) current programmed control and operating in DCM in accordance with an embodiment of the present invention.
FIG. 3 is a functional block diagram illustrating a jitter compensated controller, in accordance with an embodiment of the present invention.
FIG. 4 is a functional block diagram of a jitter compensated controller utilizing PWM duty ratio programmed control, in accordance with an embodiment of the present invention.
FIG. 5 is a functional block diagram of a jitter compensated controller utilizing PWM current programmed control, in accordance with an embodiment of the present invention.
FIG. 6 is an example schematic of a jitter compensator and arithmetic operator, in accordance with one embodiment of the present invention.



DETAILED DESCRIPTION
Embodiments of controller compensation for frequency jitter are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.
Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
For combating EMI emissions, the Federal Communications Commission (FCC) has established specifications which specify the maximum amount of EMI which can be produced by classes of electronic devices. Power supplies generate a major component of EMI emissions and minimizing the amount of EMI produced by a power supply is an important step in designing the power supply. Methods such as frequency jittering spread the energy in the harmonics of the switching frequency of the power supply over a wider frequency range to reduce the magnitude of some types of EMI emissions. However, for PWM power supplies operating in discontinuous conduction mode (DCM), frequency jittering produces variations in the output voltage of the power supply since the output voltage partially depends on the switching frequency of the power supply.
For power supplies operating in DCM, the unwanted variations in the output voltage may be corrected by the regulation provided by the feedback circuit. However, when the feedback circuit is the sole mechanism to reduce the undesirable effects of the jitter, the amount of frequency jitter which could be implemented is limited. Thus, embodiments of the present invention compensate for the frequency jittering within the controller such that the unwanted variations in the output voltage are reduced.
Referring first to FIG. 1, a functional block diagram of an example switching power supply 100 is illustrated including input VIN 102, an energy transfer element T1 104, a primary winding 106 of the energy transfer element T1 104, a secondary winding 108 of the energy transfer element T1 104, a switch S1 110, an input return 111, a clamp circuit 112, a rectifier D1 114, an output capacitor C1 116, a load 118, an output quantity UO, an output voltage VO, an output current IO, a feedback circuit 120, a feedback signal UFB 122, a constant open loop signal UCOL 124, a switch S2 126, a controller input UC 128, a jitter compensated controller 130, a drive signal 132, a current sense input 134, and switch current ID 136. The example switching power supply 100 illustrated in FIG. 1 is configured generally as a flyback regulator, which is one example of a switching power supply topology which may benefit from the teachings of the present invention. However, it is appreciated that other known topologies and configurations of switching power supply regulators may also benefit from the teachings of the present invention.
The switching power supply 100 provides output power to the load 118 from an unregulated input VIN 102. Typically the input VIN 102 is a rectified and filtered ac line voltage. The input VIN 102 is coupled to the energy transfer element T1 104. In some embodiments of the present invention the energy transfer element T1 104 may be a coupled inductor. In other embodiments of the present invention the energy transfer element T1 104 may be a transformer. In the example of FIG. 1, the energy transfer element T1 104 includes two windings, a primary winding 106 and a secondary winding 108 with NP number of turns for the primary winding 106 and NS number of turns for the secondary winding 108. However, it should be appreciated that the energy transfer element T1 may have more than two windings. The primary winding 106 is further coupled to the switch S1 110, which is then further coupled to the input return 111. In addition, the clamp circuit 112 is coupled across the primary winding 106 of the energy transfer element T1 104. The secondary winding 108 of the energy transfer element T1 104 is coupled to the rectifier D1 114. In the example of FIG. 1, the rectifier D1 114 is exemplified as a diode. However, in some embodiments the rectifier D1 114 may be a transistor used as a synchronous rectifier. Both the output capacitor C1 116 and the load 118 are coupled to the rectifier D1 114. An output is provided to the load 118 and may be provided as either an output voltage VO, output current IO, or a combination of the two.
In addition, the switched mode power supply 100 further comprises circuitry to regulate the output which is exemplified as output quantity UO. In general, the output quantity UO is either an output voltage VO, output current IO, or a combination of the two. A feedback circuit 120 is coupled to sense the output quantity UO from the output of the power supply 100 and produces the feedback signal UFB 122. The feedback circuit 120 is coupled to switch S2 126. When the switch S2 126 is in position one, the feedback circuit 120 is coupled to one terminal of the jitter compensated controller 130, and the controller input UC 128 is the feedback signal UFB 122. When the switch S2 126 is in position 2, one terminal of the jitter compensated controller 130 is coupled to the constant open loop signal UCOL 124, and the controller input UC 128 is the constant open loop signal UCOL 124. The jitter compensated controller 130 further includes a terminal for the current sense input 134. The current sense input 134 senses the switch current ID 136 in switch S1 110. In addition, the switch S1 110 receives the drive signal 132 from the jitter compensated controller 130.
In operation, the switched mode power supply 100 of FIG. 1 provides output power to the load 118 from an unregulated input VIN 102. The switched mode power supply 100 utilizes the energy transfer element T1 104 to transfer the voltage from the input VIN 102 between the primary 106 and the secondary 108 windings. The clamp circuit 112 is coupled to the primary winding 106 to limit the maximum voltage on the switch S1 110. Switch S1 110 is opened and closed in response to the drive signal 132 received from the jitter compensated controller 130. It is generally understood that a switch that is closed may conduct current and is considered on, while a switch that is open cannot conduct current and is considered off. In some embodiments, the switch S1 110 may be a transistor and the jitter compensated controller 130 may include integrated circuits and/or discrete electrical components. In one example, controller 130 and switch 110 could form part of an integrated circuit 150 that could be manufactured as a hybrid or monolithic integrated circuit. In operation, the switching of switch S1 110 produces a pulsating current at the rectifier D1 114. The current in the rectifier D1 114 is filtered by output capacitor C1 116 to produce a substantially constant output voltage VO, output current IO, or a combination of the two at the load 118. However, systems that utilize frequency jitter to modulate the switching frequency to reduce EMI emissions without jitter compensation according to embodiments of the present invention may produce an undesired variation at the output.
The power supply 100 illustrated in FIG. 1 may operate in either open loop or closed loop operation. However, it should be appreciated that the open loop operation is shown for illustration purposes. In practice, the power supply 100 will operate in closed loop operation. In closed loop operation, the switch S2 126 is in position one and the output quantity UO is sensed and regulated. In general, the output quantity UO is either an output voltage VO, output current IO, or a combination of the two. The feedback circuit 120 senses the output quantity UO from the output of the power supply 100 to provide the feedback signal UFB 122 to the jitter compensated controller 130. When the switch S2 126 is in position one, the controller input UC 128 is the feedback signal UFB 122. In open loop operation, the switch S2 126 is in position two and the controller input UC 128 is the constant open loop signal UCOL 124. The constant open loop signal UCOL 124 may in one example be a constant voltage or in another example may be a constant current. In general, the controller input UC 128 is either a voltage signal or a current signal. In the example of FIG. 1, the jitter compensated controller 130 also receives another input from the current sense input 134 which relays the sensed switch current ID 136 in the switch S1 110. The switch current ID 136 may be sensed in a variety of ways, such as for example the voltage across a discrete resistor or the voltage across a transistor when the transistor is conducting.
When the switch S2 is in position 1, the jitter compensated controller 130 outputs a drive signal 132 to operate the switch S1 110 in response to various system inputs to substantially regulate the output quantity UO to the desired value. In one embodiment, the drive signal 132 may be a rectangular pulse waveform with varying lengths of logic high and logic low sections, with a logic high value corresponding to a closed switch and a logic low corresponding to an open switch. As mentioned above, systems that utilize frequency jitter to modulate the switching frequency to reduce EMI emissions without jitter compensation according to embodiments of the present invention may produce an undesired variation at the output especially when the power supply is operating in discontinuous conduction mode (DCM). The jitter compensated controller 130 compensates for the frequency modulation to negate the variations in the output of the power supply 100.
The switching current of various modes of operation is illustrated in FIG. 2A. A diagram of an example switching current waveform of the switched mode power supply of FIG. 1 is illustrated including switching period TS 204, a switch on-time tON 206, a switch off-time tOFF 208, trapezoidal shape 210 and triangular shape 212. FIG. 2A illustrates the general waveforms of the switch current ID 202 with respect to time when the controller is operating in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In one example, the general waveforms of switch current ID 202 represent the switch current ID 136 illustrated in FIG. 1.
During any switching period TS 204, switch S1 110 may conduct in response to the drive signal 132 from the controller 130 to regulate the output quantity UO. The switching period TS 204 may be separated into two sections of time: switch on-time tON 206 and switch off-time tOFF 208. Switch on-time tON 206 denotes the portion of the switching period TS 204 where the switch S1 110 may conduct. Switch off-time tOFF 208 denotes the remaining portion of the switching period TS 204 when the switch S1 110 cannot conduct. The current waveform of FIG. 2A illustrates two fundamental modes of operation. The trapezoidal shape 210 is characteristic of continuous conduction mode (CCM) whereas the triangular shape 212 is characteristic of discontinuous conduction mode (DCM). During CCM, the switch current ID 202 is substantially non-zero immediately after the start of the switch on-time tON 206. At DCM, the switch current ID 202 is substantially zero immediately after the beginning of the switch on-time tON 206. During the switch off-time tOFF 208, the switch current ID 202 is substantially zero for both CCM and DCM.
During DCM, the output power is related to various power supply characteristics, such as the switching period TS 204 or the switching frequency fS of the switched mode power supply. It should be appreciated that the switching period TS 204 is the reciprocal of the switching frequency fS and vice versa, or mathematically: TS=1/fS. When frequency jittering of the switching frequency fS is utilized to reduce EMI emissions, the resultant frequency modulation also carries over to the output power. In other words, modulation of the switching frequency fS also results in a ripple at the output of the switched mode power supply. For a flyback converter (as shown in FIG. 1) operating in DCM, the output power POUT can be given by:




  
    
      
        
          
            P
            OUT
          
          =
          
            
              1
              2
            
            ⁢
            
              LI
              PEAK
              2
            
            ⁢
            
              f
              S
            
          
        
        ,
      
    
    
      
        (
        1
        )
      
    
  




where IPEAK is the peak value of the current through the primary winding 106, fS is the switching frequency and L is the inductance of the primary winding 106 of energy transfer element T1 104. For the flyback converter of FIG. 1, IPEAK is also the peak value of the switch current ID 136. As mentioned above, the switching period TS 204 is the reciprocal of the switching frequency fS and equation (1) may be rewritten in terms of the switching period, TS:





  
    
      
        
          P
          OUT
        
        =
        
          
            1
            2
          
          ⁢
          
            
              LI
              PEAK
              2
            
            
              T
              S
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




When frequency jittering is utilized and the switching period TS is modulated by a small amount, δ(t) (herein also referred to as the jitter fraction) then the output power POUT is given by:




  
    
      
        
          P
          OUT
        
        =
        
          
            1
            2
          
          ⁢
          
            
              LI
              PEAK
              2
            
            
              (
              
                
                  T
                  S
                
                +
                
                  
                    T
                    S
                  
                  ⁢
                  
                    δ
                    ⁡
                    
                      (
                      t
                      )
                    
                  
                
              
              )
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




The jitter fraction δ(t) represents the percentage amount to modulate the switching period TS. In general, the jitter fraction is referenced as δ(t) to denote that the jitter fraction δ(t) is a function of time where t is time. The switching period TS is modulated by the jitter fraction δ(t) and the modulated switching period TS, TS+TSδ(t), also changes with time t. In some embodiments the magnitude of the jitter fraction δ(t) may be a value between zero and one, representing the percentage amount to modulate the switching period TS 202, or mathematically: 0<|δ(t)|≦1. In some embodiments of the present invention, the jitter fraction δ(t) is utilized to reduce EMI emissions of a switched mode power supply. The output voltage VO for a resistive load of the switched mode power supply may be given by:




  
    
      
        
          
            V
            O
          
          =
          
            
              
                N
                S
              
              
                N
                P
              
            
            ⁢
            
              
                
                  RLI
                  PEAK
                  2
                
                
                  2
                  ⁢
                  
                    
                  
                  ⁢
                  
                    
                      T
                      S
                    
                    ⁡
                    
                      (
                      
                        1
                        +
                        
                          δ
                          ⁡
                          
                            (
                            t
                            )
                          
                        
                      
                      )
                    
                  
                
              
            
          
        
        ,
      
    
    
      
        (
        4
        )
      
    
  




where R represents the resistance of the load 118. Equation (4) may be rewritten:





  
    
      
        
          V
          O
        
        =
        
          
            I
            PEAK
          
          ⁢
          
            
              N
              S
            
            
              N
              P
            
          
          ⁢
          
            
              RL
              
                2
                ⁢
                
                  
                
                ⁢
                
                  
                    T
                    S
                  
                  ⁡
                  
                    (
                    
                      1
                      +
                      
                        δ
                        ⁡
                        
                          (
                          t
                          )
                        
                      
                    
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




However, for a typical converter in DCM, the peak current IPEAK may also be given by:





  
    
      
        
          
            I
            PEAK
          
          =
          
            
              
                V
                IN
              
              ⁢
              
                DT
                S
              
            
            L
          
        
        ,
      
    
    
      
        (
        6
        )
      
    
  




where VIN 102 is the input voltage and D is the duty ratio. In addition, DTS is also the switch on-time tON 206 since the duty ratio D is the ratio of switch on-time tON 206 to the total switching period TS 204. However, when frequency jittering is utilized to modulate the switching period TS 204 by the jitter fraction δ(t) with the controller 130 utilizing duty ratio programmed control, the peak current IPEAK will also vary as demonstrated:





  
    
      
        
          I
          PEAK
        
        =
        
          
            
              V
              IN
            
            ⁢
            
              
                DT
                S
              
              ⁡
              
                (
                
                  1
                  +
                  
                    δ
                    ⁡
                    
                      (
                      t
                      )
                    
                  
                
                )
              
            
          
          L
        
      
    
    
      
        (
        7
        )
      
    
  




As illustrated by equations (3) and (5), during DCM the output power (and the output voltage VO) is responsive to the switching frequency fS (or switching period TS) and any subsequent modulations to the switching frequency fS and switching period TS. The peak current IPEAK is also responsive to the switching period (or switching period TS) and any subsequent modulations to the switching frequency fS and switching period TS. As will be illustrated further and in accordance with embodiments of the present invention, the switched mode power supply 100 may compensate for variations in the output power POUT and output voltage VO caused by the jitter fraction δ(t).
Compensation for the jitter may be provided by the jitter compensated controller 130 (as will be further discussed below). In addition to various modes of operation, such as CCM and DCM, the switched mode power supply 100 may also utilize various modes of control. In one example, the jitter compensated controller 130 may utilize pulse width modulation (PWM) duty ratio programmed control. In another example, the jitter compensated controller 130 may utilize pulse width modulation (PWM) current programmed control.
Referring next to FIG. 2B, another diagram of an example of a switching current waveform is illustrated including switch current ID 214, switching period TS 216, switch on-time tON 218, and switch off-time tOFF 220. In one example, the current waveform of FIG. 2B demonstrates the general switch current ID 136 of FIG. 1 with respect to time when pulse width modulation (PWM) control of the switch S1 110 is utilized by the jitter compensated controller 130 operating in DCM to regulate the output quantity UO. In particular, FIG. 2B demonstrates the general switch current ID 136 with respect to time when PWM duty ratio programmed control is utilized.
PWM control of the switch S1 110 may be utilized with both CCM and DCM modes of operation of the power supply. As illustrated in FIG. 2B, the switch S1 110 conducts at the beginning of each switching period TS 216. In one example of PWM control, regulation may be accomplished by modulation of the duty cycle, also known as the duty ratio, of the switch S1 110. In general, the duty ratio is the ratio of the switch on-time tON 218 to the switching period TS 216. In one example, modulation of the duty ratio may be accomplished by changing the switch on-time tON 218 while the switching period TS 216 remains fixed. This mode of control is known as fixed frequency voltage mode control, fixed frequency voltage mode PWM or fixed frequency PWM duty ratio programmed control.
However, the term “fixed frequency control” does not necessarily entail that the switching frequency fS of the switch S1 110 remains unchanged. Thus, the use of the term “fixed frequency” control as used herein indicates that the switching frequency fS of the switch is not used as a control variable to regulate the output quantity UO. For the example of fixed frequency duty ratio programmed control, the switch on-time or the duty ratio is utilized as the control variable to regulate the output quantity UO. For the various embodiments of the present invention, frequency modulation for EMI emissions with jitter compensation may still be utilized alongside fixed frequency control modes since the switching frequency fS is not utilized as a control variable to regulate the output quantity UO.
It should also be appreciated that compensation and control are different concepts. Control of a variable to provide a quantity at a desired value is performed as a closed loop function requiring feedback regarding the quantity. For control, the quantity is sensed and compared to the desired value for that quantity. When there is an error between the sensed quantity and the desired value, the variable is controlled to reduce the error between the sensed quantity and the desired value for that quantity. On the other hand, compensation of a variable to produce a desired value for a quantity is performed as an open loop function that does not require feedback regarding the quantity. For compensation, known relationships between the variable and the quantity are utilized to provide the desired value for the quantity. The variable is adjusted to balance the effects of the known relationships and to provide the quantity at the desired value. However control and compensation may be utilized together. For example, a power supply may include a controller to regulate an output voltage of the power supply. The controller may receive feedback information representative of the output voltage and then controls the duty ratio of a switch to provide the desired output voltage based on the feedback. According to embodiments of the present invention, the controller may include jitter compensation that adjusts the duty ratio independent of the feedback signal based on a known relationship between the amount that the switching frequency is modulated and its known effect on the output voltage. In this example, the duty ratio of the switch is controlled in response to a feedback signal and is compensated for the modulated switching frequency independent of the feedback signal.
Referring next to FIG. 2C, another diagram of an example of a switching current waveform is illustrated including switch current ID 222, switching period TS 224, switch on-time tON 226, switch off-time tOFF 228, and a maximum current threshold IMAX 230. In one example, FIG. 2C demonstrates the general switch current ID 136 of FIG. 1 with respect to time when PWM control of the switch S1 110 is utilized by the jitter compensated controller 130 to regulate the output quantity UO. In particular, FIG. 2B demonstrates the general switch current ID 136 with respect to time when PWM current programmed control is utilized.
The switch S1 110 conducts at the beginning of each switching period TS 224. Switch S1 110 conducts until the switch current ID 222 reaches the maximum current threshold IMAX 230. In one example, control of the maximum current threshold IMAX 230 at a constant switching period TS 202 (otherwise known as fixed switching frequency fS) maintains the peak of the switch current ID 222 at a value required to regulate the output quantity UO. In general, a higher maximum current threshold IMAX 230 results in a longer switch on-time tON 226. In some embodiments of the present invention, the maximum current threshold IMAX 230 is also the peak primary current IPEAK. The regulation is accomplished by a fixed frequency PWM technique known as fixed frequency PWM current mode control, fixed frequency PWM current programmed control, and/or peak current mode control.
As mentioned above, the term “fixed frequency control” does not necessarily entail that the switching frequency fS of the switch S1 110 remains unchanged and the use of the term “fixed frequency” control indicates that the switching frequency fS of the switch is not used as a control variable to regulate the output quantity UO. For the example of fixed frequency current mode control, the value of the maximum current threshold IMAX 230 is utilized as the control variable to regulate the output quantity UO. For the various embodiments of the present invention, frequency modulation for EMI emissions with jitter compensation may still be utilized alongside fixed frequency control modes since the switching frequency fS is not utilized as a control variable to regulate the output quantity UO.
Utilizing the various modes of control, including the modes of control mentioned above, the jitter compensated controller 130 may compensate for the jitter fraction δ(t). For PWM duty ratio programmed control, as discussed with respect to FIG. 2B, the jitter compensated controller 130 may compensate the duty ratio of the power supply 100 to offset the effects of frequency jitter (or in other words frequency modulation) on the output power POUT and output voltage VO of the power supply 100. By combining equation (5) and equation (7) from above, the output voltage VO may be given as:




  
    
      
        
          V
          O
        
        =
        
          
            V
            IN
          
          ⁢
          D
          ⁢
          
            
              N
              S
            
            
              N
              P
            
          
          ⁢
          
            
              
                
                  RT
                  S
                
                ⁡
                
                  (
                  
                    1
                    +
                    
                      δ
                      ⁡
                      
                        (
                        t
                        )
                      
                    
                  
                  )
                
              
              
                2
                ⁢
                
                  
                
                ⁢
                L
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




In accordance with an embodiment of the present invention, the jitter compensated controller 130 may offset the effects of frequency jitter by substituting the duty ratio D with a compensated duty ratio DCOMP:




  
    
      
        
          D
          COMP
        
        =
        
          D
          ⁢
          
            
              1
              
                1
                +
                
                  δ
                  ⁡
                  
                    (
                    t
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




However, square-root functions are difficult to implement. The exact compensated duty ratio DCOMP of equation (9) may then be expressed as the first order approximation of a power series expansion:





  
    
      
        
          D
          COMP
        
        ≈
        
          D
          (
          
            1
            -
            
              
                1
                2
              
              ⁢
              
                δ
                ⁡
                
                  (
                  t
                  )
                
              
            
          
          )
        
      
    
    
      
        (
        10
        )
      
    
  




By utilizing the approximate compensated duty ratio as illustrated by equation (10), the jitter compensated controller 130 may offset the effects of the jitter fraction δ(t). It should be appreciated that the amount multiplied against the duty ratio D may be referred to herein as the compensation factor. For equation (10), the compensation factor is:




  
    
      
        1
        -
        
          
            1
            2
          
          ⁢
          
            δ
            ⁡
            
              (
              t
              )
            
          
        
      
    
    
      
        (
        11
        )
      
    
  




The compensation factor may generally be written as: where k is the compensation coefficient. For equation (10) and (11), the compensation coefficient





  k
  =
  
    -
    
      
        1
        2
      
      .
    
  




Equations (10) and (11) illustrate the value of the approximate compensated duty ratio DCOMP and the compensation factor when first order approximation of a power series is utilized. However, it should be appreciated that other approximations may be used. The magnitude of the compensation coefficient may be a value:





  0
  <
  
    
    k
    
  
  ≤
  
    
      1
      2
    
    .
  




In another embodiment of the present invention, when PWM duty ratio programmed control is utilized the value of k=−0.45. As illustrated by the general form of the compensation factor in equation (12), the value of the compensation coefficient and the jitter fraction, kδ(t), is the percentage amount which the duty ratio D must change to arrive at an approximated compensated duty ratio DCOMP.

For example, if the value of kδ(t) is −0.09, that corresponds to a 9% change to the duty ratio D to arrive at a compensated duty ratio DCOMP. Or in other words, the approximate compensated duty ratio DCOMP is 91% of the duty ratio D when kδ(t) is −0.09. If the value of kδ(t) is +0.09, that also corresponds to a 9% change to the duty ratio D to arrive at the approximate compensated duty ratio DCOMP. However, the approximate compensated duty ratio DCOMP is 109% of the duty ratio D when kδ(t) is +0.09.
For another example, the magnitude of the jitter fraction δ(t), |δ(t)|, is 20% or 0.20 As such, the compensation factor utilizing the first order power series approximation from equation (11) is 0.9, corresponding to




  k
  =
  
    -
    
      
        1
        2
      
      .
    
  




Or in other words, the approximate compensated duty ratio DCOMP from equation (10) is 90% of the duty ratio D. However when the magnitude of the jitter fraction |δ(t)| is 20% (or 0.20), the compensation factor from equation (9) equals 0.91 and as a result the exact compensated duty ratio DCOMP from equation (9) is 91% of the duty ratio D. Even for a reasonably large magnitude of the jitter fraction |δ(t)| of 20%, the error between the exact compensated duty ratio DCOMP from equation (9) and the approximate compensated duty ratio DCOMP from equation (10) is relatively small. However utilizing the knowledge that a 20% jitter fraction δ(t) produces an exact compensation factor of 0.91 from equation (9), the general compensation factor equation of equation (12) may be further tailored to approximate the compensated duty ratio DCOMP with less error than the first order power series approximation shown in equation (11). For a 20% jitter fraction δ(t), the compensation coefficient k may be chosen to equal k=−0.45 such that the compensation factor would substantially equal 0.91. In one embodiment, the compensation coefficient may be a value:





  0
  <
  
    
    k
    
  
  ≤
  
    
      1
      2
    
    .
  




For PWM current programmed control, as discussed with respect to FIG. 2C, the jitter compensated controller may compensate the peak current IPEAK of the power supply 100 to offset the effects of frequency jitter (or in other words frequency modulation) on the output power POUT and output voltage VO of the power supply 100. In one embodiment of the present invention, IPEAK is also the maximum current threshold IMAX 230. Equation (5) above illustrates that the output voltage VO is also a function of the peak current IPEAK. In accordance with an embodiment of the present invention, the jitter compensated controller 130 may offset the effects of frequency jittering by substituting the peak current IPEAK with a compensated peak current ICOMP given by:

ICOMP=IPEAK√{square root over (1+δ(t))}  (13)

However as mentioned above, square-root functions are difficult to implement. The compensated peak current ICOMP may then be expressed as the first order approximation of a power series expansion:





  
    
      
        
          I
          COMP
        
        ≈
        
          
            I
            PEAK
          
          (
          
            1
            +
            
              
                1
                2
              
              ⁢
              
                δ
                ⁡
                
                  (
                  t
                  )
                
              
            
          
          )
        
      
    
    
      
        (
        14
        )
      
    
  




First order approximation of a power series expansion may be utilized since the jitter fraction δ(t) is a small value. However, it should be appreciated that other approximations may be used. It should be appreciated that the amount multiplied against the peak current IPEAK may be referred to herein as the compensation factor. For equation (14), the compensation factor is:





  
    
      
        1
        +
        
          
            1
            2
          
          ⁢
          
            δ
            ⁡
            
              (
              t
              )
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




In comparing the compensation factor of equation (15) with the formula for the general compensation factor shown in equation (12), the compensation coefficient





  k
  =
  
    
      1
      
        2
        ⁢
        
          
        
      
    
    .
  




However, as mentioned above, the compensation coefficient k may be altered depending on how accurate an approximation of the compensation factor is needed.

Referring next to FIG. 3, a functional block diagram of the jitter compensated controller 330 is illustrated. Jitter compensated controller 330 is one possible implementation of the jitter compensated controller 130 of FIG. 1. Jitter compensated controller 330 is illustrated as including a jitter block 302, a jitter signal UJ(t) 303, an oscillator 304, a clock signal 306, a jitter compensator 308, jitter compensator signal UJC(t) 309, an arithmetic operator 310, a compensated controller input signal UCOMP 311, and a pulse width modulator (PWM) 312. Also illustrated in FIG. 3 are feedback circuit 120, feedback signal UFB 122, switch S2 126, constant open loop signal UCOL 124, controller input UC 128, drive signal 332 and current sense input 134. It should be appreciated that drive signal 332 is one example of the drive signal 132 of FIG. 1.
The feedback circuit 120, feedback signal UFB 122, switch S2 126, constant open loop signal UCOL 124, controller input UC 128 and current sense input 134 couple and function as described with respect to FIG. 1. The jitter block 302 couples to the oscillator 304 and the jitter compensator 308 and outputs jitter signal UJ(t) 303. The oscillator also couples to the PWM 312 and outputs the clock signal 306 to the PWM 312. The jitter compensator 308 also couples to the arithmetic operator 310 and outputs the jitter compensator signal UJC(t) 309. In addition to the jitter compensator signal UJC(t) 309, the arithmetic operator 310 receives the controller input UC 128. The arithmetic operator also couples to the PWM 312 and the resultant compensated controller input signal UCOMP 311 is received by the PWM 312. Optionally, the PWM 312 may be coupled to receive the current sense input 134. Utilizing the various signals, the PWM 312 outputs the drive signal 332 which operates the switch S1 110 and regulates various switching parameters to substantially regulate the output quantity UO to the desired value.
The drive signal 332 controls the turning on and turning off of the switch S1 110. In one example, the drive signal 332 may be a rectangular pulse waveform with varying lengths of logic high and logic low sections, with a logic high value corresponding to a closed switch and a logic low corresponding to an open switch. When the switch S1 110 is a MOSFET, the drive signal 332 may be analogous to the gate signal of a transistor with a logic high value corresponding to a closed switch and a logic low corresponding to an open switch. Various components, such as the jitter block 302, oscillator 304, jitter compensator 308 and PWM 312 affect the resultant drive signal 332. Jitter block 302 provides the amount of modulation of the switching frequency fS or switching period TS. In one embodiment of the present invention, jitter block 302 provides the amount of frequency modulation to reduce EMI emissions of the power supply 100. The jitter block 302 provides jitter signal UJ(t) 303, which represents the jitter fraction δ(t) of the equations above. Since the jitter fraction δ(t) changes with time, the jitter signal UJ(t) 303 also changes with time and is referenced accordingly. As mentioned, the jitter fraction δ(t) may be a percentage amount of change to the switching period TS and the magnitude of the jitter fraction δ(t) can be a value between zero and one. The jitter signal UJ(t) 303 is then sent to the oscillator 304.
In some embodiments of the present invention, the oscillator 304 outputs the clock signal 306 which provides the switching period TS to the PWM 312. Utilizing the jitter fraction δ(t) from the jitter signal UJ(t) 303, the oscillator 304 modulates the switching period TS by the jitter fraction δ(t). The resultant modulated switching period TS is sent to PWM 312 through clock signal 306. In embodiments of the present invention, the clock signal 306 is a rectangular pulse waveform. In one example, the rising edge of the clock signal 306 indicates the beginning of a switching period TS.
The jitter signal UJ(t) 303 is also sent to the jitter compensator 308. As discussed with regards to the above equations, specifically equation (11), equation (12) and equation (15), in one embodiment the jitter compensator 308 determines the compensation factor for the duty ratio D or the peak current IPEAK from the jitter signal UJ(t) 303. In one example, the jitter signal UJ(t) 303 provides information regarding the jitter fraction δ(t) and the jitter compensator 308 determines the compensation factor for the duty ratio D or the peak current IPEAK from the jitter signal UJ(t) 303. The jitter compensator 308 then sends information regarding the compensation factor of equation (12) to the arithmetic operator 310 through jitter compensator signal UJC(t) 309. Depending upon the mode of control, in some embodiments of the present invention the jitter compensator signal UJC(t) 309 represents the compensation factor of equation (11) or equation (15). However, as mentioned above the compensation coefficient k of equation (11) or equation (15) may be altered depending upon how much accuracy is needed in approximating the compensation factor. In one embodiment, the compensation coefficient k may be chosen to minimize the error in approximation. It should also be appreciated that the jitter compensator signal UJC(t) 309 may also represent the amount, kδ(t). In various examples, the jitter compensator signal UJC(t) 309 may represent the percentage amount of change to either the duty ratio D or the peak current IPEAK. In general, the jitter compensated signal UJC(t) 309 represents some manipulation of the jitter fraction δ(t). Since the jitter fraction δ(t) changes with time t, the jitter compensated signal UJC(t) 309 also changes with time t and is referenced accordingly. Signals such as the jitter signal UJ(t) 303 and jitter compensated signal UJC(t) 309 may be represented as a voltage signal or a current signal.
Arithmetic operator 310 couples to the jitter compensator 308, switch S2 126 and the pulse width modulator (PWM) 312. In operation, the arithmetic operator 310 receives the jitter compensator signal UJC(t) 309 and the controller input UC 128. Functionally, the arithmetic operator 310 may perform a number of arithmetic operations such as addition, subtraction, multiplication and division to the various inputs to the arithmetic operator 310 to provide a resultant output.
In open loop configuration, the controller input UC 128 is a constant open loop signal UCOL 124. In some embodiments, the constant open loop signal UCOL 124 provides information regarding the value of the duty ratio D or the peak current IPEAK of the power supply 100. In closed loop configuration, the controller input UC 128 is the feedback signal UFB 122. The feedback signal UFB 122 facilitates the regulation of the output quantity UO. In some embodiments, the feedback signal UFB 122 provides information regarding the value of the output quantity UO which is used to determine the duty ratio D or the peak current IPEAK utilized to regulate the output quantity UO. The constant open loop signal UCOL 124 and feedback signal UFB 122 may be represented as a voltage signal or a current signal.
The arithmetic operator 310 utilizes the received jitter compensator signal UJC(t) 309 and the controller input UC 128 to produce an output which is sent to the PWM 312. The output of the arithmetic operator 310 is referred to as the compensated controller input UCOMP 311. The compensated controller input UCOMP 311 may be represented as a voltage signal or a current signal. In some embodiments, the compensated controller input UCOMP 311 is the compensated duty ratio DCOMP or the compensated peak current ICOMP as illustrated with regards to equation (10) and equation (14). The PWM 312 then utilizes the compensated controller input UCOMP 311 outputted from the arithmetic operator 310 to produce the drive signal 332.
In one example, the jitter compensator 308 sends the arithmetic operator 310 information regarding the compensation factor of equation (12). Depending upon the mode of control, the jitter compensator signal UJC(t) 309 represents the compensation factor of equation (11) or equation (15). When the jitter compensator signal UJC(t) 309 represents the compensation factor of equation (12), the arithmetic operator 310 performs multiplication to multiply the compensation factor of equation (12) with the controller input UC 128. Depending on the mode of control, the arithmetic operator 310 performs multiplication to provide the compensated controller input UCOMP 311 representative of either the compensated duty ratio DCOMP or the compensated peak current ICOMP of equations (10) and (14).
In one embodiment, the jitter compensated controller 330 utilizes PWM duty ratio programmed control and the controller input UC 128 represents the value of the duty ratio D to regulate the output quantity UO while the jitter compensator signal UJC(t) 309 represents the compensation factor of equation (11). However, it should be appreciated that the compensation coefficient k of equation (11) maybe be chosen depending on how accurate an approximation for the compensated duty ratio DCOMP is needed. The arithmetic operator 310 then performs multiplication to output the compensated duty ratio DCOMP of equation (10). The compensated controller input UCOMP 311 outputted by the arithmetic operator 310 and received by the PWM 312 represents the compensated duty ratio DCOMP of equation (10).
In another embodiment, the jitter compensated controller 130 utilizes PWM current programmed control and the controller input UC 128 represents the value of the peak current IPEAK to regulate the output quantity UO while the jitter compensator signal UJC(t) 309 represents the compensation factor of equation (15). However, it should be appreciated that the compensation coefficient k of equation (15) may be chosen depending on how accurate an approximation for the compensated peak current ICOMP is needed. The arithmetic operator 310 then performs multiplication to output the compensated peak current ICOMP of equation (14). The compensated controller input UCOMP 311 outputted by the arithmetic operator 310 and received by the PWM 312 would represent the compensated peak current ICOMP of equation (14).
It should also be appreciated that the jitter compensator signal UJC(t) 309 may also represent the product of compensation coefficient and the jitter fraction, kδ(t). For this embodiment, the arithmetic operator 310 may perform multiplication along with addition or subtraction depending on the value of the product of the compensation coefficient and the jitter fraction, kδ(t). The arithmetic operator 310 may add a value substantially equal to one to the jitter compensator signal UJC(t) 309 representative of the product of compensation coefficient and the jitter fraction, kδ(t), to calculate the compensation factor of equation (12). The arithmetic operator 310 then multiplies the resultant compensation factor to the controller input UC 128. As mentioned above, the controller input UC 128 provides information which is used to determine the duty ratio D or the peak current IPEAK of the power supply 100. Depending on the mode of operation, the arithmetic operator 310 outputs the compensated controller input UCOMP 311 representative of the compensated duty ratio DCOMP or the compensated peak current ICOMP.
As mentioned above, the arithmetic operator 310 may perform multiplication along with addition or subtraction when the jitter compensator signal UJC(t) 309 represents the product of compensation coefficient and the jitter fraction, kδ(t). In another embodiment, the arithmetic operator 310 may multiply the jitter compensator signal UJC(t) 309 with the controller input UC 128. The resultant product is then added to the controller input UC 128 by the arithmetic operator 310. As mentioned above, the controller input UC 128 provides information which is used to determine the duty ratio D or the peak current IPEAK of the power supply 100. Depending on the mode of operation, the arithmetic operator 310 outputs the compensated controller input UCOMP 311 representative of the compensated duty ratio DCOMP or the compensated peak current ICOMP.
Referring next to FIG. 4, a functional block diagram of the jitter compensated controller 430 is illustrated. Jitter compensated controller 430 is one possible implementation of the jitter compensated controller 130 of FIG. 1 or jitter compensated controller 330 of FIG. 3 utilizing PWM duty ratio programmed control. Jitter compensated controller 430 is illustrated as including jitter block 302, jitter signal UJ(t) 303, oscillator 304, clock signal 306, a jitter compensator 408, a jitter compensator signal UJC(t) 409, a multiplier 410, a compensated controller input UCOMP 411 and a pulse width modulator (PWM) 412. The PWM 412 further includes a sawtooth waveform generator 402 and comparator 404. Also illustrated in FIG. 4 is feedback circuit 120, feedback signal UFB 122, switch S2 126, constant open loop signal UCOL 124, controller input UC 128, and drive signal 432. It should be appreciated that drive signal 432 is one example of the drive signal 132 of FIG. 1 or drive signal 332 of FIG. 3.
The feedback circuit 120, feedback signal UFB 122, switch S2 126, constant open loop signal UCOL 124, controller input UC 128, jitter block 302, jitter signal UJ(t) 303, oscillator 304, and clock signal 306 couple and function as described with respect to FIGS. 1 and 3. The jitter compensator 408 couples to the jitter block 302 and receives the jitter signal UJ(t) 303 and outputs the jitter compensator signal UJC(t) 409. The sawtooth waveform generator 402 is coupled to the oscillator 304 and receives the clock signal 306. The sawtooth waveform generator 402 further couples to comparator 404. In the illustrated example, the output of the sawtooth waveform generator 402 is received at the inverting input of the comparator 404. As shown in FIG. 4, the non-inverting input of comparator 404 is coupled to the multiplier 410 and receives the output of the multiplier 410. The comparator 404 outputs the drive signal 432. For the example shown in FIG. 4, the multiplier 410 is one example of the arithmetic operator 310 when the jitter compensated signal UJC(t) 409 represents the compensation factor.
The sawtooth waveform generator 402 receives the clock signal 306 which provides the sawtooth waveform generator 402 with the switching period TS and subsequent jitter fraction δ(t), in other words the modulated switching period TS. A sawtooth waveform is output with the same period as the switching period TS and subsequent jitter fraction δ(t) provided by the oscillator 304. In some embodiments, the sawtooth waveform generator 402 determines the maximum switching period TS of the power supply 100. In the example of FIG. 4, the jitter compensated controller 430 utilizes PWM duty ratio programmed control and the jitter compensator 408 is one example of jitter compensator 308 of FIG. 3 where the jitter compensator 408 outputs a jitter compensated signal UJC(t) 409 representative of the compensation factor. For example, equation (11) illustrates one example of the compensation factor with a compensation coefficient of




  k
  =
  
    -
    
      
        1
        2
      
      .
    
  




In one example, the jitter compensated signal UJC(t) 409 is a voltage signal. The controller input UC 128 provides information which is used to determine the value of the duty ratio D of the power supply 100 when the jitter compensated controller 430 utilizes PWM duty ratio programmed control. As mentioned above, the controller input UC 128 may be either the feedback signal UFB 122 or the constant open loop signal UCOL 124 depending whether the power supply 100 is operating in a closed loop configuration or an open loop configuration. For the example embodiment shown in FIG. 4, the constant open loop signal UCOL 124 provides information regarding the value of the duty ratio D of the power supply 100 operating in open loop configuration. However, most power supplies operate in a closed loop configuration. In closed loop configuration, the feedback signal UFB 122 provides information regarding the value of the output quantity UO which is used to determine the duty ratio D to regulate the output quantity UO.

The multiplier 410 receives the jitter compensator signal UJC(t) 409 and the controller input UC 128. As mentioned above, the multiplier 410 is one example of the arithmetic operator 310 of FIG. 3. The multiplier 410 multiplies the jitter compensator signal UJC(t) 409 and the controller input UC 128 to produce the compensated controller input UCOMP 411 which is sent to the non-inverting input of comparator 404. In one embodiment, the jitter compensator signal UJC(t) 409 provides the compensation factor of equation (11). The compensated controller input UCOMP 411 output from the multiplier 410 sets the duty ratio for the power supply 100. In the example illustrated in FIG. 5, the compensated controller input UCOMP 411 represents the compensated duty ratio DCOMP. Equation (10) illustrates one example of the compensated duty ratio DCOMP in accordance with embodiments of the present invention. The comparator 404 receives the compensated controller input UCOMP 411 and outputs the drive signal 432. When the voltage at the non-inverting input of the comparator 404 is greater than the voltage on the inverting input of the comparator 404, the comparator 404 outputs a logic high value. When the voltage on the inverting input of the comparator 404 is greater than the voltage on the non-inverting input of the comparator 404, the comparator 404 outputs a logic low value. In this sense, the output of multiplier 410 may set the duty ratio D of the power supply 100.
Referring next to FIG. 5, a functional block diagram of the jitter compensated controller 530 is illustrated. Jitter compensated controller 530 is one possible implementation of jitter compensated controller 130 of FIG. 1 or jitter compensated controller 330 of FIG. 3 utilizing PWM current programmed control. Jitter compensated controller 530 is illustrated as including jitter block 302, jitter signal UJ(t) 303, oscillator 304, clock signal 306, a jitter compensator 508, jitter compensator signal UJC(t) 509, a multiplier 510, a compensated controller input UCOMP 511 and a pulse width modulator (PWM) 512. PWM 512 further includes a comparator 506 and a latch 504. Also illustrated in FIG. 5 are feedback circuit 120, feedback signal UFB 122, switch S2 126, constant open loop signal UCOL 124, controller input UC 128, drive signal 532 and current sense input 134. It should be appreciated that drive signal 532 is one example of the drive signal 132 of FIG. 1 or drive signal 332 of FIG. 3.
The feedback circuit 120, feedback signal UFB 122, switch S2 126, constant open loop signal UCOL 124, controller input UC 128, current sense input 134, jitter block 302, oscillator 304 and clock signal 306 couple and function as described with respect to FIGS. 1 and 3. The jitter compensator 508 couples to jitter block 302 and receives the jitter signal UJ(t) 303 and outputs the jitter compensator signal UJC(t) 509. The comparator 506 couples to the current sense input 134 and the output of the multiplier 510. For the example shown in FIG. 5, the multiplier 510 is one example of the arithmetic operator 310 when the jitter compensated signal UJC(t) 509 represents the compensation factor. The compensated controller input UCOMP 511 output from the multiplier 510 is received at the inverting input of the comparator 506 while the current sense signal 134 is received at the non-inverting input of comparator 506. The output of the comparator 506 couples to latch 504. Latch 504 further couples to oscillator 304 and receives the clock signal 306. In one example, latch 504 is an S-R latch and the clock signal is received at the S-input of latch 504 while the output of comparator 506 is received at the R-input of latch 504. The output of the latch 504 provides the drive signal 532.
In the example of FIG. 5, the jitter compensated controller 530 utilizes PWM current programmed control and the jitter compensator 508 is one example of jitter compensator 308 of FIG. 3 where the jitter compensator 508 outputs a jitter compensated signal UJC(t) 509 representative of the compensation factor. For example, equation (15) illustrates one example of the compensation factor. In addition to the jitter compensated signal UJC(t) 509, the multiplier 510 also receives the controller input UC 128. The controller input UC 128 provides information which is used to determine the value of the peak current IPEAK when the jitter compensated controller 530 utilizes PWM current programmed control. As mentioned above, the controller input UC 128 may either be the feedback signal UFB 122 or the constant open loop signal UCOL 124 depending on whether the power supply 100 is operating in a closed loop configuration or an open loop configuration. For the example embodiment shown in FIG. 5, the constant open loop signal UCOL 124 provides information regarding the value of the peak current IPEAK when the power supply 100 is operating in open loop configuration. However, most power supplies operate in a closed loop configuration. In closed loop configuration, the feedback signal UFB 122 provides information regarding the value of the output quantity UO which is used to determine the peak current IPEAK to regulate the output quantity UO.
The multiplier 510 receives the jitter compensator signal UJC(t) 509 and the controller input UC 128. The multiplier 510 multiplies the jitter compensator signal UJC(t) 509 and the controller input UC 128 to produce the compensated controller input signal UCOMP 511 which is sent to the inverting input of comparator 506. The output of the multiplier 510 sets the peak current IPEAK for the jitter compensated controller 530. In the example illustrated in FIG. 5, the compensated controller input signal UCOMP 511 represents the compensated peak current ICOMP. Equation (14) illustrates one example of the compensated peak current ICOMP in accordance with embodiments of the present invention. The comparator 506 compares the compensated controller input signal UCOMP 511 with the value of the current sense input 134. When the value of the current sense input 134 is greater than the compensated controller input signal UCOMP 511, the comparator 506 outputs a logic high value. When the compensated controller input signal UCOMP 511 is greater than the value of the current sense input 134, the comparator 506 outputs a logic low value. The output of the comparator 506 is then sent to the R-input of latch 504.
The clock signal 306 is received at the S-input of latch 504. The clock signal 306 provides the switching period TS and subsequent jitter fraction δ(t) of the switched mode power supply 100. At the beginning of a switching period TS, the value of the current sense input 134 is less than the compensated controller input signal UCOMP 511. In other words, the switch current ID 136 sensed at the current sense input 134 is less than the compensated peak current ICOMP. As such, the output of comparator 506 is a logic low value. At the beginning of the switching period TS, the clock signal 306 pulses to a logic high value while the output of the comparator is a logic low value resulting in a logic high output of the latch and the switch S1 110 closes. The clock signal 306 then quickly falls to a logic low value and results in the latch 504 holding the previous output value (for this example, a logic high value). Once the value of the current sense input 134 reaches the value of the compensated controller input signal UCOMP 511, or in other words the switch current ID 136 sensed at the current sense input 134 reaches the compensated peak current ICOMP, the output of the comparator 506 pulses to a logic high value. As a result the output of the latch 504 switches to a logic low value and the switch S1 110 opens. The switch current ID 136 sensed by the current sense input 134 begins to fall due to the open switch S1 110 and the output of the comparator 506 becomes a logic low value resulting in the latch 504 holding the previous output value (for this example, a logic low value) until the clock signal 306 pulses to a logic high value at the beginning of the next switching period TS. The output of the latch 504 provides the drive signal 532 for the switch S1 110 of the power supply 100.
Referring next to FIG. 6, an example schematic of the jitter compensator 609 and arithmetic operator 602 is illustrated including controller input IC 128, drive signal 632, jitter signal UJ(t) 603, pulse width modulator (PWM) 640, a first transistor 604, a second transistor 606, a current source 608 with constant current IA, a current source 610 with input current IX, input return 611, resistor 612, a first voltage source VB 614, a second voltage source VB 616, current source 618 with offset current IO, resistor 622, voltage VCC 624, and a duty ratio signal UD 626. Arithmetic operator 602 and jitter compensator 609 are possible implementations of the arithmetic operator 310 and jitter compensator 308, respectively, of FIG. 3. It should be appreciated that the duty ratio signal UD 626 is one example of the compensated controller input UCOMP 311 of FIG. 3. In addition, the jitter signal UJ(t) 603 is one example of the jitter signal UJ(t) 303 of FIG. 3. For the example of FIG. 6, the controller input 128 is referenced as IC rather than UC (as seen in previous figures) to denote that the controller input IC 128 is a current signal. The jitter compensated current is referenced as IJC(t) to denote that the jitter compensated current IJC(t) is a function of time t.
Arithmetic operator 602 includes a differential amplifier comprising first transistor 604, second transistor 606, tail current ITAIL, and current source 608 with constant current IA. In addition, the differential amplifier further includes jitter compensator 609. As shown in FIG. 6, jitter compensator 609 may be implemented as a current source 609 which produces jitter compensated current IJC(t). The jitter compensated current IJC(t) may be one example of the jitter compensator signal UJC(t) 309 of FIG. 3. In the example of FIG. 6, the first transistor 604 and the second transistor 606 are NPN-type bipolar junction transistors. However, it should be appreciated that other transistor types may be used. Current source 608 of the differential amplifier is coupled to input return 611 such that a positive constant current IA flows to the input return 611. Current source 609 of the differential amplifier is coupled to input return 611 such that a positive jitter compensated current IJC(t) flows to the input return 611. The current sources 608 and 609 are coupled such that the tail current ITAIL of the differential amplifier is substantially equal to the sum of the constant current IA and the jitter compensated current IJC(t), mathematically: ITAIL=IA+IJC(t). In addition, the current source 609 couples to and receives the jitter signal UJ(t) 603. In one embodiment, the value of the jitter compensated current IJC(t) provided by current source 609 may be determined by the jitter signal UJ(t) 603. It should be appreciated that the current source 609 may be a voltage controlled current source or a current controlled current source when the jitter signal UJ(t) 603 is either a voltage signal or a current signal, respectively.
One end of current source 610 with input current IX couples to the base of the first transistor 604 while the other end of current source 610 couples to the voltage VCC 624. Current source 610 also couples to and receives the controller input IC 128. In one embodiment, the value of the input current IX provided by the current source 610 may be determined by the controller input IC 128 and the offset current IO provided by current source 618. In one embodiment, the value of the input current IX is proportional to the value of the controller input IC 128. For the example of FIG. 6, when the controller input IC 128 is a current signal, the current source 610 may be a current controlled current source. However, it should be appreciated that when the controller input UC 128 is a voltage signal, the current source 610 may be a voltage controlled current source. Resistor 612 couples to the current source 610 and the base of the first transistor 604 at node VB1. As illustrated, the voltage at node VB1 is also the base voltage of the first transistor 604. The resistor 612 further couples to the positive end of the first voltage source VB 614 while the negative end of the first voltage source VB 614 couples to the input return 611. In the example of FIG. 6, the current source 618 with offset current IO is coupled to the controller input IC 128 and the current source 610 such that the current source 610 receives the difference between the controller input IC 128 and the offset current IO. The current source 618 with offset current IO also couples to input return 611 such that a positive offset current IO flows to input return 611. In one embodiment of the present invention, the current source 618 with offset IO current is optional.
The positive end of the second voltage source VB 616 couples to the base of the second transistor 606. The negative end of the second voltage source VB 616 is coupled to input return 611. As illustrated in FIG. 6, the base voltage of the second transistor 606 is denoted as VB2. In addition, the base voltage VB2 of the second transistor 606 is substantially equal to the second voltage source VB 616. In some embodiments of the invention, the value of the first voltage source VB 614 and the second voltage source VB 616 are substantially equal. The second voltage source VB 616 sets the base voltage VB2 of the second transistor 606.
Resistor 622 with resistance R1 and the PWM 640 are further coupled to the second transistor 606. The PWM 640 is one possible implementation of the PWM 312 shown in FIG. 3. The resistor 622 is coupled between the voltage VCC 624 and the collector of the second transistor 606. The duty ratio signal UD 626 is output from arithmetic operator 602 to PWM 640. It should be appreciated that the duty ratio signal UD 626 represents the duty ratio D or the compensated duty ratio DCOMP (when jitter compensation is used) for the power supply. As explained above, the duty ratio signal UD 626 is one example of the compensated controller input UCOMP 311 of FIG. 3. In the example of FIG. 6, the duty ratio signal UD 626 is the collector voltage of the second transistor 606. As discussed above with respect to FIG. 4, the PWM 412 may comprise of a comparator 404 and a sawtooth waveform generator 402. For the example shown in FIG. 6, the PWM 640 comprises a comparator which receives the sawtooth waveform 628 at the non-inverting input and the duty ratio signal UD 626 at the inverting input. The sawtooth waveform 628 of FIG. 6 has a maximum voltage substantially equal to the voltage VCC 624 with a minimum voltage set to VMIN. In one embodiment of the present invention, the minimum voltage VMIN of the sawtooth waveform 628 may be substantially equal to zero. However, it should be appreciated that the minimum voltage VMIN may be set to a voltage which is less than VCC 624.
In the example of FIG. 6, the voltage VCC 624 minus the product of half the tail current ITAIL/2 and the resistance R1 of resistor 622, mathematically:




  
    
      V
      CC
    
    -
    
      
        
          I
          TAIL
        
        ⁢
        
          R
          1
        
      
      2
    
  
  ,




sets the maximum duty ratio DMAX (illustrated in the duty ratio to controller input relationship 630) of the power supply 100. In one example, the resistance R1 of resistor 622 and the constant current IA are chosen such that the product of half of the tail current ITAIL/2 and the resistance R1 of resistor 622, mathematically: (ITAILR1)/2, is substantially equal to VCC−VMIN. When the product (ITAILR1)/2 is substantially equal to VCC−VMIN, the maximum duty ratio DMAX is substantially equal to one.

In another embodiment, the resistance R1 of resistor 622 and the constant current IA are chosen such that the maximum duty ratio DMAX is substantially equal to 0.78. In other words, the product of half of the tail current ITAIL/2 and the resistance R1 of resistor 622, mathematically: (ITAILR1)/2, should be substantially equal to 78% of the difference between voltage VCC 624 and the minimum voltage VMIN, mathematically:




  
    
      
        I
        TAIL
      
      ⁢
      
        R
        1
      
    
    2
  
  =
  
    0.78
    ⁢
    
      
        (
        
          
            V
            CC
          
          -
          
            V
            
              MI
              ⁢
              
                
              
              ⁢
              N
            
          
        
        )
      
      .
    
  




The PWM 640 couples between resistor 622 and second transistor 606. In the example of FIG. 6, the inverting input of the comparator which comprises PWM 640 couples to the second transistor 606. When the second transistor 606 is an NPN-type bipolar junction transistor, the inverting input of the comparator couples to the collector of the second transistor 606. The comparator then outputs the drive signal 632. It should be appreciated that drive signal 632 is one example of the drive signal 132 of FIG. 1 or drive signal 332 of FIG. 3.
The differential amplifier provides a current I2 which is dependent upon the tail current ITAIL and base voltages VB1 and VB2 of the first transistor 604 and the second transistor 606, respectively. From the example of FIG. 6, current I2 is the collector current of the second transistor 606. When the differential amplifier includes current source 609 with jitter compensated current IJC(t) due to jitter compensation by the controller 330, the tail current ITAIL is dependent on the constant current IA and the jitter compensated current IJC(t). In one embodiment current source 609 with jitter compensated current IJC(t) can be analogous to the jitter compensator 308. Current source 609 is controlled by jitter signal UJ(t) 603 to produce jitter compensated current IJC(t). In the example of FIG. 6, the jitter compensator signal UJC(t) produced by current source 609 which comprises the jitter compensated current IJC(t) may represent the percentage amount of change to the duty ratio D, i.e. kδ(t), where k is the compensation coefficient and δ(t) is the jitter fraction as discussed above. For the example of FIG. 6, the jitter compensator signal UJC(t) is a current signal.
The current I2 produced by the differential amplifier may be expressed as:




  
    
      
        
          
            I
            2
          
          =
          
            
              I
              TAIL
            
            
              1
              +
              
                e
                
                  
                    (
                    
                      
                        V
                        
                          B
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      -
                      
                        V
                        
                          B
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                    )
                  
                  /
                  
                    V
                    T
                  
                
              
            
          
        
        ,
      
    
    
      
        (
        16
        )
      
    
  




where VT represents the thermal voltage of the first and second transistor 604 and 606. When there is no jitter compensated current IJC(t) produced by current source 609, the tail current ITAIL is substantially equal to the constant current IA produced by current source 608. For the example of FIG. 6, the second base voltage VB2 is set to a constant value and is substantially equal to the second voltage source VB 616. As will be discussed further, the first base voltage VB1 of first transistor 604 is partially determined by the controller input IC 128.

The second base voltage VB2 of second transistor 606 is substantially equal to the second voltage source VB 616 and in one embodiment of the present invention the first voltage source VB 614 and the second voltage source VB 616 are substantially equal to each other. When the input current IX is substantially equal to zero and the first voltage source VB 614 and the second voltage source VB 616 are substantially equal to each other, the first base voltage VB1 is substantially equal to the second base voltage VB2. As such the current I2 produced by the differential amplifier from equation (16) is substantially equal to half the tail current ITAIL/2. When there is no jitter compensated current IJC(t) produced by current source 609, the current I2 is substantially equal to IA/2.
In the example of FIG. 6, the duty ratio signal UD 626 is the collector voltage of second transistor 606. When the first base voltage VB1 and the second base voltage VB2 are substantially equal, the current though resistor 622 is substantially equal to half the tail current ITAIL/2 and the collector voltage of the second transistor 606 is substantially equal to




  
    V
    CC
  
  -
  
    
      
        
          I
          TAIL
        
        ⁢
        
          R
          1
        
      
      2
    
    .
  




The duty ratio signal UD 626 then outputs the collector voltage of the second transistor 606 to the inverting input of the comparator of PWM 640. The resultant output of the comparator of PWM 640, with the sawtooth waveform 628 bounded between the voltage VCC 624 and VMIN, would be a drive signal 632 with a duty ratio substantially equal to DMAX when the first base voltage VB1 and the second base voltage VB2 are substantially equal.

When the input current IX produced by current source 610 due to the controller input IC 128 generates a voltage across resistor 612 such that the first base voltage VB1 increases to a value greater than the second base voltage VB2, the resultant current I2 produced by the differential amplifier (as shown by equation (16)) is less than the current I2 when the first base voltage VB1 is substantially equal to the second base voltage VB2. In other words, the resultant current I2 produced by the differential amplifier is less than half the tail current ITAIL/2 when the first base voltage VB1 is greater than the second base voltage VB2. As such the value of the duty ratio signal UD 626, or in other words the collector voltage of second transistor 606, when the first base voltage VB1 is greater than the second base voltage VB2 would be greater than the value of the duty ratio signal UD 626 when the first base voltage VB1 is substantially equal to the second base voltage VB2. As a result the duty ratio D of the drive signal 632 is less than the maximum duty ratio DMAX.
In the example of FIG. 6, the current source 610 with input current IX is a current controlled current source which is dependent upon the controller input IC 128. The current source 610 with input current IX is proportional to the controller input IC 128. In general, if the controller input IC 128 increases then the input current IX provided by current source 610 also increases. Conversely, if the controller input IC 128 decreases then the input current IX provided by current source 610 also decreases. However, a current source 618 with offset current IO may be included such that the duty ratio provided by the drive signal 632 would follow the characteristics of the duty ratio to controller input relationship 630.
The duty ratio to controller input relationship 630 illustrates how the duty ratio D changes with the controller input IC 128. As seen in the duty ratio to controller input relationship 630, the duty ratio D is substantially equal to the maximum duty ratio DMAX until the controller input IC 128 reaches the offset current IO. When the controller input IC 128 is greater than the offset current IO, the duty ratio D decreases with an increase of the controller input IC 128. As discussed above, when the first base voltage VB1 is greater than the second base voltage VB2, the duty ratio D provided by the drive signal 632 is less than the maximum duty ratio DMAX. The greater the value of the first base voltage VB1 with respect to the second base voltage VB2 corresponds to a smaller duty ratio D. In the example of FIG. 6, the first base voltage VB1 is substantially equal to the second base voltage VB2 until the controller input IC 128 is greater than the offset current IO provided by current source 618. In other words, when the controller input IC 128 is less than the offset current IO provided by current source 618, the current source 610 provides an input current IX substantially equal to zero. When input current IX is substantially equal to zero, the first base voltage VB1 is substantially equal to the second base voltage VB2 and the duty ratio D is substantially equal to the maximum duty ratio DMAX. Once the controller input IC 128 is greater than the offset current IO, an input current IX is provided by current source 610 such that the first base voltage VB1 may increase to a value greater than the second base voltage VB2 which leads to a duty ratio D which is less than the maximum duty ratio DMAX.
With the offset current IO provided by the current source 618, the input current IX is dependent upon the difference between the controller input IC 128 and the offset current IO, mathematically: IC−IO. When the controller input IC 128 is less than the offset current IO, input current IX is substantially equal to zero. When the controller input IC 128 is greater than the offset current IO, the input current IX is proportional to the difference between the controller input IC 128 and the offset current IO. In another embodiment, when the controller input IC 128 is greater than the offset current IO, the input current IX is linearly proportional to the difference between the controller input IC 128 and the offset current IO. By utilizing the offset current IO provided by current source 618, the duty ratio D is substantially the maximum duty ratio DMAX until the controller input IC 128 is greater than the offset current JO.
In addition, current source 609 provides a jitter compensated current IJC(t) such that the duty ratio signal UD 626 may provide a compensated duty ratio DCOMP, such as the compensated duty ratio DCOMP of equation (10). Current source 609 receives jitter signal UJ(t) 603 to produce the jitter compensated current IJC(t). Accounting for the current source 609, the current I2 produced by the differential amplifier may be expressed as:




  
    
      
        
          I
          2
        
        =
        
          
            
              I
              A
            
            +
            
              
                I
                JC
              
              ⁡
              
                (
                t
                )
              
            
          
          
            1
            +
            
              e
              
                
                  (
                  
                    
                      V
                      
                        B
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    -
                    
                      V
                      
                        B
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                /
                
                  V
                  T
                
              
            
          
        
      
    
    
      
        (
        17
        )
      
    
  




Equation (17) illustrates the current I2 produced by the differential amplifier from equation (16) when ITAIL=IA+IJC(t). For illustration purposes, the denominator of equation (17) may be considered a constant for a given value of the controller input IC 128 and equation (17) may be expressed as:

I2=n(IA+IJC(t))  (18)

From FIG. 6, the duty ratio signal UD 626 may be expressed as:

UD=VCC−R1I2  (19)

When there is no jitter compensated current IJC(t), the current I2=nIA and the duty ratio signal UD 626 from equation (19) without jitter compensation may be expressed as:

UD=VCC−R1nIA  (20)

When there is jitter compensated current IJC(t) provided by the current source 609, the duty ratio signal UD 626 outputs the compensated duty ratio signal UDCOMP to the PWM 640 and the current I2=n(IA+IJC(t)) and the compensated duty ratio signal UDCOMP may be expressed as:

UDCOMP=VCC−R1n(IJC(t)+IA)  (21)

With the sawtooth waveform 628 with the maximum voltage VCC 624 and a minimum voltage VMIN, the duty ratio D may be expressed as:




  
    
      
        D
        =
        
          
            
              V
              CC
            
            -
            
              U
              D
            
          
          
            
              V
              CC
            
            -
            
              V
              
                MI
                ⁢
                
                  
                
                ⁢
                N
              
            
          
        
      
    
    
      
        (
        22
        )
      
    
  




By substituting the duty ratio signal UD 626 from equation (20) into equation (22), the duty ratio D may also be expressed as:




  
    
      
        D
        =
        
          
            
              R
              1
            
            ⁢
            
              nI
              A
            
          
          
            
              V
              CC
            
            -
            
              V
              
                MI
                ⁢
                
                  
                
                ⁢
                N
              
            
          
        
      
    
    
      
        (
        23
        )
      
    
  




With the sawtooth waveform 628 with the maximum voltage VCC 624 and a minimum voltage VMIN, the compensated duty ratio DCOMP may be expressed as:




  
    
      
        
          D
          COMP
        
        =
        
          
            
              V
              CC
            
            -
            
              U
              DCOMP
            
          
          
            
              V
              CC
            
            -
            
              V
              
                MI
                ⁢
                
                  
                
                ⁢
                N
              
            
          
        
      
    
    
      
        (
        24
        )
      
    
  




Again, by substituting the compensated duty ratio signal UDCOMP from equation (21) into equation (24), the compensated duty ratio DCOMP may also be expressed as:





  
    
      
        
          D
          COMP
        
        =
        
          
            
              R
              1
            
            ⁢
            
              n
              ⁡
              
                (
                
                  
                    
                      I
                      JC
                    
                    ⁡
                    
                      (
                      t
                      )
                    
                  
                  +
                  
                    I
                    A
                  
                
                )
              
            
          
          
            
              V
              CC
            
            -
            
              V
              
                M
                ⁢
                
                  
                
                ⁢
                I
                ⁢
                
                  
                
                ⁢
                N
              
            
          
        
      
    
    
      
        (
        25
        )
      
    
  




Utilizing the duty ratio D from equation (23), the compensated duty ratio DCOMP may be expressed in terms of the duty ratio D:





  
    
      
        
          D
          COMP
        
        =
        
          D
          ⁡
          
            (
            
              1
              +
              
                
                  
                    I
                    JC
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
                
                  I
                  A
                
              
            
            )
          
        
      
    
    
      
        (
        26
        )
      
    
  




By comparing the compensation factor,




  
    1
    +
    
      
        
          I
          JC
        
        ⁡
        
          (
          t
          )
        
      
      
        I
        A
      
    
  
  ,




from equation (26) with the general compensation factor, 1+kδ(t), from equation (12), the differential amplifier performs as an arithmetic operator to provide jitter compensation to the controller when:





  
    
      
        
          
            
              I
              JC
            
            ⁡
            
              (
              t
              )
            
          
          
            I
            A
          
        
        =
        
          k
          ⁢
          
            
          
          ⁢
          
            δ
            ⁡
            
              (
              t
              )
            
          
        
      
    
    
      
        (
        30
        )
      
    
  




As illustrated in FIG. 6, the current source 609 which provides the jitter compensated current IJC(t) receives the jitter signal UJ(t) 603. As mentioned above, the jitter signal UJ(t) 603 represents the jitter fraction δ(t) provided by jitter block 302. The current source 609 acts as the jitter compensator 308 which provides a jitter compensator signal UJC(t) 309. In the example of FIG. 6, the jitter compensated current IJC(t) is the jitter compensator signal UJC(t) 309 and the jitter compensated current IJC(t) represents the percentage amount of change kδ(t) to duty ratio D to compensate for the jitter fraction δ(t).
While the invention herein disclosed has been described by means of specific embodiments, examples and applications thereof, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope of the invention set forth in the claims.

## Claims

1. A controller for use in a power supply, the controller comprising:
a drive signal generator coupled to output a drive signal having a switching period and a duty ratio to control switching of a switch in response to an input signal to regulate an output of the power supply, the switch to be coupled to the controller;
a jitter signal generator coupled to provide a jitter signal, wherein the switching period of the drive signal varies in response to the jitter signal, and wherein the jitter signal is representative of a first percentage amount to modulate the switching period of the drive signal;
a compensator signal generator coupled to provide a compensator signal responsive to the jitter signal, wherein the compensator signal is representative of a second percentage amount to decrease the duty ratio in response to the jitter signal increasing the switching period of the drive signal; and
an arithmetic operator coupled to adjust the input signal of the controller in response to the compensator signal to provide a compensated input signal, wherein the drive signal generator is coupled to adjust the duty ratio of the drive signal by the second percentage amount in response to the compensated input signal.

2. The controller of claim 1, further comprising an oscillator coupled between the jitter signal generator and the drive signal generator to provide a clock signal having a switching period, wherein the switching period of the clock signal varies in response to the jitter signal and wherein the switching period of the drive signal is substantially equal to the switching period of the clock signal.

3. The controller of claim 2, wherein the drive signal generator comprises:
a latch coupled to output the drive signal, wherein the latch is further coupled to be set in response to the clock signal; and
a comparator coupled to reset the latch in response to a comparison of a current sense signal and the compensated input signal.

4. The controller of claim 1, wherein the input signal is a feedback signal representative of an output of the power supply.

5. The controller of claim 1, wherein the arithmetic operator comprises a multiplier, and wherein the compensated input signal is representative of the compensator signal multiplied with the input signal.

6. The controller of claim 1, wherein the drive signal generator comprises:
a sawtooth waveform generator coupled to provide a sawtooth waveform signal having a switching period substantially equal to the switching period of the drive signal; and
a comparator coupled to output the drive signal in response to a comparison of the sawtooth waveform signal with the compensated input signal.

7. The controller of claim 1, wherein the second percentage amount to change the duty ratio is proportional to the first percentage amount to modulate the switching period of the drive signal.

8. The controller of claim 1, wherein the compensator signal generator is coupled to generate the compensator signal independent of the input signal.

9. A power supply, comprising:
an energy transfer element;
a switch coupled to the energy transfer element such that a current flows through the energy transfer element and the power switch during an on time of the switch; and
a controller coupled to provide a drive signal to control the switch to regulate an output of the power supply, wherein the drive signal includes a switching period and a duty ratio, the controller comprising:
a drive signal generator coupled to output a drive signal in response to an input signal to regulate the output of the power supply;
a jitter signal generator coupled to provide a jitter signal, wherein the switching period of the drive signal varies in response to the jitter signal, and wherein the jitter signal is representative of a first percentage amount to modulate the switching period of the drive signal;
a compensator signal generator coupled to provide a compensator signal responsive to the jitter signal, wherein the compensator signal is representative of a second percentage amount to decrease the duty ratio in response to the jitter signal increasing the switching period of the drive signal; and
an arithmetic operator coupled to adjust the input signal of the controller in response to the compensator signal to provide a compensated input signal, wherein the drive signal generator is coupled to adjust the duty ratio of the drive signal by the second percentage amount in response to the compensated input signal.

10. The power supply of claim 9, further comprising an oscillator coupled between the jitter signal generator and the drive signal generator to provide a clock signal having a switching period, wherein the switching period of the clock signal varies in response to the jitter signal and wherein the switching period of the drive signal is substantially equal to the switching period of the clock signal.

11. The power supply of claim 10, wherein the drive signal generator comprises:
a latch coupled to output the drive signal, wherein the latch is further coupled to be set in response to the clock signal; and
a comparator coupled to reset the latch in response to a comparison of a current sense signal and the compensated input signal.

12. The power supply of claim 9, wherein the input signal is a feedback signal representative of an output of the power supply.

13. The power supply of claim 9, wherein the arithmetic operator comprises a multiplier, and wherein the compensated input signal is representative of the compensator signal multiplied with the input signal.

14. The power supply of claim 9, wherein the drive signal generator comprises:
a sawtooth waveform generator coupled to provide a sawtooth waveform signal having a switching period substantially equal to the switching period of the drive signal; and
a comparator coupled to output the drive signal in response to a comparison of the sawtooth waveform signal with the compensated input signal.

15. The power supply of claim 9, wherein the second percentage amount to change the duty ratio is proportional to the first percentage amount to modulate the switching period of the drive signal.

16. The power supply of claim 9, wherein the compensator signal generator is coupled to generate the compensator signal independent of the input signal.

17. The power supply of claim 9, wherein the switch and the controller are integrated into a single monolithic integrated device.