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Contract No. DE-AC36-08GO28308

Impact of Accelerated StressTests on SiC MOSFET Precursor 

Parameters

Preprint

Joseph P. Kozak and Khai D. T. Ngo

Virginia Polytechnic Institute and State University

Douglas DeVoto and Joshua Major

National Renewable Energy Laboratory

Presented at International Symposium on 3D Power Electronics 

Integration and Manufacturing (3D PEIM)

College Park, Maryland

June 25 – 27, 2018

Suggested Citation 

Kozak, Joseph P., Khai D. T. Ngo, Douglas DeVoto, and Joshua Major. 

2018. “Impact of Accelerated Stress-Tests on SiC MOSFET Precursor 

Parameters: Preprint.” Golden, CO: National Renewable Energy Laboratory. 

NREL/CP-5400-71331. https://www.nrel.gov/docs/fy18osti/71331.pdf.

Conference Paper

NREL/CP-5400-71331

August 2018
NOTICE

This work was authored in part by the National Renewable Energy Laboratory, operated by Alliance for Sustainable 

Energy, LLC, for the U.S. Department of Energy (DOE) under Contract No. DE-AC36-08GO28308. Funding 

provided by U.S. Department of Energy Office of Energy Efficiency and Renewable Energy Vehicle Technologies 

Office. The views expressed in the article do not necessarily represent the views of the DOE or the U.S. 

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that the U.S. Government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce 

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Impact of Accelerated Stress-Tests on SiC MOSFET 

Precursor Parameters

Joseph P. Kozak* and Khai D.T. Ngo

Bradley Dept. of Electrical and Computer Engineering

Virginia Tech

Blacksburg, VA, USA

*jpkozak@vt.edu

Douglas J. DeVoto, Joshua J. Major

National Renewable Energy Laboratory (NREL)

Golden, CO, USA

Abstract— Incorporating SiC power MOSFETs is very 

attractive for advancing power electronic system performance, yet 

the system reliability with new devices remains in question. This 

work presents an overview of accelerated lifetime tests and the 

packaging and semiconductor failure mechanisms they excite. The 

experiments explained here includes High Temperature Gate Bias 

(HTGB), Switching Cycling, Power Cycling, and Thermal 

Cycling. These experiments stress different failure mechanisms, 

that show degradation in different device parameters including, 

but not limited to, threshold voltage and on-resistance. These four 

experiments help illustrate the spectrum between device and 

package degradation that can be used to design more reliable 

power electronic circuits.

Keywords—Silicon Carbide, MOSFET, Accelerated Testing, 

Reliability

I. INTRODUCTION 

The integration of wide-bandgap (WBG) materials into 

power semiconductor devices is a necessary step to progress 

power electronics systems to be lighter, smaller, and more 

efficient. Silicon carbide (SiC) power metal oxide 

semiconductor field effect transistors (MOSFETs), in

comparison to silicon devices, have most notable advantages in 

electrical breakdown field, thermal conductivity, electron 

saturation drive velocity, and irradiation tolerance [1]-[3]. In 

addition, SiC transistors have been shown to be able to operate 

at higher temperatures (on average at a 25°C higher operating 

temperature to Si [2]). While the material’s characteristics are 

well known, and significant research has been invested into 

characterizing SiC MOSFETs for circuit applications, the 

degradation of these new devices under various operating 

conditions is not fully understood [4]. 

This work investigates various accelerated lifetime test 

(ALT) procedures and discusses their impact on packaging and 

semiconductor degradation of SiC MOSFETs. Fig. 1 categorizes 

a spectrum of ALTs by the test’s target failure mechanism –

packaging-based failure or semiconductor-based failure. While 

there are other ALTs, the experiments shown here help illustrate 

the spectrum between device and package degradation under 

various accelerated test methods.

The left side of Fig. 1 shows experiments that traditionally 

stress the packaging (extrinsic) failure mechanisms. In this work 

the package is defined as all components outside of the SiC 

MOSFET, including die attach material, electrical interconnects, 

encapsulant, and heat sink. These components are composed of 

various materials with different coefficient of thermal expansion 

rates, which causes stresses to develop when the package 

undergoes thermal changes. Failures within, or between, these 

components typically occur under accelerated thermal aging, 

thermal cycling, and power cycling tests due to large 

temperature swings that permeate throughout the entire package. 

The right side of Fig. 1 shows some experiments that are 

focused on stressing semiconductor (intrinsic) failure 

mechanisms. A major weakness within the semiconductor itself 

is the crystallographic mismatch at the interface of the SiC-SiO2

layers in the MOSFET. This interface region consists of 

numerous trap charges including – interface traps, oxide traps, 

fixed charges, and mobile ions [5], [6]. Under various energy

profiles, these charges can shift the threshold voltage (Vth) of the 

device. In addition to shifting Vth, time-dependent dielectric 

breakdown caused by Fowler-Nordheim tunneling can greatly 

weaken the oxide layer of the MOS structure degrading the 

semiconductor performance itself [7].

Fig. 1 Accelerated lifetime test spectrum.

This work surveys the effects of two semiconductor-based 

and two packaging-based lifetime experiments on SiC 

The information, data, or work presented herein was funded in part by the U.S. 

Department of Energy, under Award Number DE-EE0007305. This work was 

authored in part by Alliance for Sustainable Energy, LLC, the manager and operator 

of the National Renewable Energy Laboratory for the U.S. Department of Energy 

(DOE) under Contract No. DE-AC36-08GO28308. The views expressed in the 

article do not necessarily represent the views of the DOE or the U.S. Government. 

The U.S. Government retains and the publisher, by accepting the article for 

publication, acknowledges that the U.S. Government retains a nonexclusive, paidup, irrevocable, worldwide license to publish or reproduce the published form of this 

work, or allow others to do so, for U.S. Government purposes.
2

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MOSFETs. Section II explores work focusing on hightemperature gate bias (HTGB) experiments [5]-[9] and

Switching Cycling [10]. Section III inspects package level 

degradation from both Power Cycling experiments [11]-[15], 

and Thermal Cycling experiments [10], [16], [17]. The effects 

and changes of different device characteristics are discussed, 

with a focus on Vth and ON-resistance (RDSon). 

II. SEMICONDUCTOR FOCUSED LIFETIME TESTS

A. High Temperature Gate Bias

One of the most sensitive areas of the MOSFET structure is 

within the gate oxide layer. Significant research has gone into 

better processing techniques and reliability of the gate oxide, 

especially for SiC devices [18]. This is in part because of the 

greater crystallographic mismatch between SiC and the SiO2

oxide in comparison to Si [19]; in addition, the wider bandgap 

of SiC allows for more Fowler-Nordheim tunneling current to 

take place [7]. To test the resilience of the oxide layer, a HTGB 

experiment can be conducted. 

This HTGB experiment raises the temperature of the 

semiconductor device to a stressful state, generally between 

125°C and 175°C for SiC [7]. Under these conditions, a high 

electric field is applied onto the gate of the MOSFET (with the 

upper limit near 3MV/cm) to stress the oxide layer within the 

device [5], [7], [9]. After a predetermined time, measurements 

of the device characteristics can be taken to observe the full 

effects of the electric field, which can most predominantly be 

seen by shifts in threshold voltage. Another experimental profile 

is shown in Fig. 2 where a device is stressed under both a 

positive and negative bias for set amounts of time (tsoak). A

common technique when rotating between the two stress-bias 

voltages is to ramp the voltage up/down to the +VGS or –VGS

values. This will minimize degradation and excessive trap 

charge states [5], [9]. Fig. 3-6 shows degradation effects from 

different HTGB experiments. The main degradation is trap 

movement at the oxide interface and can be observed in shifts 

within the threshold voltage and semiconductor related 

parameters and less on packaging related parameters. 

Fig. 2 HTGB experiment showing the soak times for both a +VGS and -VGS bias,

with ramping voltages between the two bias values [6].

Fig. 3 Static Vth measurements after HTGB tests in [7]. 

Fig. 4 Static RDSon measurements after HTGB tests in [7].

Fig. 5 Dependence of Vth shifts on stress bias for devices with T = 150°C and t

= 1 hour [8].

Fig. 6 Dependence of Vth shift on stress temperature for devices with VGS = 

15V, t = 1 hour [8].
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B. Switching Cycling

The HTGB experiments are focused on stressing the gate 

oxide and semiconductor itself through a high electric field on 

the gate terminal. This high electric field is held at a steady state, 

DC-bias. Under normal converter-oriented, operating 

conditions, the electric field is transient through the switching 

events. To stress the oxide and semiconductor under parameters 

closer to normal operating conditions, Switching Cycling has 

been introduced [10]. A variation on HTGB and hightemperature reverse bias (HTRB) testing [20] (not detailed in 

this work), Switching Cycling applies a DC-bias across the 

drain-source of the device while switching the device on/off 

continuously. 

The device under test (DUT) is placed in a clamped, 

inductive switching circuit and switched continuously. A high 

Drain-Source voltage (VDS) equal to 90% of the breakdown 

voltage is applied onto the device generating a high electric field 

similar to HTRB experiments. The DUT is then switched on and 

off continuously stressing the device primarily through the 

transient electric field generated by switching events. The ontime is set to 150 nanoseconds to decrease conduction losses and 

self-heating effects in the device. Fig. 7 shows the continuous 

switching nature of the Switching Cycling experiment in [10].

The electrical parameters that have shown most changes 

from Switching Cycling includes output characteristics, transfer 

characteristics (including Vth), Drain-Source leakage current, 

and Gate-Source leakage. Fig. 8-11 show these changes over 

time. The primary degradation can be seen on the semiconductor 

with the large shift in Vth, Drain-Source leakage current, and 

Gate-Source leakage current. Packaging-based degradation is 

minimal, as can be seen in the small shift in RDSon. 

Fig. 7 VDS (top) and IDS (bottom) waveforms from Switching Cycling as explain 

in [10].

Fig. 8 Changes in Drain-Source leakage current over time as a result of 

Switching Cycling.

Fig. 9 Changes in Gate-Source leakage over time as a result of Switching 

Cycling.

Fig. 10 Normalized Vth changes over time as a result of Switching Cycling.

Fig. 11 Normalized RDSon changes over time as a result of Switching Cycling.

III. PACKAGING FOCUSED LIFETIME TESTS

A. Power Cycling

Power Cycling experiments focus on the package 

degradation of a device exploiting the different coefficients in 

thermal expansion of the packaging layers. A large change in 

temperature (ΔTT) [21] causes these different layers to expand at 

different rates creating a mechanical stress throughout the

packaged device [11], [12], [14], [15]. The ΔTT is generated 

through the self-heating effects (conduction losses) from a 

Drain-Source current flowing through the DUT [14]. The case 

or device temperature is monitored and current flows through 

the device until a designated maximum temperature is reached. 

A constant current source and control device are used to turn the 

current on/off through the device and is described in more detail 

in [11]-[13], [22], [23]. In the off-state, the DUT operating 

temperature is monitored and the system is held off until the

lower bounded temperature is reached. The experimental rate of 

the heating and cooling periods can be designed to match 

different industry applications [11], [12] through current 

magnitude, and cooling systems. A general power cycling 

temperature profile is shown in Fig. 12, where ttoooo represents the 

time the current conducts through the device, and ttoooooo when the 

device is in the off-state. 
4

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Fig. 12 General temperature stress profile for Power Cycling.

This thermal profile applies a mechanical stress throughout 

the packaged device. The most common degradation through 

Power Cycling includes wire-bond lift-off, and solder 

degradation. Wire-bond lift-off can be best seen through a large 

step change in RDSon, [11]-[13], [22]. Solder degradation can be 

seen by incremental changes in RDSon [12],[14], as well as 

changes in thermal resistance (Zth) [11], [13], [14], [23]. While 

the temperature rise of the device is caused from the conduction 

losses through the device there is little degradation of the 

intrinsic nature of the semiconductor itself. Degradation 

depicting the changes in RDSon from wire-bond lift-off and VDS

from wire bond lift-off and solder degradation are shown in Fig. 

13 and Fig. 14.

Fig. 13 On-resistance evolution through accelerated test in [15].

Fig. 14 Measured on-state voltage drop and fitting curves for devices during 

power cycling tests in [24].

B. Thermal Cycling

Similar to Power Cycling, Thermal Cycling stresses the 

interconnections of packaging layers (solder joints, wire bonds, 

etc.) through the mismatch in the coefficients of thermal 

expansion [17], [24]. Unlike Power Cycling however, the ΔTT is

generated completely through external means such as a hot plate

or thermal shock chamber and not the conduction losses of the 

device [17]. As a result the Tave, Tmin, and Tmax can be controlled 

with more precision and used to excite different failure 

mechanisms. It has been shown in [24] that the chosen ΔTT range 

and Tave have a large effect on the degradation of the device. 

Fig. 15 shows a generic thermal cycling experimental profile 

including the rise and fall times, as well as the dwell/soak time 

at Tmax and Tmin.

The work conducted in [10] involved an experimental 

temperature profile that had a Tmin of -40°C, Tmax of 175°C and 

ΔTT of 215°C. The rise and fall times were 10 minutes each with 

both the high and low temperature dwell times set to 10 minutes. 

Fig. 16 and Fig. 17 show changes in the RDSon and Vth parameters.

Fig. 17 shows that the changes in Vth are minimal and Fig. 16

[10] shows a 44% RDSon change from its initial value after 2,000 

cycles. These results, along with those shown in [17], depict that 

Thermal Cycling is set to degrade the device package as opposed 

to the semiconductor device itself. 

Fig. 15 General Thermal Cycling temperature profile.

Fig. 16 Normalized changes of RDSon over time from Thermal Cycling [10].

Fig. 17 Changes in Vth over time from Thermal Cycling [10].
5

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IV. CONCLUSION

SiC power MOSFETs have demonstrated properties that can 

enhance power converter performance over traditional 

technologies. The reliability of SiC MOSFETs have remained in 

question and ALTs have only begun to show the results 

necessary to qualify the technology. Table I summarizesthe four 

test methods described in this work. It also shows the ALT main 

stress mechanism (package or semiconductor), the system-level 

parameter in which changes are seen, and a general length for 

failure to mature. These tests all show how a packaged 

semiconductor survives under extreme conditions that are much 

harsher than industry-standard, operating conditions. 

TABLE I

ACCELERATED LIFETIME EXPERIMENTS AND ASSOCIATED STRESS 

MECHANISMS

ALT Stress 

Mechanism

System 

Level 

Parameter

Time to Failure

HTGB Semiconductor VVtth 1000+ hours

Switching 

Cycling

Semiconductor VVtth 100 hours

Power 

Cycling

Package RRDDDD , ZZtth 100-1000+ hours

Thermal 

Cycling

Package RRDDDD 1000+ hours

ACKNOWLEDGMENT

Funding was provided by the U.S. Department of Energy 

Advanced Manufacturing Office through the Wide Bandgap 

Generation (WBGen) Fellowship at the Center for Power 

Electronics Systems (CPES) at Virginia Tech and through the 

Electric Drive Technologies Program within the Vehicle 

Technologies Office.

REFERENCES

[1] H. Di, J. Noppakunkajorn, and B. Sarlioglu, "Efficiency comparison of 

SiC and Si-based bidirectional DC-DC converters," in Transportation 

Electrification Conference and Expo (ITEC), 2013 IEEE, 2013, pp. 1-7.

[2] W. Gangyao, W. Fei, G. Magai, L. Yang, A. Huang, and M. Das, 

"Performance comparison of 1200V 100A SiC MOSFET and 1200V 

100A silicon IGBT," in Energy Conversion Congress and Exposition 

(ECCE), 2013 IEEE, 2013, pp. 3230-3234.

[3] L. D. Stevanovic, K. S. Matocha, P. A. Losee, J. S. Glaser, J. J. Nasadoski, 

and S. D. Arthur, "Recent advances in silicon carbide MOSFET power 

devices," in Applied Power Electronics Conference and Exposition 

(APEC), 2010 Twenty-Fifth Annual IEEE, 2010, pp. 401-407.

[4] L. C. Yu, G. T. Dunne, K. S. Matocha, K. P. Cheung, J. S. Suehle, and K. 

Sheng, "Reliability Issues of SiC MOSFETs: A Technology for HighTemperature Environments," IEEE Transactions on Device and 

Materials Reliability, vol. 10, pp. 418-426, 2010.

[5] A. J. Lelis, R. Green, D. B. Habersat, and M. El, "Basic Mechanisms of 

Threshold-Voltage Instability and Implications for Reliability Testing of 

SiC MOSFETs," IEEE Transactions on Electron Devices, vol. 62, pp. 

316-323, 2015.

[6] A. J. H. Lelis, D.; Green, R.; Ogunniyi, A.; Gurfinkel, M.; Suehle, J.; 

Goldsman, N., "Time Dependence of Bias-Stress-Induced SiC MOSFET 

Threshold-Voltage Instability Measurements," IEEE Transactions on 

Electron Devices, 2008.

[7] Z. Chen, Y. Yao, M. Danilovic, and D. Boroyevich, "Performance 

evaluation of SiC power MOSFETs for high-temperature applications," 

in 2012 15th International Power Electronics and Motion Control 

Conference (EPE/PEMC), 2012, pp. DS1a.8-1-DS1a.8-9.

[8] R. Green, A. Lelis, and D. Habersat, "Application of reliability test 

standards to SiC Power MOSFETs," in Reliability Physics Symposium 

(IRPS), 2011 IEEE International, 2011, pp. EX.2.1-EX.2.9.

[9] A. J. Lelis, R. Green, and D. B. Habersat, "SiC MOSFET reliability and 

implications for qualification testing," in 2017 IEEE International 

Reliability Physics Symposium (IRPS), 2017, pp. 2A-4.1-2A-4.4.

[10] J. P. Kozak, D. DeVoto, J. Major, and K. Ngo, "Trends in SiC MOSFET 

Threshold Voltage and ON-Resistance Measurements from Thermal 

Cycling and Electrical Switching Stresses," presented at the Conference 

on Integrated Power Electronics Systems (CIPS), Stuttgart, Germany, 

2018.

[11] L. R. GopiReddy, L. M. Tolbert, and B. Ozpineci, "Power Cycle Testing 

of Power Switches: A Literature Survey," IEEE Transactions on Power 

Electronics, vol. 30, pp. 2465-2473, 2015.

[12] C. Durand, M. Klingler, D. Coutellier, and H. Naceur, "Power Cycling 

Reliability of Power Module: A Survey," IEEE Transactions on Device 

and Materials Reliability, vol. 16, pp. 80-97, 2016.

[13] U. Scheuermann and S. Schuler, "Power cycling results for different 

control strategies," Microelectronics Reliability, vol. 50, pp. 1203-1209, 

2010/09/01/ 2010.

[14] U. M. Choi, F. Blaabjerg, and S. Jørgensen, "Power Cycling Test Methods 

for Reliability Assessment of Power Device Modules in Respect to 

Temperature Stress," IEEE Transactions on Power Electronics, vol. 33, 

pp. 2531-2551, 2018.

[15] N. Baker, S. Munk-Nielsen, and S. Bęczkowski, "Test setup for long term 

reliability investigation of Silicon Carbide MOSFETs," in 2013 15th 

European Conference on Power Electronics and Applications (EPE), 

2013, pp. 1-9.

[16] F. Mohn, C. Liu, and J. Schuderer, "Reliable Interconnection 

Technologies for High-Temperature Operation of SiC MOSFETs," in 

PCIM Europe 2017; International Exhibition and Conference for Power 

Electronics, Intelligent Motion, Renewable Energy and Energy 

Management, 2017, pp. 1-8.

[17] H. Cui, "Accelerated temperature cycle test and Coffin-Manson model for 

electronic packaging," in Annual Reliability and Maintainability 

Symposium, 2005. Proceedings., 2005, pp. 556-560.

[18] S. Yang, D. Xiang, A. Bryant, P. Mawby, L. Ran, and P. Tavner, 

"Condition Monitoring for Device Reliability in Power Electronic 

Converters: A Review," IEEE Transactions on Power Electronics, vol. 

25, pp. 2734-2752, 2010.

[19] T. C. Yang and K. C. Saraswat, "Effect of physical stress on the 

degradation of thin SiO<sub>2</sub> films under electrical stress," IEEE 

Transactions on Electron Devices, vol. 47, pp. 746-755, 2000.

[20] D. A. Gajewski, B. Hull, D. J. Lichtenwalner, S. H. Ryu, E. Bonelli, H. 

Mustain, et al., "SiC power device reliability," in 2016 IEEE International 

Integrated Reliability Workshop (IIRW), 2016, pp. 29-34.

[21] U. M. Choi, et al, "Advanced Accelerated Power Cycling Test for 

Reliability Investigation of Power Device Modules," IEEE Transactions 

on Power Electronics, vol. 31, pp. 8371-8386, 2016.

[22] A. Ibrahim, J. P. Ousten, R. Lallemand, and Z. Khatir, "Power Cycling 

Tests in High Temperature Conditions of SiC-MOSFET Power Modules 

and Ageing Assessment," in CIPS 2016; 9th International Conference on 

Integrated Power Electronics Systems, 2016, pp. 1-6.

[23] H. Luo, F. Iannuzzo, and F. Blaabjerg, "Solder layer degradation 

measurement for SiC-MOSFET Modules under accelerated power 

cycling conditions," presented at the 10th International Conference on 

Integrated Power Electronics Systems, Stuttgart, Germany, 2018.

[24] H. Luo, F. Iannuzzo, F. Blaabjerg, M. Turnaturi, and E. Mattiuzzo, 

"Aging precursors and degradation effects of SiC-MOSFET modules 

under highly accelerated power cycling conditions," in 2017 IEEE Energy 

Conversion Congress and Exposition (ECCE), 2017, pp. 2506-2511.