# Patent

## Title
Soft switching power electronic transformer

## Abstract

This patent document discloses power electronic transformers having a high-frequency link. An example apparatus include a transformer having a primary winding and a secondary winding, the transformer is configured to receive a primary power signal having a first frequency, a primary converter configured to selectively oscillate polarity of the primary windings with respect to the secondary windings at a second frequency, the second frequency substantially substantially higher than the first frequency, a secondary converter coupled to the secondary winding, the secondary converter configured to provide a load power signal using a high frequency power signal generated using the secondary winding. The secondary converter can be configured to reduce current flow in the primary winding when the polarity of the primary winding is switched, the reduced current follow is configured to reduce disturbances resulting from leakage inductance of the transformer.

## Background
PRIORITY AND RELATED APPLICATIONS
This document claims the benefit under 35 U.S.C. Section 119(e), to U.S. Provisional Patent Application Ser. No. 61/224,790, filed on Jul. 10, 2009, and is incorporated herein by reference in its entirety.


STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT UNDER 37 C.F.R. 401.14(a)(f)(4)
This invention was made with government support under N00014-07-1-0463 and N00014-07-1-0968 awarded by the Office of Naval Research (ONR). The government has certain rights in the invention.


TECHNICAL FIELD
This patent document pertains generally to electronic transformers. More particularly, but not by way of limitation, this patent document pertains to methods and apparatus for power electronic transformers including a high-frequency AC-AC link for both AC and DC power conversion.
BACKGROUND
A transformer can be used to change and transmit electric power from one voltage level to another voltage level. It can also maintain isolation between two voltage level circuitry. Typically, the transformer is one of the heaviest, bulkiest and most expensive parts in a transmission and distribution system. The large size of the transformer is due, in part, to the low frequency of operation. Power density increases as the operating frequency of the transformer increases, resulting in a smaller transformer size and weight. To change operating frequency from a Hz level to a kHz level, power electronics can be used. Power electronics in combination with reduced sized, high-frequency transformers is known as power electronic transformers.
OVERVIEW
The present inventors have recognized an opportunity to replace the bulky, expensive, low frequency transformer with a high-frequency power electronic transformer having a low number of semiconductor switches and/or no DC link. In the disclosed topologies, alternate sets of mutually coupled primary windings can be switched mutually exclusively, with reduced switch requirements. Additionally, no DC link need be included. Other features of the disclosed topologies include one or more of: three-phase high-frequency transformer with multiple windings; mutually exclusive switching of coupled-primary windings to generate high-frequency waveform; and direct AC-AC power conversion with no intermediate stage or storage or virtual DC link.
Advantageously, the disclosed power electronic transformers provide high-frequency AC-AC power conversion, allowing for reduction in size and weight relative to conventional transformers, electronic tap changing or controllable input power factor.
These and other embodiments, advantages, and aspects of the present power electronic transformers will be set forth in part in following Detailed Description. This Overview is intended to provide some examples of the subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the present invention. The Detailed Description is included to provide further information about the present patent application.



BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings, like numerals can be used to describe similar components throughout the several views. Like numerals having different letter suffixes can be used to represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
FIG. 1 shows power electronic transformer in a power transfer system according to one embodiment of the present subject matter.
FIG. 2 shows a three-phase (3Ø) push-pull topology 200 for a power electronic transformer (PET) according to one embodiment of the present subject matter.
FIG. 3 illustrates generally a flowchart of a method 300 to control a push-pull PET transformer according to one embodiment of the present subject matter.
FIGS. 4A and 4B show space vectors used for a control method according to one embodiment if the present subject matter.
FIG. 5 shows converter switching pulses for one cycle of a PET according to one embodiment of the present subject matter.
FIG. 6A shows a DC-DC converter circuit using two H-bridge converters connected to each other through a transformer according to one embodiment of the present subject matter.
FIG. 6B shows DC-DC converter switching pulses and circuit measurements according to one embodiment of the present subject matter.
FIG. 7 shows a PET topology for a single phase AC-DC system according to one embodiment of the present subject matter.
FIG. 8A shows a 3Ø PET according to one embodiment of the present subject matter.
FIG. 8B shows a waveform associated with a 3Ø PET according to one embodiment of the present subject matter.
FIG. 9 shows a single phase PET topology according to one embodiment of the present subject matter.
FIG. 10 shows a 3Ø AC-DC PET push-pull topology according to one embodiment of the present subject matter.
FIG. 11 shows a vector diagram illustrating the six sectors associated with the switching states of a two-level inverter according to one embodiment of the present subject matter.
FIG. 12 shows a switching interval Ts where S1 of a primary converter is ON during the first half of the switching cycle and S2 is ON during the second half of the switching cycle for a 3Ø AC-DC PET push-pull topology according to one embodiment of the present subject matter.



DETAILED DESCRIPTION
In this patent document, power electronic transformer topologies and control strategies are described. It has been found that by using power electronic transformers (PETs), dramatic reductions in size and/or weight can be achieved. For example, a power electronic transformer having a rating of 140 kV, 20 kHz and 20 A can weigh about 450 lbs. In contrast, a conventional transformer having a rating of 100 kV, 60 Hz and 20 A can weigh about 35 tons. A high-frequency waveform at the primary windings (three windings) can be generated using H-Bridge topology (three H-bridges).
In various embodiments, the topologies and control strategies use a single high frequency link that allows bi-directional power flow, adjustable frequency and voltage magnitude regeneration, input power factor correction, electrical isolation, high voltage transfer, and high power density resulting in reduced transformer size. In various embodiments, control strategy methods associated with the various PET topologies allow elimination of clamp circuits on the primary, the secondary or both the primary and secondary sides of the PET. Various control methods discussed also reduce or substantially eliminate disturbances associated with leakage inductance, and reduce or substantially eliminate switching losses associated with various PET topologies. These topologies also provide single-stage power conversion eliminating DC coupling and DC devices including high voltage DC capacitors that can be unreliable.
FIG. 1 shows power electronic transformer in a power transfer system according to one embodiment of the present subject matter. The system 100 includes a first power source 101, a primary converter 102, a high frequency transformer 103, a secondary converter 104, and a remote device 105. In various embodiments, the first power source 101 is an electrical utility grid system, or at least a portion of such a system. The remote device 105 can be an energy-consuming device such as a motor, or a electric or hybrid vehicle receiving a charge. In some embodiments, the remote device 105 is a second power source such as a wind turbine generator, photovoltaic cell, or a power storage device such as a battery or a capacitor. In some embodiments, the remote device 105 can consume energy and source energy. It is understood that in various embodiments, the remote device can include other energy consuming devices and power source devices without departing from the scope of the present subject matter including, but not limited to, single-phase devices, 3-phase devices and DC devices.
FIG. 2 shows a three-phase (3Ø) push-pull topology 200 for a power electronic transformer (PET) according to one embodiment of the present subject matter. The PET includes a high frequency transformer (HFT) 206 with a set of primary windings, a1, a2, b1, b2, c1, c2, coupled to legs of a three-phase device through a primary converter 202 including two switches S1, S2. The HFT 206, as also includes a core and a set of secondary windings A, B, C. The secondary windings couple to a matrix converter 204. The PET receives a 3Ø low frequency power signal at the primary windings a1, a2, b1, b2, c1, c2, and uses the two switches S1, S2, of the primary converter 202 to produce a high frequency waveform on the primary windings of the high frequency transformer. A secondary high frequency waveform is generated on the by magnetically coupling the primary windings to secondary windings using the core of the HFT 206. The PET modulates the secondary high frequency waveform using the matrix converter 204 to a desired 3Ø waveform u, v, w for use by the load 205. The matrix converter 204 modulates the secondary high frequency waveform according to the needs of the load. Frequency and voltage of the modulated waveform can be selected to match the operating parameters of the load. For example, voltage can be selected using a ratio of primary turns to secondary turns of the corresponding windings of the high frequency transformer of the PET.
In some embodiments, each switches S1 and S2 are implemented using a single two-quadrant semiconductor switch. The switches S1 and S2 can be switched opposite each other at a desired high frequency. For example, switches S1 and S2 can be switched in a complementary fashion with a 50% duty cycle such that S1 is closed or conducting when S2 is open or non-conducting and vice versa. It is understood that other duty cycles are possible for S1 and S2 without departing from the scope of the present subject matter. The illustrated PET 200 includes two primary windings for each phase of the transformer. For example, primary windings a1 and a2 are associated with a first phase of the transformer, primary windings b1 and b2 are associated with a second phase of the transformer, and primary windings c1 and c2 are associated with a third phase of the transformer. A first switch S1 couples together a first terminal of a first winding a1, b1, c1, of each phase for a first portion of a switching cycle and also decouples a first terminal of the second winding a2, b2, c2, of each phase. During a second portion of the switching cycle, a second switch S2 couples together the first terminal of a second winding a2, b2, c2, of each phase and also decouples the first terminal of the first winding a1, b1, c1, of each phase. The first a1, b1, c1, and second a2, b2, c2 winding of each phase each have a second terminal coupled to a phase va, vb, vc of the source 201 and each phase pair of windings are oriented with opposite polarity with respect to their corresponding secondary winding.
The transformer 200 includes some leakage inductance (not shown) on both the primary and secondary windings. Leakage inductance can cause disturbances such as spikes in voltage and current when the winding is connected and disconnected from a circuit and current is flowing in the winding or the circuit at the time of the switch event. Resistor, capacitor and diode (RCD) clamp circuits can be used to dissipate these disturbances. Because the push-pull topology 200 couples and decouples two primary windings, disturbances caused by leakage inductance is dealt with in the primary windings separately from the secondary winding, thus RCD clamp circuits can be coupled to both the primary and secondary windings. In situations where the power source is a high voltage source, it is impractical to use RCDs to reduce the effects of leakage inductance in the primary windings. RCDs sink energy and can reduce efficiency of a circuit, even more so with high voltage circuits. RCDs require the capacitor of the RCD to be maintained at a voltage twice the magnitude of the circuit voltage. The higher voltages required to maintain the voltage of the RCD capacitors require the use of switches having higher voltage ratings. Control and manufacturing of power semiconductor switches at high voltage is technically challenging.
A control strategy for the illustrated push-pull PET of FIG. 2, according to one embodiment of the present subject matter, can eliminate RCDs for controlling disturbances caused by leakage inductance of the primary windings. Leakage inductance disturbances can be eliminated when switching occurs with no current flowing in a winding. This can be called zero-current switching (ZCS). In addition to eliminating the leakage inductance effect, ZCS can also significantly reduce switching losses, such as thermal losses, associated with operating the primary winding switches S1, S2. In various examples, the current in ZCS can be zero or a non-zero small value.
In various embodiments, the topology 200 includes a matrix converter 204 coupled to the secondary windings A, B, C. The matrix converter 204 transforms the high frequency output waveform of the transformer to a load waveform having selectable voltage and frequency. According to various embodiments, a method of operating the matrix converter 204 includes applying a zero vector to the output of the transformer to cause the primary winding currents to go to zero. When the primary winding currents are zero, S1 and S2 can be switched without producing switching losses or disturbances associated with the leakage inductance of the primary windings.
FIG. 3 illustrates generally a flowchart of a method 300 to control a push-pull PET transformer according to one embodiment of the present subject matter. The method includes: at 301, receiving a low frequency power signal at a primary winding; at 302, switching a polarity of the primary winding at a high frequency; at 303, generating a secondary waveform using a coupling between the primary winding and a secondary winding; and at 304, converting the secondary waveform to a load waveform having a predetermined frequency and voltage.
The method of FIG. 3 can be applied to the embodiment illustrated in FIG. 2. Input line to neutral voltages can be given by,



  
    
      v
      
        an
        i
      
    
    =
    
      
        V
        i
      
      ⁢
      
        cos
        ⁡
        
          (
          
            
              ω
              i
            
            ⁢
            t
          
          )
        
      
    
  




  
    
      v
      
        bn
        i
      
    
    =
    
      
        V
        i
      
      ⁢
      
        cos
        ⁡
        
          (
          
            
              
                ω
                i
              
              ⁢
              t
            
            -
            
              
                2
                ⁢
                π
              
              3
            
          
          )
        
      
    
  




  
    
      
        v
        
          cn
          i
        
      
      =
      
        
          V
          i
        
        ⁢
        
          cos
          ⁡
          
            (
            
              
                
                  ω
                  i
                
                ⁢
                t
              
              +
              
                
                  2
                  ⁢
                  π
                
                3
              
            
            )
          
        
      
    
    ,
  



where, vani, vbni, vcni are the phase voltages va, vb, vc on the primary side of the transformer measured between their respective voltage source and point ni, Vi is the peak voltage of the 3Ø power source, and ωi is the frequency of the 3Ø power source in radians/second. Secondary side voltages can be given by,

νAN=(−1)kνani 

νBN=(−1)kνbni 

νCN=(−1)kνcni . . . k=0,1,

where νAN, νBN, νCN are the phase voltages on the secondary side of the high frequency transformer measured across each secondary winding and point N, k=0 when S1 is on, and k=1 when S2 is on.

In some embodiments, a matrix converter can include 27 unique switching states. Six of these switching states generate synchronously rotating space vectors. These vectors result in zero common-mode voltage at the load terminals. An output voltage space vector {right arrow over (V)}0 can be defined by,




  
    
      V
      →
    
    o
  
  =
  
    
      υ
      
        un
        o
      
    
    +
    
      
        υ
        
          vn
          o
        
      
      ⁢
      
        e
        
          j2π
          3
        
      
    
    +
    
      
        υ
        
          wn
          o
        
      
      ⁢
      
        e
        
          
            -
            j2π
          
          3
        
      
    
  




where νun0 is the voltage measured on leg u with reference to point n0.

Depending on the direction of rotation, the synchronously rotating vectors can be further divided into two groups, counter-clockwise (ccw) and clockwise (cw). The three ccw rotating vectors {right arrow over (V)}1, {right arrow over (V)}3, and {right arrow over (V)}5 marked in FIG. 4A are obtained when k=0 and (uvw) are connected to (ABC), (CAB) and (BCA) respectively where, u, v, w, A, B, C are points marked in FIG. 2. When k=1, vectors {right arrow over (V)}2, {right arrow over (V)}4 and {right arrow over (V)}6 are obtained. Similarly, the space vectors rotating in clockwise direction are shown in FIG. 4B. Thus, every switching cycle, the average output voltage vector can be synthesized using these six vectors. These six vectors divide the complex plane into six symmetrical sectors. At any instant of time, the reference voltage vector will be in a particular sector. The reference voltage vector is given by,





  
    
      V
      _
    
    ref
  
  =
  
    
      
        V
        _
      
      sv
    
    =
    
      
        
          υ
          _
        
        
          un
          o
        
      
      +
      
        
          
            υ
            _
          
          
            vn
            o
          
        
        ⁢
        
          e
          
            j2π
            3
          
        
      
      +
      
        
          
            υ
            _
          
          
            wn
            o
          
        
        ⁢
        
          e
          
            
              -
              j2π
            
            3
          
        
      
    
  




Where the average voltage of each load phase u, v, w can be,




  
    
      
        υ
        _
      
      
        un
        o
      
    
    =
    
      
        V
        o
      
      ⁢
      
        cos
        ⁡
        
          (
          
            
              
                ω
                o
              
              ⁢
              t
            
            +
            φ
          
          )
        
      
    
  




  
    
      
        υ
        _
      
      
        vn
        o
      
    
    =
    
      
        V
        o
      
      ⁢
      
        cos
        ⁡
        
          (
          
            
              
                ω
                o
              
              ⁢
              t
            
            +
            φ
            -
            
              
                2
                ⁢
                π
              
              3
            
          
          )
        
      
    
  




  
    
      
        
          υ
          _
        
        
          wn
          o
        
      
      =
      
        
          V
          o
        
        ⁢
        
          cos
          ⁡
          
            (
            
              
                
                  ω
                  o
                
                ⁢
                t
              
              +
              φ
              +
              
                
                  2
                  ⁢
                  π
                
                3
              
            
            )
          
        
      
    
    ,
  



where V0 is the peak of the average output voltage of the load waveform and ωo is the frequency of the load waveform u, v, w.

This reference voltage vector Vref is generated on an average over one switching cycle Ts using the two vectors forming that sector. For example, if Vref lies in the first sector, vectors {right arrow over (V)}1 and {right arrow over (V)}2 are used, such that Vref=d1{right arrow over (V)}1+d2{right arrow over (V)}2, where d1 and d2 are the fraction of time for which vectors {right arrow over (V)}1 and {right arrow over (V)}2 are applied respectively. Mathematically, d1 and d2 are given by,



  
    
      d
      1
    
    =
    
      m
      ⁢
      
        2
        
          3
        
      
      ⁢
      
        sin
        ⁡
        
          (
          
            
              π
              3
            
            -
            α
          
          )
        
      
    
  




  
    
      d
      2
    
    =
    
      m
      ⁢
      
        2
        
          3
        
      
      ⁢
      
        sin
        ⁡
        
          (
          α
          )
        
      
    
  




  
    Where
    ,
    
      

    
    ⁢
    
      m
      =
      
        
          V
          o
        
        
          V
          i
        
      
    
  




  
    
      d
      1
    
    ,
    
      
        d
        2
      
      <=
      0.5
    
  



The values of d1 and d2 are constrained to 0.5 because {right arrow over (V)}1 and {right arrow over (V)}2 are available for a maximum of 50% of the switching cycle Ts. Hence, if only the two adjacent space vectors are used, the maximum modulation index, m is limited to 0.5. Three adjacent voltage vectors can be used to obtain a modulation index of 0.75 at the cost of additional switching.

The switching pulses for one cycle according to one embodiment of the present subject matter are shown in FIG. 5. The duty ratios d1 and d2 are compared with a triangular carrier waveform, Vtri to generate pulses pV1 and pV2. Vtri can have a peak value of 1 and its frequency is two times the frequency of S1 and S2. In sector one, {right arrow over (V)}1 is available when S1 is on, therefore, pV1 is high in the first half of the cycle and pV2 is high in the second half of the cycle. Zero vectors are applied in the remaining time of the cycle. pz is the switching pulse for the zero vector. In each half cycle, the active vectors are buffered by zero vectors on either side. In one switching cycle, ccw vectors are used, and in the following cycle, cw vectors are used to synthesize the average output voltage. As ccw and cw rotating vectors are used for an equal duration of time, unity power factor is obtained on the input side of the PET.
FIG. 6A shows a DC-DC circuit using two H-bridge converters connected to each other through a transformer. The magnetizing current of the transformer can be neglected for analysis, therefore, the transformer is approximated by its leakage inductance, L. The leakage inductance L can be used to transfer power between the two DC voltage sources, Va and Vb. The switches Sa1 and S′a1 of a first (or primary) converter 602 can be switched at a constant frequency, fs with 50% duty ratio, in a complementary fashion. The switches of a second (or secondary) converter 604 can be switched to produce an alternating voltage pulse having a duty ratio d. The switch pulses of the first converter 602 and the second converter 604 can be phase shifted from each other by time




  δ
  ⁢
  
    
      T
      s
    
    2
  




as shown in FIG. 6B. Power transfer between the two DC voltage sources can be controlled using, among other things, the phase shift between the pulses of the first converter 602 and the second converter 604. FIG. 6B, also shows the voltage, V1 and current I1 waveforms across the leakage inductance L of the DC-DC converter. In the illustrated example, the inductor current I1 goes to zero every half cycle generating an average voltage across the leakage inductance L of about zero per half cycle. Mathematically, the average voltage across the leakage inductance L over a half cycle period Ts/2 can be given by:





  
    
      <
      
        V
        L
      
      ⁢
      
        >
        
          
            T
            s
          
          2
        
      
    
    =
    
      
        
          V
          a
        
        ⁡
        
          (
          
            
              
                T
                s
              
              2
            
            -
            
              d
              ⁢
              
                
                  T
                  s
                
                2
              
            
          
          )
        
      
      +
      
        
          (
          
            
              V
              a
            
            -
            
              V
              b
            
          
          )
        
        ⁢
        d
        ⁢
        
          
            T
            s
          
          2
        
      
    
  
  ,




where Va is the voltage of one DC source, Vb is the voltage of a second DC source, Ts is the period of the switching frequency fs of Sa1 and S′a1. When <VL> is zero, the current through the primary winding can go to zero providing an opportunity to switch the primary converter without causing primary winding disturbances.

Solving for <VL>=0 gives





  
    d
    =
    
      
        V
        a
      
      
        V
        b
      
    
  
  ,




which gives the duty cycle of the voltage pulse and thus the switching schedule of the secondary switches.

For zero current switching, t3 is greater than zero, and the value of δ is limited by,




  0
  ≤
  δ
  ≤
  
    
      (
      
        1
        -
        d
      
      )
    
    ⁢
    
      
        1
        2
      
      .
    
  




Mathematically, the other values of the example of FIG. 6B are given by,




  
    
      t
      1
    
    =
    
      
        1
        4
      
      ⁢
      
        (
        
          
            T
            s
          
          +
          
            2
            ⁢
            δ
            ⁢
            
              
            
            ⁢
            
              T
              s
            
          
          -
          
            dT
            s
          
        
        )
      
    
  




  
    
      t
      2
    
    =
    
      
        dT
        s
      
      2
    
  




  
    
      t
      3
    
    =
    
      
        
          T
          s
        
        2
      
      -
      
        t
        ⁢
        
          
        
        ⁢
        1
      
      -
      
        t
        ⁢
        
          
        
        ⁢
        2
      
    
  




  
    
      I
      0
    
    =
    
      
        I
        3
      
      =
      
        
          I
          6
        
        =
        0
      
    
  




  
    
      I
      1
    
    =
    
      
        I
        0
      
      +
      
        
          
            V
            a
          
          L
        
        ⁢
        
          t
          1
        
      
    
  




  
    
      I
      2
    
    =
    
      
        I
        1
      
      +
      
        
          
            (
            
              
                V
                a
              
              -
              
                V
                b
              
            
            )
          
          L
        
        ⁢
        
          t
          2
        
      
    
  




  
    
      I
      3
    
    =
    
      
        I
        2
      
      +
      
        
          
            V
            a
          
          L
        
        ⁢
        
          t
          3
        
      
    
  




  
    
      I
      4
    
    =
    
      -
      
        I
        1
      
    
  




  
    
      I
      5
    
    =
    
      -
      
        I
        2
      
    
  




  
    
      
        P
        b
      
      =
      
        
          (
          
            
              V
              b
            
            
              T
              s
            
          
          )
        
        ⁢
        
          (
          
            
              
                
                  I
                  1
                
                +
                
                  I
                  2
                
              
              2
            
            +
            
              
                
                  -
                  
                    I
                    4
                  
                
                -
                
                  I
                  5
                
              
              2
            
          
          )
        
        ⁢
        
          t
          2
        
      
    
    ,
  



Where Pb represents the power transferred from the first converter to the second converter. The power transferred from the second converter to the first converter is given by,




  
    P
    ab
  
  =
  
    d
    ⁢
    
      
    
    ⁢
    δ
    ⁢
    
      
        
          
            V
            a
          
          ⁢
          
            V
            b
          
        
        
          2
          ⁢
          
            Lf
            s
          
        
      
      .
    
  




The power transferred between the two converters is a function of the duty ratio d of the second converter switches, the offset between the switching pulses of the first and second converters δ, the switching frequency fs, and the voltages of the first and second voltage sources Va and Vb.
FIG. 7 shows a PET topology for a single phase AC-DC system. In this topology, AC source 701 compares to the DC source connected to first converter 602 in the topology of FIG. 6A. AC source 701 has magnitude,

{circumflex over (V)}a cos(ωt).

where {circumflex over (V)}a is the peak voltage of the primary side voltage source and ω is the frequency of the primary side voltage source in radians per second.

Switches Sa1 and S′a1 of the first converter 702 can be switched at a constant frequency and at 50% duty ratio in a complementary fashion. The switches Sb1 and S′b1 of the second converter 704 can be pulse width modulated such that a duty ratio, d(t) of the switches is given by,




  
    d
    ⁡
    
      (
      t
      )
    
  
  =
  
    
      
        
          
            V
            ^
          
          a
        
        ⁢
        
          cos
          ⁡
          
            (
            
              ω
              ⁢
              
                
              
              ⁢
              t
            
            )
          
        
      
      Vdc
    
    .
  




In various examples, the switching frequency fs can be much higher than the input voltage frequency ω/2π. During one switching interval, the ac-dc converter can be approximated as a dc-dc converter with Va(t)={circumflex over (V)}a cos(ωt) and Vb=Vdc. Soft switching, or zero current switching, in the first converter can be accomplished while the inductor current is at zero at the end of each half cycle. An average voltage of zero across the inductor per half cycle can cause the inductor current to go to zero. The value of the duty cycle d can be determined by these constraints such that,



  
    
      
        〈
        
          V
          L
        
        〉
      
      
        
          T
          s
        
        2
      
    
    =
    
      
        
          
            V
            ^
          
          a
        
        ⁢
        
          cos
          ⁡
          
            (
            
              ω
              ⁢
              
                
              
              ⁢
              t
            
            )
          
        
        ⁢
        
          (
          
            
              
                T
                2
              
              2
            
            -
            
              
                d
                ⁡
                
                  (
                  t
                  )
                
              
              ⁢
              
                
                  T
                  s
                
                2
              
            
          
          )
        
      
      +
      
        
          (
          
            
              
                
                  V
                  ^
                
                a
              
              ⁢
              
                cos
                ⁡
                
                  (
                  
                    ω
                    ⁢
                    
                      
                    
                    ⁢
                    t
                  
                  )
                
              
            
            -
            
              V
              
                d
                ⁢
                
                  
                
                ⁢
                c
              
            
          
          )
        
        ⁢
        
          d
          ⁡
          
            (
            t
            )
          
        
        ⁢
        
          
            T
            s
          
          2
        
      
    
  




  
    
      d
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          
            V
            ^
          
          a
        
        ⁢
        
          cos
          ⁡
          
            (
            
              ω
              ⁢
              
                
              
              ⁢
              t
            
            )
          
        
      
      
        V
        
          d
          ⁢
          
            
          
          ⁢
          c
        
      
    
  



where <VL> equals the voltage across the leakage inductance of the high frequency transformer 703.

Accordingly, the phase shift between the switching pulses is given by,



  
    0
    ≤
    δ
    ≤
    
      
        1
        2
      
      ⁢
      
        (
        
          1
          -
          
            
              d
              ⁡
              
                (
                t
                )
              
            
            max
          
        
        )
      
    
  




  
    0
    ≤
    δ
    ≤
    
      
        1
        2
      
      ⁢
      
        (
        
          1
          -
          
            
              
                V
                ^
              
              a
            
            
              V
              
                d
                ⁢
                
                  
                
                ⁢
                c
              
            
          
        
        )
      
    
  



The phase shift δ can be a constant to achieve unity power factor at the AC source. With δ fixed, the power transferred can be calculated by integrating the power transferred per switching cycle over one period of the low frequency input waveform.




  
    
      P
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        d
        ⁡
        
          (
          t
          )
        
      
      ⁢
      δ
      ⁢
      
        
          
            V
            
              d
              ⁢
              
                
              
              ⁢
              c
            
          
          ⁢
          
            
              V
              ^
            
            a
          
          ⁢
          
            cos
            ⁡
            
              (
              
                ω
                ⁢
                
                  
                
                ⁢
                t
              
              )
            
          
        
        
          2
          ⁢
          
            Lf
            s
          
        
      
    
  




  
    
      P
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          δ
          ⁢
          
            
          
          ⁢
          
            
              V
              ^
            
            a
            2
          
        
        
          2
          ⁢
          
            Lf
            s
          
        
      
      ⁢
      
        
          cos
          2
        
        ⁡
        
          (
          
            ω
            ⁢
            
              
            
            ⁢
            t
          
          )
        
      
    
  




  
    
      P
      avg
    
    =
    
      
        1
        
          2
          ⁢
          π
        
      
      ⁢
      
        
          ∫
          0
          
            2
            ⁢
            π
          
        
        ⁢
        
          
            P
            ⁡
            
              (
              
                ω
                ⁢
                
                  
                
                ⁢
                t
              
              )
            
          
          ⁢
          
            d
            
              (
              
                ω
                ⁢
                
                  
                
                ⁢
                t
              
              )
            
          
        
      
    
  




  
    
      P
      avg
    
    =
    
      
        δ
        ⁢
        
          
        
        ⁢
        
          
            V
            ^
          
          a
          2
        
      
      
        4
        ⁢
        
          Lf
          s
        
      
    
  



The average power transferred between converter 702 and converter 704 is a function of the δ, V^a, switching frequency fs, and leakage inductance L. A power balance equation for the system of FIG. 7 can be,

P(t)=Va(t)Ia(t)=VdcIdc 

It follows then that the average current in a switching interval can be equal and given by,




  
    
      
        I
        a
      
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        1
        
          
            
              V
              ^
            
            a
          
          ⁢
          
            cos
            ⁡
            
              (
              
                ω
                ⁢
                
                  
                
                ⁢
                t
              
              )
            
          
        
      
      ⁢
      
        
          δ
          ⁢
          
            
          
          ⁢
          
            
              V
              ^
            
            a
            2
          
        
        
          2
          ⁢
          
            Lf
            s
          
        
      
      ⁢
      
        
          cos
          2
        
        ⁡
        
          (
          
            ω
            ⁢
            
              
            
            ⁢
            t
          
          )
        
      
    
  




  
    
      
        I
        a
      
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          δ
          ⁢
          
            
          
          ⁢
          
            
              V
              ^
            
            a
          
        
        
          2
          ⁢
          
            Lf
            s
          
        
      
      ⁢
      
        
          cos
          ⁡
          
            (
            
              ω
              ⁢
              
                
              
              ⁢
              t
            
            )
          
        
        .
      
    
  



This current is in phase with the voltage Va, thus, providing unity power factor.

The AC to DC PET topology of FIG. 7 can be extended to a three-phase PET topology as illustrated in FIG. 8A. The topology uses the leakage inductance L to transfer power bi-directionally between the three-phase primary side 802 of the PET and the DC secondary side 804 of the PET. The DC secondary side 804, also referred to as the secondary converter, can operate on the same principle as that of the single phase topology described above with reference to FIG. 7.
The primary side converter 802 has three legs. An analogy between the present topology and that of FIG. 7 can be made such that control of the three phase topology is a combination of different single phase topologies. For example, when switches SaA and SaB are open, only phase vb and vc can be connected connected to the primary winding of the HFT 803. In a first portion of a switching period, switches SbA and ScB can be closed and during a second portion of the switching period switches ScA and SbB can be closed resulting in the first third of the waveform of FIG. 8B. In such a situation, the primary converter 802 of the three-phase topology is analogous to the single phase topology of FIG. 7 with only two legs of the converter coupled to the line-to-line primary power signal. Control of the secondary converter 804 is identical to the single phase embodiment described above except each third of the waveform of FIG. 8B represents a switching cycle. The second third of the waveform results from switches SaA and ScB being closed during a first portion and switches ScA and SaB being closed during a second portion. The last third of the waveform results from switches SaA and SbB being closed during a first portion and switches SbA and SaB being closed during a second portion.
FIG. 9 shows a single phase PET topology according to one embodiment of the present subject matter. Unlike the topology of FIG. 7, in which the primary side converter uses a full bridge, (four switches), the topology of FIG. 9 uses a push pull configuration including a primary converter 902 having two switches S1 and S2 and a high frequency transformer 903 having two primary windings (shown on the left side). The primary converter 902 switches are switched at a high frequency in a complementary fashion with a 50% duty ratio to provide a high frequency waveform on the primary windings of the transformer 903. The topology on the secondary side of the high frequency transformer 903 is the same as discussed above with respect to FIG. 7. As a result, even though the single phase push-pull topology of FIG. 9 introduces the potential for primary winding leakage inductance disturbances independent of the secondary winding, the control of the second converter, as discussed above, provides zero switching current of the two primary converter switches. The topology of FIG. 9 uses less primary converter switches than the topology of FIG. 7 but uses an additional primary winding.
The topology of FIG. 9 can be replicated two times to form a 3Ø push pull topology. In such an embodiment, the primary converters includes six switches, the secondary converter includes twelve switches, and the operation of the switches can be applied directly from that discussed above. FIG. 10 shows a 3Ø AC-DC PET push-pull topology according to one embodiment of the present subject matter. The topology is also an extension of the single-phase push-pull topology of FIG. 9, but continues to use only two primary converter switches and a two-level inverter for the secondary converter. A PET transformer according to this topology can be used for, among other things, power transfer and conversion between a three phase AC system and a DC system. The topology includes the primary converter 1002, a high frequency link 1003 including three, three-winding high frequency transformers, and secondary converter 1004 including the two-level inverter. In various embodiments, the topology and associated control scheme provide soft switching of the primary converter 1002 for varying load conditions, power factor correction at the primary input Va, Vb, Vc, bi-direction power flow, and simplified control due to linear dependence of power flow on the available control variables. The topology is adaptable to a number of applications that include a DC link between a device and a power distribution system including, but not limited to, wind power generation, motors, batteries, photovoltaic cells, storage capacitors, or combinations thereof.
The two level inverter is switched using Space-Vector-Modulation techniques to transfer power between the AC and DC sides. Three phase voltage can be generated at the output side from the dc voltage, Vdc. DC to AC power generation has been studied extensively in literature, hence the following analysis describes only the 3Ø AC-DC PET topology.
In various embodiments, switches S1 and S2 of FIG. 10 are switched at a constant frequency and 50% duty ratio in a complementary fashion.
Mathematically, balanced low frequency three phase AC voltages can be given by,



  
    
      
        V
        a
      
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          V
          ^
        
        
          p
          ⁢
          
            
          
          ⁢
          k
        
      
      ⁢
      
        cos
        ⁡
        
          (
          
            ω
            ⁢
            
              
            
            ⁢
            t
          
          )
        
      
    
  




  
    
      
        V
        b
      
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          V
          ^
        
        
          p
          ⁢
          
            
          
          ⁢
          k
        
      
      ⁢
      
        cos
        ⁡
        
          (
          
            
              ω
              ⁢
              
                
              
              ⁢
              t
            
            -
            
              
                2
                ⁢
                π
              
              3
            
          
          )
        
      
    
  




  
    
      
        V
        c
      
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          V
          ^
        
        
          p
          ⁢
          
            
          
          ⁢
          k
        
      
      ⁢
      
        cos
        ⁡
        
          (
          
            
              ω
              ⁢
              
                
              
              ⁢
              t
            
            +
            
              
                2
                ⁢
                π
              
              3
            
          
          )
        
      
    
  



where Vpk is the peak voltage of the AC source.

A primary switching interval, Ts can be divided into two halves, one half when S1 is ON and the other half when S2 is ON. When S1 is ON, a primary voltage space vector {right arrow over (V)}sv(t) is given by,





  
    
      
        V
        →
      
      sv
    
    ⁡
    
      (
      t
      )
    
  
  =
  
    
      
        V
        a
      
      ⁡
      
        (
        t
        )
      
    
    +
    
      
        
          V
          b
        
        ⁡
        
          (
          t
          )
        
      
      ⁢
      
        e
        
          j
          ⁢
          
            
              2
              ⁢
              π
            
            3
          
        
      
    
    +
    
      
        
          V
          c
        
        ⁡
        
          (
          t
          )
        
      
      ⁢
      
        e
        
          j
          ⁢
          
            
              4
              ⁢
              π
            
            3
          
        
      
    
  




When S2 is ON, the primary voltage space vector is 180 degrees out of phase of {right arrow over (V)}sv(t). A space vector can provide a phase relationship of a voltage waveform.

Thus, the primary voltage space vector is a vector that oscillates 180 degrees as it rotates. The oscillation frequency is determined by the switching frequency of S1 and S2 of the primary converter and the rotation is determined by the frequency of the AC voltage source coupled to the primary converter.
The secondary converter control scheme seeks to provide soft switching of the primary converter switches and pulse width modulation of the secondary winding voltage waveform to transfer power between the AC source coupled to the primary converter and the DC source coupled to the secondary converter. An secondary voltage space vector of the two level inverter can be given by

{right arrow over (V)}o=VA+VBej2π/3+Vce−j2π/3. 

A space vector can also be used to synthesize a waveform from an inverter such as the two-level inverter 1004 of FIG. 10. A switching cycle of the two level inverter 1004 can be represented as a space vector graph having six sectors. Each sector is bounded by a switch state of the three complementary switch pairs of the two level inverter. For example, if switch Sa and Sb are ON and switch Sc is OFF, the voltage across the DC source of FIG. 10 can be given by,





  
    
      
        
          
            V
            ⇀
          
          o
        
        =
        
        ⁢
        
          
            V
            
              d
              ⁢
              
                
              
              ⁢
              c
            
          
          +
          
            
              V
              
                d
                ⁢
                
                  
                
                ⁢
                c
              
            
            ⁢
            
              
                e
                
                  j2π
                  /
                  3
                
              
              .
            
          
        
      
    
  
  
    
      
        =
        
        ⁢
        
          
            V
            
              d
              ⁢
              
                
              
              ⁢
              c
            
          
          ⁢
          
            e
            
              jπ
              /
              3
            
          
        
      
    
  




The above example is shown as vector V2 in FIG. 11. FIG. 11 is a vector diagram illustrating the six sectors associated with the switching states of the two-level inverter. The six boundary vectors indicate switching states of the complementary switching pairs of the two-level inverter, where the first digit represents switch pair Sa and S′a with Sa ON, the second digit represents switch pair Sb and S′b with Sb ON, and the third digit represents switch pair Sc and S′c with Sc ON. Two additional switching states (0,0,0) and (1,1,1) represent zero vectors at the origin of the graph. The switching pairs operate in complementary fashion such that when one switch of the pair is ON, the other switch of the pair is OFF. FIG. 11 further shows an example state of the system of FIG. 10 where the primary space vector {right arrow over (Vsv)} is in sector 1 and primary converter switch S1 is ON. With S1 ON,





  
    
      
        V
        sv
      
      ⇀
    
    =
    
      
        3
        2
      
      ⁢
      
        V
        
          p
          ⁢
          
            
          
          ⁢
          k
        
      
      ⁢
      
        e
        
          jω
          ⁢
          
            
          
          ⁢
          t
        
      
    
  
  ,




The secondary vectors bordering the first sector include vector V1 when switch Sa is ON and switches Sb and Sc are OFF and vector V2 when switches Sa and Sb are ON and switch Sc is OFF.

To determine the duty cycle of each applied vector, set

{right arrow over (V)}sc=d1{right arrow over (V)}1+d2{right arrow over (V)}2 

where d1 and d2 are the duty ratios for the two level inverter switch states associated with secondary space vectors V1 and V2 respectively. In general, the duty cycles will be applied symmetrically about an offset from the center of the interval that defines the S1 pulse. For example FIG. 12 shows a switching interval Ts where S1 of the primary converter is ON during the first half of the switching cycle and S2 is ON during the second half of the switching cycle. While S1 is ON and Vs is in the first vector, the voltage pulse across the leakage inductance of a secondary winding is shown. The pulse can be multi leveled and offset from the center of the S1 pulse by δTs/2 (1210). The pulse itself can be symmetrical, for example, the V1 voltage can be applied with a d1 duty cycle (1211) between two portions of the V2 voltage, where each V2 portion is applied for half of the d2 duty ratio (1212).

Zero vectors 1213 are applied outside the duty cycles of the inverter switches. Zero vectors may be applied with switches Sa, Sb and Sc all ON or all OFF. Soft switching for S1 and S2 can be obtained when the primary currents, Ia, Ib and Ic go to zero every half cycle. The primary currents Ia, Ib and Ic can go to zero when the average voltage applied across the primary windings is configured to be zero over each half cycle.
Mathematically, the offset δ can be determined from



  
    
      
        
          T
          s
        
        4
      
      -
      
        (
        
          
            δ
            ⁢
            
              
                T
                s
              
              2
            
          
          +
          
            
              (
              
                
                  
                    d
                    1
                  
                  +
                  
                    d
                    2
                  
                
                2
              
              )
            
            ⁢
            
              
                T
                s
              
              2
            
          
        
        )
      
    
    ≥
    0
  




  
    δ
    ≤
    
      
        1
        2
      
      ⁢
      
        (
        
          1
          -
          
            
              
                3
              
              ⁢
              
                
                  V
                  ^
                
                
                  p
                  ⁢
                  
                    
                  
                  ⁢
                  k
                
              
            
            
              V
              
                d
                ⁢
                
                  
                
                ⁢
                c
              
            
          
        
        )
      
    
  



With the value of δ fixed, average phase currents, as well as an average dc current, are given by,




  
    
      I
      a
    
    =
    
      
        
          
            
              V
              ^
            
            
              p
              ⁢
              
                
              
              ⁢
              k
            
          
          ⁢
          δ
        
        
          4
          ⁢
          
            Lf
            s
          
        
      
      ⁢
      
        cos
        ⁡
        
          (
          α
          )
        
      
    
  




  
    
      I
      b
    
    =
    
      
        
          
            
              V
              ^
            
            
              p
              ⁢
              
                
              
              ⁢
              k
            
          
          ⁢
          δ
        
        
          4
          ⁢
          
            Lf
            s
          
        
      
      ⁢
      
        cos
        ⁡
        
          (
          
            α
            -
            
              2
              ⁢
              
                π
                /
                3
              
            
          
          )
        
      
    
  




  
    
      I
      c
    
    =
    
      
        
          
            
              V
              ^
            
            pk
          
          ⁢
          δ
        
        
          4
          ⁢
          
            Lf
            s
          
        
      
      ⁢
      
        cos
        ⁡
        
          (
          
            α
            +
            
              2
              ⁢
              
                π
                /
                3
              
            
          
          )
        
      
    
  




  
    
      I
      
        d
        ⁢
        
          
        
        ⁢
        c
      
    
    =
    
      
        3
        ⁢
        
          V
          
            p
            ⁢
            
              
            
            ⁢
            k
          
          2
        
        ⁢
        δ
      
      
        8
        ⁢
        
          Lf
          s
        
        ⁢
        
          V
          
            d
            ⁢
            
              
            
            ⁢
            c
          
        
      
    
  



The average power is given by





  
    P
    avg
  
  =
  
    
      3
      ⁢
      
        V
        
          p
          ⁢
          
            
          
          ⁢
          k
        
        2
      
      ⁢
      δ
    
    
      8
      ⁢
      
        Lf
        s
      
    
  




Pavg is noted to be directly proportional to δ and the square of Vpk.

The power electronic transformers described herein may, for example, find use in applications requiring a high-frequency transformer, related to grid connection of wind power generators, related to power transmission and distribution, or electric drives. In certain examples, the present power electronic transformers are used in conjunction with wind power generators. Wind plants typically produce electrical energy at relatively low voltage (e.g., about 690V), which is transformed into medium voltage energy (e.g., about 34.5 kV) by power transformers. The AC to DC PET topologies illustrated herein provide controllable bi-directional energy transfer. Applications include exchanging power between a power grid and an energy storage device such as a battery back for a hybrid or electric vehicle. In addition to charging the battery pack, the topology allows energy to be transferred from the battery pack to the grid, such as during peak energy demand. In certain examples, the present power electronic transformers are used in transmission and distribution systems. Transformers are a building block of various transmission and distribution systems. As a result, transformer reliability is important. The present inventors have recognized that due to the use of numerous semiconductor switches, which the inventors have found to make transformer operation more complicated and less reliable, previous attempts to replace conventional transformers with power electronic transformers would likely have failed. However, the disclosed scheme of power electronic transformers use is simpler—involving less switches—and is believed to be suitable for use in transmission and distribution systems.
Additional Notes
The examples disclosed herein can be verified by stimulation or theoretical analysis.
The above Detailed Description includes references to the accompanying drawings, which form a part of the Detailed Description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.”
All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable Inconsistencies, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.
In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, assembly, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
The above description is intended to be illustrative, and not restrictive. For example, while some of the above-described examples are described as comprising only two (high voltage rated) semiconductor switches, numerous lower voltage rated switches connected together may alternatively be used. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. Also, in the above Detailed Description, various features may have been grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter can lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

## Claims

1. An apparatus comprising:
a transformer having primary windings and secondary windings, the primary windings of the transformer configured to receive a first multi-phase power signal having a first frequency, wherein the primary windings include, for each phase of the multi-phase power signal, a first primary winding and a second primary winding magnetically coupled in direct phase opposition to the first primary winding;
a primary converter configured to generate a second multi-phase power signal having a second frequency at the secondary windings, the second frequency substantially higher than the first frequency, wherein the primary converter includes:
a first switch configured to couple together the first primary windings of each phase; and
a second switch configured to couple together the second primary windings of each phase;

a secondary converter coupled to the secondary windings, the secondary converter configured to provide a load power signal using the second multi-phase power signal; and
wherein the secondary converter is configured to reduce current flow in the primary windings at or near a switch event of at least one of the first and second switches of the primary converter, the reduced current flow configured to reduce disturbances from leakage inductance of the transformer.

2. The apparatus of claim 1, wherein the first switch and the second switch are two-quadrant switches.

3. The apparatus of claim 1, wherein the secondary converter is configured to couple to a direct current (DC) device.

4. The apparatus of claim 3, wherein the primary converter is configured to receive a three-phase power signal; and the transformer is a three-phase transformer.

5. A method comprising:
receiving a first alternating current (AC) power signal having a first frequency at multiple first and second primary windings of a transformer;
selectively coupling together the first primary windings of the transformer to provide a second AC power signal having a second frequency using a first switch of a primary converter, wherein the second frequency is substantially higher than the first frequency;
selectively coupling together the second primary windings of the transformer to provide the second AC power signal using a second switch of the primary converter;
receiving the second AC power signal from a secondary winding of the transformer; and
modulating the second AC power signal using a secondary converter to generate an output power signal having third frequency.

6. The method of claim 5, wherein receiving the first AC power signal includes receiving a first three-phase AC power signal.

7. The method of claim 5, wherein receiving the second AC power signal includes receiving a second three-phase AC power signal from the secondary winding of the transformer.

8. The method of claim 5, wherein modulating the second AC power signal includes controlling the second converter to generate an average output power signal having a third frequency equal to substantially zero hertz.

9. The method of claim 5, wherein modulating the second AC power signal includes pulse width modulating the secondary power signal with a symmetric pulse.

10. The method of claim 5, wherein modulating the second AC power signal includes pulse width modulating the secondary power signal to provide a unity power factor at the primary converter.

11. A system comprising:
a power grid;
a high frequency link coupled to the power grid, wherein the high frequency link includes:
a transformer having primary windings and secondary windings, the primary windings of the transformer configured to receive a first multi-phase power signal having a first frequency, wherein the primary windings include, for each phase of the multi-phase power signal, a first primary winding and a second primary winding magnetically coupled in direct phase opposition to the first primary winding;
a primary converter configured to generate a second multi-phase power signal having a second frequency at the secondary windings, the second frequency substantially higher than the first frequency, wherein the primary converter includes:
a first switch configured to couple together the first primary windings of each phase; and
a second switch configured to couple together the second primary windings of each phase;

a secondary converter coupled to the secondary windings, the secondary converter configured to provide a load power signal using the second multi-phase power signal; and
wherein the secondary converter is configured to reduce current flow in the primary windings at or near a switch event of at least one of the first and second switches of the primary converter, the reduced current flow configured to reduce disturbances from leakage inductance of the transformer;

an electronic device coupled to the high frequency link, wherein the electronic device is at least one of a wind generator, a hybrid vehicle, a photovoltaic cell, or an energy storage device; and
wherein the high frequency link is configured to bi-directionally exchange energy between the power grid and the electronic device.