# Patent

## Title
Rotary decoration driving device

## Abstract

A device for measuring the duration of a time slot or interval includes a first clock for supplying pulses of period T and a second clock, whose pulses are shifted with respect to the first. A digital circuit counts the number of pulses of the clocks, which are followed by a complete period T and which occur between the start signal and the stop signal. An analog circuit determines the times separating the start signal and the start of the first pulses of the clocks after the start signal and the times separating the stop signal and the end of the final periods of the clocks before the stop signal, and converts the analog data into digital data. A processing circuit determines the duration of the time slot, and resolves any ambiguity situation, which could lead to a clock period counting error.

## Background
The present invention relates to a device for measuring the duration of a time slot or interval.

The field of the invention is that of chronometry, the precise time measurement of a short or infinitely long time period between a measurement start and measurement stop signal.

This type of problem occurs in all devices where a precise time measurement is necessary over very long periods, particularly in devices used in the field of laser telemetry.

In the field of very accurately measuring time use is made: time compared with the measuring time: such methods not being usable in the case where the acquisition time must be limited and also averaging is only possible if the measured phenomenon has an appropriate stationarity relative to the averaging time; clock for a rough measurement and on the determination of a time compliment by an analog method which gives the accuracy to the measurement: such a method being described in the article entitled "The vernier time-measuring technique" by Robert G. Baron (proceedings of the IRE, January 1957), but this method lengthens significantly the measuring time (5 .mu.s measurement time for a resolution of 20 .mu.s with 100 megahertz clocks), so that it limits the number of possible measurements well below the implementation frequency of certain events.

The French patent application filed under No. 93 08145 on Feb. 7, 1993 and entitled "Device for measuring the duration of a time slot" describes a process for measuring time making it possible to remove the counting ambiguity of a clock stroke and which takes account of non-synchronism problems. This process is not suitable for measuring long time durations exceeding 10 us, as a result of the discharge of a capacitor of the circuit which can lead to a significant error on long measurement intervals, particularly for medium distance telemetry applications (exceeding 1 km).

The invention aims at solving these problems.

More specifically, it relates to a device for measuring the duration of a time slot between a start signal (D) and a stop signal (F), characterized in that it comprises: followed by a complete period T and which are between the start signal (D) and the stop signal (F), separating the signal (D) and the start of the first pulse of the other clock commencing after (D) and on the other hand the time t.sub.2 separating the stop signal (F) from the end of the final period of the first clock completed before (F), and able to convert the analog data obtained into digital data, basis of data supplied by the digital circuit and those supplied by the analog circuit previously converted into digital data.

This device makes it possible to very accurately measure very long time intervals or slots. Moreover, the start (D) and stop (F) signals can be completely clock-asynchronous. This is interesting for applications of the "flight time" telemetry type, in which (D) and (F) are given by the start of a light pulse and by the reception of the pulse reflected on an object, whereby said two signals (D) and (F) can be asynchronous with respect to the clock.

According to a special embodiment of the invention, the analog circuit can also comprise: dividing circuit, produced by the first ramp generator and on the other the start (D) and stop (F) signals of the time slot to be measured.

According to another embodiment of the invention, the digital circuit is provided with a second clock, whose pulses are shifted with respect to those of the first clock, the digital circuit also counting the number of pulses of the second clock followed by a complete period and which occur between the start signal (D) and the stop signal (F), the analog circuit determining on the one hand the time separating the signal (D) and the start of the first pulse of the second clock commencing after (D) and, on the other hand, the time separating the stop signal (F) from the end of the final period of the second clock completed before (F), said analog circuit being able to convert the analog data obtained into digital data and the device also has means able to determine which of the counts performed on one of the two clocks (H.sub.1, H.sub.2) is to be taken into account, so as to resolve any ambiguity situation which could lead to a clock period counting error.

Thus, it is possible to remove any ambiguity situation in the case where one of the signals (D) and (F) coincides with a clock pulse.

Other aspects and embodiments can be gathered from the dependent claims.

The invention is described in greater detail hereinafter relative to non-limitative embodiments and with reference to the attached drawings, wherein show:

FIG. 1 The measuring principle of a time slot according to the invention.

FIG. 2 A diagram of a device for performing the invention.

FIG. 3 The principle of the method according to a particular embodiment in the invention, in the case where ambiguity situations must be removed.

FIG. 4 A diagram of another device for performing the invention according to a second embodiment.

In order to measure the duration of a given time interval or slot, according to the invention, measurement takes place of the rough part of the time slot in digital manner and the fine part in analog manner. The thus acquired parameters are then recombined in order to obtain the result. Therefore the time measurement is obtained by associating a digital quantity in the form of a number of counted clock periods and analog quantities obtained by converting times into voltage amplitudes.

This principle is illustrated with the aid of the timing diagram of FIG. 1. The aim is to measure the time slot t.sub.v between the interval start pulse D and the interval stop pulse to be measured F. For this purpose use is made of a basic clock H of period T. The number of clock pulses n followed by a complete period T is counted for the duration t.sub.v. The total time corresponding to the passing of this period is equal to nT. As the clock is not synchronous with the start signal D and stop signal F, it is also necessary to determine on the one hand the time t.sub.1, elapsing between the start signal D and the beginning of the first clock pulse commencing after D1 and, on the other hand, the time t.sub.2 elapsing between the stop signal F and the end of the final clock period completed before the signal F. To obtain the duration of the time slot t.sub.v, it is then merely necessary to add the three measured times: t.sub.1 +nT+T.sub.2.

To determine t.sub.1 and t.sub.2 use is made of a triangular signal R of period 2T, amplitude A and synchronous with the basic clock of period T. At any instant, if a is the amplitude measured on the ramp, the t elapsed since the start of the ramp is equal to A/T.a. By sampling the ramps on the appearance of the start signal D and the stop signal F, amplitudes a.sub.1 and a.sub.2 are obtained, which respectively respresent t.sub.1 and t.sub.2.

If the starting pulse occurs during a rising ramp, we obtain: ##EQU1##

If the starting pulse occurs during a falling ramp, we obtain: ##EQU2##

If the stop pulse F occurs on a rising ramp, we obtain: ##EQU3##

If the stop pulse F occurs on a falling ramp, we obtain: ##EQU4##

t.sub.1 and t.sub.2 are then digitized, which gives two corresponding values T.sub.1 and T.sub.2. Thus, the duration of the time slot is obtained: t.sub.v =nT+T.sub.1 +T.sub.2.

A device for performing the invention is shown in FIG. 2. A clock H supplies pulses of period T to one of the inputs of an AND gate, designated by the reference 2. This clock H can be produced from a crystal quartz oscillator operating e.g. at a frequency of 200 MHz. The other input of the AND gate receives a signal from the output Q of a R-S flip-flop designated by the reference 4, to whose input S is supplied the start signal D, whilst the input R is controlled by the stop signal F. The unit constituted by the AND gate, flip-flop 4 and clock H constitutes a digital measuring circuit making it possible to obtain a rough value of the time slot to be measured. This value is equal to nT, in which n is the number clock periods T which have elapsed between the start signal D and the stop signal F and is counted in a counter 3.

In parallel, a division of the frequency of the signals of the clock H is performed by a divider 6, e.g. formed by a flip-flop, the output of said divider supplying a ramp generator 8. This generator can be implemented by the constant current charging and discharging of a capacitor. The period and gradient of these ramps are very well defined. The output of the ramp generator 8 is supplied to a fast analog-digital converter 10 (e.g. of the flash type or fast sampler+converter), whereof another input receives a signal e.g. from a flip-flop 12, controlled by the start signal D and stop signal F of the period to be measured. Thus, the converter 10 samples the information on the amplitude of the ramp at the start time D and stop time F of the time slot to be measured, as well as the information relative to the parity of the ramp at these instants, i.e. its rising or falling character. This converter makes it possible to obtain information concerning the values T.sub.1 and T.sub.2 and which is stored in a memory 13.

The rough information relating to nT and the "fine" information relating to the slots T.sub.1 and T.sub.2 are supplied to a processing circuit 14, which calculates the duration t.sub.v of the time slot to be measured.

This device makes it possible to obtain a good precision, because it gives freedom from any synchronization of the measurement start signal D and stop signal F relative to the timer or chronometer clock H. It also makes it possible to obtain freedom from the limited capacity of the chronometer for determining a small and a very long time deviation able to vary between a few seconds and infinity, due to the fact that its frequency is fixed.

This device also makes it possible to determine long time intervals with a constant precision, no matter what the duration of said time interval. This is not true in the case of the prior art time slot duration measuring devices, particularly that described in French patent application 93 08145 of Feb. 7, 1993. Thus, the latter device a capacitor is discharged at the start of the measurement of the time slot and at the end of said measurement the same capacitor is charged. However, the charge measured immediately after the arrival of the signal D can vary before reaching the final part of the time slot to be measured, just prior to the stop signal F and this increases as the time slot to be measured lengthens. In the device according to the invention, this problem is avoided by using recurrent ramps.

Finally, this type of device can easily be integrated in order to bring about a compact circuit.

An embodiment of the invention makes it possible to take account of problems linked with ambiguity situations on the start signal D and the stop signal F. These problems arise when one or other of the signals occur simultaneously at a rising or falling front or edge of the signals of the clock. The counter of the digital part of the device, which determines the rough measurement of the time slot, can then count a supplementary clock pulse, which would not have been counted.

So as to solve this problem, the invention proposes a device operating on the principle illustrated in FIG. 3. In accordance with what has already been explained hereinbefore, a clock H.sub.1 supplies signals of period T. A divider makes it possible to generate signals S.sub.1 of period 2T synchronized with the signals of the clock H.sub.1. It is thus possible to generate rising and falling ramps R.sub.1 of amplitude A. A delay or lag device makes it possible to generate a second signal of clock H.sub.2, on the basis of the signal H.sub.1, the signals H.sub.2 being shifted by T/2 with respect to the signals of H.sub.1. Thus, a falling edge of a square wave pulse of H.sub.2 corresponds to a rising edge of a square wave pulse of H.sub.1, as can be seen in FIG. 3. This signal of clock H.sub.2 makes it possible to generate in the manner described hereinbefore for clock H.sub.1, a signal S.sub.2 of period 2T, which will itself control a ramp R.sub.2 of the same amplitude A as the ramp R.sub.1. When the measurement start signal D occurs, simultaneous sampling takes place of the two ramps R.sub.1 and R.sub.2. If there is e.g. ambiguity between D and H.sub.1, i.e. if the signal D is superimposed on a rising edge of a square wave pulse of H.sub.1, it is not possible for there to be simultaneously ambiguity between the signal D and the signals generated by H.sub.2, due to the shift by a half-period between the two channels. Consequently, it is merely necessary to identify the clock which is not in an ambiguity situation with the start signal D and to then only retain the sampled value of the corresponding ramp R in order to determine t.sub.1. For example, if the ambiguity situation occurs between the start signal D and the clock H.sub.1, the valid clock for determining the measurement of t.sub.1 is the clock H.sub.2 and the value to be taken into account is that measured on the ramp R.sub.2.

The same situation occurs for any ambiguity on the signal F. When the stop signal F occurs, simultaneous sampling takes place on the two ramps R.sub.1 and R.sub.2. For t.sub.2 is taken the value of the ramp R.sub.1 or R.sub.2 from the clock H.sub.1 or H.sub.2 not having an ambiguity with the signal F.

In the case where the ambiguity situation exists simultaneously on D and F, it is possible to add a third circuit with a clock H.sub.3 shifted with respect to H.sub.2 and H.sub.1.

In the case where there is no ambiguity, neither with the clock H.sub.1, nor with the clock H.sub.2, the time values obtained (t.sub.1 or t.sub.2) will be taken on one or other of the two circuits corresponding to the two clocks.

The device corresponding to this embodiment of the invention is illustrated in FIG. 4, where in a first block 24 a first counter 25 receives on its authorization input CE a counting order from a flip-flop 23 and on its input C the signals of clock H.sub.1. The output data from the first counter 25 are transmitted to a processing circuit 22 by means of a switching or routing circuit 36 controlled by an OR gate 32.

The D-flip-flops 26 and 30 receive the signals D and F by means of an OR function 40, 41 on their input D. The flip-flop 23, which supplies the authorization signal CE is also controlled by the signals D and F, which are both delayed by a quantity close to three propagation times in the gates by the devices 19, 42, which are e.g. constituted by time lags in the logic gates. The first AND gate 27 implements the AND function of the output of the flip-flop 26 and the clock H.sub.2. The signals of the latter are obtained from H.sub.1 and a lag circuit 18, e.g. constituted by propagation times in the gates.

In the second block 28 a second counter 29 receives on its authorization input CE a counting order from flip-flop 23. The data of said counter 29 are transmitted to the processing circuit 22 via the circuit 36. The second D-flip-flop 30 functions in the manner described hereinbefore. The second AND gate 31 implements the AND function between the output of the circuit 30 and the clock H.sub.1.

The output of the circuit 32 controls the operation of the switching or routing circuit 36 to obtain the reading of the counter 25 or 29, whose D-flip-flop 26 or 30 has not switched first. It detects the first of the flip-flops 26 or 30 which has switched and it authorizes the reading of the counter, whose flip-flop has not changed state.

If there is an uncertainty situation, e.g. at the start of the count, for one or other of the counters, the first of the presence identification circuits 26, 30 which switches validates the choice between the clocks H.sub.1 or H.sub.2. The validated counter is left unchanged, whereas the other counter is zeroed prior to the arrival of the second clock pulse following the signal D. This is carried out by the circuits 44, 45 and 46, 47 respectively for the first and second counters. The circuits 44 and 46 are AND gates, whereas circuits 45 and 47 are of the time shaping type.

A R-S-flip-flop 33 receives on its set input the output of an OR gate 34, whereof the inputs correspond to the signals D and F delayed by the circuits 42 and 19. The flip-flop 33 receives on its other input the outputs of the two AND gates 27, 31.

This flip-flop 33 controls an input of an analog-digital converter 50 and an input of an analog-digital converter 52. Another input of each of these converters 50, 52 is connected to the clock H.sub.1, respectively H.sub.2 by means of a flip-flop 51, respectively 53, which makes it possible to generate a signal S.sub.1, respectively S.sub.2 of period 2T, and a ramp generator 59, respectively 57, for generating a ramp R1, respectively R2. Downstream of the analog-digital converters, there are two memories 60, 62 and a switching circuit 56 controlled by the circuit 32.

## Claims

1. A device for measuring duration of a time slot between a start signal (D) and a stop signal (F), comprising: first clock; are followed by a complete period T and which occur between said start signal (D) and said stop signal (F), and for counting number of pulses of said second clock which are followed by a complete period T, which occur between said start (D) and said stop signal (F); (D) and start of first pulse of said first clock commencing after (D), (2) time t2 separating said stop signal (F) from end of final period of said first clock completed before (F), (3) time t3 separating said start signal (D) and start of first pulse of said second clock commencing after (D), and (4) time t4 separating the stop signal (F) from end of final period of said second clock pulses completed before (F), and for converting analog data obtained into digital data; basis of data supplied by said digital circuit and those supplied by said analog circuit previously converted into digital data; and clocks is to be taken into account, so as to resolve any ambiguity situation which could lead to a clock period counting error.

2. A device according to claim 1, wherein said analog circuit also comprises: dividing circuit; and first ramp generator, and said start signal (D) and stop signal (F) of said time slot to be measured.

3. A device according to claim 2, and further comprising a flip-flop for transmitting said start signal (D) and stop signal (F) of said time slot to be measured to said first analog-to-digital converter.

4. A device according to claim 1, wherein said digital circuit further comprises: delayed after passage in a first delay circuit and, on its reset input by said delayed stop signal (F) following passage in a delay circuit; gate, a first OR gate, a second AND gate, and means for time shaping of the signals; gate, a second OR gate, a fourth AND gate, a signal time shaping means; and of said flip-flops has switched first.

5. A device according to claim 4, wherein: authorization input CE a counting order from said R-S flip-flop; circuit by means of a switching circuit controlled by said OR gate; said start signal (D) and said stop signal (F) and pulses from said first clock; and first D-flip-flop, and the pulses from said second clock.

6. A device according to claim 4, wherein: authorization input (CE) a counting order from said R-S flip-flop; means of a switching circuit; receiving said start signal (D) and said stop signal (F), and pulses from said second clock (H.sub.2); and said D-flip-flops and pulses from said second clock (H.sub.2).

7. A device according to claim 3, wherein said flip-flop is adapted to receive an output of an OR gate, whose inputs correspond to the delayed signals (D) and (F), and outputs of said first and third AND gates.

8. A device according to claim 7, further comprising a second analog-to-digital converter controlled by said output of said flip-flop and by an output of a second ramp generator, which is controlled by an output of a second divider of said pulses of said second clock.

9. A device according to claim 4, wherein said flip-flop is adapted to receive an output of an OR gate, whose inputs correspond to the delayed signals (D) and (F), and outputs of said first and third AND gates.

10. A device according to claim 9, further comprising a second analog-digital converter controlled by said output of said flip-flop and by an output of a second ramp generator, which is controlled by an output of a second divider of said pulses of said second clock.

11. A device for measuring duration of a time slot between a start signal (D) and a stop signal (F), comprising: first clock, are followed by a complete period T and which occur between said start signal (D) and said stop signal (F), and for counting number of pulses of said second clock which are followed by a complete period T, which occur between said start (D) and said stop signal (F), time t.sub.1 separating said start signal (D) and start of first pulse of said first clock commencing after (D), (2) time t.sub.2 separating said stop signal (F) from end of final period of said first clock completed before (F), and for converting analog data obtained into digital data, time t.sub.3 separating said start signal (D) and start of first pulse of said second clock commencing after (D), and (4) time t.sub.4 separating the stop signal (F) from end of final period of said second clock completed before (F), and for converting analog data obtained into digital data, basis of data supplied by said digital circuit and those supplied by said analog circuits previously converted into digital data, and clock is to be taken into account, so as to resolve any ambiguity situation which could lead to a clock period counting error.

12. A device according to claim 11, wherein each of said first and second analog circuits comprises: circuit, generator, and said start signal (D) and stop signal (F) of said time slot to be measured.

13. A device according to claim 12, further comprising a flip-flop for transmitting said start signal (D) and stop signal (F) of said time slot to be measured to said first and second analog circuits.

14. A device according to claim 13, wherein said digital circuit further comprises: delayed after passage a first delay circuit and, on its reset input by said delayed stop signal (F) following passage in a delay circuit; gate, a first OR gate, a second AND gate, and means for time shaping of the signals; gate, a second gate, a fourth AND gate, a signal time shaping means; and of said flip-flops has switched first.

15. A device according to claim 14, wherein: authorization input CE a counting order from said R-S flip-flop; circuit by means of a switching circuit controlled by said OR gate; said start signal (D) and said stop signal (F) and pulses from said first clock; and first D-flip-flop, and the pulses from said second clock.

16. A device according to claim 14, wherein: authorization input (CE) a counting order from said R-S flip-flop; means of a switching circuit; receiving said start signal (D) and said stop signal (F), and pulses from said second clock (H.sub.2); and one of said D-flip-flops and pulses from said second clock (H.sub.2).

17. A device according to claim 13, wherein said flip-flop is adapted to receive an output of an OR gate, whose inputs correspond to the delayed signals (D) and (F), and outputs of said first and third AND gates.

18. A device according to claim 14, wherein said flip-flop is adapted to receive an output of an OR gate, whose inputs correspond to the delayed signals (D) and (F), and outputs of said first and third AND gates.