# Patent

## Title
Analog circuit test device

## Abstract

The invention relates to a test device for an analog circuit to be mounted on a mixed circuit including said analog circuit and a synchronous digital circuit. The test device includes a disturbance emulator connected to a first supply source (UrefD) capable of disturbing a second supply source (UrefA) of the analog circuit, the first and second supply sources being optionally merged, the emulator being adapted for receiving data representative of the evolution, during a given duration, of the average (μI) and the typical deviation (σI) of a first inrush current (I) that would be applied to the first supply source by the digital circuit, and being adapted for applying to the first supply source during successive intervals, each successive interval having said duration, a second inrush current (Irep) equal to the sum of the average and of the product of the typical deviation and of a pseudo-random signal varying according to a Gaussian law.

## Background
FIELD OF THE INVENTION
The present invention relates to a method and a device for testing an analog circuit of a circuit having digital and analog parts.
DISCUSSION OF PRIOR ART
A combined digital/analog circuit comprises analog components and logic (or digital) components which can be connected to a same power source or to different power sources which corrupt one another with noise through various parasitic elements, such as resistors, capacitors, or inductances.
FIG. 1 schematically shows a combined electronic circuit 10 comprising analog components, forming a circuit 12 (A), called analog circuit. Circuit 12 may correspond to amplifiers, analog filters, analog-to-analog, analog-to-digital or digital-to-analog converters, oscillators, etc. Circuit 10 also comprises logic components, for example, logic gates, flip-flops, etc. forming a circuit 14 (D) called logic circuit or digital circuit. The power supply of the components of analog circuit 12 is obtained by connecting circuit 12 to a source of a first reference potential VrefA and to a source of a second reference potential, for example, ground GNDA of the analog circuit. Voltage UrefA, which corresponds to the difference between the first and second reference potentials, is called the power supply voltage of the analog circuit. The power supply of the components of digital circuit 14 is obtained by connecting circuit 14 to a source of a third reference potential VrefD and to a source of a fourth reference potential, for example, ground GNDD of the digital circuit. Voltage UrefD, which corresponds to the difference between the third and fourth reference potentials, is called the power supply voltage of the digital circuit.
In most cases, digital circuit 14 operates synchronously, that is, it operates at the rate of one or several clock signals which time the operation of logic components such as flip-flops. Thereby, during the operation of digital circuit 14, many simultaneous or nearly simultaneous switchings of the signals used by the logic components can be observed. Such simultaneous or nearly simultaneous switchings translate as significant current surges on the side of the power supply of digital circuit 14. This translates as noise on the side of analog circuit 12, especially as to the power supply of analog circuit 12, the potential distribution in the substrate of analog circuit 12, etc. As an example, temporary variations of power supply voltage UrefA can be observed. Such noise on the side of analog circuit 12 causes a degradation of the performances of analog circuit 12.
Generally, in the development of electronic circuit 10, analog circuit 12 is tested independently from digital circuit 14, especially to determine its performance. However, in such a test, the noise affecting analog circuit 12, especially the variations of power supply voltage UrefA of analog circuit 12 due to the operation of digital circuit 14, is not taken into account. The performance degradation of analog circuit 12, which result from the joint use of analog and digital circuits 12 and 14 thus cannot be determined.
To take into account the noise in analog circuit 12, especially the variation of power supply voltage UrefA of analog circuit 12 due to the operation of digital circuit 14, a possibility is to form a test device comprising analog circuit 12 to be tested and digital circuit 14. However, since the structure of digital circuit 14 may greatly vary during the development process of electronic circuit 10, it is necessary to construct a new test circuit for each possible variation of digital circuit 14, which is too expensive.
It is thus desired to test analog circuit 12, rather than with digital circuit 14, with a circuit having a much simpler structure simulating the noise of power supply voltage UrefD which would be observed in the operation of digital circuit 14.
FIG. 2 shows a test device 20 comprising analog circuit 12 and an emulator 22 intended to reproduce, at least partially, the noise of power supply voltage UrefD due to digital circuit 14.
Emulator 22 must meet several requirements. It must be as simple as possible so that the manufacturing cost of test circuit 20 is as low as possible. It must however reproduce the noise of power supply voltage UrefD due to digital circuit 14 with a sufficient accuracy so that the test provides pertinent data relative to the performance decrease of analog circuit 12. Finally, a same emulator 22 must, after reprogramming, be able to reproduce the noise due to different digital circuits 14, to avoid having to design a test device 20 for each digital circuit 14 with which analog circuit 12 is capable of being used.
SUMMARY OF THE INVENTION
The present invention aims at a method and at a device for testing an analog circuit intended to operate jointly with a synchronous digital circuit.
According to another object, the test device has a relatively simple design.
According to another object, the test device enables to reproduce noise of the power supply voltage close to that which would be observed during the operation of the digital circuit.
According to another object, the test device enables to easily test an analog circuit intended to be used with different digital circuits.
The present invention thus provides a device for testing an analog circuit, for a combined circuit comprising this analog circuit and a synchronous digital circuit, said test device comprising a noise emulator connected to a first power supply source capable of disturbing a second power supply source of the analog circuit, where the first and second power supply sources may be a single supply source, the emulator being capable of receiving data representative of the variation, over a given time period, of the average and of the standard deviation of a first surge current which would be applied to the first power supply source by the digital circuit, and being capable of applying to the first power supply source, over successive intervals, each successive interval having the duration of said time period, a second surge current equal to the sum of the average and of the product of the standard deviation and of a pseudo-random signal varying according to a Gaussian law.
According to an embodiment of the present invention, the device comprises at least one circuit for providing the pseudo-random signal capable of providing a new value of the pseudo-random signal for each successive interval; and a noise generation circuit capable of applying the second surge current to the first power supply source.
According to an embodiment of the present invention, the noise generation circuit comprises a processing unit receiving the pseudo-random signal and the representative data and providing control signals; and noise elements, each noise element being connected to the first power supply source and being capable of being controlled by one of the control signals to provide an elementary surge current.
According to an embodiment of the present invention, the noise generation circuit comprises a first stage comprising a transmission element receiving a clock signal; second successive stages each comprising several groups of at least one transmission element, the input of said at least one transmission element of each group being connected to the output of the transmission element or of one of the transmission elements of the previous stage; and a last stage comprising a first plurality of transmission elements, the input of each of the first plurality of transmission elements being connected to one of the transmission elements of the previous stage and the output of each of the first plurality of transmission elements being connected to a second plurality of transmission elements.
According to an embodiment of the present invention, each noise element comprises a switching element, receiving one of the control signals, in series with a capacitor, the switching element being capable of being on or off according to the control signal.
According to an embodiment of the present invention, each of the first plurality of transmission elements has a transmission duration which depends on the transmission element.
According to an embodiment of the present invention, the device further comprises a circuit for providing a clock signal to the circuit for providing the pseudo-random signal and to the noise generation circuit.
The present invention also provides a method for testing an analog circuit for a combined circuit comprising this analog circuit and a synchronous digital circuit, comprising the steps of:
providing a test device or a test device simulation comprising or simulating the analog circuit and a noise emulator connected to a first power supply source capable of disturbing a second power supply source of the analog circuit, where first and second power supply sources may be a single supply source;
providing the emulator with data representative of the variation, over a given time period, of the average and of the standard deviation of a first surge current which would be applied to the first power supply source by the digital circuit; and
having the emulator apply or simulate the fact of applying to the first power supply source, over successive intervals, each interval having the duration of said time period, a second surge current equal to the sum of the average and of the product of the standard deviation and of a pseudo-random signal varying according to a Gaussian law.
According to an embodiment of the present invention, the provision of said representative data comprises the steps of:
estimating the variation of the first surge current over several successive intervals each having said duration; and
determining, for each first time among first successive times of an interval having said duration, the average of the values of the first surge current at second times, each second time being equal to the first time modulo said duration, and the standard deviation of the values of the first surge current at said second times.



BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing objects, features, and advantages of the present invention, as well as others, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, among which:
FIG. 1, previously described, schematically shows a digital/analog electronic circuit;
FIG. 2, previously described, schematically shows a device for testing an analog circuit;
FIG. 3 shows an example of the variation of the surge current in the operation of a digital circuit;
FIG. 4 shows an example of the variation of the average and of the standard deviation of the surge current in the operation of a digital circuit;
FIG. 5 illustrates the principle of surge current reproduction;
FIG. 6 shows, in the form of a block diagram, an example of a method for determining statistical characteristics of the surge current of a digital circuit;
FIG. 7 shows an embodiment of a noise emulator according to the invention;
FIG. 8 schematically shows an embodiment of a portion of the emulator of FIG. 7;
FIG. 9 illustrates the operation of the emulator portion of FIG. 8;
FIG. 10 shows an embodiment of another portion of the emulator of FIG. 7;
FIGS. 11 and 12 illustrate the operating principle of the emulator portion of FIG. 10; and
FIGS. 13 and 14 show variations of the emulator of FIG. 7.



DETAILED DESCRIPTION
For clarity, the same elements have been designated with the same reference numerals in the different drawings.
The applicant has set about constructing a noise emulator having a relatively simple structure and enabling, in operation, to reproduce the surge current peaks resulting from the operation of a conventional digital circuit. First, the applicant has envisaged the possibility of using a digital circuit emulator enabling to obtain surge current peaks distributed randomly along time. However, the applicant has shown that during the test of an analog circuit with such an emulator, the obtained performance decrease is not representative of the effective performance decrease observed when the analog circuit operates with the digital circuit. The applicant has then further examined the variation of the surge current observed during the operation of a conventional digital circuit.
FIG. 3 shows an example of the variation of surge current I during the operation of a synchronous digital circuit rated by a clock signal of period P. The applicant has shown that, for most synchronous digital circuits, the variation curve of surge current I has remarkable statistical characteristics. Indeed, the variation curve of surge current I comprises surge current peaks 24 which are not randomly distributed along time but which occur substantially at the same times for each clock cycle or group of clock cycles. However, the amplitude of the current peaks generally varies from one clock cycle to the other or from one group of clock cycles to another.
The applicant has shown that it is sufficient to design a noise emulator which, in operation, enables to obtain a surge current Irep reproducing a number of statistical characteristics of the surge current I which would be observed with the digital circuit. More specifically, the applicant has shown that it is sufficient for the reproduced surge current Irep to have the same average and the same standard deviation as the surge current I which would be observed with the digital circuit. The testing of an analog circuit with the noise emulator then enables to determine a performance decrease representative of the performance decrease effectively observed when the analog circuit operates jointly with the digital circuit.
To achieve this, it is sufficient for the noise emulator to enable to obtain a reproduced surge current Irep according to the following relation:

Irep(t)=μI(t[T])+σI(t[T])*X(t)   (1)

where T is a reference duration, for example, equal to the clock period of the digital circuit or to a multiple of the clock period;
t[T] means t modulo T;
μI corresponds to the average of surge current I over interval [0, T];
σI corresponds to the standard deviation of the surge current over interval [0, T]; and
X is a random function obeying a normal distribution. Function X is constant over each interval [kT, (k+1)T], where k is an integer greater than or equal to zero.
When the variation curve of surge current I associated with a digital circuit is known for a duration equal to N*T, average μI may be obtained from the following relation, for t ranging within [0, T]:




  
    
      
        
          
            μ
            I
          
          ⁡
          
            (
            t
            )
          
        
        =
        
          
            1
            N
          
          ⁢
          
            
              ∑
              
                k
                =
                0
              
              
                k
                =
                N
              
            
            ⁢
            
              I
              ⁡
              
                (
                
                  t
                  +
                  kT
                
                )
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




and standard deviation σI may be obtained from the following relation, for t ranging within [0, T]:





  
    
      
        
          
            σ
            I
          
          ⁡
          
            (
            t
            )
          
        
        =
        
          
            
              1
              N
            
            ⁢
            
              
                ∑
                
                  k
                  =
                  0
                
                
                  k
                  =
                  N
                
              
              ⁢
              
                
                  (
                  
                    
                      I
                      ⁡
                      
                        (
                        
                          t
                          +
                          kT
                        
                        )
                      
                    
                    -
                    
                      
                        μ
                        I
                      
                      ⁡
                      
                        (
                        t
                        )
                      
                    
                  
                  )
                
                2
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




FIG. 4 shows examples of variation curves of average μI and of standard deviation σI obtained from the variation curve of surge current I shown in FIG. 3.
FIG. 5 illustrates the principle of the determination of the reproduced surge current Irep based on relation (1) and shows, in dotted lines, the variation curves of average μI and of standard deviation σI which are produced for each successive time interval of duration T, in thin lines, function X and, in thick lines, the obtained variation curve of reproduced current Irep.
FIG. 6 shows, in the form of a block diagram, an example of a method for determining average μI and standard deviation σI of the surge current associated with digital circuit 14, such statistical characteristics being then provided to emulator 22 to test analog circuit 12.
Step 30 gathers all the steps generally implemented in the design of digital circuit 14. As an example, the design of digital circuit 14 comprises:
a specification determination step comprising, for example, dividing digital circuit 14 into different functional blocks;
a step of description of the behavior of each functional block in a hardware description language (HDL), for example, VHDL or Verilog;
a step of simulation of the behavioral description, for example implemented by means of the SMASH software sold by Dolphin Integration;
a generally-called “Synthesis” step which comprises providing, based on the HDL behavioral description, a file called Netlist, for example, in Verilog language, which corresponds to a list of interconnections of logic gates of a library;
a step of simulation after synthesis of the Netlist file, for example implemented by means of the SMASH software sold by Dolphin Integration;
a generally-called “placing and routing” step which comprises, based on the Netlist file, determining a concrete representation of digital circuit 14 where the positions of the logic components and of the tracks connecting them are specified. The result of the “placing and routing” step is a geometric description of digital circuit 14, called Layout, for example in format GDS2. It is also possible to provide a so-called delay file, for example, in SDF format, which contains the delays of the gates and interconnections. Further, the placing and routing step may cause a modification of the Netlist file, for example, when a clock tree must be provided. A new Netlist file, for example, in Verilog language, is then provided; and
a step of simulation of the modified Netlist file taking the delays into account, for example, implemented by means of the SMASH software sold by Dolphin Integration.
At step 32, digital circuit 14 is simulated based on the modified Netlist file and on the delay file, to determine an estimate of the variation of surge current I resulting from the operation of digital circuit 14. Such a simulation may be implemented with the SMASH software sold by Dolphin Integration. Such a simulation is generally reserved to analog circuits. The result of step 32 is the obtaining of files, for example, in DAT format, representative of the variation of surge current I along time.
At step 34, a statistic processing of the files obtained at the previous step is carried out to determine functions μI and σI. For this purpose, the variation curve of surge current I is divided into N intervals of duration T, where duration T may correspond to the period of the clock signal of the digital circuit or to a multiple of this period. Over time interval [0, T], M successive times ti are defined, i being an integer ranging between 0 and M−1, and times ti ranging between 0 and T. Average μI and standard deviation σI are determined at times ti based on relations (2) and (3) as follows:




  
    
      
        
          
            μ
            I
          
          ⁡
          
            (
            
              t
              i
            
            )
          
        
        =
        
          
            1
            N
          
          ⁢
          
            
              ∑
              
                k
                =
                0
              
              
                k
                =
                N
              
            
            ⁢
            
              I
              ⁡
              
                (
                
                  
                    t
                    i
                  
                  +
                  kT
                
                )
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  
  
    
      
        
          
            σ
            I
          
          ⁡
          
            (
            
              t
              i
            
            )
          
        
        =
        
          
            
              1
              N
            
            ⁢
            
              
                ∑
                
                  k
                  =
                  0
                
                
                  k
                  =
                  N
                
              
              ⁢
              
                
                  (
                  
                    
                      I
                      ⁡
                      
                        (
                        
                          
                            t
                            i
                          
                          +
                          kT
                        
                        )
                      
                    
                    -
                    
                      
                        μ
                        I
                      
                      ⁡
                      
                        (
                        
                          t
                          i
                        
                        )
                      
                    
                  
                  )
                
                2
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




FIG. 7 shows an embodiment of a noise emulator 22 according to the invention. Emulator 22 comprises an interface circuit 42 capable of receiving data DATA. Interface circuit 42 provides a clock period reference ST to a circuit 44 capable of providing a clock signal CLK. To simplify the rest of the description, it is considered that duration T corresponds to the period of clock signal CLK. Interface 42 provides an initialization reference SINI to a circuit 46 receiving clock signal CLK and providing a signal SX. Further, interface circuit 42 provides signals Sμ and Sσ to a noise generation circuit 48 connected to reference voltage source VrefD and to ground GNDD. Noise generation circuit 48 also receives clock signal CLK and signal SX.
Interface circuit 42 for example comprises a shift register, data DATA being provided in series to the register.
Data DATA comprise signals Sμ and Sσ, clock period reference ST, and initialization reference SINI. Signal Sμ is representative of average μI and signal Sσ is representative of standard deviation σI. Signals Sμ and Sσ are not necessarily identical to data μI and σI obtained at step 34 of the previously-described method. Indeed, a prior processing of data μI and σI may be provided before their transmission to interface circuit 42.
Circuit 44 for providing clock signal CLK for example has the structure of a ring oscillator. Signal CLK for example corresponds to a periodic square signal of duty cycle 1⁄2, having its period depending on reference ST. As an example, circuit 44 may comprise an inverter having its output looped back on its input, with a propagation time that may be modified according to reference ST.
According to a variation, circuit 44 for providing clock signal CLK is not integrated to emulator 22. Clock signal CLK used by emulator 22 is then provided by a device external to emulator 22.
Circuit 46 provides signal SX which is representative of random value X obeying a reduced centered Gaussian distribution. Circuit 46 is capable of providing a new value of signal SX for each clock cycle CLK.
FIG. 8 shows a simplified embodiment of circuit 46. Circuit 46 comprises a succession of five flip-flops L0 to L4, each receiving clock signal CLK. Each flip-flop L0 to L4 delivers a bit bit0 to bit4. A processing unit 49 receives bits bit0 to bit4 and clock signal CLK and provides signal SX. The output of flip-flop L0 drives the input of flip-flop L1. The output of flip-flop L1 drives the input of flip-flop L2. The output of flip-flop L2 drives a first input of an adder SUM. The output of adder SUM drives flip-flop L3. The output of flip-flop L3 drives the input of flip-flop L4. The output of flip-flop L4 drives the input of flip-flop L0 and a second input of adder SUM. Adder SUM for example corresponds to an XOR-type logic gate. The position of adder SUM may be modified with respect to what is shown in FIG. 8.
The operation of circuit 46 is the following: the initial values of bits bit0 to bit4 are imposed by reference SINI provided by interface circuit 42. In operation, for each rising edge of clock signal CLK, each flip-flop L0 to L4 reproduces at its output the binary value present at its input during the previous period of the clock signal. A new series of bits bit0 to bit4 is thus obtained for each clock cycle CLK.
FIG. 9 shows an example of the variation of bits bit0 to bit4 for five successive cycles of clock signal CLK. Calling Y the sum of bits bit0 to bit4, it can be shown that Y corresponds to a pseudo-random value which is all the closer to a Gaussian distribution of average μY and of standard deviation σY as the chain of flip-flops L0 to L4 is long. In practice, circuit 46 comprises a number of flip-flops that may be greater than 30. Random value X following a reduced centered Gaussian distribution may be equal to the ratio between value Y, minus μY, and σY. The signal SX provided by processing unit 49 is equal to X. As an example, signal SX is coded over 32 bits. In practice, the number of flip-flops of circuit 46 may be equal to the number of bits of signal SX. According to a variation, processing unit 49 is not present at the level of circuit 46 and the bits of signal SX correspond to bits bit0 to bit4. Value X may then be determined at the level of noise generation circuit 48 or at the level of an intermediary circuit between circuit 46 and circuit 48.
FIG. 10 shows an embodiment of noise generation circuit 48. Circuit 48 for example has a structure similar to that of a clock tree. A clock tree enables to transmit the clock signal to the different logic components of a digital circuit and generally comprises several successive stages of inverters or of amplifiers (an amplifier corresponding to two series-assembled inverters). As an example, the first stage comprises an amplifier receiving the clock signal. The second stage comprises several amplifiers having their inputs connected to the output of the amplifier of the first stage. The next stages each comprise several groups of amplifiers, the inputs of the amplifiers of a same group being connected to the output of one of the amplifiers of the previous stage. The last stage of the clock tree comprises several groups of amplifiers, the inputs of the amplifiers of a same group being connected to the output of one of the amplifiers of the previous stage and the output of each amplifier being connected to a logic component of the digital circuit, generally a flip-flop.
As an example, in FIG. 10, a noise generation circuit 48 based on the structure of a three-stages clock tree, with a first stage comprising an amplifier R receiving clock signal CLK and a second stage comprising two amplifiers R′ having their inputs connected to the output of amplifier R has been shown. The last stage of circuit 48 comprises a number M, equal to 4 in FIG. 10, of amplifiers Ri, with i ranging between 0 and M−1. The inputs of amplifiers Ri are connected to the output of one of amplifiers R′ of the previous stage. The output of each amplifier Ri is connected to a number L, equal to 2 in FIG. 10, of switchable amplifiers Qi,j, with j ranging between 0 and L−1. The output of each amplifier Qi,j is connected to a terminal of a capacitor Ci,j having its other terminal connected to ground GNDD or to reference potential VrefD. Amplifiers Qi,j have an identical propagation delay.
As described previously, number M corresponds to the number of times ti, with i ranging between 0 and M−1, in interval [0, T] for which average μI and standard deviation σI have been determined. With each amplifier Ri, with i ranging between 0 and M−1, is associated a propagation time Δi corresponding to the time required for a signal received at the input of amplifier Ri to be provided at the output of amplifier Ri. Clock signal CLK which propagates in the first stages of circuit 48 arrives substantially simultaneously at the level of amplifiers Ri. Clock signal CLK then reaches amplifiers Qi,j, with j ranging between 0 and L−1, after a delay Δi. Amplifiers Ri have propagation times which differ from one another so that the difference between Δi and Δi−1, with i ranging between 1 and M−1, is equal to the difference between ti and ti−1. Amplifiers Qi,j having the same propagation time, clock signal CLK reaches capacitors Ci,j according to the same sequence as times ti. In the present example illustrated in FIG. 10, considering that clock signal CLK reaches capacitors C0,0 and C0,1 at a time t′0, the same clock signal CLK reaches capacitors C1,0 and C1,1 at a time t′1, capacitors C2,0 and C2,1 at a time t′2, and capacitors C3,0 and C3,1 at a time t′3, with times t′0, t′1, t′2, and t′3 following one another according to the same sequence as respective times t0, t1, t2, and t3.
Each amplifier Qi,j is controlled by a control signal Si,j and may be on or off according to the value of signal Si,j. Control signals Si,j are provided by a processing unit 50 receiving signals CLK, Sμ, Sσ, and SX When off, amplifier Qi,j does not transmit clock signal CLK received at its input. When on, amplifier Qi,j transmits the clock signal received at its input with a propagation time which is identical for all amplifiers Qi,j.
Capacitors Ci,j are identical. As an example, the capacitance of each capacitor Ci,j is on the order of 100 fF. The application of a rising edge of clock signal CLK across a capacitor Ci,j translates as a current surge propagating to reference voltage source VrefD, which is connected to each of amplifiers R, R′, Ri, and Qi,j. Thereby, at a given time, the amplitude of the surge current of circuit 48 depends on the number of capacitors which are simultaneously being charged. Number L corresponds to the accuracy with which the amplitude of the surge current may be obtained. Indeed, as will be described in further detail hereafter, circuit 48 can provide a surge current that can substantially take L+1 values.
Initially, processing unit 50 receives signals Sμ, Sσ. For each new clock cycle, processing unit 50 receives a new value of signal SX and determines the reproduced surge current Irep to be obtained from relation (1) during a clock cycle. It then determines the control signals Si,j to be provided so that, all along the clock cycle, the number of capacitors Ci,j being simultaneously charged or discharged at a given time enables to obtain the desired value of the surge current at this time. Control signals Si,j may be determined from a look-up table or a calculation algorithm. Control signals Si,j may be simultaneously sent to all amplifiers Qi,j, or successively sent to amplifiers Qi,j during a clock cycle. Further, the control signals Si,j determined during a clock cycle may be transmitted to amplifiers Qi,j during the next clock cycle.
FIG. 11 schematically shows an example of a variation curve of the reproduced surge current Irep likely to be obtained with circuit 48 of FIG. 10. Two successive clock cycles P0, P1 in the operation of circuit 48 have been shown.
FIG. 12 shows, for cycles P0, P1, the values of control signals Si,j provided by processing unit 50 and enabling to obtain the surge current of FIG. 11. It is assumed that a control signal Si,j is at state “0” when the corresponding amplifier Qi,j is off and is at state “1” when the corresponding amplifier Qi,j is on. To simplify the description of the operation of circuit 48, only the currents due to the charge of capacitors Ci,j are considered. Further, the propagation delay in amplifiers Qi,j has been neglected. The operation of circuit 48 will now be detailed for clock cycle P0. At time t′0, a rising edge of clock signal CLK reaches amplifier Q0,0 and Q0,1. Since control signals S0,0 and S0,1 are at “0”, the associated capacitors C0,0 and C0,1 are not charged and the surge current is zero. At time t′1, the rising edge of the clock signal reaches amplifiers Q1,0 and Q1,1. Since signal S1,0 is at “1” and signal S51,1 is at “0”, only capacitor C1,1 charges, which corresponds to a surge current I1. At time t′2, the rising edge of clock signal CLK reaches amplifiers Q2,0 and Q2,1. Since control signals S2,0 and S2,1 both are at “1”, capacitors C2,0 and C2,1 charge, which corresponds to a greater surge current I2. At time t′3, the rising edge of clock signal CLK reaches amplifiers Q3,0 and Q3,1. Control signals S3,0 and S3,1 being at “0”, capacitors C3,0 and C3,1 are not charged and the surge current is zero.
More specifically, when a rising edge of clock signal CLK reaches a capacitor Ci,j, a fast rise of the surge current followed by a fast decrease of the surge current can be observed. Thereby, to obtain a “smooth” curve of surge current Irep, the charges of capacitors Ci,j and Ci+1,j must not be too distant from each other, that is, M must be sufficiently large. In this case, when a rising edge of clock signal CLK reaches a capacitor Ci,j and, after a given delay, a capacitor Ci+1,j, the current surge due to the charge of capacitor Ci,j is not over when the current surge due to the charge of capacitor Ci+1,j starts. Thereby, to obtain a surge current of determined intensity at a given time, the number of capacitors to be charged at this given time is determined by taking into account the number of capacitors having started being charged at the times preceding the given time and which may still be under charge.
The surge current which results from the operation of emulator 22 is essentially due to the charge and to the discharge of capacitors Ci,j. However, processing unit 50 may, on determination of control signals Si,j, take into account the contribution of surge current Irep of the other components of emulator 22.
The previously-described embodiment relates to an emulator 22 of a test device 20 of an analog circuit 12 for a digital/analog circuit 10 powered by a single power supply field UrefD and rated by a single clock signal CLK. However, the present invention may apply to the testing of an analog circuit intended to equip a combined circuit powered by several different power supply sources and rated by several different clock signals.
FIG. 13 shows in the form of a block diagram an emulator 60 which corresponds to a variation of emulator 22 adapted to the case where the combined circuit comprises a first digital circuit portion powered by a first supply field and a second digital circuit portion powered by a second supply field. Emulator 60 comprises two noise generation circuits 62, 64, each receiving clock signal CLK and signal SX. Interface circuit 42 provides first noise generation circuit 62 with signals Sμ1 and Sσ1 representative of the average and of the standard deviation μI1 and σI1 of the surge current due to the portion of the digital circuit connected to a potential VrefD1. Interface circuit 42 provides second noise generation circuit 64 with signals Sμ2 and Sσ2 representative of the average and of the standard deviation μI2 and σI2 of the surge current due to the portion of the digital circuit connected to a potential VrefD2. The operation of each noise generation circuit 62, 64 may be identical to what has been previously described for noise generation circuit 48.
FIG. 14 shows an emulator 70 which corresponds to a variation of emulator 22 adapted to the case where the combined circuit comprises a first digital circuit portion rated by a first clock signal CLK1 and a second digital circuit portion rated by a second clock signal CLK2. Interface circuit 42 is capable of providing a first period reference ST1 to a first circuit 72 for providing clock signal CLK1 and a second clock period reference ST2 to a second circuit 74 for providing clock signal CLK2. Interface circuit 42 provides a first noise generation circuit 80 with signals Sμ1 and Sσ1 representative of the average and of the standard deviation μI1 and σI1 of the surge current due to the portion of the digital circuit rated by clock signal CLK1. Interface circuit 42 provides a second noise generation circuit 82 with signals Sμ2 and Sσ2 representative of the average and of the standard deviation μI2 and σI2 of the surge current due to the portion of the digital circuit rated by clock signal CLK2. A first circuit 76 provides a pseudo-random signal SX1 to circuit 80 and a second circuit 78 provides a second pseudo-random signal SX2 to second noise generation circuit 82.
The present invention enables to form a device 20 for testing a particularly simple analog circuit 12. Indeed, emulator 22 has a much simpler structure than that of digital circuit 14 while reproducing the noise of power supply voltage UrefA due to the operation of digital circuit 14. The present invention thus enables to test analog circuit 12 and, in particular, to determine the performance decreases of analog circuit 12 when power supply voltage UrefA of analog circuit 12 is corrupted with noise. Based on the obtained results, several actions may be envisaged to limit the performance decrease of analog circuit 12. As an example, a better isolation between the digital and analog circuits may be provided. Further, the operating frequency range of combined circuit 10 may be narrowed. Digital circuit 14 may also be modified to better distribute the current surge peaks, for example, to spread them in time.
Emulator 22 according to the invention further provides a great flexibility of use since data DATA provided to emulator 22 are representative of the standard deviation and average curves over a clock cycle or several successive clock cycles and thus have a low bulk.
Further, a same emulator 22 may be used to reproduce the noise of power supply voltage UrefA which would be due to different types of digital circuit 14. Indeed, it is sufficient for this purpose to modify the values of average μI and of standard deviation σI provided to interface circuit 42. The complexity of the noise likely to be reproduced by a same emulator depends on number M of branches of the last stage of noise generation circuit 48 and on number L of capacitors per branch of the last stage of noise generation circuit 48.
Although a method for testing an analog circuit has been described, it should be clear that the test method may be implemented by software means to test an analog circuit simulation. In this case, the method implements a software simulation of emulator 22 which is used with a software simulation of analog circuit 12. The implementation of the test method is identical to what has been previously described, the electronic circuit elements being replaced with software elements.
Of course, the present invention is likely to have various alterations and modifications which will occur to those skilled in the art. In particular, any circuit capable of causing a current surge may be used instead of each capacitor Ci,j of noise generation circuit 48 or at least of some of them. As an example, each capacitor Ci,j may be replaced with a circuit comprising one or several MOS transistors. Further, although embodiments in which the digital/analog circuit comprises an analog circuit and a digital circuit connected to separate power supplies have been described, it should be clear that the present invention also applies to a digital/analog circuit in which the analog circuit and the digital circuit are connected to a single power supply likely to be corrupted with noise during the operation of the digital circuit.

## Claims

1. A device (20) for testing an analog circuit (12), for a combined circuit (10) comprising this analog circuit and a synchronous digital circuit (14), said test device comprising a noise emulator (22) connected to a first power supply source (UrefD) capable of disturbing a second power supply source (UrefA) of the analog circuit, where the first and second power supply sources may be a single supply source, the emulator being capable of receiving data representative of a variation curve, over a given time period, of an average (μI) and of a standard deviation (σI) of a first surge current (I) which would be applied to the first power supply source by the digital circuit, and being capable of applying to the first power supply source, over successive intervals, each successive interval having a duration of said time period, a second surge current (Irep) equal to:


Irep(t)=μI(t[T])+σI(t[T])*X(t)

where t[T] is t modulo T and X is a random function obeying a normal distribution and obtained from a pseudo-random signal.

2. The device of claim 1, comprising:
at least one circuit (46) for providing the pseudo-random signal (SX) capable of providing a new value of the pseudo-random signal for each successive interval; and
a noise generation circuit (48) capable of applying the second surge current (Irep) to the first power supply source (UrefD).

3. The device of claim 2, wherein the noise generation circuit (48) comprises:
a processing unit (50) receiving the pseudo-random signal (SX) and the representative data and providing control signals (Si,j); and
noise elements (Qi,j, Ci,j), each noise element being connected to the first power supply source (UrefD) and being capable of being controlled by one of the control signals to provide an elementary surge current.

4. The device of claim 3, wherein the noise generation circuit (48) comprises:
a first stage comprising a transmission element (R) receiving a clock signal (CLK);
second successive stages, each comprising several groups of at least one transmission element (R′), the input of said at least one transmission element of each group being connected to the output of the transmission element or of one of the transmission elements of the previous stage; and
a last stage comprising a first plurality of transmission elements (Ri), the input of each of the first plurality of transmission elements being connected to one of the transmission elements of the previous stage and the output of each of the first plurality of transmission elements being connected to a second plurality of noise elements (Qi,j, Ci,j).

5. The device of claim 4, wherein each noise element (Qi,j, Ci,j) comprises a switching element (Qi,j), receiving one of the control signals (Si,j), in series with a capacitor (Ci,j), the switching element being capable of being on or off according to the control signal.

6. The device of claim 4, wherein each of the first plurality of transmission elements (Ri) has a transmission duration which depends on the transmission element.

7. The device of claim 2, further comprising a circuit (44) for providing a clock signal (CLK) to the circuit (46) for providing the pseudo-random signal (SX) and to the noise generation circuit (48).

8. A method for testing an analog circuit (12) for a combined circuit (10) comprising this analog circuit and a synchronous digital circuit (14), comprising the steps of:
providing a test device (20) or a test device simulation comprising or simulating the analog circuit and a noise emulator (22) connected to a first power supply source (UrefD) capable of disturbing a second power supply source (UrefA) of the analog circuit, where first and second power supply sources may be a single supply source;
providing the emulator with data representative of a variation curve, over a given time period, of an average (μI) and of a standard deviation (σI) of a first surge current (I) which would be applied to the first power supply source by the digital circuit; and
having the emulator apply or simulate application to the first power supply source, over successive intervals, each interval having a duration of said time period, a second surge current (Irep) equal to:


Irep(t)=μI(t[T])+σI(t[T])*X(t)


where t[T] is t modulo T and X is a random function obeying a normal distribution and obtained from a pseudo-random signal.

9. The method of claim 8, wherein the provision of said representative data comprises the steps of:
estimating the variation curve of the first surge current (I) over several successive intervals each having said duration; and
determining, for each first time among first successive times of an interval having said duration, the average of the values of the first surge current at second times, each second time being equal to the first time modulo said duration, and the standard deviation of the values of the first surge current at said second times.