# Patent

## Title
Inverter circuit and display

## Abstract

An inverter circuit includes: first to third transistors; and first and second capacity elements. The first transistor makes/breaks connection between an output terminal and a first voltage line in response to potential difference between an input terminal and the first voltage line or its correspondent. The second transistor makes/breaks connection between a second voltage line and the output terminal in response to potential difference between a gate of the second transistor and the output terminal or its correspondent. The third transistor makes/breaks connection between a gate of the second transistor and a third voltage line in response to potential difference between the input terminal and the third voltage line or its correspondent. The first and second capacity elements are inserted in series between the input terminal and the gate of the second transistor. A junction between the first and second capacity elements is connected to the output terminal.

## Background
BACKGROUND
The present disclosure relates to an inverter circuit suitably applicable to, for example, a display using organic EL (Electro Luminescence) elements. Moreover, the disclosure relates to a display including the above-described inverter circuit.
In recent years, in the field of displays displaying an image, displays using, as light-emitting elements of pixels, current drive type optical elements of which light emission luminance changes depending on the value of a current flowing therethrough, for example, organic EL elements have been developed for commercialization. Unlike liquid crystal elements or the like, the organic EL elements are self-luminous elements. Therefore, in displays (organic. EL displays) using the organic EL elements, color gradation is obtained by controlling the value of a current flowing through the organic EL elements.
As in the case of liquid crystal displays, the organic EL displays are of a simple (passive) matrix system and an active matrix system as a drive system. In the former system, a configuration thereof is simple; however, there is an issue such as difficulty in achieving a large and high-definition display. Therefore, at present, the active matrix system has been increasingly developed. In this system, a current flowing through a light-emitting element arranged in each pixel is controlled by a driving transistor.
In the above-described driving transistor, in some cases, a threshold voltage Vth or mobility μ temporally changes, or the threshold voltage Vth or mobility μ varies from one pixel to another due to variations in a manufacturing process. In the case where the threshold voltage Vth or mobility μ varies from one pixel to another, the value of a current flowing through the driving transistor varies from one pixel to another, so even if the same voltage is applied to gates of the driving transistors, light emission luminance varies from one organic EL element to another, thereby impairing uniformity of a screen. Therefore, as described in Japanese Unexamined Patent Application Publication No. 2008-083272, a display having a function of correcting a change in the threshold voltage Vth or mobility μ has been developed.
Correction of the threshold voltage Vth or mobility μ is performed by a pixel circuit arranged in each pixel. For example, as illustrated in FIG. 71, the pixel circuit includes a driving transistor Tr100 controlling a current flowing through an organic EL element 111, a writing transistor Tr200 writing a voltage of a signal line DTL to the driving transistor Tr100, and a retention capacitor Cs. In other words, the pixel circuit has a 2Tr1C circuit configuration. The driving transistor Tr100 and the writing transistor Tr200 each are configured of, for example, an n-channel MOS type thin film transistor (TFT).
FIG. 70 illustrates an example of voltage waveforms applied to the pixel circuit and an example of changes in a gate voltage Vg and a source voltage Vs of the driving transistor Tr100. A part (A) in FIG. 70 illustrates a state where a signal voltage Vsig and an offset voltage Vofs are applied to the signal line DTL. A part (B) in FIG. 70 illustrates a state where a voltage Vdd turning the writing transistor Tr200 on and a voltage Vss turning the writing transistor Tr200 off are applied to a writing line WSL. A part (C) in FIG. 70 illustrates a state where a high voltage VccH and a low voltage VccL are applied to a power supply line PSL. Moreover, parts (D) and (E) in FIG. 70 illustrate states where the gate voltage Vg and the source voltage Vs of the driving transistor Tr100 are momentarily changed depending on the application of voltages to the power supply line PSL, the signal line DTL and the writing line WSL.
It is obvious from FIG. 70 that a WS pulse P is applied to the writing line WSL twice in a period of 1 H, and threshold correction is performed by a first WS pulse P and mobility correction and signal writing are performed by a second WS pulse P. In other words, in FIG. 70, WS pulses P are used for not only signal writing but also threshold correction and mobility correction of the driving transistor Tr100.
SUMMARY
In an active matrix system display, a horizontal drive circuit (not illustrated) driving a signal line DTL or a writing scanning circuit (not illustrated) sequentially selecting pixels 113 is basically configured by including a shift register (not illustrated), and includes buffer circuits (not illustrated) corresponding to rows or columns of the pixels 113, respectively. For example, the buffer circuits in the writing scanning circuit each are configured by connecting two inverter circuits to each other in series. In this case, for example, as illustrated in FIG. 72, the inverter circuits each have a single-channel type circuit configuration in which two n-channel MOS type transistors Tr1 and Tr2 are connected to each other in series. An inverter circuit 200 illustrated in FIG. 72 is inserted between a high-voltage wiring line LH to which a high-level voltage is applied and a low-voltage wiring line LL to which a low-level voltage is applied. A gate of the transistor Tr2 on a side close to the high-voltage wiring line LH is connected to the high-voltage wiring line LH, and a gate of the transistor Tr1 on a side close to the low-voltage wiring line LL is connected to an input terminal IN. Moreover, a connection point C between the transistor Tr1 and the transistor Tr2 is connected to an output terminal OUT.
In the inverter circuit 200, for example, as illustrated in FIG. 73, when a voltage (an input voltage Vin) of the input terminal IN is at a voltage Vss, a voltage (an output voltage Vout) of the output terminal OUT is not at a voltage Vdd but at a voltage Vdd−Vth. In other words, the voltage Vout of the output terminal OUT includes a threshold voltage Vth2 of the transistor Tr2; therefore the output voltage Vout is greatly affected by variations in the threshold voltage Vth2 of the transistor Tr2.
Therefore, it is considered that, for example, as illustrated in an inverter circuit 300 in FIG. 74, a gate and a drain of the transistor Tr2 are electrically separated from each other, and a high-voltage wiring line LH2 to which a higher voltage Vdd2 (≧Vdd+Vth2) than the voltage Vdd of the drain is applied is connected to the gate. Moreover, for example, a bootstrap type circuit configuration as illustrated in an inverter circuit 400 in FIG. 75 is considered. More specifically, a circuit configuration in which a transistor Tr10 is inserted between the gate of the transistor Tr2 and the high-voltage wiring line LH so as to connect a gate of a transistor Tr10 to the high-voltage wiring line LH and a capacity element C10 is inserted between a connection point D between the gate of the transistor Tr2 and a source of the transistor Tr10 and the connection point C is considered.
However, in any of the circuits in FIGS. 72, 74 and 75, even in the case where the input voltage Vin is high, that is, even in the case where the output voltage Vout is low, a current (a through current) flows from the high-voltage wiring line LH to the low-voltage wiring line LL through the transistors Tr1 and Tr2. As a result, power consumption in the inverter circuits is increased. Moreover, in the circuits in FIGS. 72, 74 and 75, for example, as illustrated in a point encircled by a broken line in a part (B) in FIG. 73, when the input voltage Vin is at the voltage Vdd, the output voltage Vout is not at the voltage Vss, and a peak value of the voltage Vout of the output terminal OUT varies. As a result, threshold correction or mobility correction in the driving transistor Tr100 varies from one pixel circuit 112 to another, thereby causing variations in luminance.
The above-described issues may occur not only in a scanning circuit of the display but also any other devices.
It is desirable to provide an inverter circuit allowed to prevent variations in an output voltage while reducing power consumption, and a display including the inverter circuit.
According to an embodiment of the disclosure, there is provided a first inverter circuit including: a first transistor, a second transistor and a third transistor each having channels of same conduction type; a first capacity element and a second capacity element; and an input terminal and an output terminal. In this case, the first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage (an input voltage) of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a gate voltage of the second transistor and a voltage (an output voltage) of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the second transistor and a third voltage line in response to a potential difference between the input voltage and a voltage of the third voltage line or a potential difference corresponding thereto. The first capacity element and the second capacity element are inserted in series between the input terminal and the gate of the second transistor, and an electrical connection point between the first capacity element and the second capacity element is electrically connected to the output terminal.
According to an embodiment of the disclosure, there is provided a first display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the first inverter circuit.
In the first inverter circuit and the first display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the third voltage line is arranged between the gate of the second transistor and the third voltage line. Moreover, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line. Therefore, for example, when gate voltages of the first transistor and the third transistor are switched from high to low, on-resistances of the first transistor and the third transistor are gradually increased to increase time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Further, for example, when the gate voltages of the first transistor and the third transistor are switched from low to high, the on-resistances of the first transistor and the third transistor are gradually reduced to reduce time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Moreover, in the embodiment of the disclosure, the first capacity element and the second capacity element are connected in series to the gate of the second transistor, and the first capacity element and the second capacity element are connected in parallel to the output terminal; therefore, the voltage transient of the output terminal is slower than that of the gate of the second transistor. As a result, for example, when the gate voltages of the first transistor and the third transistor are switched from high to low, a gate-source voltage of the second transistor exceeds a threshold voltage of the second transistor to turn the second transistor on, and immediately after that, the first transistor and the third transistor are turned off. At this time, the output voltage is changed to a voltage of the second voltage line. Moreover, for example, when the gate voltages of the first transistor and the third transistor are switched from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage is changed to a voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided a second inverter circuit including: a first transistor, a second transistor and a third transistor each having channels of same conduction type; a first capacity element and a second capacity element; and an input terminal and an output terminal. In this case, a gate of the first transistor is electrically connected to the input terminal, and one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal. One terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal. A gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the second transistor. The first capacity element and the second capacity element are inserted in series between the input terminal and the gate of the second transistor, and an electrical connection point between the first capacity element and the second capacity element is electrically connected to the output terminal.
According to an embodiment of the disclosure, there is provided a second display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the second inverter circuit.
In the second inverter circuit and the second display according to the embodiment of the disclosure, the third transistor having a gate connected to the input terminal is arranged between the gate of the second transistor and the third voltage line. Moreover, the first transistor having a gate connected to the input terminal is arranged between the source of the second transistor and the first voltage line. Therefore, for example, when gate voltages of the first transistor and the third transistor are switched from high to low, on-resistances of the first transistor and the third transistor are gradually increased to increase time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Further, for example, when the gate voltages of the first transistor and the third transistor are switched from low to high, the on-resistances of the first transistor and the third transistor are gradually reduced to reduce time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Moreover, in the embodiment of the disclosure, the first capacity element and the second capacity element are connected in series to the gate of the second transistor, and the first capacity element and the second capacity element are connected in parallel to the output terminal; therefore, the voltage transient of the output terminal is slower than that of the gate of the second transistor. As a result, for example, when the gate voltages of the first transistor and the third transistor are switched from high to low, a gate-source voltage of the second transistor exceeds a threshold voltage of the second transistor to turn the second transistor on, and immediately after that, the first transistor and the third transistor are turned off. At this time, the output voltage is changed to a voltage of the second voltage line. Moreover, for example, when the gate voltages of the first transistor and the third transistor are switched from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage is changed to a voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided a third inverter circuit including: a first transistor, a second transistor and a third transistor each having channels of same conduction type; an, input terminal and an output terminal; and a control element. The control element includes a first terminal electrically connected to the input terminal, a second terminal electrically connected to the output terminal, and a third terminal electrically connected to a gate of the second transistor. The control element allows a voltage transient of the second terminal to be slower than a voltage transient of the third terminal when a falling-edge voltage or a rising-edge voltage is applied to the first terminal. In this case, the first transistor makes or breaks electrical connection between the output terminal and the first voltage line in response to a potential difference between a voltage (an input voltage) of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a gate voltage of the second transistor and a voltage (an output voltage) of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the second transistor and a third voltage line in response to a potential difference between the input voltage and a voltage of the third voltage line or a potential difference corresponding thereto.
According to an embodiment of the disclosure, there is provided a third display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the third inverter circuit.
In the third inverter circuit and the third display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the third voltage line is arranged between the gate of the second transistor and the third voltage line. Moreover, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line.
Therefore, in the case where the first to third transistors are of an n-channel type, when gate voltages of the first transistor and the third transistor are switched from high to low, on-resistances of the first transistor and the third transistor are gradually increased to increase time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Further, when the gate voltages of the first transistor and the third transistor are switched from low to high, the on-resistances of the first transistor and the third transistor are gradually reduced to reduce time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. On the other hand, in the case where the first to third transistors are of a p-channel type, when the gate voltages of the first transistor and the third transistor are switched from low to high, the on-resistances of the first transistor and the third transistor are gradually increased to increase time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Further, when the gate voltages of the first transistor and the third transistor are switched from high to low, the on-resistances of the first transistor and the third transistor are gradually reduced to reduce time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line.
Moreover, in the third inverter circuit and the third display according to the embodiment of the disclosure, in the control element, the first terminal, the second terminal and the third terminal are electrically connected to the input terminal, the output terminal and the gate of the second transistor, respectively, and when a falling-edge voltage or a rising-edge voltage is applied to the first terminal, the voltage transient of the second terminal is slower than that of the third terminal.
Therefore, in the case where the first to third transistors are of an n-channel type, when gate voltages of the first transistor and the third transistor are switched from high to low, a gate-source voltage of the second transistor exceeds a threshold voltage of the second transistor to turn the second transistor on, and immediately after that, the first transistor and the third transistor are turned off. At this time, the output voltage is changed to a voltage of the second voltage line. Moreover, when the gate voltages of the first transistor and the third transistor are switched from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage is changed to a voltage of the first voltage line. On the other hand, in the case where the first to third transistors are of a p-channel type, when the gate voltages of the first transistor and the third transistor are switched from low to high, the gate-source voltage of the second transistor exceeds the threshold voltage of the second transistor to turn the second transistor on, and immediately after that, the first transistor and the third transistor are turned off. At this time, the output voltage is changed to the voltage of the second voltage line. Further, when the gate voltages of the first transistor and the third transistor are switched from high to low, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage is changed to the voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided a fourth inverter circuit including: a first transistor, a second transistor and a third transistor each having channels of same conduction type; an input terminal and an output terminal; and a control element. The control element includes a first terminal electrically connected to the input terminal, a second terminal electrically connected to the output terminal, and a third terminal electrically connected to a gate of the second transistor. The control element allows a voltage transient of the second terminal to be slower than a voltage transient of the third terminal when a falling-edge voltage or a rising-edge voltage is applied to the first terminal. In this case, a gate of the first transistor is electrically connected to the input terminal, one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal. One terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal. A gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the second transistor.
According to an embodiment of the disclosure, there is provided a fourth display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the fourth inverter circuit.
In the fourth inverter circuit and the fourth display according to the embodiment of the disclosure, the third transistor having a gate connected to the input terminal is arranged between the gate of the second transistor and the third voltage line. Moreover, the first transistor having a gate connected to the input terminal is arranged between the source of the second transistor and the first voltage line.
Therefore, in the case where the first to third transistors are of an n-channel type, when gate voltages of the first transistor and the third transistor are switched from high to low, on-resistances of the first transistor and the third transistor are gradually increased to increase time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Moreover, in the case where the gate voltages of the first transistor and the third transistor are switched from low to high, the on-resistances of the first transistor and the third transistor are gradually reduced to reduce time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. On the other hand, in the case where the first to third transistors are of a p-channel type, when the gate voltages of the first transistor and the third transistor are switched from low to high, the on-resistances of the first transistor and the third transistor are gradually increased to increase time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line. Further, when the gate voltages of the first transistor and the third transistor are switched from high to low, the on-resistances of the first transistor and the third transistor are gradually reduced to reduce time necessary to charge the gate and the source of the second transistor to the voltages of the first voltage line and the third voltage line.
Moreover, in the fourth inverter circuit and the fourth display according to the embodiment, in the control element, the first terminal, the second terminal and the third terminal are electrically connected to the input terminal, the output terminal and the gate of the second transistor, respectively, and when a falling-edge voltage is applied to the first terminal, the voltage transient of the second terminal is slower than that of the third terminal.
Therefore, in the case where the first to third transistors are of a n-channel type, when gate voltages of the first transistor and the third transistor are switched from high to low, a gate-source voltage of the second transistor exceeds a threshold voltage of the second transistor to turn the second transistor on, and immediately after that, the first transistor and the third transistor are turned off. At this time, the output voltage is changed to a voltage of the second voltage line. Moreover, when the gate voltages of the first transistor and the third transistor are switched from low to high, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage is changed to a voltage of the first voltage line. On the other hand, in the case where the first to third transistors are of a p-channel type, when the gate voltages of the first transistor and the third transistor are switched from low to high, the gate-source voltage of the second transistor exceeds the threshold voltage of the second transistor to turn the second transistor on, and immediately after that, the first transistor and the third transistor are turned off. At this time, the output voltage is changed to the voltage of the second voltage line. Further, when the gate voltages of the first transistor and the third transistor are switched from high to low, the first transistor and the third transistor are turned on, and immediately after that, the second transistor is turned off. At this time, the output voltage is changed to the voltage of the first voltage line.
The first to fourth inverter circuits and the first to fourth displays according to the embodiment of the disclosure may further include a delay element inputting, to the gate of the third transistor, a voltage with a waveform obtained by delaying a waveform of a signal voltage applied to the input terminal. In such a case, a slower signal than a signal applied to the gate of the first transistor is applied to the gate of the third transistor; therefore, when the gate voltages of the first transistor and the third transistor are switched from high to low or from low to high, time necessary for the gate-source voltage of the second transistor to exceed the threshold voltage of the second transistor is allowed to be reduced.
According to an embodiment of the disclosure, there is provided a fifth inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor each having channels of same conduction type; a first capacity element and a second capacity element; and an input terminal and an output terminal. In this case, the first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage (an input voltage) of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a voltage of a first terminal which is one terminal of a source and a drain of the fifth transistor and a voltage (an output voltage) of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the fifth transistor and a third voltage line in response to a potential difference between the input voltage and a voltage of the third voltage line or a potential difference corresponding thereto. The fourth transistor makes or breaks electrical connection between the first terminal and a fourth voltage line in response to a potential difference between the input voltage and a voltage of the fourth voltage line or a potential difference corresponding thereto. The first capacity element and the second capacity element are inserted in series between the input terminal and the gate of the fifth transistor, and an electrical connection point between the first capacity element and the second capacity element is electrically connected to the first terminal. The fifth transistor makes or breaks electrical connection between a fifth voltage line and the first terminal in response to a voltage between terminals of the first capacity element or a voltage corresponding thereto.
According to an embodiment of the disclosure, there is provided a fifth display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the fifth inverter circuit.
In the fifth inverter circuit and the fifth display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the third voltage line is arranged between the gate of the fifth transistor and the third voltage line. Moreover, the fourth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the fourth voltage line is arranged between the gate of the second transistor and the fourth voltage line. Further, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line. Therefore, for example, when gate voltages of the third transistor, the fourth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line. Further, for example, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line. Moreover, in the embodiment of the disclosure, the first capacity element and the second capacity element connected in series to each other are inserted between the input terminal and the gate of the fifth transistor. Further, the source of the fifth transistor is electrically connected between the first capacity element and the second capacity element. Therefore, the first capacity element and the second capacity element are connected in parallel to the source of the fifth transistor, and the first capacity element and the second capacity element are connected in series to the gate of the fifth transistor; therefore, a voltage transient of the source of the fifth transistor is slower than that of the gate of the fifth transistor. As a result, for example, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the fourth transistor is turned off. At this time, while the second transistor is turned on, the first transistor is turned off; therefore, the output voltage is changed to a voltage of the second voltage line. Moreover, for example, when the gate voltages of the fourth transistor and the first transistor are switched from low to high, the fourth transistor and the first transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided a sixth inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor each having channels of same conduction type; a first capacity element and a second capacity element; and an input terminal and an output terminal. In this case, a gate of the first transistor is electrically connected to the input terminal, one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal. One terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal. A gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the fifth transistor. A gate of the fourth transistor is electrically connected to the input terminal, one terminal of a drain and a source of the fourth transistor is electrically connected to a fourth voltage line, and the other terminal of the fourth transistor is electrically connected to a gate of the second transistor. One terminal of a drain and a source of the fifth transistor is electrically connected to a fifth voltage line, and the other terminal of the fifth transistor is electrically connected to the gate of the second transistor. The first capacity element and the second capacity element are inserted in series between the input terminal and the gate of the fifth transistor, and an electrical connection point between the first capacity element and the second capacity element is electrically connected to the first terminal.
According to an embodiment of the disclosure, there is provided a sixth display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the sixth inverter circuit.
In the sixth inverter circuit and the sixth display according to the embodiment of the disclosure, the third transistor having a gate connected to the input terminal is arranged between the gate of the fifth transistor and the third voltage line. Moreover, the fourth transistor having a gate connected to the input terminal is arranged between the gate of the second transistor and the fourth voltage line. Further, the first transistor having a gate connected to the input terminal is arranged between the source of the second transistor and the first voltage line. Therefore, for example, when gate voltages of the third transistor, the fourth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line. Moreover, for example, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line. Moreover, the first capacity element and the second capacity element connected in series to each other are inserted between the input terminal and the gate of the fifth transistor. Further, the source of the fifth transistor is electrically connected between the first capacity element and the second capacity element. Therefore, the first capacity element and the second capacity element are connected in parallel to the source of the fifth transistor, and the first capacity element and the second capacity element are connected in series to the gate of the fifth transistor; therefore, a voltage transient of the source of the fifth transistor is slower than that of the gate of the fifth transistor. As a result, for example, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the fourth transistor is turned off. At this time, while the second transistor is turned on, the first transistor is turned off; therefore, the output voltage is changed to a voltage of the second voltage line. Moreover, for example, when the gate voltages of the fourth transistor and the first transistor are switched from low to high, the fourth transistor and the first transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided a seventh inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type; a first capacity element and a second capacity element; and an input terminal and an output terminal. In this case, the first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage (an input voltage) of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a gate voltage of the second transistor and a voltage (an output voltage) of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the fifth transistor and a third voltage line in response to a potential difference between the input voltage and a voltage of the third voltage line or a potential difference corresponding thereto. The fourth transistor makes or breaks electrical connection between a first terminal which is one terminal of a source and a drain of the fifth transistor and a fourth voltage line in response to a potential difference between the input voltage and a voltage of the fourth voltage line or a potential difference corresponding thereto. The first capacity element and the second capacity element are inserted in series between the input terminal and the gate of the fifth transistor, and an electrical connection point between the first capacity element and the second capacity element is electrically connected to the first terminal. The fifth transistor makes or breaks electrical connection between a fifth voltage line and the first terminal in response to a voltage between terminals of the first capacity element or a voltage corresponding thereto. The sixth transistor makes or breaks electrical connection between a gate of the second transistor and a sixth voltage line in response to a potential difference between the input voltage and a voltage of the sixth voltage line or a potential difference corresponding thereto. The seventh transistor makes or breaks electrical connection between the first terminal and the gate of the second transistor in response to a gate voltage of the fifth transistor or a voltage corresponding thereto.
According to an embodiment of the disclosure, there is provided a seventh display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the seventh inverter circuit.
In the seventh inverter circuit and the seventh display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the third voltage line is arranged between the gate of the fifth transistor and the third voltage line. Moreover, the fourth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the fourth voltage line is arranged between the source of the fifth transistor and the fourth voltage line. Further, the sixth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the sixth voltage line is arranged between the gate of the second transistor and the sixth voltage line. Moreover, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line. Therefore, for example, when gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line, the sixth voltage line and the first voltage line. Moreover, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line, the sixth voltage line and the first voltage line. Further, in the embodiment of the disclosure, the first capacity element and the second capacity element connected in series to each other are inserted between the input terminal and the gate of the fifth transistor. Moreover, the first terminal of the fifth transistor is electrically connected between the first capacity element and the second capacity element. Therefore, the first capacity element and the second capacity element are connected in parallel to the source of the fifth transistor, and the first capacity element and the second capacity element are connected in series to the gate of the fifth transistor; therefore, a voltage transient of the source of the fifth transistor is slower than that of the gate of the fifth transistor. As a result, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the fourth transistor and the sixth transistor are turned off. At this time, while the second transistor is turned on, the first transistor is turned off; therefore, the output voltage is changed to a voltage of the second voltage line. Moreover, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the third transistor, the fourth transistor, the sixth transistor and the first transistor are turned on, and the immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided an eighth inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor each having channels of same conduction type; an input terminal and an output terminal; and a control element. The control element includes a second terminal electrically connected to the input terminal, a third terminal electrically connected to a first terminal which is one terminal of a source and a drain of the fifth transistor, and a fourth terminal electrically connected to a gate of the fifth transistor. The control element allows a voltage transient of the third terminal to be slower than a voltage transient of the fourth terminal when a falling-edge voltage or a rising-edge voltage is applied to the second terminal. The first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage (an input voltage) of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a voltage of the first terminal and a voltage (an output voltage) of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the fifth transistor and a third voltage line in response to a potential difference between the input voltage and a voltage of the third voltage line or a potential difference corresponding thereto. The fourth transistor makes or breaks electrical connection between the first terminal and a fourth voltage line in response to a potential difference between the input voltage and a voltage of the fourth voltage line or a potential difference corresponding thereto. The fifth transistor makes or breaks electrical connection between a fifth voltage line and the first terminal in response to a voltage between the fourth terminal and the third terminal or a voltage corresponding thereto.
According to an embodiment of the disclosure, there is provided an eighth display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the eighth inverter circuit.
In the eighth inverter circuit and the eighth display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the third voltage line is arranged between the gate of the fifth transistor and the third voltage line. Moreover, the fourth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the fourth voltage line is arranged between the gate of the second transistor and the fourth voltage line. Further, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line.
Therefore, for example, in the case where the first to fifth transistors are of an n-channel type, when gate voltages of the third transistor, the fourth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line. On the other hand, in the case where the first to fifth transistors are of a p-channel type, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from low to high, on-resistances of the third transistor, the fourth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from high to low, the on-resistances of the third transistor, the fourth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line and the first voltage line.
Moreover, in the eighth inverter circuit and the eighth display according to the embodiment of the disclosure, when a falling-edge voltage or a rising-edge voltage is applied to the second terminal electrically connected to the input terminal, a voltage transient of the third terminal electrically connected to the source of the fifth transistor is slower than that of the fourth terminal electrically connected to the gate of the fifth transistor.
As a result, in the case where the first to fifth transistors are of an n-channel type, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the fourth transistor is turned off. At this time, while the second transistor is turned on, the first transistor is turned off; therefore, the output voltage is changed to a voltage of the second voltage line. Moreover, when the gate voltages of the fourth transistor and the first transistor are switched from low to high, the fourth transistor and the first transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line. On the other hand, in the case where the first to fifth transistors are of a p-channel type, when the gate voltages of the third transistor, the fourth transistor and the first transistor are switched from low to high, the gate-source voltage of the fifth transistor exceeds the threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the fourth transistor is turned off. At this time, while the second transistor is turned on, the first transistor is turned off; therefore, the output voltage is changed to the voltage of the second voltage line. Moreover, when the gate voltages of the fourth transistor and the first transistor are switched from high to low, the fourth transistor and the first transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to the voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided a ninth inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type; an input terminal and an output terminal; and a control element. The control element includes a second terminal electrically connected to the input terminal, a third terminal electrically connected to a first terminal which is one terminal of a source and a drain of the fifth transistor, and a fourth terminal electrically connected to a gate of the fifth transistor. The control element allows a voltage transient of the third terminal to be slower than a voltage transient of the fourth terminal when a falling-edge voltage or a rising-edge voltage is applied to the second terminal. The first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage (an input voltage) of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a gate voltage of the second transistor and a voltage (an output voltage) of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the fifth transistor and a third voltage line in response to a potential difference between the input voltage and a voltage of the third voltage line or a potential difference corresponding thereto. The fourth transistor makes or breaks electrical connection between the first terminal and a fourth voltage line in response to a potential difference between the input voltage and a voltage of the fourth voltage line or a potential difference corresponding thereto. The fifth transistor makes or breaks electrical connection between a fifth voltage line and the first terminal in response to a voltage between the fourth terminal and the third terminal or a voltage corresponding thereto. The sixth transistor makes or breaks electrical connection between a gate of the second transistor and a sixth voltage line in response to a potential difference between the input voltage and a voltage of the sixth voltage line or a potential difference corresponding thereto. The seventh transistor makes or breaks electrical connection between the first terminal and the gate of the second transistor in response to a gate voltage of the fifth transistor or a voltage corresponding thereto.
According to an embodiment of the disclosure, there is provided a ninth display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the ninth inverter circuit.
In the ninth inverter circuit and the ninth display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the third voltage line is arranged between the gate of the fifth transistor and the third voltage line. Moreover, the fourth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the fourth voltage line is arranged between the source of the fifth transistor and the fourth voltage line. Further, the sixth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the sixth voltage line is arranged between the gate of the second transistor and the sixth voltage line. Moreover, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line.
Therefore, in the case where the first to seventh transistors are of an n-channel type, when gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line, the sixth voltage line and the first voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line, the sixth voltage line and the first voltage line. On the other hand, in the case where the first to seventh transistors are of a p-channel type, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line, the sixth voltage line and the first voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, the on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor and the second transistor to the voltages of the third voltage line, the fourth voltage line, the sixth voltage line and the first voltage line.
Moreover, in the ninth inverter circuit and the ninth display according to the embodiment of the disclosure, when a falling-edge voltage or a rising-edge voltage is applied to the second terminal electrically connected to the input terminal, a voltage transient of the third terminal electrically connected to the source of the fifth transistor is slower than that of the fourth terminal electrically connected to the gate of the fifth transistor.
As a result, in the case where the first to seventh transistors are of an n-channel type, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the fourth transistor and the sixth transistor are turned off. At this time, while the second transistor is turned on, the first transistor is turned off; therefore, the output voltage is changed to a voltage of the second voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the third transistor, the fourth transistor, the sixth transistor and the first transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line. On the other hand, in the case where the first to seventh transistors are of a p-channel type, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the gate-source voltage of the fifth transistor exceeds the threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the fourth transistor and the sixth transistor are turned off. At this time, while the second transistor is turned on, the first transistor is turned off; therefore, the output voltage is changed to the voltage of the second voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, the third transistor, the fourth transistor, the sixth transistor and the first transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to the voltage of the first voltage line.
The fifth to ninth inverter circuits and the fifth to ninth displays according to the embodiment of the disclosure may further include a delay element inputting, to the gate of the third transistor, a voltage with a waveform obtained by delaying a waveform of a signal voltage applied to the input terminal. In such a case, a slower signal than a signal applied to the gates of the first transistor and the fourth transistor is applied to the gate of the third transistor. As a result, when the gate voltages of the first transistor, the third transistor and the fourth transistor are switched from high to low or from low to high, time necessary for the gate-source voltage of the fifth transistor to exceed the threshold voltage of the fifth transistor is allowed to be reduced.
According to an embodiment of the disclosure, there is provided a tenth inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type. The tenth inverter circuit further includes a first capacity element, a second capacity element and a third capacity element; and an input terminal and an output terminal. In this case, the first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage (an input voltage) of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a gate voltage of the second transistor and a voltage of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the fifth transistor and a third voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the third voltage line or a potential difference corresponding thereto. The fourth transistor makes or breaks electrical connection between a first terminal which is one terminal of a source and a drain of the fifth transistor and a fourth voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the fourth voltage line or a potential difference corresponding thereto. The first capacity element and the second capacity element are inserted in series between the input terminal and a gate of the fifth transistor, and an electrical connection point between the first capacity element and the second capacity element is electrically connected to the first terminal. The third capacity element is inserted between a gate of the second transistor and the output terminal. The fifth transistor makes or breaks electrical connection between a fifth voltage line and the first terminal in response to a voltage between terminals of the first capacity element or a voltage corresponding thereto. The sixth transistor makes or breaks electrical connection between the gate of the second transistor and a sixth voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the sixth voltage line or a potential difference corresponding thereto. The seventh transistor makes or breaks electrical connection between a seventh voltage line and the gate of the second transistor in response to a potential difference between the voltage of the first terminal and the gate voltage of the second transistor or a potential difference corresponding thereto.
According to an embodiment of the disclosure, there is provided a tenth display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the tenth inverter circuit.
In the tenth inverter circuit and the tenth display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the third voltage line is arranged between the gate of the fifth transistor and the third voltage line. Moreover, the fourth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the fourth voltage line is arranged between the gate of the seventh transistor and the fourth voltage line. Further, the sixth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the sixth voltage line is arranged between the gate of the second transistor and the sixth voltage line. Moreover, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line. Therefore, for example, when gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor. Moreover, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor. Moreover, in the embodiment of the disclosure, the first capacity element and the second capacity element connected in series to each other are inserted between the input terminal and the gate of the fifth transistor. Further, the source of the fifth transistor is electrically connected between the first capacity element and the second capacity element. Therefore, the first capacity element and the second capacity element are connected in parallel to the source of the fifth transistor, and the first capacity element and the second capacity element are connected in series to the gate of the fifth transistor; therefore, a voltage transient of the source of the fifth transistor is slower than that of the gate of the fifth transistor. Therefore, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the third transistor is turned off. At this time, while the seventh transistor is turned on, the fourth transistor is turned off, and while the second transistor is turned on, the sixth transistor is turned off, and after that, the seventh transistor is turned off. As a result, the output voltage is changed to a voltage of the second voltage line. Moreover, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the third transistor, the fourth transistor and the sixth transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided an eleventh inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type. The eleventh inverter circuit further includes: a first capacity element, a second capacity element and a third capacity element; and an input terminal and an output terminal. In this case, a gate of the first transistor is electrically connected to the input terminal, one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal. One terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal. A gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the fifth transistor. A gate of the fourth transistor is electrically connected to the input terminal, one terminal of a drain and a source of the fourth transistor is electrically connected to a fourth voltage line, and the other terminal of the fourth transistor is electrically connected to a gate of the seventh transistor. One terminal of a drain and a source of the fifth transistor is electrically connected to a fifth voltage line, and the other terminal of the fifth transistor is electrically connected to the gate of the seventh transistor. A gate of the sixth transistor is electrically connected to the input terminal, one terminal of a drain and a source of the sixth transistor is electrically connected to a sixth voltage line, and the other terminal of the sixth transistor is connected to a gate of the second transistor. One terminal of a drain and a source of the seventh transistor is electrically connected to a seventh voltage line, and the other terminal of the seventh transistor is electrically connected to the gate of the second transistor. The first capacity element and the second capacity element are inserted in series between the input terminal and a gate of the fifth transistor. An electrical connection point between the first capacity element and the second capacity element is electrically connected to the gate of the seventh transistor. The third capacity element is inserted between the gate of the second transistor and the output terminal.
According to an embodiment of the disclosure, there is provided an eleventh display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the eleventh inverter circuit.
In the eleventh inverter circuit and the eleventh display according to the embodiment of the disclosure, the third transistor having a gate connected to the input terminal is arranged between the gate of the fifth transistor and the third voltage line. The fourth transistor having a gate connected to the input terminal is arranged between the gate of the seventh transistor and the fourth voltage line. The sixth transistor having a gate connected to the input terminal is arranged between the gate of the second transistor and the sixth voltage line. The first transistor having a gate connected to the input terminal is arranged between the source of the second transistor and the first voltage line. Therefore, for example, when gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor. Moreover, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor. Moreover, in the embodiment of the disclosure, the first capacity element and the second capacity element connected in series to each other are inserted between the input terminal and the gate of the fifth transistor. Further, the source of the fifth transistor is electrically connected between the first capacity element and the second capacity element. Therefore, the first capacity element and the second capacity element are connected in parallel to the source of the fifth transistor, and the first capacity element and the second capacity element are connected in series to the gate of the fifth transistor; therefore, a voltage transient of the source of the fifth transistor is slower than that of the gate of the fifth transistor. Therefore, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the third transistor is turned off. At this time, while the seventh transistor is turned on, the fourth transistor is turned off, and while the second transistor is turned on, the sixth transistor is turned off, and after that, the seventh transistor is turned off. As a result, the output voltage is changed to a voltage of the second voltage line. Moreover, for example, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the third transistor, the fourth transistor and the sixth transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line.
According to an embodiment of the disclosure, there is provided a twelfth inverter circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type. The twelfth inverter circuit further includes an input terminal and an output terminal; and a control element. The control element includes a second terminal electrically connected to the input terminal, a third terminal electrically connected to a gate of the seventh transistor, and a fourth terminal electrically connected to a gate of the fifth transistor. The control element allows a voltage transient of the third terminal to be slower than a voltage transient of the fourth terminal when a falling-edge voltage or a rising-edge voltage is applied to the second terminal. The first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto. The second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a gate voltage of the second transistor and a voltage of the output terminal or a potential difference corresponding thereto. The third transistor makes or breaks electrical connection between a gate of the fifth transistor and a third voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the third voltage line or a potential difference corresponding thereto. The fourth transistor makes or breaks electrical connection between a first terminal which is one terminal of a source and a drain of the fifth transistor and a fourth voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the fourth voltage line or a potential difference corresponding thereto. The fifth transistor makes or breaks electrical connection between a fifth voltage line and the first terminal in response to a voltage between the fourth terminal and the third terminal or a voltage corresponding thereto. The sixth transistor makes or breaks electrical connection between a gate of the second transistor and a sixth voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the sixth voltage line or a potential difference corresponding thereto. The seventh transistor makes or breaks electrical connection between a seventh voltage line and the gate of the second transistor in response to a potential difference between the voltage of the first terminal and the gate voltage of the second transistor or a potential difference corresponding thereto.
According to an embodiment of the disclosure, there is provided a twelfth display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form. The drive section includes a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, and each of the inverter circuits includes the same constituent elements as those in the twelfth inverter circuit.
In the twelfth inverter circuit and the twelfth display according to the embodiment of the disclosure, the third transistor performing an on/off operation in response to a potential difference between an input voltage and the voltage of the third voltage line is arranged between the gate of the fifth transistor and the third voltage line. Moreover, the fourth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the fourth voltage line is arranged between the gate of the seventh transistor and the fourth voltage line. Further, the sixth transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the sixth voltage line is arranged between the gate of the second transistor and the sixth voltage line. Moreover, the first transistor performing an on/off operation in response to a potential difference between the input voltage and the voltage of the first voltage line is arranged between the source of the second transistor and the first voltage line.
Therefore, in the case where the first to seventh transistors are of an n-channel type, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor. On the other hand, in the case where the first to seventh transistors are of a p-channel type, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually increased to increase time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, the on-resistances of the third transistor, the fourth transistor, the sixth transistor and the first transistor are gradually reduced to reduce time necessary to charge the gates and the sources of the fifth transistor, the seventh transistor and the second transistor to the voltages of the voltage lines corresponding to the third transistor, the fourth transistor, the sixth transistor and the first transistor.
Moreover, in the twelfth inverter circuit and the twelfth display according to the embodiment of the disclosure, when a falling-edge voltage is applied to the second terminal electrically connected to the input terminal, a voltage transient of the third terminal electrically connected to the source of the fifth transistor is slower than that of the fourth terminal electrically connected to the gate of the fifth transistor.
Therefore, in the case where the first to seventh transistors are of an n-channel type, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, a gate-source voltage of the fifth transistor exceeds a threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the third transistor is turned off. At this time, while the seventh transistor is turned on, the fourth transistor is turned off, and while the second transistor is turned on, the sixth transistor is turned off, and after that, the seventh transistor is turned off. As a result, the output voltage is changed to a voltage of the second voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the third transistor, the fourth transistor and the sixth transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to a voltage of the first voltage line. On the other hand, in the case where the first to seventh transistors are of a p-channel type; when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from low to high, the gate-source voltage of the fifth transistor exceeds the threshold voltage of the fifth transistor to turn the fifth transistor on, and immediately after that, the third transistor is turned off. At this time, while the seventh transistor is turned on, the fourth transistor is turned off, and while the second transistor is turned on, the sixth transistor is turned off, and after that, the seventh transistor is turned off. As a result, the output voltage is changed to the voltage of the second voltage line. Moreover, when the gate voltages of the third transistor, the fourth transistor, the sixth transistor and the first transistor are switched from high to low, the third transistor, the fourth transistor and the sixth transistor are turned on, and immediately after that, the fifth transistor is turned off. At this time, while the second transistor is turned off, the first transistor is turned on; therefore, the output voltage is changed to the voltage of the first voltage line.
The tenth to twelfth inverter circuits and the tenth to twelfth displays according to the embodiment of the disclosure may further include a delay element inputting, to the gate of the third transistor, a voltage with a waveform obtained by delaying a waveform of a signal voltage applied to the input terminal. In such a case, a slower signal than a signal applied to the gate of the first transistor is applied to the gate of the third transistor; therefore, when the gate voltages of the first transistor and the third transistor are switched from high to low or from low to high, time necessary for the voltage between the gate of the fifth transistor and the first terminal to exceed the threshold voltage of the fifth transistor is allowed to be reduced.
In the first to fourth inverter circuits and the first to fourth displays according to the embodiment of the disclosure, a period where the first transistor and the second transistor are simultaneously turned on is almost eliminated; therefore, a current (a through current) hardly flows between the voltage lines through the first transistor and the second transistor. Accordingly, power consumption is allowed to be reduced. Moreover, when the gate voltages of the first transistor and the third transistor are switched from high to low, the output voltage is changed to the voltage of the second voltage line or the voltage of the first voltage line, and when the gate voltages of the first transistor and the third transistor are switched from low to high, the output voltage is changed to a voltage opposite to the above-described voltage; therefore, variations in the output voltage is allowed to be eliminated. As a result, for example, variations in threshold correction or mobility correction in a driving transistor from one pixel circuit to another are allowed to be reduced, and variations in luminance from one pixel to another are allowed to be reduced.
Moreover, in the first to fourth inverter circuits and the first to fourth displays according to the embodiment of the disclosure, in the case where a voltage with a voltage waveform obtained by delaying a waveform of a signal voltage applied to the input terminal is applied to the gate of the third transistor, when the gate voltages of the first transistor and the third transistor are switched from high to low or from low to high, time necessary for the gate-source voltage of the second transistor to exceed the threshold voltage of the second transistor is allowed to be reduced. Therefore, the speed of circuit operation is allowed to be increased.
In the fifth to ninth inverter circuits and the fifth to ninth displays according to the embodiment of the disclosure, a period where the first transistor and the second transistor are simultaneously turned on or a period where the fourth transistor and the fifth transistor are simultaneously turned on is almost eliminated; therefore, a current (a through current) hardly flows between the voltage lines through these transistors; therefore, power consumption is allowed to be reduced. Moreover, when the gate voltage of the first transistor is switched from high to low, the output voltage is changed to the voltage of the second voltage line or the voltage of the first voltage line, and when the gate voltage of the first transistor is switched from low to high, the output voltage is changed to a voltage opposite to the above-described voltage. Therefore, a shift of a peak value of the output voltage from a desired value is allowed to be reduced. As a result, for example, variations in threshold correction or mobility correction in a driving transistor from one pixel circuit to another are allowed to be reduced, and variations in luminance from one pixel to another are allowed to be reduced.
Moreover, in the fifth to ninth inverter circuits and the fifth to ninth displays according to the embodiment of the disclosure, in the case where a voltage with a voltage waveform obtained by delaying a waveform of a signal voltage applied to the input terminal is applied to the gate of the third transistor, when the gate voltage of the first transistor is switched from high to low or from low to high, time necessary for the gate-source voltage of the fifth transistor to exceed the threshold voltage of the fifth transistor is allowed to be reduced. Therefore, the speed of circuit operation is allowed to be increased.
In the tenth to twelfth inverter circuits and the tenth to twelfth displays according to the embodiment of the disclosure, a period where the first transistor and the second transistor are simultaneously turned on is almost eliminated; therefore, a current (a through current) hardly flows between the voltage lines through the first transistor and the second transistor. Accordingly, power consumption is allowed to be reduced. Moreover, when the gate voltage of the first transistor is switched from high to low, the output voltage is changed to the voltage of the second voltage line or the voltage of the first voltage line, and when the gate voltage of the first transistor is switched from low to high, the output voltage is changed to a voltage opposite to the above-described voltage. Therefore, a shift of a peak value of the output voltage from a desired value is allowed to be reduced. As a result, for example, variations in threshold correction or mobility correction in a driving transistor from one pixel circuit to another are allowed to be reduced, and variations in luminance from one pixel to another are allowed to be reduced.
Moreover, in the embodiment of the disclosure, the first capacity element and the second capacity element are not connected directly to the output terminal; therefore, a coupling amount applied to the gate and the source of the fifth transistor is not affected by parasitic capacitance in an output stage. Therefore, a voltage between the gate of the fifth transistor and the first terminal is allowed to be increased, thereby increasing the speed of the inverter circuit. Moreover, in the embodiment of the disclosure, only one common voltage line on a low voltage side and only one common voltage line on a high voltage side may be arranged. Therefore, in such a case, it is not necessary to increase the resistance to pressure of the inverter circuit.
Further, in the embodiment of the disclosure, in the case where a voltage with a voltage waveform obtained by delaying a waveform of a signal voltage applied to the input terminal is applied to the gate of the third transistor, when the gate voltages of the first transistor, the third transistor, the fourth transistor and the sixth transistor are switched from high to low or from low to high, time necessary for a voltage between the gate of the fifth transistor and the fourth terminal to exceed the threshold voltage of the fifth transistor is allowed to be reduced. Therefore, the speed of circuit operation is allowed to be further increased.
Other and further objects, features and advantages of the disclosure will appear more fully from the following description.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram illustrating an example of an inverter circuit according to a first embodiment of the disclosure.
FIG. 2 is a waveform chart illustrating an example of input/output signal waveforms of the inverter circuit in FIG. 1.
FIG. 3 is a waveform chart illustrating an example of an operation of the inverter circuit in FIG. 1.
FIG. 4 is a circuit diagram for describing an example of an operation of the inverter circuit in FIG. 1.
FIG. 5 is a circuit diagram for describing an example of an operation following FIG. 4.
FIG. 6 is a circuit diagram for describing an example of an operation following FIG. 5.
FIG. 7 is a circuit diagram for describing an example of an operation following FIG. 6.
FIG. 8 is a circuit diagram for describing an example of an operation following FIG. 7.
FIG. 9 is a circuit diagram illustrating an example of an inverter circuit according to a second embodiment of the disclosure.
FIGS. 10A to 10D are circuit diagrams illustrating variations of a delay element in FIG. 9.
FIG. 11 is a waveform chart illustrating an example of an operation of the inverter circuit in FIG. 9.
FIG. 12 is a waveform chart illustrating an example of input/output signal waveforms of the delay element in FIG. 9.
FIG. 13 is a circuit diagram for describing an example of an operation of the inverter circuit in FIG. 9.
FIG. 14 is a circuit diagram illustrating a modification of the inverter circuit in FIG. 9.
FIG. 15 is a waveform chart illustrating an example of an operation of the inverter circuit in FIG. 14.
FIG. 16 is a circuit diagram illustrating another modification of the inverter circuit in FIG. 9.
FIG. 17 is a circuit diagram illustrating another modification of the inverter circuit in FIG. 14.
FIG. 18 is a circuit diagram illustrating an example of an inverter circuit according to a third embodiment of the disclosure.
FIG. 19 is a waveform chart illustrating an example of input/output signal waveforms of the inverter circuit in FIG. 18.
FIG. 20 is a waveform chart illustrating an example of an operation of the inverter circuit in FIG. 18.
FIG. 21 is a circuit diagram for describing an example of an operation of the inverter circuit in FIG. 18.
FIG. 22 is a circuit diagram for describing an example of an operation following FIG. 21.
FIG. 23 is a circuit diagram for describing an example of an operation following FIG. 22.
FIG. 24 is a circuit diagram for describing an example of an operation following FIG. 23.
FIG. 25 is a circuit diagram for describing an example of an operation following FIG. 24.
FIG. 26 is a circuit diagram for describing an example of an operation following FIG. 25.
FIG. 27 is a circuit diagram illustrating an example of an inverter circuit according to a fourth embodiment of the disclosure.
FIG. 28 is a waveform chart illustrating an example of an operation of the inverter circuit in FIG. 27.
FIG. 29 is a circuit diagram for describing an example of an operation of the inverter circuit in FIG. 27.
FIG. 30 is a circuit diagram for describing an example of an operation following FIG. 29.
FIG. 31 is a circuit diagram for describing an example of an operation following FIG. 30.
FIG. 32 is a circuit diagram for describing an example of an operation following FIG. 31.
FIG. 33 is a circuit diagram for describing an example of an operation following FIG. 32.
FIG. 34 is a circuit diagram for describing an example of an operation following FIG. 33.
FIG. 35 is a circuit diagram illustrating a modification of the inverter circuit in FIG. 27.
FIG. 36 is a circuit diagram illustrating another modification of the inverter circuit in FIG. 27.
FIG. 37 is a circuit diagram illustrating an example of the inverter circuit in FIG. 18 including a delay element.
FIG. 38 is a circuit diagram illustrating an example of the inverter circuit in FIG. 27 including a delay element.
FIGS. 39A to 39D are circuit diagrams illustrating variations of the delay element in FIGS. 37 and 38.
FIG. 40 is a waveform chart illustrating an example of an operation of the inverter circuits in FIGS. 37 and 38.
FIG. 41 is a waveform chart illustrating an example of input/output signal waveforms of the delay element in FIGS. 37 and 38.
FIG. 42 is a circuit diagram for describing an example of an operation of the inverter circuits in FIGS. 37 and 38.
FIG. 43 is a circuit diagram illustrating an example of an inverter circuit according to a fifth embodiment of the disclosure.
FIG. 44 is a waveform chart illustrating an example of input/output signal waveforms of the inverter circuit in FIG. 43.
FIG. 45 is a waveform chart illustrating an example of an operation of the inverter circuit in FIG. 43.
FIG. 46 is a circuit diagram for describing an example of an operation of the inverter circuit in FIG. 43.
FIG. 47 is a circuit diagram for describing an example of an operation following FIG. 46.
FIG. 48 is a circuit diagram for describing an example of an operation following FIG. 47.
FIG. 49 is a circuit diagram for describing an example of an operation following FIG. 48.
FIG. 50 is a circuit diagram for describing an example of an operation following FIG. 49.
FIG. 51 is a circuit diagram for describing an example of an operation following FIG. 50.
FIG. 52 is a circuit diagram illustrating an example of an inverter circuit according to a sixth embodiment of the disclosure.
FIG. 53 is a circuit diagram for describing parasitic capacitance of the inverter circuit in FIG. 43.
FIG. 54 is a circuit diagram for describing a parasitic capacitance of the inverter circuit in FIG. 52.
FIG. 55 is a waveform chart for describing an example of an operation of the inverter circuit in FIG. 52.
FIG. 56 is a waveform chart for describing another example of the operation of the inverter circuit in FIG. 52.
FIG. 57 is a waveform chart for describing still another example of the operation of the inverter circuit in FIG. 52.
FIG. 58 is a circuit diagram illustrating a modification of the inverter circuit in FIG. 52.
FIG. 59 is a circuit diagram illustrating another modification of the inverter circuit in FIG. 52.
FIG. 60 is a waveform chart for describing an example of an operation of the inverter circuit in FIG. 59.
FIG. 61 is a circuit diagram illustrating an example of the inverter circuit in FIG. 43 including a delay element.
FIG. 62 is a circuit diagram illustrating an example of the inverter circuit in FIG. 52 including a delay element.
FIG. 63 is a circuit diagram illustrating an example of the inverter circuit in FIG. 58 including a delay element.
FIGS. 64A to 64D are circuit diagrams illustrating variations of the delay element in FIGS. 61 to 63.
FIG. 65 is a waveform chart illustrating an example of an operation of the inverter circuits in FIGS. 61 to 63.
FIG. 66 is a waveform chart illustrating an example of input/output waveforms of the delay element in FIGS. 61 to 63.
FIG. 67 is a circuit diagram for describing an example of an operation of the inverter circuits in FIGS. 61 to 63.
FIG. 68 is a schematic view of a display as an application example of the inverter circuit according to any of the above-described embodiments and modifications thereof.
FIG. 69 is a circuit diagram illustrating an example of a writing line drive circuit and a pixel circuit in FIG. 68.
FIG. 70 is a waveform chart illustrating an example of an operation of the display in FIG. 68.
FIG. 71 is a circuit diagram illustrating an example of a pixel circuit of a display in related art.
FIG. 72 is a circuit diagram illustrating an example of an inverter circuit in related art.
FIG. 73 is a waveform chart illustrating an example of input/output signal waveforms of the inverter circuit in FIG. 72.
FIG. 74 is a circuit diagram illustrating another example of an inverter circuit in related art.
FIG. 75 is a circuit diagram illustrating still another example of an inverter circuit in related art.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the disclosure will be described in detail below referring to the accompanying drawings. Descriptions will be given in the following order.

    1. First Embodiment (refer to FIGS. 1 to 8)
    2. Second Embodiment (refer to FIGS. 9 to 13)
    3. Modifications of First and Second Embodiments (refer to FIGS. 14 to 17)
    4. Third Embodiment (refer to FIGS. 18 to 26)
    5. Fourth Embodiment (refer to FIGS. 27 to 34)
    6. Modifications of Third and Fourth Embodiments (refer to FIGS. 35 to 42)
    7. Fifth Embodiment (refer to FIGS. 43 to 51)
    8. Sixth Embodiment (refer to FIGS. 52 to 57)
    9. Modifications of Fifth and Sixth Embodiments (refer to FIGS. 58 to 67)
    10. Application Example (refer to FIGS. 68 to 70)
    11. Description of related art (refer to FIGS. 71 to 75)


First Embodiment
Configuration
FIG. 1 illustrates an example of a whole configuration of an inverter circuit 1 according to a first embodiment of the disclosure. The inverter circuit 1 outputs, from an output terminal OUT, a pulse signal (for example, refer to a part (B) in FIG. 2) with a substantially inverted signal waveform of a signal waveform (for example, refer to a part (A) in FIG. 2) of a pulse signal applied to an input terminal IN. The inverter circuit 1 is preferably formed on amorphous silicon or amorphous oxide semiconductor, and includes three transistors Tr1, Tr2 and Tr3 each having channels of same conduction type. In addition to the above-described three transistors Tr1, Tr2 and Tr3, the inverter circuit 1 includes two capacity elements C1 and C2, the input terminal IN and the output terminal OUT. In other words, the inverter circuit 1 has a 3Tr2C circuit configuration.
The transistors Tr1, Tr2 and Tr3 correspond to specific examples of “a first transistor”, “a second transistor” and “a third transistor” in the disclosure, respectively. Moreover, the capacity elements C1 and C2 correspond to specific examples of “a first capacity element” and “a second capacity element” in the disclosure, respectively.
The transistors Tr1, Tr2 and Tr3 are configured of, for example, n-channel MOS (Metal Oxide Semiconductor) type thin-film transistors (TFTs). The transistor Tr1 makes or breaks electrical connection between the output terminal OUT and a low-voltage line LL in response to, for example, a potential difference Vgs1 between a voltage (an input voltage Vin) of the input terminal IN and a voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr1 is electrically connected to the input terminal IN, and one terminal of a source and a drain of the transistor Tr1 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr1 is electrically connected to the output terminal OUT. The transistor Tr2 makes or breaks electrical connection between a high-voltage line LH and the output terminal OUT in response to a potential difference Vgs2 between a gate voltage Vg2 of the transistor Tr2 and a voltage (an output voltage Vout) of the output terminal OUT (or a potential difference corresponding thereto). A gate of the transistor Tr2 is electrically connected to a drain of the transistor Tr3, and one terminal of a source and a drain of the transistor Tr2 is electrically connected to the output terminal OUT, and the other terminal not connected to the output terminal OUT of the transistor Tr2 is electrically connected to the high-voltage line LH. The transistor Tr3 makes or breaks electrical connection between the gate of the transistor Tr2 and the low-voltage line LL in response to a potential difference Vgs3 between the input voltage Vin and the voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr3 is electrically connected to the input terminal IN, and one terminal of a source and the drain of the transistor Tr3 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr3 is electrically connected to the gate of the transistor Tr2. In other words, the transistors Tr1 and Tr3 are connected to the same voltage line (the low-voltage line LL), and a terminal on a side close to the low-voltage line LL of the source and the drain of the transistor Tr1 and a terminal on a side close to the low-voltage line LL of the source and the drain of the transistor Tr3 have the same potential.
The low-voltage line LL corresponds to a specific example of “a first voltage line” and “a third voltage line” in the disclosure. The high-voltage line LH corresponds to a specific example of “a second voltage line” in the disclosure.
The high-voltage line LH is connected to a power supply (not illustrated) outputting a higher voltage (a constant voltage) than the voltage VL of the low-voltage line LL, and the voltage VH of the high-voltage line LH is at a voltage Vdd during the drive of the inverter circuit 1. The low-voltage line LL is connected to a power supply (not illustrated) outputting a lower voltage (a constant voltage) than the voltage VH of the high-voltage line LH, and the voltage VL of the low-voltage line LL is at a voltage Vss(<Vdd) during the drive of the inverter circuit 1.
The capacity elements C1 and C2 are inserted in series between the input terminal IN and the gate of the transistor Tr2. An electrical connection point B between the capacity element C1 and the capacity element C2 is electrically connected to the output terminal OUT. The capacity element C1 is inserted on a side close to the gate of the transistor Tr2, and the capacity element C2 is inserted on a side close to the gate of the transistor Tr1. The capacity of the capacity element C2 is larger than that of the capacity element C1. Both of the capacities of the capacity elements C1 and C2 preferably satisfy the following expression (1). If the capacities of the capacity elements C1 and C2 satisfy the expression (1), at a falling edge of an input voltage Vin which will be described later, a gate-source voltage of the transistor Tr2 is allowed to reach a threshold voltage Vth2 or over of the transistor Tr2, and the output voltage Vout is allowed to be switched from low to high.

C2(Vdd−Vss)/(C1+C2)>Vth2  (1)

The inverter circuit 1 corresponds to an inverter circuit (an inverter circuit 200 in FIG. 72) in related art further including a control element 10 and the transistor Tr3 which are inserted between the transistors Tr1 and Tr2 in an output stage and the input terminal IN. In this case, for example, as illustrated in FIG. 1, the control element 10 includes a first terminal P1 electrically connected to the input terminal IN, a second terminal P2 electrically connected to the output terminal OUT and a third terminal P3 electrically connected to the gate of the transistor Tr2. For example, as illustrated in FIG. 1, the control element 10 further includes the capacity elements C1 and C2. For example, when a falling-edge voltage is applied to the first terminal P1, the control element 10 allows a voltage transient of the second terminal P2 to be slower than a voltage transient of the third terminal P3. More specifically, when the falling-edge voltage is applied to the input terminal IN, the control element 10 allows a voltage transient of the source (a terminal on a side close to the output terminal OUT) of the transistor Tr2 to be slower than a voltage transient of the gate of the transistor Tr2. Note that the operation of the control element 10 will be described with the following description of the operation of the inverter circuit 1.
Operation
Next, an example of the operation of the inverter circuit 1 will be described below referring to FIGS. 3 to 8. FIG. 3 is a waveform chart illustrating an example of the operation of the inverter circuit 1. FIGS. 4 to 8 are circuit diagrams sequentially illustrating an example of the operation of the inverter circuit 1.
First, when the input voltage Vin is high (Vdd), the transistors Tr1 and Tr3 are turned on, and the gate voltage Vg2 and the source voltage Vs2 of the transistor Tr2 are charged to a voltage VL (=Vss) of the low-voltage line LL (refer to FIGS. 3 and 4). Therefore, the transistor Tr2 is turned off (in the case where the transistor Tr2 is turned off at a voltage Vgs2=0 V), and the voltage Vss is taken out as the output voltage Vout. At this time, the capacity element C2 is charged to a voltage of Vdd−Vss.
Next, when the input voltage Vin is switched (reduced) from high (Vdd) to low (Vss), gate voltages Vg1 and Vg3 of the transistors Tr1 and Tr3 are switched (reduced) from the voltage Vdd to the voltage Vss (refer to FIGS. 3 and 5). Therefore, a change in the gate voltage of the transistor Tr1 propagates to the source (the output terminal OUT) of the transistor Tr2 through the capacity element C2 to change (reduce) the source voltage Vs2 (the output voltage Vout) of the transistor Tr2 by ΔV1′. Moreover, the change in the gate voltage of the transistor Tr1 also propagates to the gate of the transistor Tr2 through the capacity elements C1 and C2 to change (reduce) the gate voltage Vg2 of the transistor Tr2 by ΔV2′. However, at this time, the transistors Tr1 and Tr3 are on. Therefore, a current flows from the low-voltage line LL to the source (the output terminal OUT) of the transistor Tr2 and the gate of the transistor Tr2 so as to charge the source (the output terminal OUT) of the transistor Tr2 and the gate of the transistor Tr2 to the voltage Vss.
In this case, as the gate voltages of the transistors Tr1 and Tr3 are switched (reduced) from the voltage Vdd to the voltage Vss, on-resistances of the transistors Tr1 and Tr3 are gradually increased to increase time necessary to charge the source (the output terminal OUT) and the gate of the transistor Tr2 to the voltage VL of the low-voltage line LL.
Moreover, when full capacity at the source (the output terminal OUT) of the transistor Tr2 and full capacity at the gate of the transistor Tr2 are compared to each other, the capacity elements C1 and C2 are connected in parallel to the source (the output terminal OUT) of the transistor Tr2, and the capacity elements C1 and C2 are connected in series to the gate of the transistor Tr2. Therefore, the voltage transient of the source (the output terminal OUT) of the transistor Tr2 is slower than that of the gate of the transistor Tr2. As a result, time necessary to charge the source (the output terminal OUT) of the transistor Tr2 to the voltage VL of the low-voltage line LL is longer than time necessary to charge the gate of the transistor Tr2 to the voltage VL of the low-voltage line LL.
Moreover, in the case where the input voltage Vin is at a voltage Vss+Vth1 or over, and further at a voltage Vss+Vth3 or over, the transistors Tr1 and Tr3 operate in a linear region. Note that Vth1 is a threshold voltage of the transistor Tr1, and Vth3 is a threshold voltage of the transistor Tr3. On the other hand, in the case where the input voltage Vin is smaller than the voltage Vss+Vth1, and further smaller than the voltage Vss+Vth3, the transistors Tr1 and Tr3 operate in a saturation region. Therefore, although a current illustrated in FIG. 5 flows through the source (the output terminal OUT) and the gate of the transistor Tr2, each of the terminals of the transistors Tr1 and Tr3 is not allowed to be charged to the voltage Vss.
When the input voltage Vin is switched from the voltage Vdd to the voltage Vss, ultimately, the gate-source voltage Vgs2 of the transistor Tr2 is changed to a voltage ΔV1−ΔV2 (refer to FIGS. 3 and 6). At this time, when the gate-source voltage Vgs2 of the transistor Tr2 exceeds the threshold voltage Vth2 of the transistor Tr2, the transistor Tr2 is turned on, and the current starts to flow from the high-voltage line LH.
When the transistor Tr2 is on, the source voltage Vs2 (an output voltage Vout) of the transistor Tr2 is increased by the transistor Tr2 in addition to the transistor Tr1. Moreover, as the capacity element C1 is connected between the gate and the source of the transistor Tr2, a bootstrap is caused, and the gate voltage Vg2 of the transistor Tr2 is increased with an increase in the source voltage Vs2 (the output voltage Vout) of the transistor Tr2. After that, when the source voltage Vs2 (the output voltage Vout) and the gate voltage Vg2 of the transistor Tr2 reach the voltage Vss−Vth1 or over, further the voltage Vss−Vth3 or over, the transistors Tr1 and Tr3 are turned off, and the source voltage Vs2 (the output voltage Vout) and the gate voltage Vg2 of the transistor Tr2 are increased only by the transistor Tr2.
After a lapse of a certain period, the source voltage Vs2 (the output voltage Vout) of the transistor Tr2 is changed to the voltage Vdd to output the voltage Vdd from the output terminal OUT (refer to FIGS. 3 and 7). Then, after a lapse of another certain period, the input voltage Vin, is switched (increased) from low (Vss) to high (Vdd) (refer to FIGS. 3 and 8). At this time, in a stage where the input voltage Vin is lower than the voltage Vss+Vth1, and further lower than a voltage Vss+Vth3, the transistors Tr1 and Tr3 are off. Therefore, coupling through the capacity elements C1 and C2 is applied to the source (the output terminal OUT) and the gate of the transistor Tr2 to increase the source voltage Vs2 (the output voltage Vout) and the gate voltage Vg2 of the transistor Tr2. After that, when the input voltage Vin reaches the voltage Vss+Vth1 or over, and further the voltage Vss+Vth3 or over, the transistors Tr1 and Tr3 are turned on. Therefore, a current flows toward the source (the output terminal OUT) and the gate of the transistor Tr2 so as to charge the source (the output terminal OUT) and the gate of the transistor Tr2 to the voltage Vss.
In this case, as the gate voltages of the transistors Tr1 and Tr3 are switched (increased) from the voltage Vss to the voltage Vdd, on-resistances of the transistors Tr1 and Tr3 are gradually reduced to relatively reduce time necessary to charge the source (the output terminal OUT) and the gate of the transistor Tr2 to the voltage VL of the low-voltage line LL. Ultimately, the source voltage Vs2 (the output voltage Vout) and the gate voltage Vg2 of the transistor Tr2 reach the voltage Vss, and the output terminal outputs the voltage Vss (refer to FIGS. 3 and 4).
As described above, the inverter circuit 1 according to the first embodiment outputs, from the output terminal OUT, a pulse signal (for example, refer to the part (B) in FIG. 2) with a substantially inverted signal waveform of a signal waveform (for example, refer to the part (A) in FIG. 2) of a pulse signal applied to the input terminal IN.
Effects
The inverter circuit 200 in related art illustrated in FIG. 72 has, for example, a single channel type circuit configuration in which two n-channel MOS type transistors Tr1 and Tr2 are connected to each other in series. In the inverter circuit 200, for example, as illustrated in FIG. 73, when the input voltage Vin is at the voltage Vss, the output voltage Vout is not at the voltage Vdd but at a voltage Vdd−Vth2. In other words, the output voltage Vout includes the threshold voltage Vth2 of the transistor Tr2, and the output voltage Vout is greatly affected by variations in the threshold voltage Vth2 of the transistor Tr2.
Therefore, it is considered that, for example, as illustrated in an inverter circuit 300 in FIG. 74, the gate and the drain of the transistor Tr2 are electrically separated from each other, and the gate is connected to a high-voltage wiring line LH2 to which a higher voltage Vdd2 (=Vdd+Vth2) than the voltage Vdd of the drain is applied. Moreover, for example, a bootstrap type circuit configuration represented by an inverter circuit 400 in FIG. 75 is considered.
However, in any of the circuits in FIGS. 72, 74 and 75, even in the case where the input voltage Vin is high, that is, even in the case where the output voltage Vout is low, a current (a through current) flows from the high-voltage wiring line LH to a low-voltage wiring line LL through the transistors Tr1 and Tr2. As a result, power consumption in the inverter circuits is increased. Moreover, in the circuits in FIGS. 72, 74 and 75, for example, as illustrated in a point encircled by a broken line in a part (B) in FIG. 73, when the input voltage Vin is at the voltage Vdd, the output voltage Vout is not at the voltage Vss, and a peak value of the output voltage Vout varies. Therefore, for example, in the case where the inverter circuits are used in a scanner in an active matrix organic EL display, threshold correction or mobility correction in a driving transistor varies from one pixel circuit to another, thereby causing variations in luminance.
On the other hand, in the inverter circuit 1 according to the first embodiment, the transistors Tr1 and Tr3 performing an ON/OFF operation in response to a potential difference between the input voltage Vin and the voltage VL of the low-voltage line LL are arranged between the gate of the transistor Tr2 and the low-voltage line LL and between the source of the transistor Tr2 and the low-voltage line LL. Therefore, when the gate voltages of the transistors Tr1 and Tr3 are switched (reduced) from high (Vdd) to low (Vss), on-resistances of the transistors Tr1 and Tr3 are gradually increased to increase time necessary to charge the gate and the source of the transistor Tr2 to the voltage VL of the low-voltage line LL. Moreover, when the gate voltages of the transistors Tr1 and Tr3 are switched (increased) from low (Vss) to high (Vdd), the on-resistances of the transistors Tr1 and Tr3 are gradually reduced to reduce time necessary to charge the gate and the source of the transistor Tr2 to the voltage VL of the low-voltage line LL. Further, in the inverter circuit 1 according to the first embodiment, the capacity elements C1 and C2 are connected in series to the gate of the transistor Tr2, and are connected in parallel to the source of the transistor Tr2. Therefore, the voltage transient of the source of the transistor Tr2 is slower than that of the gate of the transistor Tr2. As a result, when the gate voltages of the transistors Tr1 and Tr3 are switched (reduced) from high (Vdd) to low (Vss), the gate-source voltage Vgs2 of the transistor Tr2 exceeds the threshold voltage Vth2 of the transistor Tr2, and the transistor Tr2 is turned on, and immediately after that, the transistors Tr1 and Tr3 are turned off. In other words, when the switched input voltage Vin is applied to the gate and the source of the transistor Tr2 through the capacity elements C1 and C2, and the gate-source voltage Vgs2 exceeds the threshold voltage Vth2 by a transient difference, the transistor Tr2 is turned on, and immediately after that, the transistors Tr1 and Tr3 are turned off. At this time, the output voltage Vout is changed to a voltage of the high-voltage line LH. Moreover, when the gate voltages of the transistors Tr1 and Tr3 are switched (increased) from low (Vss) to high (Vdd), the transistors Tr1 and Tr3 are turned on, and immediately after that, the transistor Tr2 is turned off. At this time, the output voltage Vout is changed to a voltage of the low-voltage line LL.
Thus, in the inverter circuit 1 according to the first embodiment, a period where the transistor Tr1 and the transistor Tr2 are simultaneously turned on is almost eliminated. Therefore, a current (a through current) hardly flows between the high-voltage line LH and the low-voltage line LL through the transistors Tr1 and Tr2. As a result, power consumption is allowed to be reduced. Moreover, when the gate voltages of the transistors Tr1 and Tr3 are switched (reduced) from high (Vdd) to low (Vss), the output voltage Vout is changed to the voltage of the high-voltage line LH, and when the gate voltages of the transistors Tr1 and Tr3 are switched (increased) from low (Vss) to high (Vdd), the output voltage Vout is changed to the voltage of the low-voltage line LL. Therefore, variations in the output voltage Vout are allowed to be eliminated. As a result, for example, variations in threshold correction or mobility correction in the driving transistor from one pixel circuit to another are allowed to be reduced, and variations in luminance from one pixel to another are allowed to be reduced.
Second Embodiment
Configuration
FIG. 9 illustrates an example of a whole configuration of an inverter circuit 2 according to a second embodiment of the disclosure. As in the case of the inverter circuit 1 according to the first embodiment, the inverter circuit 2 outputs, from the output terminal OUT, a pulse signal (for example, refer to the part (B) in FIG. 2) with a substantially inverted signal waveform of a signal waveform (for example, refer to the part (A) in FIG. 2) of a pulse signal applied to the input terminal IN. The configuration of the inverter circuit 2 differs from that of the inverter circuit 1 according to the first embodiment in including a delay element 3. Hereinafter, differences between the first and second embodiments will be mainly described, and similarities between the first and second embodiments will not be described.
The delay element 3 inputs, to the gate of the transistor Tr3, a voltage with a waveform obtained by delaying a voltage waveform of a signal voltage applied to the input terminal IN. The delay element 3 is arranged between the input terminal IN and the gate of the transistor Tr3, and inputs, to the gate of the transistor Tr3, a voltage with a slower falling edge than that of the voltage waveform of the signal voltage applied to the input terminal IN. Note that the delay element 3 may allow not only the falling edge but also the rising edge of the voltage waveform to be slower than that of the voltage waveform of the signal voltage applied to the input terminal IN. However, in this case, the delay element 3 delays the voltage waveform of the signal voltage applied to the input terminal IN so that its falling edge is slower than its rising edge.
The delay element 3 has any of circuit configurations illustrated in FIGS. 10A to 10D. In FIG. 10A, the delay element 3 includes a capacity element C3. An end of the capacity element C3 is electrically connected to the gate of the transistor Tr3, and the other end of the capacity element C3 is electrically connected to the low-voltage line LL.
In FIG. 10B, the delay element 3 includes a transistor Tr4. The transistor Tr4 is configured of a transistor having channels of same conduction type as that of the transistors Tr1, Tr2 and Tr3, for example, an n-channel MOS type TFT. A source of the transistor Tr4 is electrically connected to the gate of the transistor Tr3, and a drain of the transistor Tr4 is electrically connected to the input terminal IN. A gate of the transistor Tr4 is electrically connected to a high-voltage line LH1. The high-voltage line LH1 is electrically connected to a power supply (not illustrated) outputting a pulse signal allowing the transistor Tr4 to perform an ON/OFF operation.
In FIG. 10C, the delay element 3 includes the above-described transistor Tr4 and a transistor Tr5. The transistor Tr5 is configured of a transistor having channels of same conduction type as that of the transistors Tr1, Tr2 and Tr3, for example, an n-channel MOS type TFT. A gate and a source of the transistor Tr5 are electrically connected to the gate of the transistor Tr3, and a drain of the transistor Tr5 is electrically connected to the input terminal IN.
In FIG. 10D, the delay element 3 includes the above-described transistor Tr4 and the above-described capacity element C3.
Operation and Effects
FIG. 11 illustrates an example of the operation of the inverter circuit 2. Note that FIG. 11 illustrates waveforms in the case where a circuit configuration illustrated in FIG. 10D is used as the delay element 3. The basic operation of the inverter circuit 2 is the same as that illustrated in FIGS. 3 to 8. A different operation from that illustrated in FIGS. 3 to 8 is performed when the input voltage Vin is switched (reduced) from high (Vdd) to low (Vss) and when the input voltage Vin is switched (increased) from low (Vss) to high (Vdd).
When the input voltage Vin is switched (reduced) from high (Vdd) to low (Vss), the gate voltages of the transistors Tr1 and Tr3 are changed from the voltage Vdd to the voltage Vss. In the inverter circuit 1 according to the first embodiment, the voltage change causes a voltage change by ΔV1 in the source of the transistor Tr2 through the capacity element C2, and further causes a voltage change by ΔV2 in the gate of the transistor Tr2 through the capacity elements C1 and C2. In this case, a coupling amount of ΔV2 is applied to the gate of the transistor Tr2, because the gate voltage Vg3 of the transistor Tr3 is reduced from the voltage Vdd to the voltage Vss, and as a result, the on-resistance of the transistor Tr3 is gradually increased to slow a voltage transient for charging the gate of the transistor Tr2 to the voltage Vss. In other words, the coupling amount of ΔV2 is applied to the gate of the transistor Tr2, because the transistor Tr3 is switched from on to off at a timing of applying coupling.
On the other hand, in the embodiment, a signal voltage as illustrated in FIG. 12 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, an off point (a point of switching from on to off) of the transistor Tr3 is delayed, compared to the case where the input voltage Vin is applied as is to the gate of the transistor Tr3. In other words, the transistor Tr3 is still on at the timing of applying coupling through the capacity element C2 (refer to FIG. 13). Therefore, ultimately, the coupling amount (ΔV2) applied to the gate of the transistor Tr2 is allowed to be reduced to be smaller than that in related art (refer to a part (C) in FIG. 11), and a gate-source voltage Vgs2 of the transistor Tr2 is allowed to be increased. As a result, the speed of the inverter circuit 2 is allowed to be increased.
In the embodiment, even in the case where the input voltage Vin is switched (increased) from low (Vss) to high (Vdd), a signal voltage as illustrated in FIG. 12 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, as the off point of the transistor Tr3 is delayed, the transistor Tr3 is turned on after the transistor Tr1 is turned on, and there is a possibility that a current (a through current) flows from the high-voltage line LH to the low-voltage line LL, in a state where the output voltage Vout is switched. However, when an operation point at which the transistor Tr3 is turned on and the waveform of the signal voltage, applied to the gate of the transistor Tr3 are considered, even though the signal voltage applied to the gate of the transistor Tr3 is delayed, the time of turning the transistor Tr3 on is hardly changed at the rising edge as illustrated in FIG. 12, and on the other hand, the time of turning the transistor Tr3 off is largely changed at the falling edge. Therefore, a period where the above-described through current flows is extremely short, and the power consumption of the inverter circuit 2 is not much different from that of the inverter circuit 1.
In the first embodiment, coupling caused by a change in the input voltage Vin is applied to the source and the gate of the transistor Tr2 so that the gate-source voltage Vgs2 of the transistor Tr2 has a value equal to or higher than the threshold voltage Vth2 of the transistor Tr2 with use of a difference in voltage transient between the source and the gate of the transistor Tr2. At this time, the output terminal OUT outputs the voltage of the high-voltage line LH as the output voltage Vout, but the voltage transient of the output terminal OUT is highly dependent on the gate-source voltage Vgs2 of the transistor Tr2. In other words, in the case where the gate-source voltage Vgs2 of the transistor Tr2 is rapidly increased, the output voltage Vout rapidly rises, and in the case where the gate-source voltage Vgs2 of the transistor Tr2 is gradually increased, the out voltage Vout gradually rises.
Therefore, to increase the speed of the inverter circuit 1, it is necessary for the gate-source voltage Vgs2 of the transistor Tr2 to rapidly rise, and as a method of doing so, for example, it is considered to increase the capacity of the capacity element C2. However, in the case where the capacity of the capacity element C2 is increased, an area occupied by the inverter circuit 1 is increased. As a result, for example, in the case where the inverter circuit 1 including the capacity element C2 with a larger capacity is used for a scanner or the like in an organic EL display, an area occupied by the inverter circuit 1 in a peripheral part (a frame) of a display panel may be increased to interfere with a reduction in the area of the frame. Moreover, an increase in the capacity of the capacity element C2 causes a larger voltage change than ΔV1 in the source (the output terminal OUT) of the transistor Tr2, thereby causing a larger voltage change than ΔV2 in the gate of the transistor Tr2. As a result, even though the capacity of the capacity element C2 is increased, the gate-source voltage Vgs2 of the transistor Tr2 has a value not much different from ΔV1−ΔV2; therefore, an increase in the capacity of the capacity element C2 does not much contribute to an increase in the speed of the inverter circuit 1.
On the other hand, in the embodiment, the signal voltage as illustrated in FIG. 12 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, the speed of the inverter circuit 2 is allowed to be increased without increasing the capacity of the capacity element C2.
Modifications of First and Second Embodiments
In the first and second embodiments, the transistors Tr1, Tr2 and Tr3 are configured of the n-channel MOS type TFTs, but they may be configured of, for example, p-channel MOS type TFTs. However, in this case, the high-voltage line LH and the low-voltage line LL change places, and a transient response when the transistors Tr1, Tr2 and Tr3 are switched (increased) from low (Vss) to high (Vdd) and a transient response when the transistors Tr1, Tr2 and Tr3 are switched (reduced) from high (Vdd) to low (Vss) are opposite to each other.
Moreover, in the second embodiment, the signal voltage as illustrated in FIG. 12 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3, but such a signal may be applied to the gate of the transistor Tr3 by another method. For example, as illustrated in an inverter circuit 4 in FIG. 14, an input terminal IN2 may be provided independently of the input terminal IN, and the input terminal IN2 and the gate of the transistor Tr3 may be electrically connected to each other so as to externally apply a signal as illustrated in a part (B) in FIG. 15 to the input terminal IN2.
Further, in the second embodiment and the modifications thereof, in the case where the input voltage Vin, is switched (increased) from low (Vss) to high (Vdd), a current (a through current) may flow from the high-voltage line LH to the low-voltage line LL; therefore, an element for preventing such a current flow may be added. For example, as illustrated in FIGS. 16 and 17, a transistor Tr6 may be further included in the control element 10. Note that the transistor Tr5 is configured of a transistor having channels of the same conduction type as that of the transistors Tr1, Tr2 and Tr3, for example, an n-channel MOS type TFT.
The transistor Tr6 is connected in parallel to the transistor Tr1, and a gate of the transistor Tr6 is connected to the input terminal IN. In such a case, when the input voltage Vin is switched (reduced) from high (Vdd) to low (Vss), an on-period of the transistor Tr3 is increased, and on the other hand, when the input voltage Vin is switched (increased) from low (Vss) to high (Vdd), before turning the transistor Tr3 on, the transistor Tr6 is allowed to be turned on by the input voltage Vin which is not delayed. As a result, the through current is allowed to be reduced.
Third Embodiment
Configuration
FIG. 18 illustrates an example of a whole configuration of an inverter circuit 1 according to a third embodiment of the disclosure. The inverter circuit 1 outputs, from an output terminal OUT, a pulse signal (for example, refer to a part (B) in FIG. 19) with a substantially inverted signal waveform of a signal waveform (for example, refer to a part (A) in FIG. 19) of a pulse signal applied to an input terminal IN. The inverter circuit 1 is preferably formed on amorphous silicon or amorphous oxide semiconductor, and includes five transistors Tr1 to Tr5 each having channels of same conduction type. In addition to the above-described five transistors Tr1 to Tr5, the inverter circuit 1 includes two capacity elements C1 and C2, the input terminal IN and the output terminal OUT. In other words, the inverter circuit 1 has a 5Tr2C circuit configuration.
The transistors Tr1, Tr2 and Tr3 correspond to specific examples of “a first transistor”, “a second transistor” and “a third transistor” in the disclosure, respectively. Moreover, the transistors Tr4 and Tr5 correspond to specific examples of “a fourth transistor” and “a fifth transistor” in the disclosure, respectively. Further, the capacity elements C1 and C2 correspond to specific examples of “a first capacity element” and “a second capacity element” in the disclosure, respectively.
The transistors Tr1 to Tr5 are configured of thin-film transistors (TFTs) each having channels of same conduction type, for example, n-channel MOS (Metal Oxide Semiconductor) type thin-film transistors (TFTs). The transistor Tr1 makes or breaks electrical connection between the output terminal OUT and a low-voltage line LL in response to, for example, a potential difference Vgs1 between a voltage (an input voltage Vin) of the input terminal IN and a voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr1 is electrically connected to the input terminal IN, and one terminal of a source and a drain of the transistor Tr1 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr1 is electrically connected to the output terminal OUT. The transistor Tr2 makes or breaks electrical connection between a high-voltage line LH1 and the output terminal OUT in response to a potential difference Vgs2 between a voltage Vs5 of one terminal (a first terminal X) which is not connected to a high-voltage line LH2 of a source and a drain of the transistor Tr5 and a voltage (an output voltage Vout) of the output terminal OUT (or a potential difference corresponding thereto). A gate of the transistor Tr2 is electrically connected to the first terminal X of the transistor Tr5. One terminal of a source and a drain of the transistor Tr2 is electrically connected to the output terminal OUT, and the other terminal not connected to the output terminal OUT of the transistor Tr2 is electrically connected to a high-voltage line LH'.
The transistor Tr3 makes or breaks electrical connection between a gate of the transistor Tr5 and the low-voltage line LL in response to a potential difference Vgs3 between the input voltage Vin and the voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr3 is electrically connected to the input terminal IN. One terminal of a source and a drain of the transistor Tr3 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr3 is electrically connected to the gate of the transistor Tr5. The transistor Tr4 makes or breaks electrical connection between the first terminal X of the transistor Tr5 and the low-voltage line LL in response to a potential different Vgs4 between the input voltage Vin and the voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr4 is electrically connected to the input terminal IN. One terminal of a source and a drain of the transistor Tr4 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr4 is electrically connected to the first terminal X of the transistor Tr5. In other words, the transistors Tr1, Tr3 and Tr4 are connected to the same voltage line (the low-voltage line LL). Therefore, a terminal on a side close to the low-voltage line LL of the transistor Tr1, a terminal on a side close to the low-voltage line LL of the transistor Tr3 and a terminal on a side close to the low-voltage line LL of the transistor Tr4 have the same potential. The transistor Tr5 makes and breaks electrical connection between a high-voltage line LH2 and the first terminal X in response to a voltage Vgs5 between terminals of the capacity element C1 (or a potential difference corresponding thereto). The gate of the transistor Tr5 is electrically connected to the terminal not connected to the low-voltage line LL of the source and the drain of the transistor Tr3. One terminal of the source and the drain of the transistor Tr5 is electrically connected to the high-voltage line LH2. The other terminal not connected to the high-voltage line LH2 of the transistor Tr5 is connected to the gate of the transistor Tr2 and the terminal not connected to the low-voltage line LL of the source and the drain of the transistor Tr4.
The low-voltage line LL corresponds to a specific example of “a first voltage line”, “a third voltage line” and “a fourth voltage line” in the disclosure. The high-voltage line LH1 and the high-voltage line LH2 correspond to specific examples of “a second voltage line” and “a fifth voltage line” in the disclosure, respectively.
The high-voltage lines LH1 and LH2 are connected to a power supply (not illustrated) outputting a higher voltage (a constant voltage) than the voltage VL of the low-voltage line LL. A voltage VH1 of the high-voltage line LH1 is at a voltage Vdd1 during the drive of the inverter circuit 1, and a voltage VH2 of the high-voltage line LH2 is at a voltage Vdd2 (≧Vdd1−Vdd2) during the drive of the inverter circuit 1. Note that Vth2 is a threshold voltage of the transistor Tr2. On the other hand, the low-voltage line LL is connected to a power supply (not illustrated) outputting a lower voltage (a constant voltage) than the voltage VH1 of the high-voltage line LH1, and the voltage VL of the low-voltage line LL is at a voltage Vss (<Vdd1) during the drive of the inverter circuit 1.
The capacity elements C1 and C2 are inserted in series between the input terminal IN and the gate of the transistor Tr2. An electrical connection point B between the capacity element C1 and the capacity element C2 is eclectically connected to the first terminal X of the transistor Tr5. The capacity element C1 is inserted on a side close to the gate of the transistor Tr5, and the capacity element C2 is inserted on a side close to the gate of the transistor Tr1. The capacity of the capacity element C2 is larger than that of the capacity element C1. Both of the capacities of the capacity elements C1 and C2 preferably satisfy the following expression (1). If the capacities of the capacity elements C1 and C2 satisfy the expression (1), at a falling edge of an input voltage Vin which will be described later, a gate-source voltage of the transistor Tr5 is allowed to reach a threshold voltage Vth5 or over of the transistor Tr5, and the transistor Tr5 is allowed to be turned on. As a result, the output voltage Vout is allowed to be switched from low to high.

C2(Vdd−Vss)/(C1+C2)>Vth5  (1)

The inverter circuit 1 corresponds to an inverter circuit (an inverter circuit 200 in FIG. 72) in related art further including a control element 10 and the transistors Tr1 to Tr5 which are inserted between the transistors Tr1 and Tr2 in an output stage and the input terminal IN. In this case, for example, as illustrated in FIG. 18, the control element 10 includes a terminal P1 electrically connected to the input terminal IN, a terminal P2 electrically connected to the first terminal X of the transistor Tr5, and a terminal P3 electrically connected to the gate of the transistor Tr5. Moreover, for example, as illustrated in FIG. 18, the control element 10 includes the capacity elements C1 and C2.
The terminals P1, P2 and P3 correspond to specific examples of “a second terminal”, “a third terminal” and “a fourth terminal” in the disclosure, respectively.
For example, when a falling-edge voltage is applied to the terminal P1, the control element 10 allows a voltage transient of the second terminal P2 to be slower than a voltage transient of the third terminal P3. More specifically, when the falling-edge voltage is applied to the input terminal IN, the control element 10 allows a voltage transient of the source (the first terminal X) of the transistor Tr5 to be slower than a voltage transient of the gate of the transistor Tr5. Note that the operation of the control element 10 will be described with the following description of the operation of the inverter circuit 1.
Operation
Next, an example of the operation of the inverter circuit 1 will be described below referring to FIGS. 20 to 39. FIG. 20 is a waveform chart illustrating an example of the operation of the inverter circuit 1. FIGS. 21 to 26 are circuit diagrams sequentially illustrating an example of the operation of the inverter circuit 1.
First, when the input voltage V1 is high (Vdd1), the transistors Tr1, Tr3 and Tr4 are turned on. Then, the gate voltage Vg2 and the source voltage Vs2 of the transistor Tr2 are charged to a voltage VL (=Vss) of the low-voltage line LL, and the gate voltage Vg5 and the source voltage Vs5 of the transistor Tr5 are charged to the voltage VL (=Vss) of the low-voltage line LL (refer to FIGS. 20 and 21). Therefore, the transistor Tr2 is turned off (in the case where the transistor Tr2 is turned off at a voltage Vgs2=0 V), and the transistor Tr5 is turned off (in the case where the transistor Tr5 is turned off at a voltage Vgs5=0 V), and the voltage Vss is taken out as the output voltage Vout. At this time, the capacity element C2 is charged to a voltage of Vdd2−Vss.
Next, when the input voltage Vin is switched (reduced) from high (Vdd1) to low (Vss), gate voltages Vg1, Vg3 and Vg4 of the transistors Tr1, Tr3 and Tr4 are switched (reduced) from the voltage Vdd1 to the voltage Vss (refer to FIGS. 20 and 22). Therefore, a change in the gate voltage Vg1 of the transistor Tr1 propagates to the gate of the transistor Tr2 through the capacity element C2 to change (reduce) the gate voltage Vg2 of the transistor Tr2 by ΔV1′. Moreover, the change in the gate voltage Vg1 of the transistor Tr1 propagates to the gate of the transistor Tr5 through the capacity elements C1 and C2 to change (reduce) the gate voltage Vg5 of the transistor Tr5 by ΔV2′. However, at this time, the transistors Tr3 and Tr4 are on. Therefore, a current flows from the low-voltage line LL to the source and the gate of the transistor Tr5 so as to charge the source and the gate of the transistor Tr5 to the voltage Vss.
In this case, as the gate voltages of the transistors Tr3 and Tr4 are switched (reduced) from the voltage Vdd1 to the voltage Vss, on-resistances of the transistors Tr3 and Tr4 are gradually increased to increase time necessary to charge the source and the gate of the transistor Tr5 to the voltage VL of the low-voltage line LL.
Moreover, when full capacity at the source of the transistor Tr5 and full capacity at the gate of the transistor Tr5 are compared to each other, the capacity elements C1 and C2 are connected in parallel to the source of the transistor Tr5, and the capacity elements C1 and C2 are connected in series to the gate of the transistor Tr5. Therefore, the voltage transient of the source of the transistor Tr5 is slower than that of the gate of the transistor Tr5. As a result, time necessary to charge the source of the transistor Tr5 to the voltage VL of the low-voltage line LL is longer than time necessary to charge the gate of the transistor Tr5 to the voltage VL of the low-voltage line LL.
Moreover, in the case where the input voltage Vin is at a voltage Vss+Vth3 or over, and further at a voltage Vss+Vth4 or over, the transistors Tr3 and Tr4 operate in a linear region. Note that Vth3 is a threshold voltage of the transistor Tr3, and Vth4 is a threshold voltage of the transistor Tr4. On the other hand, in the case where the input voltage Vin is smaller than the voltage Vss+Vth3, and further smaller than the voltage Vss+Vth4, the transistors Tr3 and Tr4 operate in a saturation region. Therefore, although the current illustrated in FIG. 22 flows through the source and the gate of the transistor Tr5, each of the terminals of the transistors Tr3 and Tr4 is not allowed to be charged to the voltage Vss.
When the input voltage Vin is switched from the voltage Vdd1 to the voltage Vss, ultimately, the gate-source voltage Vgs5 of the transistor Tr5 is changed to a voltage ΔV1−ΔV2 (refer to FIGS. 20 and 23). At this time, when the gate-source voltage Vgs5 of the transistor Tr5 exceeds the threshold voltage Vth5 of the transistor Tr5, the transistor Tr5 is turned on, and the current starts to flow from the high-voltage line LH2.
When the transistor Tr5 is on, the source voltage Vs5 of the transistor Tr5 is increased by the transistor Tr5 in addition to the transistor Tr4. Moreover, as the capacity element C1 is connected between the gate and the source of the transistor Tr5, a bootstrap is caused, and the gate voltage Vg5 of the transistor Tr5 is increased with an increase in the source voltage Vs5 of the transistor Tr5. After that, when the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 reach the voltage Vss−Vth3 or over, further the voltage Vss−Vth4 or over, the transistors Tr3 and Tr4 are turned off, and the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 are increased only by the transistor Tr5.
After a lapse of a certain period, when the source voltage Vs5 of the transistor Tr5 (the gate voltage Vg2 of the transistor Tr2) reaches a voltage VSS+Vth2 or over, the transistor Tr2 is turned on, and a current starts to flow from the high-voltage line LH1 (refer to FIGS. 20 and 24). Note that Vth2 is a threshold voltage of the transistor Tr2. As a result, the voltage Vout of the output terminal OUT is gradually increased from the voltage Vss. Ultimately, the gate voltage Vg2 of the transistor Tr2 is increased to the voltage VH2 of the high-voltage line LH2 by the current from the transistor Tr5 (refer to FIGS. 20 and 25). In this case, the voltage VH2 of the high-voltage line LH2 is at a voltage Vdd2 which is larger than a voltage Vdd1+Vth2 during the drive of the inverter circuit 1, so the transistor Tr2 outputs the voltage Vdd1 which is the voltage VH1 of the high-voltage line LH1 to the output terminal OUT. As a result, the output terminal OUT outputs the voltage Vdd1 (refer to FIGS. 20 and 25).
After a lapse of another certain period, the input voltage Vin is switched (increased) from low (Vss) to high (Vdd1) (refer to FIGS. 20 and 26). At this time, in a stage where the input voltage Vin is lower than the voltage Vss+Vth3, and further lower than the voltage Vss+Vth4, the transistors Tr3 and Tr4 are off. Therefore, coupling through the capacity elements C1 and C2 is applied to the source and the gate of the transistor Tr5 to increase the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5. After that, when the input voltage Vin reaches voltages Vss+Vth1, Vss−Vth3 and Vss+Vth4 or over, the transistors Tr1, Tr3 and Tr4 are turned on. Therefore, a current flows toward the source (the output terminal OUT) of the transistor Tr2 and the source and the gate of the transistor Tr5 so as to charge the source (the output terminal OUT) of the transistor Tr2 and the source and the gate of the transistor Tr5 to the voltage Vss.
In this case, as the gate voltages Vg1, Vg3 and Vg4 of the transistors Tr1, Tr3 and Tr4 are switched (increased) from the voltage Vss to the voltage Vdd1, on-resistances of the transistors Tr1, Tr3 and Tr4 are gradually reduced to relatively reduce time necessary to charge the sources and the gates of the transistors Tr2 and Tr5 to the voltage VL of the low-voltage line LL. Ultimately, the source voltage Vs2 of the transistor Tr2 and the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 reach the voltage Vss, and the output terminal outputs the voltage Vss (refer to FIGS. 20 and 21).
As described above, the inverter circuit 1 according to the third embodiment outputs, from the output terminal OUT, a pulse signal (for example, refer to the part (B) in FIG. 19) with a substantially inverted signal waveform of a signal waveform (for example, refer to the part (A) in FIG. 19) of a pulse signal applied to the input terminal IN.
Effects
The inverter circuit 200 in related art illustrated in FIG. 72 has, for example, a single channel type circuit configuration in which two n-channel MOS type transistors Tr1 and Tr2 are connected to each other in series. In the inverter circuit 200, for example, as illustrated in FIG. 73, when the input voltage Vin is at the voltage Vss, the output voltage Vout is not at the voltage Vdd but at a voltage Vdd−Vth2. In other words, the output voltage Vout includes the threshold voltage Vth2 of the transistor Tr2, and the output voltage Vout is greatly affected by variations in the threshold voltage Vth2 of the transistor Tr2.
Therefore, it is considered that, for example, as illustrated in an inverter circuit 300 in FIG. 74, the gate and the drain of the transistor Tr2 are electrically separated from each other, and the gate is connected to the high-voltage wiring line LH2 to which a higher voltage Vdd2 (≧Vdd+Vth2) than the voltage Vdd of the drain is applied. Moreover, for example, a bootstrap type circuit configuration represented by an inverter circuit 400 in FIG. 75 is considered.
However, in any of the circuits in FIGS. 72, 74 and 75, even in the case where the input voltage Vin is high, that is, even in the case where the output voltage Vout is low, a current (a through current) flows from the high-voltage wiring line LH to the low-voltage wiring line LL through the transistors Tr1 and Tr2. As a result, power consumption in the inverter circuits is increased. Moreover, in the circuits in FIGS. 72, 74 and 75, for example, as illustrated in a point encircled by a broken line in a part (B) in FIG. 73, when the input voltage Vin is at the voltage Vdd, the output voltage Vout is not at the voltage Vss, and a peak value of the output voltage Vout varies. Therefore, for example, in the case where the inverter circuits are used in a scanner in an active matrix organic EL display, threshold correction or mobility correction in a driving transistor varies from one pixel circuit to another, thereby causing variations in luminance.
On the other hand, in the inverter circuit 1 according to the third embodiment, the transistors Tr1, Tr3 and Tr4 performing an ON/OFF operation in response to a potential difference between the input voltage Vin and the voltage VL of the low-voltage line LL are arranged between the gate of the transistor Tr5 and the low-voltage line LL, between the source of the transistor Tr5 and the low-voltage line LL, and between the source of the transistor Tr2 and the low-voltage line LL. Therefore, when the gate voltages of the transistors Tr1, Tr3 and Tr4 are switched (reduced) from high (Vdd1) to low (Vss), on-resistances of the transistors Tr1, Tr3 and Tr4 are gradually increased to increase time necessary to charge the gates and the sources of the transistors Tr2 and Tr5 to the voltage VL of the low-voltage line LL. Moreover, when the gate voltages of the transistors Tr1, Tr3 and Tr4 are switched (increased) from low (Vss) to high (Vdd1), the on-resistances of the transistors Tr1, Tr3 and Tr4 are gradually reduced to reduce time necessary to charge the gates and the sources of the transistors Tr2 and Tr5 to the voltage VL of the low-voltage line LL. Further, in the inverter circuit 1 according to the third embodiment, the capacity elements C1 and C2 are connected in series to the gate of the transistor Tr5, and are connected in parallel to the source of the transistor Tr5. Therefore, the voltage transient of the source of the transistor Tr5 is slower than that of the gate of the transistor Tr5. As a result, when the gate voltages of the transistors Tr1, Tr3 and Tr4 are switched (reduced) from high (Vdd1) to low (Vss), the gate-source voltage Vgs5 of the transistor Tr5 exceeds the threshold voltage Vth5 of the transistor Tr5, and the transistor Tr5 is turned on, and immediately after that, the transistors Tr1, Tr3 and Tr4 are turned off. In other words, when the switched input voltage Vin is applied to the gate and the source of the transistor Tr5 through the capacity elements C1 and C2, and the gate-source voltage Vgs5 exceeds the threshold voltage Vth5 by a transient difference, the transistors Tr2 and Tr5 are turned on, and immediately after that, the transistors Tr1, Tr3 and Tr4 are turned off. At this time, output voltage Vout is changed to a voltage of the high-voltage line LH1. Moreover, when the gate voltages of the transistors Tr1, Tr3 and Tr4 are switched (increased) from low (Vss) to high (Vdd1), the transistors Tr1, Tr3 and Tr4 are turned on, and immediately after that, the transistors Tr2 and Tr5 are turned off. At this time, the output voltage Vout is changed to a voltage of the low-voltage line LL.
Thus, in the inverter circuit 1 according to the third embodiment, a period where the transistor Tr1 and the transistor Tr2 are simultaneously turned on or a period where the transistor Tr4 and the transistor Tr5 are simultaneously turned on is almost eliminated. Therefore, a current (a through current) hardly flows between the high-voltage line LH1 and the low-voltage line LL through the transistors Tr1 and Tr2 and between the high-voltage line LH2 and the low-voltage line LL through the transistors Tr4 and Tr5. As a result, power consumption is allowed to be reduced. Moreover, when the gate voltages of the transistors Tr1, Tr3 and Tr4 are switched (reduced) from high (Vdd1) to low (Vss), the output voltage Vout is changed to the voltage of the high-voltage line LH1, and when the gate voltages of the transistors Tr1, Tr3 and Tr4 are switched (increased) from low (Vss) to high (Vdd1), the output voltage Vout is changed to the voltage of the low-voltage line LL. Therefore, variations in the output voltage Vout are allowed to be eliminated. As a result, for example, variations in threshold correction or mobility correction in the driving transistor from one pixel circuit to another are allowed to be reduced, and variations in luminance from one pixel to another are allowed to be reduced.
Fourth Embodiment
Configuration
FIG. 27 illustrates an example of a whole configuration of an inverter circuit 2 according to a fourth embodiment of the disclosure. As in the case of the inverter circuit 1 according to the third embodiment, the inverter circuit 2 outputs, from the output terminal OUT, a pulse signal (for example, refer to the part (B) in FIG. 19) with a substantially inverted signal waveform of a signal waveform (for example, refer to the part (A) in FIG. 19) of a pulse signal applied to the input terminal IN. The configuration of the inverter circuit 2 differs from that of the inverter circuit 1 according to the third embodiment in further including transistors Tr6 and Tr7 preceding the transistors Tr1 and Tr2 in an output stage. Hereinafter, differences between the third and fourth embodiments will be mainly described, and similarities between the third and fourth embodiments will not be described.
The transistors Tr6 and Tr7 are configured of transistors each having channels of the same conduction type as that of the transistor Tr1 or the like, for example, n-channel MOS type TFTs. The transistor Tr6 makes or breaks electrical connection between the gate of the transistor Tr2 and the low-voltage line LL in response to, for example, a potential difference Vgs6 between the voltage (the input voltage Vin) of the input terminal IN and the voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr6 is electrically connected to the input terminal IN, and one terminal of a source and a drain of the transistor Tr6 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr6 is electrically connected to the gate of the transistor Tr2. The transistor Tr7 makes or breaks electrical connection between the source (the first terminal X) of the transistor Tr5 and the gate of the transistor Tr2 in response to a potential difference Vgs7 between the gate voltage Vg5 of the transistor Tr5 and the voltage Vs5 of the source (the first terminal X) of the transistor Tr5 (or a potential difference corresponding thereto). A gate of the transistor Tr7 is electrically connected to the gate of the transistor Tr5. One terminal of a source and a drain of the transistor Tr7 is electrically connected to the source (the first terminal X) of the transistor Tr5, and the other terminal not connected to the first terminal X of the transistor. Tr7 is electrically connected to the gate of the transistor Tr2.
Operation
Next, an example of the operation of the inverter circuit 2 will be described below referring to FIGS. 28 to 47. FIG. 28 is a waveform chart illustrating an example of the operation of the inverter circuit 2. FIGS. 29 to 34 are circuit diagrams sequentially illustrating an example of the operation of the inverter circuit 2.
First, when the input voltage Vin is high (Vdd1), the transistors Tr1, Tr3, Tr4 and Tr6 are turned on. Then, the gate voltage Vg2 and the source voltage Vs2 of the transistor Tr2 are charged to the voltage VL (=Vss) of the low-voltage line LL, and the gate voltage Vg5 and the source voltage Vs5 of the transistor Tr5 are charged to the voltage VL (=Vss) of the low-voltage line LL (refer to FIGS. 28 and 29). Therefore, the transistor Tr2 is turned off (in the case where the transistor Tr2 is turned off at a voltage Vgs2=0 V), and the transistor Tr5 is turned off (in the case where the transistor Tr5 is turned off at a voltage Vgs5=0 V), and then the voltage Vss is taken out as the output voltage Vout. At this time, the capacity element C2 is charged to a voltage of Vdd2−Vss.
Next, when the input voltage Vin is switched (reduced) from high (Vdd1) to low (Vss), gate voltages Vg1, Vg3, Vg4 and Vg6 of the transistors Tr1, Tr3, Tr4 and Tr6 are switched (reduced) from the voltage Vdd1 to the voltage Vss (refer to FIGS. 28 and 30). Therefore, a change in the gate voltage Vg1 of the transistor Tr1 propagates to the source of the transistor Tr5 through the capacity element C2 to change (reduce) the source voltage Vs5 of the transistor Tr5 by ΔV1′. Moreover, the change in the gate voltage Vg1 of the transistor Tr1 also propagates to the gate of the transistor Tr5 through the capacity elements C1 and C2 to change (reduce) the gate voltage Vg5 of the transistor Tr5 by ΔV2′. However, at this time, the transistors Tr3, Tr4 and Tr6 are on. Therefore, a current flows from the low-voltage line LL to the source and the gate of the transistor Tr5 and the source and the drain of the transistor Tr7 so as to charge the source and the gate of the transistor Tr5 and the source and the drain of the transistor Tr7 to the voltage Vss.
In this case, as the gate voltages of the transistors Tr3, Tr4 and Tr6 are switched (reduced) from the voltage Vdd1 to the voltage Vss, on-resistances of the transistors Tr3, Tr4 and Tr6 are gradually increased to increase time necessary to charge the source and the gate of the transistor Tr5 and the source and the drain of the transistor Tr1 to the voltage VL of the low-voltage line LL.
Moreover, when full capacity at the source of the transistor Tr5 and full capacity at the gate of the transistor Tr5 are compared to each other, the capacity elements C1 and C2 are connected in parallel to the source of the transistor Tr5, and the capacity elements C1 and C2 are connected in series to the gate of the transistor Tr5. Therefore, the voltage transient of the source of the transistor Tr5 is slower than that of the gate of the transistor Tr5. As a result, time necessary to charge the source of the transistor Tr5 to the voltage VL of the low-voltage line LL is longer than time necessary to charge the gate of the transistor Tr5 to the voltage VL of the low-voltage line LL.
Moreover, in the case where the input voltage Vin is at a voltage VSS+Vth3 or over, and further at a voltage Vss+Vth4 or over, the transistors Tr3 and Tr4 operate in a linear region. On the other hand, in the case where the input voltage Vin is smaller than the voltage Vss+Vth3, and further smaller than the voltage Vss+Vth4, the transistors Tr3 and Tr4 operate in a saturation region. Therefore, although the current illustrated in FIG. 30 flows through the source and the gate of the transistor Tr5, each of the terminals of the transistors Tr3 and Tr4 is not allowed to be charged to the voltage Vss.
When the input voltage Vin is switched from the voltage Vdd1 to the voltage Vss, ultimately, the gate-source voltage Vgs5 of the transistor Tr5 is changed to a voltage ΔV1−ΔV2 (refer to FIGS. 28 and 31). At this time, when the gate-source voltage Vgs5 of the transistor Tr5 exceeds the threshold voltage Vth5 of the transistor Tr5, the transistor Tr5 is turned on, and the current starts to flow from the high-voltage line LH2. Moreover, at this time, when the gate voltage Vg2 of the transistor Tr2 is at a voltage Vss−ΔV3, and the transistor Tr7 operates at a saturation region.
When the transistor Tr5 is on, the source voltage Vs5 of the transistor Tr5 is increased by the transistor Tr5 in addition to the transistors Tr4 and TR6. Moreover, as the capacity element C1 is connected between the gate and the source of the transistor Tr5, a bootstrap is caused, and the gate voltage Vg5 of the transistor Tr5 is increased with an increase in the source voltage Vs5 of the transistor Tr5. After that, when the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 reach the voltage Vss−Vth3 or over, further the voltage Vss−Vth4 or over, the transistors Tr1 and Tr4 are turned off, and when the source voltage Vs5 of the transistor Tr5 reaches a voltage Vss−Vth6 or over, the transistor Tr6 is turned off. As a result, the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 are increased by a current from the transistor Tr5. Moreover, when the gate voltage Vg5 of the transistor Tr5 is increased, the transistor Tr7 is switched from the saturation region to the linear region to operate, and the source voltage Vs5 of the transistor Tr5 and the gate voltage Vg2 of the transistor Tr2 have the same potential.
After a lapse of a certain period, when the source voltage Vs5 of the transistor Tr5 (the gate voltage Vg2 of the transistor Tr2) reaches a voltage Vss+Vth2 or over, the transistor Tr2 is turned on, and a current starts to flow from the high-voltage line LH1 (refer to FIGS. 28 and 32). As a result, the voltage Vout of the output terminal OUT is gradually increased from the voltage Vss. Ultimately, the gate voltage Vg2 of the transistor Tr2 is increased to the voltage VH2 of the high-voltage line LH2 by the current from the transistor Tr5 (refer to FIGS. 28 and 33). In this case, the voltage VH2 of the high-voltage line LH2 is at a voltage Vdd2 which is larger than a voltage Vdd1+Vth2 during the drive of the inverter circuit 2, so the transistor Tr2 outputs the voltage Vdd1 which is the voltage VH1 of the high-voltage line LH1 to the output terminal OUT. As a result, the output terminal OUT outputs the voltage Vdd1 (refer to FIGS. 28 and 33).
After a lapse of another certain period, the input voltage Vin is switched (increased) from low (Vss) to high (Vdd1) (refer to FIGS. 28 and 34). At this time, in a stage where the input voltage Vin is lower than the voltage VSS+Vth3, and further lower than the voltage Vss+Vth4, the transistors Tr3 and Tr4 are off. Therefore, coupling through the capacity elements C1 and C2 is applied to the source and the gate of the transistor Tr5 to increase the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5. After that, when the input voltage Vin reaches voltages Vss+Vth1, Vss+Vth3, Vss+Vth4 and Vss+Vth6 or over, the transistors Tr1, Tr3, Tr4 and Tr6 are turned on. Therefore, a current flows toward the source (the output terminal OUT) of the transistor Tr2 and the source and the gate of the transistor Tr5 so as to charge the source (the output terminal OUT) of the transistor Tr2 and the source and the gate of the transistor Tr5 to a voltage Vss.
In this case, the gate of the transistor Tr7 is connected to the gate of the transistor Tr5. As the capacity elements C1 and C2 are connected in series to the gate of the transistor Tr5, the voltage transient of the gate of the transistor Tr5 is fast. Accordingly, the voltage transient of the gate of the transistor Tr7 is fast, and the transistor Tr7 is turned off early. When the transistor Tr7 is turned off, the gate of the transistor Tr2 and the gate of the transistor Tr5 are interrupted by each other. As a result, as illustrated in FIG. 34, the transistor Tr6 charges the gate of the transistor Tr2, and the transistor Tr4 charges the source of the transistor Tr5. Therefore, the voltage transient of the gate of the transistor Tr2 is faster than the voltage transient of the source of the transistor Tr2, and the voltage transient of the gate of the transistor Tr5 is faster than the voltage transient of the source of the transistor Tr5. As a result, at a rising edge of the input voltage Vin, a period where the transistors Tr1 and Tr2 are simultaneously on is allowed to be further reduced, and a current (a through current) flowing between the high-voltage line LH1 and the low-voltage line LL and between the high-voltage line LH2 and the low-voltage line LL is allowed to be further reduced.
Thus, in the inverter circuit 2 according to the fourth embodiment, a period where the transistor Tr1 and the transistor Tr2 are simultaneously turned on is almost eliminated. Therefore, as a current (a through current) hardly flows between the high-voltage line LH1 and the low-voltage line LL and between the high-voltage line LH2 and the low-voltage line LL, power consumption is allowed to be reduced. Moreover, when the gate voltages of the transistors Tr1 and Tr3 are switched (reduced) from high (Vdd1) to low (Vss), the output voltage Vout is changed to the voltage of the high-voltage line LH, and when the gate voltages of the transistors Tr1 and Tr3 are switched (increased) from low (Vss) to high (Vdd1), the output voltage Vout is changed to the voltage of the low-voltage line LL. Therefore, variations in the output voltage Vout are allowed to be eliminated. As a result, for example, variations in threshold correction or mobility correction in the driving transistor from one pixel circuit to another are allowed to be reduced, and variations in luminance from one pixel to another are allowed to be reduced.
Modifications of Third and Fourth Embodiments
In the third and fourth embodiments, as illustrated in FIGS. 35 and 36, a capacity element C3 for bootstrap may be arranged between the gate of the transistor Tr2 and the source (the output terminal OUT) of the transistor Tr2.
Moreover, in the third and fourth embodiments, for example, as illustrated in FIGS. 37 and 38, a delay element 3 may be arranged between the input terminal IN and the gate of the transistor Tr3.
The delay element 3 inputs, to the gate of the transistor Tr3, a voltage with a waveform obtained by delaying a voltage waveform of a signal voltage applied to the input terminal IN. For example, the delay element 3 inputs, to the gate of the transistor Tr3, a voltage with a slower falling edge than that of the voltage waveform of the signal voltage applied to the input terminal IN. Note that the delay element 3 may allow not only the falling edge but also the rising edge of the voltage waveform to be slower than that of the voltage waveform of the signal voltage applied to the input terminal IN. However, in this case, the delay element 3 delays the voltage waveform of the signal voltage applied to the input terminal IN so that its falling edge is slower than its rising edge.
The delay element 3 has any of circuit configurations illustrated in FIGS. 39A to 39D. In FIG. 39A, the delay element 3 includes a capacity element C4. An end of the capacity element C4 is electrically connected to the gate of the transistor Tr3, and the other end of the capacity element C4 is electrically connected to the low-voltage line LL.
In FIG. 39B, the delay element 3 includes a transistor Tr9. The transistor Tr9 is configured of a transistor having channels of same conduction type as that of the transistor Tr1 or the like, for example, an n-channel MOS type TFT. A source of the transistor Tr9 is electrically connected to the gate of the transistor Tr3, and a drain of the transistor Tr9 is electrically connected to the input terminal IN. A gate of the transistor Tr9 is electrically connected to a high-voltage line LH3. The high-voltage line LH3 is electrically connected to a power supply (not illustrated) outputting a pulse signal allowing the transistor Tr9 to perform an ON/OFF operation.
In FIG. 39C, the delay element 3 includes the above-described transistor Tr9 and a transistor Tr10. The transistor Tr10 is configured of a transistor having channels of same conduction type as that of the transistor Tr1 or the like, for example, an n-channel MOS type TFT. A gate and a source of the transistor Tr10 are electrically connected to the gate of the transistor Tr3, and a drain of the transistor Tr10 is electrically connected to the input terminal IN.
In FIG. 39D, the delay element 3 includes the above-described transistor Tr9 and the above-described capacity element C4.
Operation and Effects
FIG. 40 illustrates an example of the operation of the inverter circuit according to any of the modifications. Note that FIG. 40 illustrates waveforms in the case where a circuit configuration illustrated in FIG. 39D is used as the delay element 3. The basic operations of the inverter circuits according to the modifications are the same as that illustrated in FIGS. 20 to 25 or FIGS. 28 to 34. A different operation from that illustrated in FIGS. 20 to 25 or FIGS. 28 to 34 is performed when the input voltage Vin is switched (reduced) from high (Vdd1) to low (Vss) and when the input voltage Vin is switched (increased) from low (Vss) to high (Vdd1).
When the input voltage Vin is switched (reduced) from high (Vdd1) to low (Vss), the gate voltages of the transistors Tr3 and Tr4 are changed from the voltage Vdd1 to the voltage Vss. In the inverter circuits 1 and 2 according to the third and fourth embodiments, the voltage change causes a voltage change by ΔV1 in the source of the transistor Tr5 through the capacity element C2, and further causes a voltage change by ΔV2 in the gate of the transistor Tr5 through the capacity elements C1 and C2. In this case, a coupling amount of ΔV2 is applied to the gate of the transistor Tr5, because the gate voltage Vg3 of the transistor Tr3 is reduced from the voltage Vdd1 to the voltage Vss, and as a result, the on-resistance of the transistor Tr3 is gradually increased to slow a voltage transient for charging the gate of the transistor Tr5 to the voltage Vss. In other words, the coupling amount of ΔV2 is applied to the gate of the transistor Tr5, because the transistor Tr3 is switched from on to off at a timing of applying coupling.
On the other hand, in the modifications, a signal voltage as illustrated in FIG. 41 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, an off point (a point of switching from on to off) of the transistor Tr3 is delayed, compared to the case where the input voltage Vin is applied as is to the gate of the transistor Tr3. In other words, the transistor Tr3 is still on at the timing of applying coupling through the capacity element C2 (refer to FIG. 42). Therefore, ultimately, the coupling amount (ΔV2) applied to the gate of the transistor Tr5 is allowed to be reduced to be smaller than that in related art, and a gate-source voltage Vgs5 of the transistor Tr5 is allowed to be increased. As a result, the speed of the inverter circuit is allowed to be increased.
In the modifications, even in the case where the input voltage Vin is switched (increased) from low (Vss) to high (Vdd1), a signal voltage as illustrated in FIG. 41 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, as the off point of the transistor Tr3 is delayed, and the transistor Tr3 is turned on after the transistor Tr1 is turned on, and there is a possibility that a current (a through current) flows from the high-voltage line LH1 to the low-voltage line LL in a state where the output voltage Vout is switched. However, when an operation point at which the transistor Tr3 is turned on and the waveform of the signal voltage applied to the gate of the transistor Tr3 are considered, even though the signal voltage applied to the gate of the transistor Tr3 is delayed, the time of turning the transistor Tr3 on is hardly changed at the rising edge as illustrated in FIG. 42, and on the other hand, the time of turning the transistor Tr3 off is largely changed at the falling edge. Therefore, a period where the above-described through current flows is extremely short, and the power consumption of the inverter circuits according to the modifications is not much different from that of the inverter circuits 1 and 2.
In the third and fourth embodiments, coupling caused by a change in the input voltage Vin is applied to the source and the gate of the transistor Tr5 so that the gate-source voltage Vgs5 of the transistor Tr5 has a value equal to or higher than the threshold voltage Vth5 of the transistor Tr5 with use of a difference in voltage transient between the source and the gate of the transistor Tr5. At this time, the output terminal OUT outputs the voltage of the high-voltage line LH1 as the output voltage Vout, but the voltage transient of the output terminal OUT is highly dependent on the gate-source voltage Vgs2 of the transistor Tr2. In other words, in the case where the gate-source voltage Vgs2 of the transistor Tr2 is rapidly increased, the output voltage Vout rapidly rises, and in the case where the gate-source voltage Vgs2 of the transistor Tr2 is gradually increased, the output voltage Vout gradually rises.
Therefore, to increase the speed of the inverter circuit, it is necessary for the gate-source voltage Vgs2 of the transistor Tr2 to rapidly rise, as a method of doing so, for example, it is considered to increase the capacity of the capacity element C2. However, in the case where the capacity of the capacity element C2 is increased, an area occupied by the inverter circuit is increased. As a result, for example, in the case where the inverter circuit including the capacity element C2 with a larger capacity is used for a scanner or the like in an organic EL display, an area occupied by the inverter circuit in a peripheral part (a frame) of a display panel may be increased to interfere with a reduction in the area of the frame. Moreover, an increase in the capacity of the capacity element C2 causes a larger voltage change than ΔV1 in the source (the output terminal OUT) of the transistor Tr2, thereby causing a larger voltage change than ΔV2 in the gate of the transistor Tr2. As a result, even though the capacity of the capacity element C2 is increased, the gate-source voltage Vgs2 of the transistor Tr2 has a value not much different from ΔV1−ΔV2; therefore, an increase in the capacity of the capacity element C2 does not much contribute to an increase in the speed of the inverter circuit.
On the other hand, in the modifications, the signal voltage as illustrated in FIG. 41 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, the speed of the inverter circuit is allowed to be increased without increasing the capacity of the capacity element C2.
Moreover, in the third and fourth embodiments and the modifications thereof, the transistors Tr1 to Tr10 are configured of the n-channel MOS type TFTs, but they may be configured of, for example, p-channel MOS type TFTs. However, in this case, a transient response when the transistors Tr1 to Tr10 are switched (increased) from low to high and a transient response when the transistors Tr1 to Tr10 are switched (reduced) from high to low are opposite to each other. Moreover, the high-voltage line LH1 is replaced with a low-voltage line LL1, and the high-voltage line LH2 is replaced with a low-voltage line LL2, and the low-voltage line LL is replaced with the high-voltage line LH.
Note that in this case, the low-voltage lines LL1 and LL2 are connected to a power supply (not illustrated) outputting a lower voltage (a constant voltage) than the voltage of the high-voltage line LH. The voltage of the low-voltage line LL1 is at a voltage Vss1 during the drive of the inverter circuit, and the voltage of the low-voltage line LL2 is at a voltage Vss2 (≦Vss1−Vth2) during the drive of the inverter circuit. On the other hand, the high-voltage line LH is connected to a power supply (not illustrated) outputting a higher voltage (a constant voltage) than the voltages of the low-voltage lines LL1 and LL2, and the voltage of the high-voltage line LH is at a voltage Vdd (>Vss1) during the drive of the inverter circuit.
Fifth Embodiment
Configuration
FIG. 43 illustrates an example of a whole configuration of an inverter circuit 1 according to a fifth embodiment of the disclosure. The inverter circuit 1 outputs, from an output terminal OUT, a pulse signal (for example, refer to a part (B) in FIG. 44) with a substantially inverted signal waveform of a signal waveform (for example, refer to a part (A) in FIG. 44) of a pulse signal applied to an input terminal IN. The inverter circuit 1 is preferably formed on amorphous silicon or amorphous oxide semiconductor, and includes seven transistors Tr1 to Tr7 each having channels of same conduction type. In addition to the above-described seven transistors Tr1 to Tr7, the inverter circuit 1 includes three capacity elements C1 to C3, the input terminal IN and the output terminal OUT. In other words, the inverter circuit 1 has a 7Tr3C circuit configuration.
The transistors Tr1, Tr2, Tr3, Tr4, Tr5, Tr6 and Tr7 correspond to specific examples of “a first transistor”, “a second transistor”, “a third transistor”, “a fourth transistor”, “a fifth transistor”, “a sixth transistor”, and “a seventh transistor” in the disclosure, respectively. Moreover, the capacity elements C1, C2 and C3 correspond to specific examples of “a first capacity element”, “a second capacity element” and “a third capacity element” in the disclosure, respectively.
The transistors Tr1 to Tr7 are configured of thin-film transistors (TFTs) each having channels of same conductive type, for example, n-channel MOS (Metal Oxide Semiconductor) type thin-film transistors (TFTs). The transistor Tr1 makes or breaks electrical connection between the output terminal OUT and a low-voltage line LL in response to, for example, a potential difference Vgs1 between a voltage (an input voltage Vin) of the input terminal IN and a voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr1 is electrically connected to the input terminal IN, and one terminal of a source and a drain of the transistor Tr1 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr1 is electrically connected to the output terminal OUT. The transistor Tr2 makes or breaks electrical connection between a high-voltage line LH and the output terminal OUT in response to a potential difference Vgs2 between a voltage Vs7 of a terminal (a terminal A) not connected to the high-voltage line LH of a source and a drain of the transistor Tr7 and a voltage (output voltage Vout) of the output terminal OUT (or a potential difference corresponding thereto). A gate of the transistor Tr2 is electrically connected to the terminal A of the transistor Tr7. One terminal of a source and a drain of the transistor Tr2 is electrically connected to the output terminal OUT, and the other terminal not connected to the output terminal OUT of the transistor Tr2 is electrically connected to the high-voltage line LH.
The transistor Tr3 makes or breaks electrical connection between a gate of the transistor Tr5 and the low-voltage line LL in response to a potential difference Vgs3 between the input voltage Vin and the voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr3 is electrically connected to the input terminal IN. One terminal of a source and a drain of the transistor Tr3 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr3 is electrically connected to a gate of the transistor Tr5. The transistor Tr4 makes or breaks electrical connection between one terminal (a terminal F) not connected to the high-voltage line LH of a source and a drain of the transistor Tr5 and the low-voltage line LL in response to a potential difference Vgs4 between the input voltage Vin and the voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr4 is electrically connected to the input terminal IN. One terminal of a source and a drain of the transistor Tr4 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr4 is electrically connected to the terminal F of the transistor Tr5. The transistor Tr5 makes or breaks electrical connection between the high-voltage line LH and the terminal F in response to a voltage Vgs5 between terminals of the capacity element C1 (or a potential difference corresponding thereto). The gate of the transistor Tr5 is electrically connected to the terminal not connected to the low-voltage line LL of the source and the drain of the transistor Tr1. One terminal of the source and the drain of the transistor Tr5 is electrically connected to the high-voltage line LH. The other terminal (the terminal F) not connected to the high-voltage line LH of the transistor Tr5 is electrically connected to a gate of the transistor Tr7 and the terminal not connected to the low-voltage line LL of the source and the drain of the transistor Tr4.
The transistor Tr6 makes or breaks electrical connection between the terminal (the terminal A) not connected to the high-voltage line LH of the source and the drain of the transistor Tr7 and the low-voltage line LL in response to a potential difference Vgs6 between the input voltage Vin and the voltage VL of the low-voltage line LL (or a potential difference corresponding thereto). A gate of the transistor Tr6 is electrically connected to the input terminal IN. One terminal of a source and a drain of the transistor Tr6 is electrically connected to the low-voltage line LL, and the other terminal not connected to the low-voltage line LL of the transistor Tr6 is electrically connected to the terminal A of the transistor Tr7. In other words, the transistors Tr1, Tr3, Tr4 and Tr6 are connected to the same voltage line (the low-voltage line LL). Therefore, a terminal on a side close to the low-voltage line LL of the transistor Tr1, a terminal on a side close to the low-voltage line LL of the transistor Tr3, a terminal on a side close to the low-voltage line LL of the transistor Tr4 and a terminal on a side close to the low-voltage line. LL of the transistor Tr6 have the same potential. The transistor Tr7 makes or breaks electrical connection between the high-voltage line LH and the gate of the transistor Tr2 in response to a potential difference Vgs7 between the voltage Vs5 of the terminal (a terminal F) not connected to the high-voltage line LH of the source and the drain of the transistor Tr5 and the gate voltage Vg2 of the transistor Tr2 (or a potential difference corresponding thereto). The gate of the transistor Tr7 is electrically connected to the terminal F of the transistor Tr5. One terminal of the source and the drain of the transistor Tr7 is electrically connected to the gate of the transistor Tr2, and the other terminal not connected to the gate of the transistor Tr2 of the transistor Tr7 is electrically connected to the high-voltage line LH. In other words, the transistors Tr2, Tr5 and Tr7 are connected to the same voltage line (the high-voltage line LH). Therefore, a terminal on a side close to the high-voltage line LH of the transistor Tr2, a terminal on a side close to the high-voltage line LH of the transistor Tr5 and a terminal on a side close to the high-voltage line LH of the transistor Tr7 have the same potential.
The low-voltage line LL corresponds to a specific example of “a first voltage line”, “a third voltage line”, “a fourth voltage line” and “a sixth voltage line” in the disclosure. The high-voltage line LH corresponds to a specific example of “a second voltage line”, “a fifth voltage line” and “a seventh voltage line” in the disclosure.
The high-voltage line LH is connected to a power supply (not illustrated) outputting a higher voltage (a constant voltage) than the voltage VL of the low-voltage line LL, and the voltage VH of the high-voltage line LH is at a voltage Vdd during the drive of the inverter circuit 1. The voltage Vdd has the same voltage value as that of a high voltage of a signal voltage (the input voltage Vin) applied to the input terminal IN. On the other hand, the low-voltage line LL is connected to a power supply (not illustrated) outputting a lower voltage (a constant voltage) than the voltage VH of the high-voltage line LH, and the voltage VL of the low-voltage line LL is at a voltage Vss (<Vdd) during the drive of the inverter circuit 1.
The capacity elements C1 and C2 are inserted in series between the input terminal IN and the gate of the transistor Tr5. An electrical connection point D between the capacity element C1 and the capacity element C2 is electrically connected to the terminal F of the transistor Tr5. The capacity element C1 is inserted on a side close to the gate of the transistor Tr5, and the capacity element C2 is inserted on a side close to the gate of the transistor Tr1. The capacity of the capacity element C2 is larger than that of the capacity element C1. Both of the capacities of the capacity elements C1 and C2 preferably satisfy the following expression (1). If the capacities of the capacity elements C1 and C2 satisfy the expression (1), at a falling edge of an input voltage Vin which will be described later, a gate-source voltage of the transistor Tr5 is allowed to reach a threshold voltage Vth5 or over of the transistor Tr5, and the transistor Tr5 is allowed to be turned on. As a result, the output voltage Vout is allowed to be switched from low to high.

C2(Vdd−Vss)/(C1+C2)>Vth5  (1)

In this case, a circuit part including the capacity elements C1 and C2 configures a control element 10 in the inverter circuit 1. For example, as illustrated in FIG. 43, the control element 10 includes a terminal P1 electrically connected to the input terminal IN, a terminal P2 electrically connected to the terminal F of the transistor Tr5 and a terminal P3 electrically connected to the gate of the transistor Tr5.
The terminals P1, P2 and P3 correspond to a specific example of “a second terminal”, “a third terminal” and “a fourth terminal” in the disclosure, respectively.
For example, when a falling-edge voltage is applied to the terminal P1, the control element 10 allows a voltage transient of the terminal P2 to be slower than a voltage transient of the terminal P3. More specifically, when the falling-edge voltage is applied to the input terminal IN, the control element 10 allows a voltage transient of the source of the transistor Tr5 to be slower than a voltage transient of the gate of the transistor Tr5. Note that the operation of the control element 10 will be described with the following description of the operation of the inverter circuit 1. The source of the transistor Tr5 corresponds to a specific example of “a first terminal” in the disclosure.
Operation
Next, an example of the operation of the inverter circuit 1 will be described below referring to FIGS. 45 to 69. FIG. 45 is a waveform chart illustrating an example of the operation of the inverter circuit 1. FIGS. 46 to 51 are circuit diagrams sequentially illustrating an example of the operation of the inverter circuit 1.
First, when the input voltage Vin is high (Vdd), the transistors Tr1, Tr3, Tr4 and Tr6 are turned on. Accordingly, the gate voltages Vg2, Vg5 and Vg7 and the source voltages Vs2, Vs5 and Vs7 of the transistors Tr2, Tr5 and Tr7 are charged to the voltage VL (=Vss) of the low-voltage line LL (refer to FIGS. 45 and 46). Therefore, the transistors Tr2, Tr5 and Tr7 are turned off (in the case where the transistors Tr2, Tr5 and Tr7 are turned off at voltages Vgs2, Vgs5 and Vgs7=0 V, respectively), and the voltage Vss is taken out as the output voltage Vout. At this time, the capacity element C2 is charged to a voltage of Vdd−Vss.
Next, when the input voltage Vin is switched (reduced) from high (Vdd) to low (Vss), gate voltages Vg1, Vg3, Vg4 and Vg6 of the transistors Tr1, Tr3, Tr4 and Tr6 are switched (reduced) from the voltage Vdd to the voltage Vss (refer to FIGS. 45 and 47). Therefore, a change in the gate voltage Vg1 of the transistor Tr1 propagates to the gate of the transistor Tr7 through the capacity element C2 to change (reduce) the gate voltage Vg7 of the transistor Tr7 by ΔV1′. Moreover, the change in the gate voltage Vg1 of the transistor Tr1 also propagates to the gate of the transistor Tr5 through the capacity elements C1 and C2 to change (reduce) the gate voltage Vg5 of the transistor Tr5 by ΔV2′. However, at this time, the transistors Tr1, Tr3, Tr4 and Tr6 are on. Therefore, a current flows from the low-voltage line LL to the sources and the gates of the transistors Tr2, Tr5 and Tr7 so as to charge the sources and the gates of the transistors Tr2, Tr5 and Tr7 to the voltage Vss.
In this case, as the gate voltages of the transistors Tr1, Tr3, Tr4 and Tr6 are switched (reduced) from the voltage Vdd to the voltage Vss, on-resistances of the transistors Tr1, Tr3, Tr4 and Tr6 are gradually increased to increase time necessary to charge the sources and the gates of the transistors Tr2, Tr5 and Tr7 to the voltage VL of the low-voltage line LL.
Moreover, when full capacity at the source of the transistor Tr5 and full capacity at the gate of the transistor Tr5 are compared to each other, the capacity elements C1 and C2 are connected in parallel to the source of the transistor Tr5, and the capacity elements C1 and C2 are connected in series to the gate of the transistor Tr5. Therefore, the voltage transient of the source of the transistor Tr5 is slower than that of the gate of the transistor Tr5. As a result, time necessary to charge the source of the transistor Tr5 to the voltage VL of the low-voltage line LL is longer than time necessary to charge the gate of the transistor Tr5 to the voltage VL of the low-voltage line LL.
Moreover, in the case where the input voltage Vin is at a voltage Vss+Vth3 or over, and further at a voltage Vss+Vth4 or over, the transistors Tr3 and Tr4 operate in a linear region. Note that Vth3 is a threshold voltage of the transistor Tr3, and Vth4 is a threshold voltage of the transistor Tr4. On the other hand, in the case where the input voltage Vin is smaller than the voltage Vss+Vth3, and further smaller than the voltage Vss+Vth4, the transistors Tr3 and Tr4 operate in a saturation region. Therefore, although a current illustrated in FIG. 47 flows through the source and the gate of the transistor Tr5, each of the terminals of the transistors Tr3 and Tr4 is not allowed to be charged to the voltage Vss.
When the input voltage Vin is switched from the voltage Vdd to the voltage Vss, ultimately, the gate-source voltage Vgs5 of the transistor Tr5 is chanted to a voltage ΔV1−ΔV2 (refer to FIGS. 45 and 48). At this time, when the gate-source voltage Vgs5 of the transistor Tr5 exceeds the threshold voltage Vth5 of the transistor Tr5, the transistor Tr5 is turned on, and the current starts to flow from the high-voltage line LH.
When the transistor Tr5 is on, the source voltage Vs5 of the transistor Tr5 is increased by the transistor Tr5 in addition to the transistor Tr4. Moreover, as the capacity element C1 is connected between the gate and the source of the transistor Tr5, a bootstrap is caused, and the gate voltage Vg5 of the transistor Tr5 is increased with an increase in the source voltage Vs5 of the transistor Tr5. After that, when the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 reach the voltage Vss−Vth3 or over, further the voltage Vss−Vth4 or over, the transistors Tr3 and Tr4 are turned off, and the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 are increased only by the transistor Tr5.
After a lapse of a certain period, when the source voltage Vs5 of the transistor Tr5 (the gate voltage Vg1 of the transistor Tr7) reaches a voltage Vss+Vth7 or over, the transistor Tr7 is turned on, and a current starts to flow through the transistor Tr7 (refer to FIGS. 45 and 49). Note that Vth7 is a threshold voltage of the transistor Tr7. As a result, the source voltage Vs7 of the transistor Tr7 (the gate voltage Vg2 of the transistor Tr2) is gradually increased from the voltage Vss.
Now, the gate voltage Vg2 and the source voltage Vs2 of the transistor Tr2 will be considered below. The capacity element C3 is connected between the gate and the source of the transistor Tr2. The capacity element C3 causes a bootstrap, and the source voltage Vs2 and the gate voltage Vg2 of the transistor Tr2 are changed in conjunction with each other. The gate voltage Vg2 of the transistor Tr2 is increased by a current from the transistor Tr7 and an increase in the source voltage Vs2 of the transistor Tr2. Therefore, compared to the case where the gate voltage Vg2 of the transistor Tr2 is increased only by a current through the transistor Tr2, the voltage transient of the gate of the transistor Tr2 is faster. As a result, a gate-source voltage Vgs2 of the transistor Tr2 is gradually increased.
At this time, as the transistor Tr5 is on, the gate voltage Vg7 of the transistor Tr7 does not follow an increase in the source voltage Vs7 of the transistor Tr7 and is changed to the voltage VH (=Vdd) of the high-voltage line LH ultimately. Therefore, the current from the transistor Tr7 is reduced with an increase in the gate voltage Vg2 of the transistor Tr2 (the source voltage Vs7 of the transistor Tr7). When the case where the gate-source voltage Vgs7 of the transistor Tr7 reaches the threshold voltage Vth7 of the transistor. Tr7 is considered, a current flowing from the high-voltage line LH is reduced to an extremely small amount, and the gate voltage Vg2 of the transistor Tr2 is hardly changed by the current through the transistor Tr7. However, at this time, as the transistor Tr2 is on, and the source voltage Vs2 of the transistor Tr2 is increased, the gate voltage Vg2 of the transistor Tr2 keeps on increasing by a bootstrap operation. As a result, the transistor Tr7 is completely turned off. At this time, in the case where the gate-source voltage Vgs2 of the transistor Tr2 is at a voltage ΔVss, when the voltage ΔVss is larger than the threshold voltage Vth2 of the transistor Tr2, the gate voltage Vg2 and the source voltage Vs2 of the transistor Tr2 keeps on increasing even after the transistor Tr7 is turned off, and ultimately, the voltage VH (=Vdd) of the high-voltage line LH is taken out as the voltage Vout (refer to FIGS. 45 and 50).
Then, after a lapse of another certain period, the input voltage Vin is switched (increased) from low (Vss) to high (Vdd) (refer to FIGS. 45 and 51). At this time, in a stage where the input voltage Vin is lower than the voltage Vss+Vth3, and further lower than the voltage Vss+Vth4, the transistors Tr3 and Tr4 are off. Therefore, coupling through the capacity elements C1 and C2 is applied to the source and the gate of the transistor Tr5 to increase the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5. After that, when the input voltage Vin reaches the voltage Vss+Vth1, Vss+Vth3, Vss+Vth6 and Vss+Vth4 or over, the transistors Tr1, Tr3, Tr4 and Tr6 are turned on. Therefore, a current flows toward the source (the output terminal OUT) and the gate of the transistor Tr2 and the source and the gate of the transistor Tr5 so as to charge the source (the output terminal OUT) and the gate of the transistor Tr2 and the source and the gate of the transistor Tr5 to the voltage Vss.
In this case, as the gate voltages Vg1, Vg3, Vg4 and Vg6 of the transistor Tr1, Tr3, Tr4 and Tr6 are switched (increased) from the voltage Vdd to the voltage Vss, on-resistances of the transistors Tr1, Tr3, Tr4 and Tr6 are gradually reduced to relatively reduce time necessary to charge the sources and the gates of the transistors Tr2 and Tr5 to the voltage VL of the low-voltage line LL. Ultimately, the source voltage Vs2 of the transistor Tr2 and the source voltage Vs5 and the gate voltage Vg5 of the transistor Tr5 reach the voltage Vss, and the output terminal outputs the voltage Vss (refer to FIGS. 45 and 46).
As described above, the inverter circuit 1 according to the fifth embodiment outputs, from the output terminal OUT, a pulse signal (for example, refer to the part (B) in FIG. 44) with a substantially inverted signal waveform of a signal waveform (for example, refer to the part (A) in FIG. 44) of a pulse signal applied to the input terminal IN.
Effects
The inverter circuit 200 in related art illustrated in FIG. 72 has, for example, a single channel type circuit configuration in which two n-channel MOS type transistors Tr1 and Tr2 are connected to each other in series. In the inverter circuit 200, for example, as illustrated in FIG. 73, when the input voltage Vin is at the voltage Vss, the output voltage Vout is not at the voltage Vdd but at a voltage Vdd−Vth2. In other words, the output voltage Vout includes the threshold voltage Vth2 of the transistor Tr2, and the output voltage Vout is greatly affected by variations in the threshold voltage Vth2 of the transistor Tr2.
Therefore, it is considered that, for example, as illustrated in an inverter circuit 300 in FIG. 74, the gate and the drain of the transistor Tr2 are electrically separated from each other, and the gate is connected to the high-voltage wiring line LH2 to which a higher voltage Vdd2 (≧Vdd+Vth2) than the voltage Vdd of the drain is applied. Moreover, for example, a bootstrap type circuit configuration represented by an inverter circuit 400 in FIG. 75 is considered.
However, in any of the circuits in FIGS. 72, 74 and 75, even in the case where the input voltage Vin is high, that is, even in the case where the output voltage Vout is low, a current (a through current) flows from the high-voltage wiring line LH to the low-voltage wiring line LL through the transistors Tr1 and Tr2. As a result, power consumption in the inverter circuits is increased. Moreover, in the circuits in FIGS. 72, 74 and 75, for example, as illustrated in a point encircled by a broken line in a part (B) in FIG. 73, when the input voltage Vin is at the voltage Vdd, the output voltage Vout is not at the voltage Vss, and a peak value of the output voltage. Vout varies. Therefore, for example, in the case where the inverter circuits are used in a scanner in an active matrix organic EL display, threshold correction or mobility correction in the driving transistor varies from one pixel circuit to another, thereby causing variations in luminance.
On the other hand, in the inverter circuit 1 according to the fifth embodiment, the transistors Tr1, Tr3, Tr4 and Tr6 performing an ON/OFF operation in response to a potential difference between the input voltage Vin and the voltage VL of the low-voltage line LL are arranged between the gate of the transistor Tr5 and the low-voltage line LL, between the gate of the transistor Tr7 and the low-voltage line LL, between the gate of the transistor Tr2 and the low-voltage line LL, and between the source of the transistor Tr2 and the low-voltage line LL. Therefore, when the gate voltages of the transistors Tr1, Tr3, Tr4 and Tr6 are switched (reduced) from high (Vdd) to low (Vss), on-resistances of the transistors Tr1, Tr3, Tr4 and Tr6 are gradually increased to increase time necessary to charge the gates and the sources of the transistors Tr2, Tr5 and Tr7 to the voltage VL of the low-voltage line LL. Moreover, when the gate voltages of the transistors Tr1, Tr3, Tr4 and Tr6 are switched (increased) from low (Vss) to high (Vdd), the on-resistances of the transistors Tr1, Tr3, Tr4 and Tr6 are gradually reduced to reduce time necessary to charge the gates and the sources of the transistors Tr2, Tr5 and Tr7 to the voltage VL of the low-voltage line LL. Further in the embodiment of the disclosure, the capacity element C1 and the capacity element C2 which are connected in series to each other are inserted between the input terminal IN and the gate of the transistor Tr5. Moreover, the source of the transistor Tr5 is electrically connected between the capacity element C1 and the capacity element C2. Therefore, the capacity element C1 and the capacity element C2 are connected in parallel to the source of the transistor Tr5, and are electrically connected in series to the gate of the transistor Tr5. As a result, the voltage transient of the source of the transistor Tr5 is slower than that of the gate of the transistor Tr5. Therefore, when the gate voltages of the transistor Tr3, the transistor Tr4, the transistor Tr6 and the transistor Tr1 are switched (reduced) from high (Vdd) to low (Vss), the gate-source voltage Vgs5 of the transistor Tr5 exceeds the threshold voltage Vth5 of the transistor Tr5, and the transistor Tr5 is turned on, and immediately after that, the transistor Tr4 is turned off. At this time, while the transistor Tr7 is turned on, the transistor Tr4 is turned off, and while the transistor Tr2 is turned on, the transistor Tr6 is turned off, and after that, the transistor Tr7 is turned off. As a result, the output voltage Vout is changed to the voltage of the high-voltage line LH. Moreover, the gate voltages of the transistor Tr3, the transistor Tr4, the transistor Tr6 and the transistor Tr1 are switched (increased) from low (Vss) to high (Vdd), the transistor Tr3, the transistor Tr4 and the transistor Tr6 are turned on, and immediately after that, the transistor Tr5 is turned off. At this time, while the transistor Tr2 is turned off, the transistor Tr1 is turned on; therefore, the output voltage is changed to a voltage of the low-voltage line VL.
Thus, in the inverter circuit 1 according to the fifth embodiment, a period where the transistor Tr1 and the transistor Tr2 are simultaneously turned on, a period where the transistor Tr4 and the transistor Tr5 are simultaneously turned on, or a period where the transistor Tr6 and the transistor Tr7 are simultaneously turned on is almost eliminated. Therefore, a current (a through current) hardly flows between the high-voltage line LH and the low-voltage line LL through the transistors Tr1 and Tr2, though the transistors Tr4 and Tr5, or through the transistor Tr6 and Tr7. As a result, power consumption is allowed to be reduced. Moreover, when the gate voltages of the transistors Tr1, Tr3, Tr4 and Tr6 are switched (reduced) from high (Vdd) to low (Vss), the output voltage Vout is changed to the voltage of the high-voltage line LH, and when the gate voltages of the transistors Tr1, Tr3, Tr4 and Tr6 are switched from low (Vss) to high (Vdd), the output voltage Vout is changed to the voltage of the low-voltage line LL. Therefore, variations in the output voltage Vout are allowed to be eliminated. As a result, for example, variations in threshold correction or mobility correction in the driving transistor from one pixel circuit to another are allowed to be reduced, and variations in luminance from one pixel to another are allowed to be reduced.
Moreover, in the fifth embodiment, the capacity elements C1 and C2 are directly connected to the output terminal OUT; therefore, a coupling amount applied to the gate and the source of the transistor Tr5 are not affected by parasitic capacitance in an output stage. Therefore, the gate-source voltage Vgs5 of the transistor Tr5 is allowed to be increased, and the speed of the inverter circuit 1 is allowed to be increased accordingly.
Further in the fifth embodiment, only one common voltage line on a low voltage side and only one common voltage line on a high voltage side are arranged in the inverter circuit 1, and the voltage of the high-voltage line LH as the voltage line on the high voltage side has the same voltage value (Vdd) as that of a high voltage of the signal voltage (the input voltage Vin) applied to the input terminal IN during the drive of the inverter circuit 1. Therefore, it is only necessary for the inverter circuit 1 to have the same resistance to pressure as that of the inverter circuits in related art illustrated in FIGS. 72, 74 and 75, and it is not necessary to increase the resistance to pressure of the inverter circuit 1. Therefore, it is not necessary to use an element with high resistance to pressure in the inverter circuit 1, and there is no decline in yields due to a defect in resistance to pressure; therefore, manufacturing cost is allowed to be kept low.
Moreover, in the fifth embodiment, the inverter circuit 1 includes the minimum number of voltage lines, and as described above, the speed of the inverter circuit 1 is allowed to be increased without increasing the capacity of the capacity element C2. Therefore, for example, in the case where the inverter circuit 1 is used for a scanner or the like in an active matrix organic EL display, an area occupied by the inverter circuit 1 in a peripheral part (a frame) of a display panel is allowed to be reduced, thereby achieving a reduction in the area of the frame.
Sixth Embodiment
FIG. 52 illustrates an example of a whole configuration of an inverter circuit 2 according to a sixth embodiment of the disclosure. As in the case of the inverter circuit 1 according to the fifth embodiment, the inverter circuit 2 outputs, from the output terminal OUT, a pulse signal (for example, refer to the part (B) in FIG. 44) with a substantially inverted signal waveform of a signal waveform (for example, refer to the part (A) in FIG. 44) of a pulse signal applied to the input terminal IN. The configuration of the inverter circuit 2 differs from that of the inverter circuit 1 according to the fifth embodiment of the disclosure in increasing the capacity of the capacity element C3 and providing a subsidiary capacitance Csub between the output terminal OUT and the low-voltage line LL. Hereinafter, first, an issue which may occur in the inverter circuit 1 according to the fifth embodiment will be described, and after that, a characteristic part of the inverter circuit 2 according to the sixth embodiment will be described. Note that the subsidiary capacitance Csub corresponds to a specific example of “a fourth capacity element” in the disclosure.
Issue
The gate voltage Vg2 and the source voltage Vs2 (the output voltage Vout) of the transistor Tr2 of the inverter circuit 1 according to the fifth embodiment will be considered below. As described above, the gate voltage Vg2 of the transistor Tr2 is increased by a current from the transistor Tr7 and an increase in the source voltage Vs2 of the transistor Tr2 through the capacity element C3. At this time, as the current from the transistor Tr7 is reduced with an increase in the gate voltage Vg2 of the transistor Tr2, after the transistor Tr7 is turned off, the gate voltage Vg2 of the transistor Tr2 is increased only by an increase in the source voltage Vs2 of the transistor Tr2. In the inverter circuit 1, parasitic capacitances Cgs2 and Cgd2 as illustrated in FIG. 53 are present in the gate of the transistor Tr2. Therefore, a change amount ΔVg of the gate voltage Vg2 of the transistor Tr2 is changed relative to a change amount ΔV, of the source voltage Vs2 of the transistor Tr2 at a constant ratio g as illustrated in Mathematical Expression 1. The ratio g is called a bootstrap gain.
Mathematical Expression 1
To increase the speed of the inverter circuit 1, typically, the sizes of the transistors Tr1 and Tr2 outputting the output voltage Vout are increased. In the case where the size of the transistor Tr1 is increased, when the input voltage Vin is switched (increased) from low (Vss) to high (Vdd), a larger amount of current is allowed to flow between the gate and the source of the transistor Tr1. Therefore, when the size of the transistor Tr1 is increased, the speed of a falling-edge transient of the output voltage Vout is increased.
Next, the case where the size of the transistor Tr2 is increased will be considered below. The transistor Tr2 does not operate directly by the input voltage Vin, and the transistor Tr2 operates by the current from the transistor Tr7. When the gate voltage Vg2 of the transistor Tr2 is increased by the transistor Tr7, as illustrated in FIG. 54, coupling is applied to the output terminal OUT through a capacitance Cgs2 between the gate and the source of the transistor Tr2. The coupling amount (a change amount ΔVs) is as illustrated in Mathematical Expression 2.
Mathematical Expression 2
A ratio β of the change amount ΔV, to the change amount ΔVg is called “input gain”. Note that in FIG. 54, a state where a parasitic capacitance Cout is generated between the output terminal OUT and the low-voltage line LL.
In the case where the gate-source voltage Vgs2 of the transistor Tr2 exceeds the threshold voltage Vth2 thereof by transistor Tr7, a current flows from the transistor Tr2 to increase the output voltage Vout. In the case where the size of the transistor Tr2 is large, the current drive performance of the transistor Tr2 is high; therefore, when the gate-source voltage Vgs2 of the transistor Tr2 reaches a voltage Vth2+Va, the source voltage Vs2 of the transistor Tr2 starts to increase. The voltage Va has a small value, because the size of the transistor Tr2 is large. At this time, a change amount (a gradient in a graph illustrated in FIG. 55) per unit time of the source voltage Vs2 of the transistor Tr2 relative to a change amount per unit time of the gate voltage Vg2 of the transistor Tr2 is large, the gate-source voltage Vgs2 of the transistor Tr2 is reduced with time. Moreover, when the gate voltage Vg2 of the transistor Tr2 approaches a voltage Vdd−Vth7, the transistor Tr2 allows the gate voltage Vg2 and the source voltage Vs2 thereof to be increased by the current through the transistor Tr2. At this time, the gate-source voltage Vgs2 of the transistor Tr2 is gradually reduced more by the bootstrap gain g.
Therefore, in the case where a voltage Va has a small value, and the bootstrap gain g is small, ultimately, the gate-source voltage Vgs2 of the transistor Tr2 reaches the threshold voltage Vth2 of the transistor Tr2 before the source voltage Vs2 of the transistor Tr2 reaches the voltage Vdd. Therefore, the source voltage Vs2 of the transistor Tr2 is not allowed to increase any more. As a result, the transistor Tr2 is not allowed to output the voltage Vdd.
To solve this issue, it is considered to increase the capacity of the capacity element C3 so as to increase the bootstrap gain g. However, in such a case, an input gain is increased. When the input gain is increased, as illustrated in FIG. 56, in the case where the gate-source voltage Vgs2 of the transistor Tr2 is equal to or lower than the threshold voltage Vth2 of the transistor Tr2, a source potential Vs2 is largely increased in response to a change in the gate voltage Vg2 of the transistor Tr2. Therefore, the source potential Vs2 of the transistor Tr2 starts to increase earlier. As a result, the source voltage Vs2 of the transistor Tr2 starts to increase at a point where a change in the gate voltage Vg2 of the transistor Tr2 is not so large, and the transistor Tr2 performs threshold correction. In other words, the change amount of the source voltage Vs2 is larger than the change amount of the gate voltage Vg2 of the transistor Tr2, and the gate-source voltage Vgs2 of the transistor Tr2 is increasingly reduced to reach the threshold voltage Vth2 ultimately. Therefore, also in this case, the transistor Tr2 is not allowed to output the voltage Vdd.
Inverter circuit 2
On the other hand, in the inverter circuit 2 according to the sixth embodiment, the capacity of the capacity element C3 is increased, and the subsidiary capacitance Csub is further provided between the output terminal OUT and the low-voltage line LL.
In the case where the subsidiary capacitance Csub is provided, as represented by Mathematical Expression 3, the bootstrap gain g is not affected by the subsidiary capacitance Csub. On the other hand, as represented by Mathematical Expression 4, as the subsidiary capacitance Csub is put in a denominator, the input gain β is reduced by the subsidiary capacitance Csub.
Mathematical Expression 3
Mathematical Expression 4
Next, the case where the size of the transistor Tr2 is increased in the inverter circuit 2 is considered. When the subsidiary capacitance Csub is provided between the output terminal OUT and the low-voltage line LL, as illustrated in FIG. 57, a point where an increase in the source voltage Vs2 of the transistor Tr2 starts is delayed. At this time, the gate-source voltage Vgs2 when the increase starts has a value Vth2+Vb.
In this case, Vb>Va is established, because compared to the case where the subsidiary capacitance Csub is present and the case where the subsidiary capacitance Csub is not present, a change amount of the source voltage Vs2 of the transistor Tr2 is smaller in the case where the subsidiary capacitance Csub is present, even if a current with the same magnitude flows. It is because in the case where the subsidiary capacitance Csub is not present, to obtain the same change amount of the source voltage Vs2 as that in the case where the subsidiary capacitance Csub is present, it is necessary to increase the gate-source voltage Vgs2 of the transistor Tr2.
Thus, in the inverter circuit 2, the point where the increase in the source voltage Vs2 starts is delayed to increase the value of a voltage Vb. Therefore, even if the gate-source voltage Vgs2 of the transistor Tr2 is reduced by the current from the transistor Tr2 or the bootstrap gain g, ultimately, the gate-source voltage Vgs2 of the transistor Tr2 is allowed to keep a larger value than the threshold voltage Vth2 thereof. As a result, the transistor Tr2 is allowed to output the voltage Vdd.
Modifications of Fifth and Sixth Embodiments
In the sixth embodiment, for example, as illustrated in FIG. 58, the capacity element C3 may be removed. In this case, a parasitic capacitance Cgs2 is present between the gate and the source of the transistor Tr2, and a bootstrap gain by the parasitic capacitance Cgs2 is present. Therefore, the gate-source voltage Vgs2 of the transistor Tr2 is allowed to be increased by providing the subsidiary capacitance Csub. As a result, when the input voltage Vin is switched (increased) from low (Vss) to high (Vdd), the voltage Vdd is allowed to be taken out as the output voltage Vout.
Moreover, in the sixth embodiment, as illustrated in an inverter circuit 4 in FIG. 59, the transistors Tr3 and Tr5 and the capacity elements C1 and C2 are removed, and instead of them, transistors Tr8 and Tr9 and a capacity element C4 may be provided. The inverter circuit 4 inputs a charge held by the capacity element C4 to the gate of the transistor Tr7 to increase the gate voltage Vg2 of the transistor Tr2, and then outputs the voltage Vdd as the output voltage Vout.
The transistors Tr8 and Tr9 are configured of thin film transistors (TFTs) having channels of the same conduction type, for example, n-channel MOS type TFTs. The transistor Tr8 makes or breaks electrical connection between the high-voltage line LH and one terminal (a terminal E) not connected to the low-voltage line LL of the capacity element C4 in response to, for example, a potential difference Vgs8 between a voltage applied to an input terminal AZ1 and a voltage of the terminal E (or a potential difference corresponding thereto). A gate of the transistor Tr8 is electrically connected to the input terminal AZ1, and one terminal of a source and a drain of the transistor Tr8 is electrically connected to the high-voltage line LH, and the other terminal not connected to the high-voltage line LH of the transistor Tr8 is electrically connected to the terminal E of the capacity element C4. The transistor Tr9 makes or breaks electrical connection between the source (the terminal E) of the transistor Tr8 and the gate of the transistor Tr7 in response to, for example, a potential difference Vgs9 between a voltage applied to an input terminal AZ2 and a voltage Vs8 of the source of the transistor Tr8 (the voltage of the terminal E) (or a potential difference corresponding thereto). A gate of the transistor Tr9 is electrically connected to the input terminal AZ2. One terminal of a source and a drain of the transistor Tr9 is electrically connected to the source (the terminal E) of the transistor Tr8, and the other terminal not connected to the terminal E of the transistor Tr9 is electrically connected to the gate of the transistor Tr7.
For example, a pulse signal as illustrated in a part (B) in FIG. 60 is applied to the input terminal AZ1. For example, as illustrated in a part (C) in FIG. 60, a pulse signal with a phase opposite to that of the pulse signal applied to the input terminal AZ1 is applied to the input terminal AZ2. Therefore, the voltage Vdd is allowed to be taken out as the output voltage Vout.
Moreover, in the fifth and sixth embodiments, for example, as illustrated in FIGS. 61, 62 and 63, a delay element 3 may be arranged between the input terminal IN and the gate of the transistor Tr3.
The delay element 3 inputs, to the gate of the transistor Tr3, a voltage with a waveform obtained by delaying a voltage waveform of a signal voltage applied to the input terminal IN. For example, the delay element 3 inputs, to the gate of the transistor Tr3, a voltage with a slower falling edge than that of the voltage waveform of the signal voltage applied to the input terminal IN. Note that the delay element 3 may allow not only the falling edge but also the rising edge of the voltage waveform to be slower than that of the voltage waveform of the signal voltage applied to the input terminal IN. However, in this case, the delay element 3 delays the voltage waveform of the signal voltage applied to the input terminal IN so that its falling edge is slower than its rising edge.
The delay element 3 has any of circuit configurations illustrated in FIGS. 64A to 64D. In FIG. 64A, the delay element 3 includes a capacity element C5. An end of the capacity element C5 is electrically connected to the gate of the transistor Tr3, and the other end of the capacity element C5 is electrically connected to the low-voltage line LL.
In FIG. 64B, the delay element 3 includes a transistor Tr10. The transistor Tr10 is configured of a transistor having channels of same conduction type as that of the transistor Tr1 or the like, for example, an n-channel MOS type TFT. A source of the transistor Tr10 is electrically connected to the gate of the transistor Tr3, and a drain of the transistor Tr10 is electrically connected to the input terminal IN. A gate of the transistor Tr10 is electrically connected to a high-voltage line LH3. The high-voltage line LH3 is electrically connected to a power supply (not illustrated) outputting a pulse signal allowing the transistor Tr10 to perform an ON/OFF operation.
In FIG. 64C, the delay element 3 includes the above-described transistor Tr10 and a transistor Tr11. The transistor Tr11 is configured of a transistor having channels of same conduction type as that of the transistor Tr1 or the like, for example, an n-channel MOS type TFT. A gate and a source of the transistor Tr11 are electrically connected to the gate of the transistor Tr3, and a drain of the transistor Tr11 is electrically connected to the input terminal IN.
In FIG. 64D, the delay element 3 includes the above-described transistor Tr10 and the above-described capacity element C5.
Operation and Effects
FIG. 65 illustrates an example of the operation of the inverter circuit according to any of the modifications. Note that FIG. 65 illustrates waveforms in the case where a circuit configuration illustrated in FIG. 64D is used as the delay element 3. The basic operations of the inverter circuits according to the modifications are the same as that illustrated in FIGS. 45 to 50. A different operation from that illustrated in FIGS. 45 to 50 is performed when the input voltage Vin is switched (reduced) from high (Vdd) to low (Vss) and when the input voltage Vin is switched (increased) from low (Vss) to high (Vdd).
When the input voltage Vin is switched (reduced) from high (Vdd) to low (Vss), the gate voltages of the transistors Tr3 and Tr4 are changed from the voltage Vdd to the voltage Vss. In the inverter circuits 1 and 2 according to the fifth and sixth embodiments, the voltage change causes a voltage change by ΔV1 in the source of the transistor Tr5 through the capacity element C2, and further, causes a voltage change by ΔV2 in the gate of the transistor Tr5 through the capacity elements C1 and C2. In this case, a coupling amount of ΔV2 is applied to the gate of the transistor Tr5, because the gate voltage Vg3 of the transistor Tr3 is reduced from the voltage Vdd to the voltage Vss, and as a result, the on-resistance of the transistor Tr3 is gradually increased to slow a voltage transient for charging the gate of the transistor Tr5 to the voltage Vss. In other words, the coupling amount of ΔV2 is applied to the gate of the transistor Tr5, because the transistor Tr3 is switched from on to off at a timing of applying coupling.
On the other hand, in the modifications, a signal voltage as illustrated in FIG. 66 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, an off point (a point of switching from on to off) of the transistor Tr3 is delayed, compared to the case where the input voltage Vin is applied as is to the gate of the transistor Tr3. In other words, the transistor Tr3 is still on at the timing of applying coupling through the capacity element C2 (refer to FIG. 67). Therefore, ultimately, the coupling amount (ΔV2) applied to the gate of the transistor Tr5 is allowed to be reduced to be smaller than that in related art, and a gate-source voltage Vgs5 of the transistor Tr5 is allowed to be increased. As a result, the speed of the inverter circuit is allowed to be increased.
In the modifications, even in the case where the input voltage Vin is switched (increased) from low (Vss) to high (Vdd), a signal voltage as illustrated in FIG. 66 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr3. Therefore, the off point of the transistor Tr3 is delayed, and the transistor Tr3 is turned on after the transistor Tr1 is turned on, and there is a possibility that a current (a through current) flows from the high-voltage line LH to the low-voltage line LL in a state where the output voltage Vout is switched. However, when an operation point at which the transistor Tr3 is turned on and the waveform of the signal voltage applied to the gate of the transistor Tr3 are considered, even though the signal voltage applied to the gate of the transistor Tr3 is delayed, the time of turning the transistor Tr3 on is hardly changed at the rising edge as illustrated in FIG. 67, and on the other hand, the time of turning the transistor Tr3 off is largely changed at the falling edge. Therefore, a period where the above-described through current flows is extremely short, and the power consumption of the inverter circuits according to the modifications is not much different from that of the inverter circuits 1 and 2.
In the fifth and sixth embodiments, coupling caused by a change in the input voltage Vin is applied to the source and the gate of the transistor Tr5 so that the gate-source voltage Vgs5 of the transistor Tr5 has a value equal to or higher than the threshold voltage Vth5 of the transistor Tr5 with use of a difference in voltage transient between the source and the gate of the transistor Tr5. At this time, the output terminal OUT outputs the voltage of the high-voltage line LH as the output voltage Vout, but the voltage transient of the output terminal OUT is highly dependent on the gate-source voltage Vgs2 of the transistor Tr2. In other words, in the case where the gate-source voltage Vgs2 of the transistor Tr2 is rapidly increased, the output voltage Vout rapidly rises, and in the case where the gate-source voltage Vgs2 of the transistor Tr2 is gradually increased, the output voltage Vout gradually rises.
Therefore, to increase the speed of the inverter circuit, it is necessary for the gate-source voltage Vgs2 of the transistor Tr2 to rapidly rise, as a method of doing so, for example, it is considered to increase the capacity of the capacity element C2. However, in the case where the capacity of the capacity element C2 is increased, an area occupied by the inverter circuit is increased. As a result, for example, in the case where the inverter circuit including the capacity element C2 with a larger capacity is used for a scanner or the like in an organic EL display, an area occupied by the inverter circuit in a peripheral part (a frame) of a display panel may be increased to interfere with a reduction in the area of the frame. Moreover, an increase in the capacity of the capacity element C2 causes a larger voltage change than ΔV1 in the source (the output terminal OUT) of the transistor Tr2, thereby causing a larger voltage change than ΔV2 in the gate of the transistor Tr2. As a result, even though the capacity of the capacity element C2 is increased, the gate-source voltage Vgs2 of the transistor Tr2 has a value not much different from ΔV1−ΔV2; therefore, an increase in the capacity of the capacity element C2 does not much contribute to an increase in the speed of the inverter circuit 1.
On the other hand, in the modifications, the signal voltage as illustrated in FIG. 66 obtained by delaying the signal voltage applied to the input terminal IN by the delay element 3 is applied to the gate of the transistor Tr1. Therefore, the speed of the inverter circuit is allowed to be increased without increasing the capacity of the capacity element C2.
Moreover, in the fifth and sixth embodiments and the modifications thereof, the transistors Tr1 to Tr11 are configured of the n-channel MOS type TFTs, but they may be configured of, for example, p-channel MOS type TFTs. However, in this case, the high-voltage line LH is replaced with the low-voltage line LL, and the high-voltage line LH is replaced with the low-voltage line LL. Moreover, a transient response when the transistors Tr1 to Tr11 is switched (increased) from low to high and a transient response when the transistors Tr1 to Tr11 is switched (reduced) from high to low are opposite to each other.
APPLICATION EXAMPLE
FIG. 68 illustrates an example of a whole configuration of a display 100 as an application example of the inverter circuits 1, 2 and 4 according to the above-described embodiments and the modifications thereof. The display 100 includes, for example, a display panel 110 (a display section) and a drive circuit 120 (a drive section).
Display Panel 110
The display panel 110 includes a display region 110A in which three kinds of organic EL elements 111R, 111G and 111B emitting light of different colors are two-dimensionally arranged. The display region 110A is a region where a picture is displayed with use of light emitted from the organic EL elements 111R, 111G and 111B. The organic EL element 111R is an organic EL element emitting red light, the organic EL element 111G is an organic EL element emitting green light, and the organic EL element 111B is an organic EL element emitting blue light. Note that the organic EL elements 111R, 111G and 111B are collectively called organic EL elements 111 as necessary.
Display Region 110A
FIG. 69 illustrates an example of a circuit configuration in the display region 10A with an example of a writing line drive circuit 124 which will be described later. In the display region 110A, a plurality of pixel circuits 112 are two-dimensionally arranged so as to be paired with the organic EL elements 111, respectively. In the application example, a pair of the organic EL element 111 and the pixel circuit 112 configures one pixel 113. More specifically, as illustrated in FIG. 68, a pair of the organic EL element 111R and the pixel circuit 112 configures one red pixel 113R, a pair of the organic EL element 111G and the pixel circuit 112 configures one green pixel 113G, and a pair of the organic EL element 111B and the pixel circuit 112 configures one blue pixel 113B. Moreover, three adjacent pixels 113R, 113G and 113B configure one display pixel 114.
Each pixel circuit 112 includes, for example, a driving transistor Tr100 controlling a current flowing through the organic EL element 111, a writing transistor Tr200 writing a voltage of a signal line DTL to the driving transistor Tr100, and a retention capacitor Cs. In other words, each pixel circuit 112 has a 2Tr1C circuit configuration. The driving transistor Tr100 and the writing transistor Tr200 each are configured of, for example, an n-channel MOS type thin film transistor (TFT). The driving transistor Tr100 or the writing transistor Tr200 may be configured of, for example, a p-channel MOS type TFT.
In the display region 110A, a plurality of writing lines WSL (scanning lines) are arranged in rows, and a plurality of signal lines DTL are arranged in columns. In the display region 110A, a plurality of power supply lines PSL (members to which a power supply voltage is supplied) are arranged in rows along the writing lines WSL. One organic EL element 111 is arranged around an intersection of each of the signal lines DTL and each of the writing lines WSL. Each of the signal lines DTL is connected to an output end (not illustrated) of a signal line drive circuit 123 which will be described later and one of a drain electrode and a source electrode (both not illustrated) of the writing transistor Tr200. Each of the writing lines WSL is connected to an output end (not illustrated) of a writing line drive circuit 124 which will be described later and a gate electrode (not illustrated) of the writing transistor Tr200. Each of the power supply lines PSL is connected to an output end (not illustrated) of a power supply line drive circuit 125 which will be described later and one of a drain electrode and a source electrode (both not illustrated) of the driving transistor Tr100. The other which is not connected to the signal line DTL of the drain electrode and the source electrode (both not illustrated) of the writing transistor Tr100 is connected to a gate electrode (not illustrated) of the driving transistor Tr100 and an end of the retention capacitor Cs. The other which is not connected to the power supply line PSL of the drain electrode and the source electrode (both not illustrated) of the driving transistor Tr100 and the other end of retention capacitor Cs are connected to an anode electrode (not illustrated) of the organic EL element 111. A cathode electrode (not illustrated) of the organic EL element 111 is connected to, for example, a ground line GND.
Drive Circuit 120
Next, each circuit in the drive circuit 120 will be described referring to FIGS. 68 and 69. The drive circuit 120 includes a timing generation circuit 121, a picture signal processing circuit 122, the signal line drive circuit 123, the writing line drive circuit 124 and the power supply line drive circuit 125.
The timing generation circuit 121 controls the picture signal processing circuit 122, the signal line drive circuit 123, the writing line drive circuit 124 and the power supply line drive circuit 125 to operate in conjunction with one another. The timing generation circuit 21 outputs a control signal 121A to each of the above-described circuits in response to (in synchronization with), for example, a synchronization signal 120B entered externally.
The picture signal processing circuit 122 performs predetermined correction on the picture signal 120A entered externally, and outputs a corrected picture signal 122A to the signal line drive circuit 123. Examples of the predetermined correction include gamma correction and overdrive correction.
The signal line drive circuit 123 applies the picture signal 122A (a signal voltage Vsig) entered from the picture signal processing circuit 122 to each of the signal lines DTL in response to (in synchronization with) the input of the control signal 121A so as to write the picture signal 122A to selected pixels 113. Note that writing means applying a predetermined voltage to a gate of the driving transistor Tr100.
The signal line drive circuit 123 is configured by including, for example, a shift register (not illustrated), and includes buffer circuits (not illustrated) corresponding to columns of pixels 113, respectively. The signal line drive circuit 123 is allowed to output two kinds of voltages (Vofs and Vsig) to each of the signal lines DTL in response to (in synchronization with) the input of the control signal 121A. More specifically, the signal line drive circuit 123 sequentially supplies two kinds of voltages (Vofs and Vsig) to pixels 113 selected by the wiring line drive circuit 124 through the signal lines DTL connected to the pixels 113.
In this case, an offset voltage Vofs has a constant voltage value irrespective of the value of a signal voltage Vsig. Moreover, the signal voltage Vsig has a voltage value corresponding to the picture signal 122A. The minimum voltage of the signal voltage Vsig is lower than the offset voltage Vofs, and the maximum voltage of the signal voltage Vsig is higher than offset voltage Vofs.
The writing line drive circuit 124 is configured by including, for example, a shift register (not illustrated), and includes buffer circuits 5 corresponding to rows of pixels 113, respectively. The buffer circuits 5 each are configured of a plurality of the above-described inverter circuits 1, 2 or 4, and outputs a pulse signal with substantially the same phase as that of a pulse signal applied to an input end thereof to an output end thereof. The writing line drive circuit 124 is allowed to output two kinds of voltages (Vdd and Vss) to each of the wiring lines WSL in response to (in synchronization with) the input of the control signal 121A. More specifically, the writing line drive circuit 124 supplies two kinds of voltages (Vdd and Vss) to pixels 113 to be driven through the writing lines WSL connected to the pixels 113 so as to control the writing transistor Tr200.
In this case, the voltage Vdd has a value equal to or higher than an on-voltage of the writing transistor Tr200. The voltage Vdd is a voltage value generated from the writing line drive circuit 124 during light extinction which will be described later or during threshold correction. The voltage Vss has a lower value than the on-voltage of the writing transistor Tr200 and the voltage Vdd.
The power supply line drive circuit 125 is configured by including, for example, a shift register (not illustrated), and includes buffer circuits (not illustrated) corresponding to the rows of the pixels 113, respectively. The power supply line drive circuit 125 is allowed to output two kinds of voltages (VccH and VccL) in response to (in synchronization with) the input of the control signal 121A. More specifically, the power supply line drive circuit 125 supplies two kinds of voltages (VccH and VccL) to pixels 113 to be driven through the power supply lines PSL connected to the pixels 113 to control light emission and extinction of the organic EL elements 111.
In this case, the voltage VccL has a lower voltage value than a voltage (Vel+Vca) which is the sum of a threshold voltage Vel of the organic EL element 111 and a voltage Vca of a cathode of the organic EL element 111. Moreover, the voltage VccH has a voltage value equal to or higher than the voltage (Vel+Vca).
Next, an example of the operation (operation from light extinction to light emission) of the display 100 will be described below. In the application example, to maintain light emission luminance of the organic EL elements 111 constant even if the threshold voltage Vth or the mobility μ of the driving transistor Tr100 temporally changes, a correction operation on a change in the threshold voltage Vth or the mobility μ is incorporated.
FIG. 70 illustrates an example of voltage waveforms applied to the pixel circuit 112 and an example of changes in the gate voltage Vg and the source voltage Vs of the driving transistor Tr100. A part (A) in FIG. 70 illustrates a state where the signal voltage Vsig and the offset voltage Vofs are applied to the signal line DTL. A part (B) in FIG. 70 illustrates a state where the voltage Vdd turning the writing transistor Tr200 on and the voltage Vss turning the writing transistor Tr200 off are applied to the writing line WSL. A part (C) in FIG. 70 illustrates a state where the voltage VccH and the voltage VccL are applied to the power supply line PSL. Moreover, parts (D) and (E) in FIG. 70 illustrate states where the gate voltage Vg and the source voltage Vs of the driving transistor Tr100 are momentarily changed with the application of voltages to the power supply line PSL, the signal line DTL and the writing line WSL.
Vth Correction Preparation Period
First, preparation for Vth correction is made. More specifically, when the voltage of the writing line WSL is at the voltage Voff and the voltage of the power supply line DSL is at the voltage VccH (that is, when the organic EL element 111 emits light), the power source line drive circuit 125 reduces the voltage of the power source line DSL from the voltage VccH to the voltage VccL (T1). Then, the source voltage Vs is changed to the voltage VccL to turn the organic EL element 111 off. After that, when the voltage of the signal line DTL is at the voltage Vofs, the writing line drive circuit 124 increases the voltage of the writing line WSL from the voltage Voff to the voltage Von to change the voltage of the gate of the driving transistor Tr100 to the voltage Vofs.
First Vth Correction Period
Next, the Vth correction is performed. More specifically, while the writing transistor Tr200 is on and the voltage of the signal line DTL is at the voltage Vofs, the power source line drive circuit 125 increases the voltage of the power source line DSL from the voltage VccL to the voltage VccH (T2). Then, a current Ids flows between the drain and the source of the driving transistor Tr100, and the source voltage Vs is increased. After that, before the signal line drive circuit 123 switches the voltage of the signal line DTL from the voltage Vofs to the voltage Vsig, the writing line drive circuit 124 reduces the voltage of the writing line WSL from the voltage Von to the voltage Voff (T3). As a result, the gate of the driving transistor Tr100 is turned to a floating state, and the Vth correction stops.
First Vth Correction Stop Period
During a period where the Vth correction stops, sampling of the voltage of the signal line DTL is performed in a row (a pixel) different from a row (a pixel) on which the Vth correction has already been performed. In addition, at this time, the source voltage Vs is lower than a voltage Vofs−Vth in the row (the pixel) on which the Vth correction has already been performed; therefore, during a Vth correction stop period, the current Ids flows between the drain and the source of the driving transistor Tr100 in the row (the pixel) on which the Vth correction has already been performed, and the source voltage Vs is increased, and the gate voltage Vg is also increased by coupling through the retention capacitor Cs.
Second Vth Correction Period
Next, the Vth correction is performed again. More specifically, when the voltage of the signal line DTL is at the voltage Vofs, thereby allowing the Vth correction, the writing line drive circuit 124 increases the voltage of the writing line WSL from the voltage Voff to the voltage Von, and the gate of the driving transistor Tr100 is changed to the voltage Vofs (T4). At this time, in the case where the source voltage Vs is lower than a voltage Vofs−Vth (in the case where the Vth correction is not yet completed), the current Ids flows between the drain and the source of the driving transistor Tr100 until cutting the driving transistor Tr100 off (until the gate-source voltage Vgs is changed to the voltage Vth). After that, before the signal line drive circuit 123 switches the voltage of the signal line DTL from the voltage Vofs to the voltage Vsig, the writing line drive circuit 24 reduces the voltage of the writing line WSL from the voltage Von to the voltage Voff (T5). Therefore, the gate of the driving transistor Tr100 turns into a floating state, so the gate-source voltage Vgs is allowed to be maintained constant irrespective of the magnitude of the voltage of the signal line DTL.
Note that in the Vth correction period, in the case where the retention capacitor Cs is charged to the voltage Vth and the gate-source voltage Vgs is changed to the voltage Vth, the drive circuit 120 completes the Vth correction. However, in the case where the gate-source voltage Vgs does not reach the voltage Vth, the drive circuit 120 repeatedly executes and stops the Vth correction until the gate-source voltage Vgs reaches the voltage Vth.
Writing·μ Correction Period
After the Vth correction stop period is completed, writing and μ correction are performed. More specifically, while the voltage of the signal line DTL is at the voltage Vsig, the writing line drive circuit 124 increases the voltage of the writing line WSL from the voltage Voff to the voltage Von (T6), and the gate of the driving transistor Tr100 is connected to the signal line DTL. Therefore, the gate voltage Vg of the driving transistor Tr100 is changed to the voltage Vsig of the signal line DTL. At this time, an anode voltage of the organic EL element 111 at this stage is still smaller than the threshold voltage Vel of the organic EL element 111, so the organic EL element 111 is cut off. Therefore, the current Ids flows into an element capacitance (not illustrated) of the organic EL element 111, and the element capacitance is charged, so the source voltage Vs is increased only by ΔVy, and then the gate-source voltage Vgs reaches a voltage Vsig+Vth−ΔVy. Thus, μ correction is performed simultaneously with writing. In this case, the larger mobility μ of the driving transistor Tr100 is, the more the voltage ΔVy is increased, so when the gate-source voltage Vgs is reduced only by ΔVy before light emission, variations in mobility μ from one pixel circuit 113 to another are preventable.
Light Emission Period
Finally, the writing line drive circuit 124 reduces the voltage of the writing line WSL from the voltage Von to the voltage Voff (T7). Then, the gate of the driving transistor Tr100 is turned into a floating state, and the current Ids flows between the drain and the source of the driving transistor Tr100 to increase the source voltage Vs. As a result, a voltage equal to or higher than the threshold voltage Vel is applied to the organic EL element 111, and the organic EL element 111 emits light with desired luminance.
In the display 100 in the application example, as described above, in each pixel 113, on/off control of the pixel circuit 112 is performed, and a drive current is thereby injected into the organic EL element 111 of each pixel 113 to cause emission of light by the recombination of holes and electrons, and then the light is extracted to outside. As a result, an image is displayed on the display region 110A of the display panel 110.
In the application example, for example, the buffer circuits 5 in the writing line drive circuit 124 each are configured of a plurality of the above-described inverter circuits 1, 2 or 4. Therefore, a through current hardly flows through the buffer circuits 5; therefore, the power consumption of the buffer circuits 5 is allowed to be reduced. Moreover, variations in the output voltages of the buffer circuits 5 is small; therefore, variations in threshold correction or mobility correction of the driving transistor Tr100 from one pixel circuit 112 to another are allowed to be reduced, and variations in luminance from one pixel 113 to another are allowed to be reduced.
Although the present disclosure is described referring to the embodiments, the modifications and the application example, the disclosure is not limited thereto, and may be variously modified.
For example, in the above-described embodiments and the modifications thereof, only one common voltage line on a high voltage side and only one common voltage line on a low voltage side are arranged; however, for example, a voltage line connected to one or more of transistors on the high voltage side and a voltage line connected to other transistors on the high voltage side may be separately arranged. Likewise, a voltage line connected to one or more of a plurality of transistors on the low voltage side and a voltage line connected to the other transistors on the low voltage side may be arranged separately.
Moreover, for example, in the above-described application example, any of the inverter circuits 1, 2 and 4 according to the above-described embodiments is used in an output stage of the writing line drive circuit 124; however, instead of the output stage of the writing line drive circuit 124, the inverter circuit 1, 2 or 4 may be used in an output stage of the power supply line drive circuit 125, or may be used in both of the output stage of the writing line drive circuit 124 and the output stage of the power supply line drive circuit 125.
The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-079295 filed in the Japan Patent Office on Mar. 30, 2010, Japanese Priority Patent Application JP 2010-083268 filed in the Japan Patent Office on Mar. 31, 2010, and Japanese Priority Patent Application JP 2010-079461 filed in the Japan Patent Office on Mar. 30, 2010, the entire content of which is hereby incorporated by references.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

## Claims

1. An inverter circuit comprising:
an electrical connection point directly electrically connected to a terminal of a first capacity element and to a terminal of a second capacity element, another terminal of the second capacity element being directly electrically connected to a gate of a first transistor;
a first voltage line directly electrically connected to a drain/source of the first transistor and to a drain/source of a third transistor, a source/drain of the third transistor being directly electrically connected to another terminal of the first capacity element.

2. The inverter circuit according to claim 1, wherein said first and third transistors are of the same conduction type.

3. The inverter circuit according to claim 1, further comprising:
an input terminal directly electrically connected to a gate of the third transistor and to a terminal of a third capacity element, another terminal of the third capacity element being directly electrically connected to the first voltage line.

4. The inverter circuit according to claim 1, further comprising:
an input terminal directly electrically connected to a drain/source of a fourth transistor, a source/drain of the fourth transistor being directly electrically connected to a gate of the third transistor.

5. The inverter circuit according to claim 4, wherein a gate of the fourth transistor is directly electrically connected to a third voltage line.

6. The inverter circuit according to claim 4, further comprising:
a terminal of a third capacity element directly electrically connected to said source/drain of the fourth transistor, said first voltage line being directly electrically connected to another terminal of the third capacity element.

7. The inverter circuit according to claim 1, further comprising:
a gate of the third transistor directly electrically connected to a source/drain of a fourth transistor and to a source/drain of a fifth transistor, said source/drain of the fifth transistor being directly electrically connected to a gate of a fifth transistor.

8. The inverter circuit according to claim 7, wherein an input terminal is directly electrically connected to a drain/source of the fourth transistor and to a drain/source of the fifth transistor, said drain/source of the fourth transistor being directly electrically connected to a gate of a fourth transistor.

9. The inverter circuit according to claim 1, wherein an input terminal is directly electrically connected to said gate of the first transistor.

10. The inverter circuit according to claim 9, wherein a gate of the third transistor is directly electrically connected to said input terminal.

11. The inverter circuit according to claim 9, wherein a gate of the third transistor is directly electrically connected to another input terminal.

12. The inverter circuit according to claim 9, further comprising:
a source/drain of a sixth transistor directly electrically connected to said source/drain of the third transistor, said input terminal being directly electrically connected to a gate of the sixth transistor,
wherein a drain/source of the sixth transistor is directly electrically connected to said first voltage line.

13. The inverter circuit according to claim 9, wherein said input terminal is directly electrically connected to an input of a delay element, an output of the delay element being directly electrically connected to a gate of the third transistor.

14. The inverter circuit according to claim 13, further comprising:
a source/drain of a sixth transistor directly electrically connected to said source/drain of the third transistor, said input terminal being directly electrically connected to a gate of the sixth transistor,
wherein a drain/source of the sixth transistor is directly electrically connected to said first voltage line.

15. The inverter circuit according to claim 1, wherein said electrical connection point is directly electrically connected to a source/drain of the first transistor and to a drain/source of a second transistor, a gate of the second transistor being directly electrically connected to said source/drain of the third transistor.

16. The inverter circuit according to claim 15, wherein a source/drain of the second transistor is directly electrically connected to a second voltage line.

17. The inverter circuit according to claim 16, wherein a voltage of the second voltage line is higher than a voltage of the first voltage line.

18. The inverter circuit according to claim 1, wherein said source/drain of the first transistor is directly electrically connected to a drain/source of a second transistor, said electrical connection point being directly electrically connected to a source/drain of a fourth transistor and to a drain/source of a fifth transistor.

19. The inverter circuit according to claim 18, wherein a source/drain of the second transistor is directly electrically connected to a third voltage line.

20. The inverter circuit according to claim 18, wherein a gate of the second transistor is directly electrically connected to said electrical connection point.

21. The inverter circuit according to claim 18, wherein a drain/source of the fourth transistor is directly electrically connected to said first voltage line, a gate of the fourth transistor being directly electrically connected to said gate of the first transistor.

22. The inverter circuit according to claim 18, wherein a source/drain of the fifth transistor is directly electrically connected to a second voltage line, a gate of the fifth transistor being directly electrically connected to said source/drain of the third transistor.

23. The inverter circuit according to claim 22, wherein a gate of the second transistor is directly electrically connected to a source/drain of a sixth transistor and to a drain/source of a seventh transistor.

24. The inverter circuit according to claim 23, wherein a source/drain of the seventh transistor is directly electrically connected to said electrical connection point, a gate of the seventh transistor being directly electrically connected to said source/drain of the third transistor.

25. The inverter circuit according to claim 23, wherein a drain/source of the sixth transistor is directly electrically connected to said first voltage line, a gate of the sixth transistor being directly electrically connected to said gate of the first transistor.

26. The inverter circuit according to claim 23, wherein said second voltage is line directly electrically connected to a source/drain of the second transistor and to a source/drain of the seventh transistor, a gate of the seventh transistor being directly electrically connected to said electrical connection point.