# Patent

## Title
Data-handling system with operatively interconnected processors

## Abstract

A time division multiplex switching network comprises a data word circulating store and a random address circulating store. These two circulating stores are synchronous and have data word registers and random address registers respectively associated two by two. The bytes in the time-slots of an incoming supermultiplex highway are written in the data word registers and addresses depending on the outgoing time slots which are to be connected are written in the random address registers. These addresses are incremented at each step of the random address circulating store. When the incremented address reaches a predetermined value, a data word is read in the data word circulating store.

## Background
Field of the Invention

The present invention relates to improvements made to time-division multiplex switching networks and, more particularly, to switching networks of this type in which the buffer store is an associative type store addressable by its contents and constructed using coupled charge devices (CCD).

Description of the Prior Art

U.S. Pat. No. 3,971,892 includes a description of a time-division multiplex switching network comprising an input stage having plurality of incoming multiplex highways and a supermultiplexer converting the said incoming multiplex highways into one incoming supermultiplex highway; an output stage having outgoing supermultiplex highway and a superdemultiplexer converting the said outgoing supermultiplex highway into a plurality of outgoing multiplex highways; a buffer store having a write in input connected to the incoming supermultiplex highway and a read out output connected to the outgoing supermultiplex highway; and means for sequentially writing, in data storage locations of the buffer store, the words present in the time-slots of the incoming supermultiplex highway. The said buffer store is a circulating store addressable by its contents. The buffer store includes random address store locations associated with the said data store locations and a fixed address store giving the addresses of the component time-slots of the outgoing supermultiplex highway. Plural comparator means, each associated with a data store location, and a random address store location compare the random addresses written in the address store locations with the fixed addresses of the component time-slots of the outgoing supermultiplex highway to control read out of the word associated with a given random address when there is identity between the said given random address and a fixed address.

Assuming that there are N multiplex highways in a supermultiplex highway and 32 time-slots in each multiplex highway, the address (j-i) modulo 32N is written in the random address store location associated with the data store location containing the word in time-slot of address i in the incoming supermultiplex highway and the circulating store advances stepwise. When random address (j-i) is equal to fixed address (j-i) assigned to a given step of the circulating store, the word is read out and transferred into time-slot of address j in the outgoing supermultiplex highway.

The object of the invention is to provide a time-division multiplex switching network in which the fixed address memories included in the stages of the circulating store and the comparators associated with these fixed address memories are done eliminated.

In the prior art, the words and their associated random addresses progress unchanged in the circulating store from the input stage thereof up to the stage having a fixed address equal to the random address. In the invention, the associative buffer store is arranged as a counter and the random address which is written in the circulating store at the input stage thereof is incremented to each circulation step; the reading of the data word is ordered in the circulating store stage when the counter overflows.

The invention will now be described in detail in relation to the accompanying drawings in which:

FIG. 1 is a circuit diagram of the time-division multiplex switching network described in the aforementioned patent;

FIG. 2 is a circuit diagram of the time-division multiplex switching network in accordance with the invention;

FIG. 3 is a circuit diagram of the principle of an associative buffer store with count down;

FIGS. 4, 5 and 6 are circuit diagrams of that part of the associative buffer store; and which serves as a control store;

FIGS. 7, 8 and 9 are tables showing how the increment or decrement by one unit of the address word is performed at the rate of one bit weight per one memory step.

Referring first to FIG. 1 which relates to the prior art, each store location of buffer store 20 comprises a data octet area 200.sub.0 to 200.sub.1023 respectively, a random address area 201.sub.0 to 201.sub.1023 respectively, a comparator 202.sub.0 to 202.sub.1023 respectively and a fixed address area 203.sub.0 to 203.sub.1023 respectively. Address areas 203.sub.0 to 203.sub.1023 form a read only memory, a wired memory for example. In other words, these areas unalterably contain the binary numbers 0 to 1023.

Inputs of AND gates 204.sub.0 to 204.sub.1023 are respectively connected to octet areas 200.sub.0 to 200.sub.1023 and comparators 202.sub.0 to 202.sub.1023 ; outputs of the AND gates are connected to OR-gate 206, connected to outgoing supermultiplex highway 41. The comparators each receive a fixed address coming from the read only memory.

Buffer store 20 is the circulating type. The data octet areas are eight-bit ones and the random address areas have ten bits. Consequently, there are eight unit memories 200.sub.0,0 to 200.sub.7,0 in memory area 200.sub.0 and the same is so in the other data octet memory areas. There are ten unit memories 201.sub.0,0 to 201.sub.9,0 in the random address memory area 201.sub.0 and the same is so in the other random address memory areas.

AND-gates 207.sub.0,0 to 207.sub.7,0 are connected to the outputs of unit memories 200.sub.0,0 and to 200.sub.7,0 to the inputs of unit memories 200.sub.0,1 to 200.sub.7,1 The buffer store part concerning the data octets is not looped; it receives at each frame the eight-bit words present in the time-slots of the incoming supermultiplex highway.

AND-gates 208.sub.0,0 to 208.sub.9,0 connect the outputs of unit memories 201.sub.0,0 to 201.sub.9,0 to the inputs of unit memories 201.sub.0,1 to 201.sub.9,1. Similarly AND-gates 208.sub.0,1023 to 208.sub.9,1023 connect the outputs of unit memories 201.sub.0,1023 to 201.sub.9,1023 to the inputs of unit memories 201.sub.0,0 to 201.sub.9,0.

It can thus be seen that a data octet and a random address may be written respectively in input stages 200.sub.0 and 201.sub.0 and that the octet together with the random address cyclically move around the circulating store, the octet path being non-looped and the address path being looped.

The manner in which the associative circulating store works is as follows:

Assume that time-slot of address 0 in the incoming supermultiplex highway is to be connected to time-slot of address j in the outgoing supermultiplex highway. The incoming octet is written in register 200.sub.0 during time interval t.sub.0 and address j is written in register 201.sub.0 during the same time interval t.sub.0. Due to the circulation, the octet, together with the address of the outgoing time-slot, progress stepwise, advancing one step per time interval. At any moment, the random address may be compared with the fixed address written in the stage of the read only memory 203 which is associated with the stage of the buffer store in which octet and random address are actually lying. In particular, at time interval t.sub.j, the octet and the random address are respectively in registers 200.sub.j and 201.sub.j which are associated with stage 203.sub.j of read only memory 203, the comparison of the random and fixed addresses is positive and the octet of address 0 is read out and transferred into time-slot of address j in the outgoing supermultiplex highway.

Now assume that time-slot of address i in the incoming supermultiplex highway is to be conncted to time-slot of address j in the outgoing supermultiplex highway. The incoming octet is then written in register 200.sub.0 at time interval t.sub.i and the random address (which now is merely j) is written in register 201.sub.0 at time interval t.sub.i. At time interval t.sub.O the octet and the random address are respectively in registers 200.sub.(1024-i) and 201.sub.(1024-i). At time interval t.sub.j, the octet and the random address are respectively in registers 200.sub.(1024 -i+j) and 201.sub.(1024-i+j). Consequently, j is not written at time interval t.sub.i in register 201.sub.0 ; but instead (1024-i+j) modulo 1024, that is (j-i), is written in register 201.sub.0. The result of this is that if i=0, j is written at time interval t.sub.0 in register 201.sub.0.

FIG. 2 is an illustration of the associative circulating buffer store in accordance with the invention. It comprises 8.times.1024=8192 information bit-memories and 10.times.1024=10240 random address bit-memories. The information bit-memories are designated by: ##STR1## The information bit memories are arranged in a circulating store in which a eight-bit data word can occupy 1024 successive word locations.

The random address bit-memories are designated by: ##STR2## The random address bit memories are arranged in a circulating store in which a ten-bit address word can occupy 1024 successive word locations.

The address bit-memories are also located in counters.

As already said, while the address memory is looped from stage 601.sub.1023 (601.sub.0,1023 to 601.sub.9,1023) to stage 601.sub.0 (601.sub.0,0 to 601.sub.9,0), the data memory is not looped. Gates ##STR3## connect the stages of the data part of the buffer store. Gates ##STR4## connect the stages of the address part of the buffer store. Finally gates

connect the stages of the data part of the buffer store to an OR-gate connected to the outgoing supermultiplex highway 41.

It can be seen that FIG. 2 resembles FIG. 1 to a certain extent. However, the random addresses written in the address locations when they pass from one given word location to the next. In contrast, in the FIG. 1 system the random addresses are circulated without modification and are, at each successive location, compared with fixed addresses. This incrementation is performed by means of adders 602.sub.0 to 602.sub.1023 and unity sources 603.sub.0 to 603.sub.1023 Counters 601.sub.0 to 601.sub.1023 overflow when they reach 1024. Assume that incoming time-slot of address i is connected to outgoing time-slot of address j, and that the incoming time-slot contains a word which is written at time interval t.sub.i in input data register 600.sub.0 while address (1024-j+i) is written in input address register 601.sub.0. When this address arrives in register 601.sub.(j-i) at time interval t.sub.j, i.e. after (j-i) time intervals, the address becomes

Counter 601.sub.(j-i) overflows and operates gate 604.sub.(j-i) via wire 609.sub.(j-i) and the octet in circulation leaves at time interval t.sub.j Reference is now made to FIG. 3, wherein each stage of the address part of the buffer store assigned to the octet reading control comprises a plurality of cells C.sub.k,l with 0.ltoreq.k.ltoreq.9 and 0.ltoreq.l.ltoreq.1023. In FIG. 3, the horizontal arrows in cells C.sub.k,l represent the progression of the address words, whereas the diagonal arrows represent the progression of the carry over values. On the line of index k=0, the previous carry over is replaced by a binary digit 1.

FIG. 4 is an illustration of how a cell C.sub.k,l is set up in a coupled charge device.

Unit memory 70 temporarily stores the address bit A.sub.k,l resulting from the addition which takes place in cell C.sub.k,l. Unit memory 71 temporarily stores carry over bit R.sub.k,l resulting from the carry over of the addition which takes place in cell C.sub.k,l. Control electrode 72 controls coupling of the charge of B.sub.k,l to A.sub.k,l depending on the potential of electrode 72. Equipotential link 73 connects cell 72 to change sensor 73. CCD (charge coupled device) adder 75 receives the charges due to the previous carry over R.sub.(k-1),l and the previous address bit A.sub.k,(l-1). Potential barrier 76 enables the excess of charge of cell B.sub.k,l R.sub.k,l. Finally, electrode 77 allows to be coupled to cell the contents of cell B.sub.k,l to be cleared after an addition operation and PN junction 78 makes it possible to absorb the previous charge if necessary.

FIG. 5 is a view of an assembly of 9 cells such as that described in FIG. 4.

Cell C.sub.k,l operates in the following manner.

It can be seen that the address part of the circulating buffer store shown in FIG. 3 has 1024 output wires 610.sub.0 to 610.sub.1023 respectively connected to cells C.sub.9,0 to C.sub.9,1023. Each of wires 610.sub.0 to 610.sub.1023 is respectively connected to a wire, 609.sub.0 to 609.sub.1023 by means of an inverter circuit, discussed infra. Wire 609 .sub.(j-i) controls gate 604.sub.(j-i) which allows the reading at time interval t.sub.j of the data word entered at time interval t.sub.i. On each clock pulse defining a time interval, the charges representative of the logic levels derived from cells R.sub.(k-1),l and A.sub.k,(l-1) are transferred to cell B.sub.k,l where they are added. Potential barrier 76 allows any surplus charge to pass to cell R.sub.k,l. (Surplus charge is coupled to cell R.sub.k, the contents of cells only if A.sub.k(l-1) and R(k-1),l are both binary one values. The contents of cell R.sub.k,l consequently represents the carry over of the addition. Next solely the absence of charges in cell R.sub.k,l makes for the transfer of the contents of cell B.sub.k,l into cell A.sub.k,l ; it thus follows that the result of the addition is to be found in A.sub.k,l.

A final clock pulse on the electrode 77, FIG. 4, enables the binary signal of cell B.sub.k,l to be set back to zero.

Tables I to IV herebelow summarize the possible cases. ______________________________________ The initial situation is A.sub.k,(l-1) = 0; R.sub.(k-1),l = 0 A.sub.k,(l-1) R.sub.(k-1),l B.sub.k,l R.sub.k,l A.sub.k,l ______________________________________ 1st time 0         0        0      0     0 2nd time 0         0        0      0     0 3rd time 0         0        0      0     0 4th time 0         0        0      0     0 ______________________________________ ______________________________________ The initial situation is A.sub.k,(l-1) = 0; R.sub.(k-1),l = 0 A.sub.k,(l-1) R.sub.(k-1),l B.sub.k,l R.sub.k,l A.sub.k,l ______________________________________ 1st time 0         0        1      0     0 2nd time 0         0        1      0     0 3rd time 0         0        0      0     1 4th time 0         0        0      0     1 ______________________________________ ______________________________________ The initial situation is A.sub.k,(l-1) = 1; R.sub.(k-1),l = 0 A.sub.k,(l-1) R.sub.(k-1),l B.sub.k,l R.sub.k,l A.sub.k,l ______________________________________ 1st time 0         0        1      0     0 2nd time 0         0        1      0     0 3rd time 0         0        0      0     0 4th time 0         0        0      0     0 ______________________________________ ______________________________________ The initial situation is A.sub.k,(l-1) = 1; R.sub.(k-1),l = 1 A.sub.k,(l-1) R.sub.(k-1),l B.sub.k,l R.sub.k,l A.sub.k,l ______________________________________ 1st time 0         0        1 + 1  0     0 2nd time 0         0        1      1     0 3rd time 0         0        1      1     0 4th time 0         0        0      1     0 ______________________________________

The reading of the data octet from one of the octet registers is controlled by the carry over in cell C.sub.9,l. With this in mind, the potential derived in charge sensor 73 in FIG. 4 must be considered. However, this potential allows the octet to be read only when the value of the charge packet representative of the carry over is zero; the sign should thus be inverted. Sensor 73 is therefore connected to an inverter-regenerator, a device quite familiar to those of ordinary skill in the charge coupled device field. Such an inverter is shown in FIG. 6, wherein isolating diffused part 80 localizes the charges in the cell. PN junction 81 is biased to generate charges. 82 is an electrode connected to charge sensor 73 of cell C.sub.9,l. Clock electrode 83 controls the progression of the charges. Charge sensor 84 is connected to the output gate 604.sub.l of the octet register 600.sub.l. Finally non-biased PN junction 85 absorbs the charges.

Thus reading of the octet is controlled by control charge sensor 84.

The manner in which the address part of the buffer store works is described from the following example.

Assume that incoming time-slot of address i=3 in the incoming supermultiplex highway is to be connected to outgoing time-slot of address j=960 in the outgoing supermultiplex highway. At time interval t.sub.3, the octet of address i=3 is written in register 600.sub.0 and, at time interval t.sub.960, i.e. 957 clock pulses later, it is to be read from register 600.sub.957. An address or control word is written at time interval t.sub.3 in address register 601.sub.0. The address word reaches the value 1024 after it has circulated around to register 600.sub.957 ; this address word is normally

The foregoing reasoning assumes that, at each stage of the circulating store, a complete addition (including the propagation of the carry-overs) of unitary and the address word in the address register of this stage takes place.

In this system of complete addition at each stage, the operation of the address part of the buffer store can be summarized by the following table: number of address time-slot    register  address word ______________________________________ t.sub.0      601.sub.1021 64 = 0 0 0 1 0 0 0 0 0 0 t.sub.1      601.sub.1022 65 = 0 0 0 1 0 0 0 0 0 1 t.sub.2      601.sub.1023 66 = 0 0 0 1 0 0 0 0 1 0 ##STR5## t.sub.951    601.sub.948 1015 = 1 1 1 1 1 1 0 1 1 1 t.sub.959    601.sub.956 1023 = 1 1 1 1 1 1 1 1 1 1 ##STR6## t.sub.1023   601.sub.1020 63 = 0 0 0 0 1 1 1 1 1 1 ______________________________________

In keeping with another characteristic of the invention, the addition of unity to the address when the address passes from one stage of the buffer store to the following stage is distributed over a number of stages equal to the number of bits in the number where the counters overflow; thus the addition is not performed once at each stage.

Under these conditions and supposing that the number for which the counters overflow has eleven bits, the addition of +1 to the address occurs in ten clock pulses by initially adding +1 to the address bit of binary weight 0; then during the following time interval the carry from this first addition is added to the address bit of binary weight 1, then during the following time interval the carry over of this second addition is added to the address bit of binary weight 2, and so forth.

Table V hereinbelow represents a portion of the address part of the buffer store contained in the register and counter. In each box of TABLE V, there are two unit memories A.sub.k,(l-1) and R.sub.(k-1),l. Each box of a horizontal line corresponds to a bit of an address word. Each box of a column corresponds to one of the 1024 positions of the address part of the buffer store. The following sketch represents the locations in Table V of the added bits ##STR7## ##STR8## ______________________________________

Table V therefore represents the following additions: ##STR9##

These additions are represented in Table V of FIG. 7 by brackets connecting the two digits to be added and a vertical arrow to the resulting sum and a diagonal arrow to the carry over. These operations occur at each interval of time; 10240 elementary operations of the type indicated in Equation (1) therefore take place during each interval of time.

Coming back to the above example at time t.sub.3, the address word lies at stage 0 (stage 601.sub.0); the same is true of the data octet (stage 600.sub.0). The address progresses through the address register and counter by undergoing successive additions.

Closer consideration of the staggered addition process corresponding to position or stage 957 reveals that this position corresponds to the output of the data octet at time t.sub.960 since the octet was entered in t.sub.3.

Table VI is a repeat of Table V with the addition of the time references corresponding to this particular case.

In T.sub.952, on one line appears: A.sub.0,957 +1 .fwdarw. A.sub.0,958 and R.sub.0,958 A.sub.1,956 + R.sub.0,957 .fwdarw. A.sub.1,957 and R.sub.1,957 A.sub.2,955 + R.sub.1,956 .fwdarw. A.sub.2,955 and R.sub.2,956 A.sub.3,953 + R.sub.2,955 .fwdarw. A.sub.3,955 and R.sub.3,955 A.sub.4,953 + R.sub.3,954 .fwdarw. A.sub.4,954 and R.sub.4,954 A.sub.5,952 + R.sub.4,953 .fwdarw. A.sub.5,953 and R.sub.5,953 A.sub.6,951 + R.sub.5,952 .fwdarw. A.sub.6,952 and R.sub.6,952 A.sub.7,950 + R.sub.6,951 .fwdarw. A.sub.7,951 and R.sub.7,951 A.sub.8,949 + R.sub.7,950 .fwdarw. A.sub.8,950 and R.sub.8,950 A.sub.9,948 + R.sub.8,949 .fwdarw. A.sub.9,949 and R.sub.9,949 ______________________________________

These ten elementary operations correspond to the control word at time t.sub.952.

The calculation follows through t.sub.953, t.sub.854 . . . etc. Consider the series leading up to the complete addition corresponding to a determined number in ten steps: At t.sub.951, we have in particular ##STR10## ##STR11## At t.sub.952, we have ##STR12## ##STR13## At t.sub.953, we have ##STR14## ##STR15## At t.sub.954, we have ##STR16## ##STR17## At t.sub.955, we have ##STR18## ##STR19## At t.sub.956, we have ##STR20## ##STR21## At t.sub.957, we have ##STR22## ##STR23## At t.sub.958, we have ##STR24## ##STR25## At t.sub.959, we have ##STR26## ##STR27## At t.sub.960, we have ##STR28## ______________________________________

The last carry over R.sub.9,957 is the one which causes the reading of the data octet at time t.sub.960.

Table VII resumes the digital example of connecting incoming time-slot 3 to outgoing time-slot 960. In this table, each line represents an address word with its carry overs as before; however in this case, the table indicates the development of the address word in time by leaving the other address words out of consideration.

The first line of Table VII represents the address word at time t.sub.950+.epsilon. ; in the second line of the Table representing t.sub.951+.epsilon., the same word has advanced by one open line, etc.

In Table VII, the addition process can be followed on the digital example. In particular, the diagonal indicated by the closed loops represents the propagation of the addition in ten clock pulses terminating in overflowing of the counter at the value of 1024.

At time t.sub.3, an address other than 67 must be initialized. The initialized address results from the following analysis:

If it is assumed that the writing of an address in the address part of the buffer store occurs at time t.sub.3 as specified hereinabove, only the most significant bit is exact at that moment. The previous bit had a correct value at position 1023. At position 0, the value of the previous bit must be deducted from the value 67 + 1 = 0001000100 in binary .uparw. Its value is thus 0 ______________________________________

The previous bit had a correct value at position 1022. At position 0, it must therefore be deducted from the value 67 + 2 = 0001000101 in binary .uparw. Its value is thus 0 ______________________________________

And so forth.

The following table indicates the value of the bits which are written in register 601.sub.0 instead of 67. weight of the bits 9876543210 weight 9         0001000011   67 .uparw. weight 8         0001000100   67 + 1 .uparw. weight 7         0001000101   67 + 2 .uparw. weight 6         0001000110   67 + 3 .uparw. weight 5         0001000111   67 + 4 .uparw. weight 4         0001001000   67 + 5 .uparw. weight 3         0001001001   67 + 6 .uparw. weight 2         0001001010   67 + 7 .uparw..dwnarw. weight 1         0001001011   67 + 8 .uparw. weight 0         0001001100   67 + 9 .uparw. The value to be written in position 0 (stage 601.sub.0) is therefore (without taking the remainders into account) 0001001010 (indicated by the arrows pointing upward) ______________________________________

More generally speaking, let i still be the incoming time-slot to be connected to outgoing time-slot j. Put j-i=a (mod. 1024).

Let "." represent the logic "AND" operation, "+" the logic "OR" operation and "plus" the arithmetic "binary addition" operation.

To connect time-slot i and j, the following word is written at the input of the address store at time t: ##STR29## ##STR30## ##STR31## ##STR32## ##STR33## ##STR34## ##STR35## ##STR36## ##STR37## +2.sup.-1       ] .times. 2.sup.1 ______________________________________

The remainders to be initialized take the following values: ##STR38## ##STR39## ##STR40## ##STR41## ##STR42## ##STR43## ##STR44## ##STR45## ##STR46## +2.sup.-1       ] .times. 2.sup.1 ______________________________________

## Claims

1. A time division multiplex switching network comprising: supermultiplexer converting the said incoming multiplex highways into one incoming supermultiplex highway; superdemultiplexer converting the said out-going supermultiplex highway into a plurality of out-going multiplex highways; input data word register and further data word registers forming a data word partial circulating store and an input random address register and further random address registers forming a random address partial circulating store, said data word partial circulating store and said random address partial circulating store operating synchronously and having associated data word registers and random address registers; present in the incoming time-slots of the incoming supermultiplex highway; addresses depending on the outgoing time slots to be connected to the incoming time slots; random address register each time said addresses pass from a random address register to the next of the random address partial circulating store, and with a random address register when the incremented address stored therein has reached a predetermined value

2. A time division multiplex switching network as set forth in claim 1, in which the means for steppedly incrementing by 1 the addresses written in the input random address register consists in a unit addend register forming a counter with said random address register, said counter overflowing for a predetermined value and said reading means are operated when the incremented address has reached said counter overflowing value

3. A time division multiplex switching network as set forth in claim 1 in which the random addresses have k bits and the means for steppedly incrementing by 1 the addresses written in the input random address register are distributed addition means synchronous with the circulating buffer store successively adding 1 to the bit of binary weight 0 in a first addition, adding the carry over of said first addition to the bit of binary weight 1, in a second addition, adding the carry over of the (k-1)th addition to the bit of binary weight (k-1) in a (k-1)th addition, the carry over of said (k-1)th addition controlling said reading out means.