# Patent

## Title
Temperature independent reference circuit

## Abstract

A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

## Background
This application is a continuation of application Ser. No. 13/398,116, filed Feb. 16, 2012, which is a continuation of application Ser. No. 13/136,921, filed Aug. 15, 2011, now U.S. Pat. No. 8,125,265, which is a continuation of application Ser. No. 12/931,377, filed Jan. 31, 2011, now U.S. Pat. No. 7,999,606, which is a continuation of application Ser. No. 12/587,204, filed Oct. 02, 2009, now U.S. Pat. No. 7,893,754, each of which are entitled, “TEMPERATURE INDEPENDENT REFERENCE CIRCUIT”, each of which are assigned to the assignee of the present application.


TECHNICAL FIELD
The present disclosure generally relates to the field of temperature independent reference circuits, more particularly, to temperature independent voltage reference and temperature independent current reference circuits manufactured on a semiconductor chip.
BACKGROUND
Temperature independent reference circuits have been widely used in integrated circuits (ICs) for many years. The purpose of a temperature independent reference circuit is to produce a reference voltage and/or a reference current that are substantially constant with temperature. In prior art ICs, a temperature-compensated reference voltage and a temperature-compensated reference current are sometimes generated on the same silicon chip using separate circuits. Typically, a temperature independent voltage reference is first derived and then a temperature independent current is derived using the temperature independent voltage. A drawback of this approach, however, is that the circuitry utilized to separately generate the reference voltage and reference current is usually complex and typically occupies a large area of the semiconductor (e.g., silicon) die.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, wherein:
FIG. 1 illustrates a circuit schematic diagram of a temperature independent reference circuit for simultaneously generating both a temperature-compensated reference voltage and a temperature-compensated reference current on an integrated circuit (IC).
FIG. 2 illustrates another example circuit schematic diagram of a temperature independent reference circuit for simultaneously generating both a temperature-compensated reference voltage and a temperature-compensated reference current on an integrated circuit (IC).



DESCRIPTION OF EXAMPLE EMBODIMENTS
In the following description specific details are set forth, such as device types, conductivity types, voltages, component values, configurations, etc., in order to provide a thorough understanding of the present invention. However, persons having ordinary skill in the relevant arts will appreciate that these specific details may not be needed to practice the embodiments described.
It should be appreciated that although an IC utilizing specific transistor types in certain circuit configurations is disclosed (e.g., N-channel field-effect transistors), different transistor types (e.g., P-channel) may also be utilized in alternative embodiments. In still other embodiments, some or all of the metal-oxide-semiconductor field-effect transistor (MOSFET) devices show by way of example may be replaced with bipolar junction transistors (BJTs), insulated gate field effect transistor (IGFETs), or other device structures that provide a transistor function. Furthermore, those of skill in the art of integrated circuits and voltage and/or current reference circuits will understand that transistor devices such as those shown by way of example in the figures may be integrated with other transistor device structures, or otherwise fabricated or configured in a manner such that different devices share common connections and semiconductor regions (e.g., N-well, substrate, etc.). For purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of a circuit or IC are defined or measured.
FIG. 1 illustrates a circuit schematic diagram of a temperature independent reference circuit 100 for generating both a temperature-compensated reference voltage and a temperature-compensated reference current at the same time on an IC. (In the context of the present application, the term “IC” is considered synonymous with a monolithic device.) Temperature independent reference circuit 100 includes NPN bipolar transistors Q1, Q2, Q3 and Q4. Transistors Q1 & Q2 are matched devices with Q1 having an emitter size ratio of “a” with respect to emitter size of Q2, where “a” is an integer greater than 1. The emitter of Q2 is shown coupled to ground. The emitter of Q1, node VX, is coupled to ground through series-connected resistors R1 and R2. In the embodiment shown, a temperature independent current reference IREF flows through resistors R1 and R2, where IREF=VX/(R1+R2). The collector of Q1, node 102, is coupled to the base of Q3 and an end of resistor R3. The other end of R3, node 103, is connected to the emitter of transistor Q4. Node 103 provides a temperature independent voltage reference VREF that is derived from the temperature independent current reference IREF, as described in more detail below.
Continuing with the example of FIG. 1 the base of transistor Q4 is commonly coupled to the collector of Q3, resistor R4, and the drain of p-channel metal-oxide-semiconductor field-effect transistor (PMOS) MP1. The other end of R4 and the source of MP1 are connected to the voltage supply potential VOD. The gate of MP1 is coupled to receive a power-up (PU) signal that ensures the proper operation of the circuit. At power-up, VOD ramps up from ground potential and PU is initially low to drive current into the base of Q4. When VDD reaches a potential high enough for circuit 100 to operate, power-up signal PU transitions to high, thereby turning off MP1.
Temperature independent reference circuit 100 further includes PMOS transistor MP2 coupled between VDD and the collector of Q4. The gate and drain of MP2 are commonly coupled to the gates of matched PMOS transistors MP3 and MP4 in a current mirror configuration with NPN transistors Q1 & Q2 so as to reflect the temperature independent current reference IREF through MP4 for output elsewhere on the IC. Practitioners in the art will appreciate that the circuit of FIG. 1 generates a temperature compensated current IREF, which current is then utilized to generate a temperature compensated voltage VREF at node 103. To achieve this result, resistors R3 and R1 have a ratio of M and are matched, meaning that they have the same temperature coefficient of resistance due to the fact that they are fabricated of the same material on the IC. In one embodiment, R1 and R3 comprise a semiconductor material implanted or diffused with P type dopant.
A temperature coefficient TC may be defined as the relative change of a physical property when the temperature is changed by one degree C. The temperature coefficient of resistors R3 and R1, TC3, is positive and larger than the positive temperature coefficient of ΔVBE, TC1. In particular, ΔVBE is the difference between the voltage across base to emitter of transistors Q1 and voltage across base to emitter of transistor Q2. Resistor R2 is fabricated of a different material type (e.g., polysilicon) as compared to resistors R3 and R1. The temperature coefficient, TC2, of R2 is also positive but smaller than TC1. When this circuit is operating properly, the currents flowing thru Q1 and Q2 are forced to be equal by the current mirror transistors MP2 and MP3, resulting in a ΔVBE across the series connected resistors R1 and R2. The resistance ratio of R1/R2 is chosen such that, TC1=TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)). This makes the change over temperature in the combined resistance, R1+R2, the same as the change over temperature in ΔVBE, resulting in a current IREF flowing thru R1 and R2 that is constant over temperature.
To better understand the operation of temperature independent reference circuit 100, temperature independent current reference IREF may be expressed mathematically by the equation:




  
    
      
        
          I
          REF
        
        =
        
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              BE
            
          
          
            (
            
              
                R
                1
              
              +
              
                R
                2
              
            
            )
          
        
      
    
    
      
        (
        1
        )
      
    
  




To achieve temperature independent current reference IREF, the percent change in ΔVBE should be equal to the percent change in total resistance (R1+R2). As further shown, the percent change in ΔVBE may be calculated by the equation (2) below:




  
    
      
        
          Percent
          ⁢
          
            
          
          ⁢
          change
          ⁢
          
            
          
          ⁢
          in
          ⁢
          
            
          
          ⁢
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            BE
          
        
        =
        
          
            
              (
              
                
                  
                    Δ
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      BEF
                    
                  
                  -
                  
                    Δ
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      BEI
                    
                  
                
                
                  Δ
                  ⁢
                  
                    
                  
                  ⁢
                  
                    V
                    BEI
                  
                
              
              )
            
            ·
            100
          
          ⁢
          %
        
      
    
    
      
        (
        2
        )
      
    
  




where ΔVBEF represents the difference in base-to-emitter voltage between Q1 & Q2 at a final temperature and ΔVBEI represents the difference in base-to-emitter voltage between Q1 & Q2 voltage at an initial temperature.

It is known to one skilled in the art that ΔVBE may be determined based on the following equation:

ΔVBE=VBE2−VBE1=VT·ln a   (3)

where ln is the natural logarithm, “a” is the relative sizing ratio of Q1 with respect to Q2, and VT is a constant that varies only as temperature varies. This leads into equation (4), shown below, which gives the percent change of ΔVBE in terms of VT:





  
    
      
        
          Percent
          ⁢
          
            
          
          ⁢
          change
          ⁢
          
            
          
          ⁢
          in
          ⁢
          
            
          
          ⁢
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            BE
          
        
        =
        
          
            
              (
              
                
                  
                    
                      
                        V
                        TF
                      
                      ·
                      ln
                    
                    ⁢
                    
                      
                    
                    ⁢
                    a
                  
                  -
                  
                    
                      
                        V
                        TI
                      
                      ·
                      ln
                    
                    ⁢
                    
                      
                    
                    ⁢
                    a
                  
                
                
                  
                    
                      V
                      TI
                    
                    ⁢
                    
                      
                    
                    ·
                    ln
                  
                  ⁢
                  
                    
                  
                  ⁢
                  a
                
              
              )
            
            ·
            100
          
          ⁢
          %
        
      
    
    
      
        (
        4
        )
      
    
  




where VTF is the value of the constant VT at a final temperature and VTI is the value of the constant VT at an initial temperature.

As shown, the percent change in (R1+R2) may be calculated by the equation (5) below:




  
    
      
        
          Percent
          ⁢
          
            
          
          ⁢
          change
          ⁢
          
            
          
          ⁢
          in
          ⁢
          
            
          
          ⁢
          
            (
            
              
                R
                1
              
              +
              
                R
                2
              
            
            )
          
        
        +
        
          
            
              (
              
                
                  
                    R
                    
                      1
                      ⁢
                      F
                    
                  
                  -
                  
                    R
                    
                      1
                      ⁢
                      I
                    
                  
                
                
                  
                    R
                    
                      1
                      ⁢
                      I
                    
                  
                  +
                  
                    R
                    
                      2
                      ⁢
                      I
                    
                  
                
              
              )
            
            ·
            100
          
          ⁢
          %
        
        +
        
          
            
              (
              
                
                  
                    R
                    
                      2
                      ⁢
                      F
                    
                  
                  -
                  
                    R
                    
                      2
                      ⁢
                      I
                    
                  
                
                
                  
                    R
                    
                      1
                      ⁢
                      I
                    
                  
                  +
                  
                    R
                    
                      2
                      ⁢
                      I
                    
                  
                
              
              )
            
            ·
            100
          
          ⁢
          %
        
      
    
    
      
        (
        5
        )
      
    
  




The above equation can be realized by setting R1 and R2 depending on the percent change of the resistance of each resistor such that the total percent change over temperature of the total resistance matches the total percent change over temperature of ΔVBE. As explained above, in one embodiment, resistors R1 and R2 are manufactured of different materials, so the percentage change in resistance value over temperature is different between the two resistors.
By way of example, if we assume that ΔVBE varies by 33% over 100° C. (e.g., ΔVBEF=48 mV, ΔVBEI=36 mV), and R1 and R2 vary respectively by 60% and 6% over the same temperature range, then the ratio of R1 to R2 may be 50/50, meaning that R1 provides 30% and R2 provides 3% of the temperature compensation that substantially cancels out the 33% change of ΔVBE. In other words, the change in percentage over temperature in the combined resistance, R1+R2, is set to be the same as the change in percentage over temperature in ΔVBE, resulting in a current IREF flowing thru R1 and R2 that is substantially constant over temperature.
Turning now to the temperature independent voltage reference aspect of temperature independent reference circuit 100, the output reference voltage VREF generated at node 103 is related to the voltage across resistor R3, VR3, which is established by IREF (e.g., VR3=R3×IREF). Since IREF does not substantially vary with temperature as discussed above, the voltage VR3 possesses the same temperature coefficient as R3 (i.e., TC3). As shown, the output reference voltage VREF is the sum of the VBE of Q3 (VBE3), which typically has a temperature coefficient −2 mV/° C., plus the voltage VR3 which has a positive temperature coefficient of TC4. Stated in different mathematical terms,

VREF=VBE3+VR3   (6)

Equation (6) shows that to achieve a temperature independent voltage, VREF, the change in voltage drop VR3 over temperature must substantially equal to the absolute value of the change in VBE3 over temperature. That is, the temperature variation of VR3 is set to be approximately +2 mV/° C. to substantially cancel out the temperature variation of the VBE3.
Another way to look at it is that change in resistance R3 is made to cancel out the change in voltage VBE3 over a given temperature range, as represented in equation (7) below, where VBE3F and VBE3I are the final and initial base-emitter voltages, and VR3F and VR3I are the final and initial voltages across R3, at high and low temperatures, respectively.

VBE3F−VBE3I=−(VR3F−VR3I)   (7)

For example, let us assume that the temperature coefficient of VBE3 is exactly −2 mV/° C. so that over a 100° C. increase in temperature the voltage drop across VBE3 decreases by 200 mV. To achieve a temperature independent output reference voltage VREF, the voltage drop VR3 must also increase by 200 mV over the same 100° C. increase in temperature. Since R3 and R1 are matched resistors (i.e., made of the same material) their resistance values both change in the same percentage over a unit temperature. The reference output current IREF is set in accordance with the description provided above, which means that R3 may be determined by the following equation.




  
    
      
        
          R
          3
        
        =
        
          
            
              Δ
              ⁢
              
                
              
              ⁢
              
                V
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
            
            
              Δ
              ⁢
              
                
              
              ⁢
              
                V
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
          ·
          
            R
            1
          
        
      
    
    
      
        (
        8
        )
      
    
  




where ΔVR3=VR3F−VR3I and ΔVR1=VR1F−VR1I. The change in VR1 is set due to the resistance value of R1 and IREF. In the example, the change in VR3 is 200 mV. Therefore, R3 may be determined such that the decrease of voltage VBE3 is the same as the increase of voltage drop VR3 over a change in unit temperature.

FIG. 2 illustrates another example circuit schematic diagram of a temperature independent reference circuit 200 for simultaneously generating both a temperature-compensated reference voltage and a temperature-compensated reference current on an integrated circuit (IC). Temperature independent reference circuit 200 is identical to circuit 100 of FIG. 1 in every respect, except that resistor R4 in temperature independent reference circuit 100 is replaced by PMOS transistor MP5 in temperature independent reference circuit 200. PMOS transistor MP5 functions as another current mirror transistor, which ensures the current flowing thru NPN transistor Q3 remains constant over temperature. In addition, another advantage for replacing resistor R4 with transistor MP5 is to reduce total area of temperature independent reference circuit 200. Practitioners in the art will understand that this improvement eliminates a relatively minor error term in VREF present in the embodiment of FIG. 1. This error term tends to cause a slight change in VREF due to current density changes in the voltage VBE3.
Although the present invention has been described in conjunction with specific embodiments, those of ordinary skill in the arts will appreciate that numerous modifications and alterations are well within the scope of the present invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

## Claims

1. An integrated circuit (IC) fabricated on a semiconductor substrate comprising:
first and second bipolar transistors, the base and collector of the first bipolar transistor being coupled to the base of the second bipolar transistor;
first and second resistors coupled in series between the emitter of the second bipolar transistor and the ground potential, the first resistor comprising a first material type and the second resistor comprising a second material type, the first and second resistors having first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively;
a current mirror coupled to the first and second bipolar transistors such that a first current flows through each of the first and second bipolar transistors when power is supplied to the IC, the first and second resistance values being such that the first current is substantially constant over temperature.

2. The IC of claim 1 wherein a size ratio of the emitter of the second bipolar transistor to the emitter of the first bipolar transistor being equal to N, where N is an integer greater than 1.

3. The IC of claim 1 wherein the emitter of the first bipolar transistor is coupled to the ground potential.

4. The IC of claim 1 further comprising a third resistor coupled between a node and the collector of the second bipolar transistor, the first current flowing through the third resistor when power is supplied to the IC, the third resistor having a third resistance value, R3, and the third temperature coefficient TC3.

5. The IC of claim 4 wherein a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/ (R1+R2)).

6. The IC of claim 4 wherein the third resistor comprises the first material type.

7. The IC of claim 1 wherein the first material type comprises a p-type implant.

8. The IC of claim 7 wherein the second material type comprises polysilicon.

9. An integrated circuit (IC) fabricated on a semiconductor substrate comprising:
first and second bipolar transistors, the base and collector of the first bipolar transistor being coupled to the base of the second bipolar transistor;
first and second resistors coupled in series between the emitter of the second bipolar transistor and the ground potential, the first and second resistors having first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively;
a current mirror coupled to the first and second bipolar transistors such that a first current flows through each of the first and second bipolar transistors when power is supplied to the IC, the first and second resistance values being such that the first current is substantially constant over temperature; and
a third bipolar transistor, the emitter of the third bipolar transistor being coupled to the ground potential, the base of the third bipolar transistor being coupled to the collector of the second bipolar transistor.

10. The IC of claim 9 further comprising a fourth bipolar transistor, the base of the fourth bipolar transistor being coupled to the collector of the third bipolar transistor, the emitter of the fourth bipolar transistor being coupled to the collector of the second bipolar transistor, the collector of the fourth bipolar transistor being coupled to the current mirror.

11. The IC of claim 10 wherein the current mirror includes first and second p-channel field-effect transistors.

12. The IC of claim 11 further comprising a third p-channel field-effect transistor coupled to the first and second p-channel field-effect transistors, the third p-channel field-effect transistor being configured to output the first current.

13. The IC of claim 12 further comprising a fourth resistor coupled between a supply line and the collector of the third bipolar transistor.

14. The IC of claim 13 further comprising a fourth p-channel field-effect transistor coupled between the supply line and the collector of the third bipolar transistor.

15. The IC of claim 14 wherein the gate of the fourth p-channel field-effect transistor is coupled to receive a power-up (PU) signal that is initially low at power-up of the IC, the PU signal transitioning high after the supply line reaches a voltage potential sufficiently high enough to operate the IC.

16. The IC of claim 9 wherein the first resistor comprises a first material type and the second resistor comprises a second material type.

17. The IC of claim 16 wherein the first material type comprises a p-type implant.

18. The IC of claim 17 wherein the second material type comprises polysilicon.

19. The IC of claim 9 further comprising a third resistor coupled between a node and the collector of the second bipolar transistor, the first current flowing through the third resistor when power is supplied to the IC, the third resistor having a third resistance value, R3, and the third temperature coefficient TC3.

20. The IC of claim 19 wherein a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors. TC1, is substantially equal to TC2×(R2/(R1 +R2))+TC3×(R1/ (R1+R2)).