# Patent

## Title
Capacitive digital to analog and analog to digital converters

## Abstract

A pipelined analog-to-digital converter (ADC) comprises a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC). The ADC includes an amplifier having an input and an output. N capacitances are connected in parallel and include first ends that selectively communicate with the input and second ends. N switches selectively connect the second ends of the N capacitances to the voltage input during a first phase, one of the second ends of the N capacitances to the output of the amplifier during a second phase, and others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase. A second stage communicates with the output the amplifier.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is a Continuation of U.S. Ser. No. 11/293,917 filed Dec. 5, 2005, which claims priority under 35 U.S.C. Section 119(e) from U.S. Provisional Application No. 60/715,078, filed on Sep. 8, 2005. The disclosures of the above applications are incorporated herein by reference in their entirety.


FIELD OF THE INVENTION
The present invention relates to digital to analog (D/A) and analog to digital (A/D) converters, and more particularly to capacitive and/or resistive D/A and A/D converters.
BACKGROUND OF THE INVENTION
Digital to analog (D/A) converters can include arrays of capacitors that are selectively switched to convert a digital signal to an analog counterpart. However, mismatch between capacitors may cause the D/A converter to be non-monotonic. Monotonicity in a D/A converter means that as the digital input to the converter increases over a full-scale range, the analog output never exhibits a decrease between one conversion step and a subsequent conversion step. In other words, the slope of the transfer characteristic is never negative in a monotonic converter.
Referring now to FIG. 1A, a D/A converter 10 is shown. The D/A converter 10 includes a binary capacitor array 14, switches 16 and 18, an operational amplifier (opamp) 20, and a capacitor Cf in a feedback arrangement with the opamp 20. Each of the capacitors in the array 14 have different values. More particularly, each capacitor in the array 14 is twice the value of the preceding capacitor. Switches SW selectively switch the capacitors in the array 14 between a voltage reference and a reference potential such as ground.
In use, the D/A converter 10 has sampling and integration stages. In the sampling stage, the switch 16 closes and selective ones of the capacitors are charged to the voltage reference as determined by the switches. In the integrating phase, the switch 16 is opened and the analog output is generated. For example, a four bit array may close a first or most significant bit (MSB) switch and a least significant bit (LSB) switch to represent 9/16 of a voltage reference.
Referring now to FIG. 1B, a non-monotonic output of a D/A converter is shown. For example, the analog output exhibits a decrease from one conversion step to the subsequent conversion step as shown at in FIG. 1B at 44. The non-monotonic output may be due to capacitor mismatch. For example, the capacitor 2N−1C may be different than 2N−2C+2N−3C+ . . . +2C+C. Ideally, 2N−1C−(2N−2C+2N−3C+ . . . +2C+C)=C. In other words, the difference between the MSB capacitor and the rest of the capacitors should be equal to a smallest or LSB capacitor
Referring now to FIG. 2, a D/A converter 50 including a linear capacitor array 54 is shown. The linear capacitor array 54 includes 2N−1 capacitors that are selectively switched between a voltage reference and reference potential such as ground. While the linear capacitor array 54 inherently monotonic, the number of switches required grows exponentially with the bit resolution. For example, a 16-bit digital to analog converter includes 216−1 pairs of switches, which may be impractical.
SUMMARY OF THE INVENTION
A digital-to-analog converter (DAC) comprises a capacitive DAC that comprises N first capacitances that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one, and N first switches that selectively connect a selected one of the second ends of the N first capacitances to a common node and non-selected ones of the second ends of the N first capacitances to one of a voltage potential and a reference potential. Capacitance values of the N first capacitances are substantially equal. A second DAC communicates with the common node.
A digital-to-analog converter (DAC) comprises first converting means for converting a digital signal to an analog signal and that comprises N first capacitance means for providing capacitance that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one and N first switching means for selectively connecting one of the second ends of the N first capacitance means to a common node and others of the second ends to one of a voltage potential and a reference potential. Capacitance values of the N first capacitance means are substantially equal. Second converting means converts a digital signal to an analog signal and that communicates with the common node.
A method for providing a digital-to-analog converter (DAC) comprises connecting N first capacitances of a first capacitive DAC in parallel, wherein the N first capacitances have first ends and second ends, N is an integer greater than one, and capacitance values of the N first capacitances are substantially equal. The method includes selectively connecting a selected one of the second ends of the N first capacitances to a common node; selectively connecting others of the second ends to one of a voltage potential and a reference potential; and connecting a second DAC to the common node.
A pipelined analog-to-digital converter (ADC) comprises a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC) that includes an amplifier having an input and an output; N capacitances that are connected in parallel and that include first ends that selectively communicate with the input and second ends; N switches that selectively connect the second ends of the N capacitances to the voltage input during a first phase, one of the second ends of the N capacitances to the output of the amplifier during a second phase, and others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase. A second stage communicates with the output the amplifier.
In other features, the first phase is a sampling phase and the second phase is a residue amplification phase. When the input voltage is between zero and a first ratio of a first of the N capacitances divided by a sum of the N capacitances, the first of the N capacitances is connected to the output of the amplifier and others of the N capacitances are connected to the reference potential during the second phase. When the input voltage is between the first ratio and a second ratio of a sum of the first and a second of the N capacitances divided by a sum of the N capacitances, the first of the N capacitances is connected to the voltage reference, the second of the N capacitances is connected to the output of the amplifier and others of the N capacitances are connected to the reference potential during the second phase. When the input voltage is between the second ratio and a third ratio of a sum of the first, the second and a third of the N capacitances divided by a sum of the N capacitances, the first and the second of the N capacitances are connected to the voltage reference, the third of the N capacitances is connected to the output of the amplifier and others of the N capacitances are connected to the reference potential during the second phase.
A pipelined analog-to-digital converter (ADC) comprises first stage means for receiving an input voltage signal and that comprises converting means for converting signals that includes: amplifying means for amplifying and having an input and an output; N capacitance means for providing capacitance, that are connected in parallel and that include first ends that selectively communicate with the input and second ends; and N switching means for selectively connecting the second ends of the N capacitance means to the voltage input during a first phase, one of the second ends of the N capacitance means to the output of the amplifier during a second phase, and others of the second ends of the N capacitance means to one of a voltage reference and a reference potential during the second phase; and second stage means for communicating with the output of the amplifying means of the first stage means.
In other features, the first phase is a sampling phase and the second phase is a residue amplification phase. When the input voltage is between zero and a first ratio of a first of the N capacitances divided by a sum of the N capacitances, the N switching means connect the first of the N capacitances to the output of the amplifier and others of the N capacitances to the reference potential during the second phase. When the input voltage is between the first ratio and a second ratio of a sum of the first and a second of the N capacitances divided by a sum of the N capacitances, the N switching means connect the first of the N capacitances to the voltage reference, the second of the N capacitances to the output of the amplifier and others of the N capacitances to the reference potential during the second phase. When the input voltage is between the second ratio and a third ratio of a sum of the first, the second and a third of the N capacitances divided by a sum of the N capacitances, the N switching means connect the first and the second of the N capacitances to the voltage reference, the third of the N capacitances to the output of the amplifier and others of the N capacitances to the reference potential during the second phase.
A method for generating a residue voltage in a pipelined analog-to-digital converter (ADC) comprises providing first and second stages, wherein the first stage receives a voltage input and includes a capacitive ADC including N capacitances; selectively connecting the second ends of the N capacitances to the voltage input during a first phase; selectively connecting one of the second ends of the N capacitances to the output of the amplifier during a second phase; selectively connecting others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase; selectively connecting the first ends of the N capacitances to an amplifier input; and connecting an amplifier output to the second stage.
In other features, the first phase is a sampling phase and the second phase is a residue amplification phase. The method further comprises selectively connecting the first of the N capacitances to the output of the amplifier and others of the N capacitances to the reference potential during the second phase when the input voltage is between zero and a first ratio of a first of the N capacitances divided by a sum of the N capacitances. The method further comprises selectively connecting the first of the N capacitances to the voltage reference, the second of the N capacitances to the output of the amplifier and others of the N capacitances to the reference potential during the second phase when the input voltage is between the first ratio and a second ratio of a sum of the first and a second of the N capacitances divided by a sum of the N capacitances. The method further comprises selectively connecting the first and the second of the N capacitances to the voltage reference, the third of the N capacitances to the output of the amplifier and others of the N capacitances to the reference potential during the second phase when the input voltage is between the second ratio and a third ratio of a sum of the first, the second and a third of the N capacitances divided by a sum of the N capacitances.
A digital to analog converter (DAC) comprises X capacitive DACs that are connected in series and wherein X is an integer greater than one. Each of the X capacitive DACs comprise M switches wherein M is an integer greater than one; a signal input; a signal output; and M capacitances that communicate with the M switches, respectively, and that have first and second ends and substantially equal capacitance values. The M switches selectively connect the first ends of the M capacitances to the signal output. The M switches connect the second end of a selected one of the M capacitances to the signal input. A first DAC has a signal output that communicates with the signal input of one of the X capacitive DACs.
In other features, an amplifier has an input and an output. A feedback capacitance communicates with the input and the output of the amplifier. The first ends of the M capacitances of another one of the X DACs communicates with a reference potential during a first phase of the another one of the X DACs. The input of the amplifier selectively communicates with the first ends of the M capacitances of the another one of the X DACs during a second phase of the another one of the X DACs.
In other features, an amplifier has an input and an output. The first ends of the M capacitances of another one of the X DACs communicate with a reference potential during a first phase of the another one of the X DACs. The input of the amplifier selectively communicates with the first ends of the M capacitances of the another one of the X DACs during a second phase of the another one of the X DACs. The second ends of the of the M capacitances of the another one of the X DACs communicate with the output of the amplifier during the second phase of the another one of the X DACs. The first DAC comprises Y resistive DACs wherein Y is an integer greater than zero.
In other features, at least one of the Y resistive DACs comprises a signal output; N resistances connected in series between the voltage reference and the reference potential; N nodes between select ones of the N resistances and the reference potential; and N second switches that selectively connect the signal output of the one of the Y resistive DACs to one of the N nodes. A control module selectively generates switching signals to control the X capacitive DACs and the first DAC.
In other features, a successive approximation analog-to-digital converter comprises the DAC. The successive approximation analog-to-digital converter of comprises an amplifier having an input that selectively communicates with one of the X capacitive DACs. A successive approximation module communicates with an output of the amplifier. A decoding module communicates with an output of the successive approximation module and selectively generates switching signals for the X capacitive DACs and the first DAC.
In other features, the first DAC comprises a capacitive DAC. The capacitive DAC comprises a signal output and an amplifier having an input and an output that communicates with the signal output. M second capacitances are connected in parallel and have first ends and second ends. The first ends selectively communicate with a reference potential during a first phase of the capacitive DAC. The first ends selectively communicate with the input of the amplifier during a second phase of the capacitive DAC. M second switches selectively connect the second ends of the M second capacitances to one of the voltage reference and the reference potential during the first phase of the capacitive DAC and selectively connect the second ends of the M second capacitances to the output during the second phase of the capacitive DAC.
A digital to analog converter (DAC) comprises X capacitive converting means for converting a digital signal to an analog signal and that are connected together in series and wherein X is an integer greater than one. Each of the X capacitive converting means comprise M switching means for switching wherein M is an integer greater than one. M capacitance means for providing capacitance communicate with the M switching means, respectively, and have first and second ends and substantially equal capacitance values. The M switching means selectively connect the first ends of the M capacitance means to the signal output. The M switching means connect the second end of a selected one of the M capacitance means to the signal input. First converting means converts a digital signal to an analog signal and has a signal output that communicates with the signal input of one of the X capacitive converting means.
In other features, amplifying means for amplifying and has an input and an output. Feedback capacitance means provides capacitance and communicates with the input and the output of the amplifying means. The first ends of the M capacitance means of another one of the X converting means communicates with a reference potential during a first phase of the another one of the X converting means. The input of the amplifying means selectively communicates with the first ends of the M capacitance means of the another one of the X converting means during a second phase of the another one of the X converting means.
In other features, amplifying means for amplifying has an input and an output. The first ends of the M capacitance means of another one of the X converting means communicates with a reference potential during a first phase of the another one of the X converting means. The input of the amplifying means selectively communicates with the first ends of the M capacitance means of the another one of the X converting means during a second phase of the another one of the X converting means. The second ends of the M capacitance means of the another one of the X converting means communicate with the output of the amplifying means during the second phase of the another one of the X converting means. The first DAC comprises Y resistive converting means for converting a digital signal to an analog signal and wherein Y is an integer greater than zero.
In other features, at least one of the Y resistive converting means comprises a signal output and N resistance means for providing resistance and that is connected in series between the voltage reference and the reference potential. N nodes are located between select ones of the N resistance means and the reference potential. N second switching means selectively connect the signal output of the one of the Y resistive converting means to one of the N nodes. Control means selectively generates switching signals to control the X capacitive converting means and the first DAC.
In other features, a successive approximation analog-to-digital converter comprises the DAC. The successive approximation analog-to-digital converter comprises amplifying means for amplifying and having an input that selectively communicates with one of the X capacitive DACs and approximation means for successive approximating and that communicates with an output of the amplifying means. Decoding means communicates with an output of the successive approximation module for selectively generating switching signals for the X capacitive DACs and the first DAC.
In other features, the first DAC comprises a capacitive converting means for converting a digital signal to an analog signal. The capacitive converting means comprises a signal output and amplifying means for amplifying and having an input and an output that communicates with the signal output. M second capacitance means provides capacitance and is connected in parallel and has first ends and second ends. The first ends selectively communicate with a reference potential during a first phase of the capacitive DAC. The first ends selectively communicate with the input of the amplifying means during a second phase of the capacitive DAC. M second switching means selectively connect the second ends of the M second capacitance means to one of the voltage reference and the reference potential during the first phase of the capacitive DAC and selectively connect the second ends of the M second capacitance means to the output during the second phase of the capacitive DAC.
A method for operating a digital to analog converter (DAC) comprises connecting X capacitive DACs in series and wherein X is an integer greater than one, wherein each of the X capacitive DACs comprise M capacitances that have first and second ends and substantially equal capacitance values; selectively connecting the first ends of the M capacitances to the signal output; connecting the second end of a selected one of the M capacitances to the signal input; and connecting a signal output of a first DAC to the signal input of one of the X capacitive DACs.
In other features, the method comprises providing an amplifier having an input and an output and a feedback capacitance that communicates with the input and the output of the amplifier. The method comprises connecting the first ends of the M capacitances of another one of the X DACs with a reference potential during a first phase of the another one of the X DACs. The method comprises selectively connecting the input of the amplifier to the first ends of the M capacitances of the another one of the X DACs during a second phase of the another one of the X DACs.
In other features, the method comprises providing an amplifier having an input and an output; selectively connecting the first ends of the M capacitances of another one of the X DACs with a reference potential during a first phase of the another one of the X DACs; selectively connecting the input of the amplifier with the first ends of the M capacitances of the another one of the X DACs during a second phase of the another one of the X DACs; and selectively connecting the second ends of the of the M capacitances of the another one of the X DACs communicate with the output of the amplifier during the second phase of the another one of the X DACs.
In other features, the first DAC comprises Y resistive DACs wherein Y is an integer greater than zero. The method comprises selectively generating switching signals to control the X capacitive DACs and the first DAC. The method comprises using the X capacitive DACs to successively approximate an analog input signal. The first DAC comprises a capacitive DAC.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:
FIG. 1A is an electrical schematic of a binary capacitor array D/A converter according to the prior art;
FIG. 1B is a graph of a D/A converter;
FIG. 2 is an electrical schematic of a linear capacitor array D/A converter according to a prior art;
FIGS. 3A-3C are electrical schematics of a capacitive-resistive D/A converter in exemplary configurations;
FIG. 4A illustrates the D/A converter of FIG. 3B during a sampling phase for a first digital value;
FIG. 4B illustrates the D/A converter of FIG. 3B during an integrating phase for a first digital value;
FIG. 4C is an exemplary truth table for the circuit of FIG. 3B;
FIG. 4D is an exemplary truth table for the circuit of FIG. 3C;
FIG. 5 illustrates the D/A converter of FIG. 3B during a sampling phase for a second digital value;
FIG. 6 illustrates the D/A converter of FIG. 3B during a sampling phase for a third digital value;
FIG. 7 illustrates the D/A converter of FIG. 3B during a sampling phase for a fourth digital value;
FIG. 8A is an electrical schematic of a capacitive-capacitive D/A converter;
FIG. 8B is an electrical schematic of a capacitive-capacitive D/A converter in a sample and integrate configuration;
FIG. 8C illustrates the D/A converter of FIG. 8B during a sampling phase for a first digital value;
FIG. 8D illustrates the D/A converter of FIG. 8B during an integrating phase for a first digital value;
FIG. 8E illustrates the D/A converter of FIG. 8B during a sampling phase for a second digital value;
FIG. 8F illustrates the D/A converter of FIG. 8B during a sampling phase for a third digital value;
FIG. 8G illustrates the D/A converter of FIG. 8B during a sampling phase for a fourth digital value;
FIG. 8H is an exemplary timing diagram showing sampling and integrating phases for LSB and MSB portions;
FIG. 8I is an exemplary timing diagram showing sampling and integrating phases for LSB and MSB portions;
FIG. 8J is an exemplary truth table for the D/A converter of FIG. 8B;
FIG. 9A illustrates an N-stage capacitive D/A converter;
FIG. 9B illustrates an N-stage capacitive-resistive D/A converter;
FIG. 9C is an exemplary timing diagram showing non-overlapping sampling and integrating phases for additional stages;
FIG. 9D is an exemplary timing diagram showing overlapping sampling and integrating phases for additional stages;
FIG. 10 is an electrical schematic of a successive approximation A/D converter according to the present invention;
FIG. 11A is an electrical schematic of a pipelined A/D converter according to the present invention;
FIG. 11B-11D illustrate ideal and non-ideal residue voltages;
FIG. 12A illustrates an A/D converter that generates an ideal residue voltage according to the present invention;
FIG. 12B illustrates the A/D converter of FIG. 12A in a sampling phase;
FIG. 12C illustrates the A/D converter of FIG. 12A in a residue amplification stage for a first voltage input value;
FIG. 12D is an exemplary truth table for the A/D converter of FIG. 12A;
FIG. 13 illustrates the A/D converter of FIG. 12A in a residue amplification stage for a second voltage input value;
FIG. 14 illustrates the A/D converter of FIG. 12A in a residue amplification stage for a third voltage input value;
FIG. 15 illustrates the A/D converter of FIG. 12A in a residue amplification stage for a fourth voltage input value;
FIG. 16 is a graph illustrating variable interstage gain and an ideal residue voltage of the circuit of FIG. 12A;
FIG. 17A is a functional block diagram of a hard disk drive;
FIG. 17B is a functional block diagram of a digital versatile disk (DVD);
FIG. 17C is a functional block diagram of a high definition television;
FIG. 17D is a functional block diagram of a vehicle control system;
FIG. 17E is a functional block diagram of a cellular phone;
FIG. 17F is a functional block diagram of a set top box; and
FIG. 17G is a functional block diagram of a media player.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module, circuit and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present invention.
Referring now to FIGS. 3A and 3B, capacitive-resistive D/A converters 100, 100-1 and 100-2 are shown. For simplicity, an N=4 bit example is shown in FIGS. 3A-3C. Skilled artisans will appreciate that N can be set to other numbers of bits. Various types of output circuits 102 may be used. Additional connections 104, which may or may not be switched connections, may be used depending upon the function that is desired. For example in FIG. 3B, the DAC 100-1 is shown in a sample and integrate configuration and in FIG. 3C, a DAC 100-2 is shown with a sample and hold configuration.
In this example, the two most significant bits (MSBs) are allocated to a capacitive portion 110 and the two least significant bits (LSBs) are allocated to a resistive portion 120. In the Figures that follow, the capacitor C, will be shown with dotted lines to indicate both sample and hold and sample and integrate configurations.
The capacitive portion 110 includes capacitors C1, C2, C3 and C4. In the preferred embodiment, the capacitors C1, C2, C3 and C4 have a substantially equal capacitance value. The capacitors may have substantially the same capacitance value, in other words C1=C2=C3=C4. As will be described further below, the capacitors are selectively switched by switches SW4MSB, SW3MSB, SW2MSB, and SW1MSB (collectively switches SWM) between a voltage reference Vref, a reference potential such as ground, and a common node 130 between the resistive portion 120 and the capacitive portion 110.
The resistive portion 110 includes resistors R1, R2, R3 and R4. In the preferred embodiment, the resistors R1, R2, R3 and R4 have a substantially equal resistance value. The resistors may have the same resistance value, in other words R1=R2=R3=R4. As will be described further below, the resistors are connected in series between Vref and a reference potential such as ground. A node between the resistors is selected by switches SW4LSB, SW3LSB, SW2LSB, and SW1LSB (collectively switches SWL) and connected to the common node 130 to create a voltage divider.
The sample and integrate circuit was described above. In the sample and hold configuration, the second ends of the capacitances C1, C2, C3 and C4 are switched to the output of the amplifier during the second phase of the capacitive portion 110. The feedback capacitance Cf may be omitted.
Referring now to FIG. 4A, the D/A converter of FIG. 3B is shown during a sampling phase for a first digital value (0011). Initially, the switch 16 is closed, the switch 18 is opened and the capacitors C2, C3 and C4 are switched by respective switches to the reference potential, which may be ground. The capacitor C1 is connected to the common node. The capacitive portion 110 will be in this configuration when the desired binary value is between 0000 and 0011. One of the resistive switches SW4LSB, SW3LSB, SW2LSB, and SW1LSB is closed to create a voltage divider. In the example shown in FIG. 4A, the switch SW4LSB is closed to provide




  
    3
    4
  
  ⁢
  
    
      V
      ref
    
    .
  




A charge is accumulated on the capacitor C1 that is equal to VRDACC1, where VRDAC is the voltage provided by the resistive portion 120.

Referring now to FIG. 4B, the D/A converter of FIG. 3B is shown during an integrating phase for the first digital value (0011). In this phase, the switch 16 is opened, the switch 18 is closed and the voltage value is applied to the amplifier 20. Using a charge equalization approach, the total charge before changing the position of the switches 16 and 18 is equal to the total charge after changing the position of the switches 16 and 18:



  
    
      
        Q
        T
      
      =
      
        
          VC
          f
        
        =
        
          
            V
            RDAC
          
          ⁢
          
            C
            1
          
        
      
    
    ;
  




  
    V
    =
    
      
        V
        RDAC
      
      ⁢
      
        
          
            C
            1
          
          
            C
            f
          
        
        .
      
    
  



The value of Cf can be set equal to C1, C2, C3 and C4 or be used to scale the output voltage and not be equal to C1, C2, C3 and C4. In the example above,





  
    V
    RDAC
  
  =
  
    
      3
      4
    
    ⁢
    
      
        V
        ref
      
      .
    
  




As can be appreciated, the value can also be adjusted to




  
    
      
        V
        RDAC
      
      =
      0
    
    ,
    
      
        V
        RDAC
      
      =
      
        
          1
          4
        
        ⁢
        
          V
          ref
        
      
    
    ,
    
      

    
    ⁢
    or
  




  
    
      V
      RDAC
    
    =
    
      
        1
        2
      
      ⁢
      
        V
        ref
      
    
  



by selecting the switch SW1LSB, SW2LSB or SW3LSB, respectively. Scaling can be performed by adjusting the value of Cf relative to C1, C2, C3 and C4. For example, if Cf=C1+C2+C3+C4, then the output ranges 0 to near Vref rather than 0 to near 4 Vref in this example.

Referring now to FIG. 4C, a truth table for the exemplary converter of FIG. 3B is shown. In this example, Cf is equal to C1, C2, C3 and C4 although other values may be used for scaling. Referring now to FIG. 4D, a truth table for the exemplary converter of FIG. 3C is shown.
Referring now to FIG. 5, the D/A converter of FIG. 3B is shown during an integrating phase for a second digital value (0111). Initially, the switch 16 is closed, the switch 18 is opened and the capacitors C3 and C4 are switched by respective switches to the reference potential, which may be ground. The capacitor C2 is connected to the common node 130 and the capacitor C1 is connected to Vref. The capacitive portion 110 will be in this configuration when the desired binary value is between 0100 and 0111. One of the resistive switches SW4LSB, SW3LSB, SW2LSB, and SW1LSB is closed to create a voltage divider. In the example shown in FIG. 5, the switch SW4LSB is closed to provide




  
    3
    4
  
  ⁢
  
    
      V
      ref
    
    .
  




A charge is accumulated on the capacitor C2 that is equal to VRDACC2, where VRDAC is the voltage provided by the resistive portion. A charge is also accumulated on capacitor C1 equal to VrefC1.

During an integrating phase for the second digital value (0111) the switch 16 is opened, the switch 18 is closed and the voltage value is applied to the amplifier 20. Using a charge equalization approach, the total charge before changing the position of the switches 16 and 18 is equal to the total charge after changing the position of the switches 16 and 18:



  
    
      
        Q
        T
      
      =
      
        
          VC
          f
        
        =
        
          
            
              V
              RDAC
            
            ⁢
            
              C
              2
            
          
          +
          
            
              V
              ref
            
            ⁢
            
              C
              1
            
          
        
      
    
    ;
  




  
    V
    =
    
      
        
          V
          RDAC
        
        ⁢
        
          
            C
            2
          
          
            C
            f
          
        
      
      +
      
        
          V
          ref
        
        ⁢
        
          
            
              C
              1
            
            
              C
              f
            
          
          .
        
      
    
  



The value of Cf can be set equal to C1, C2, C3 and C4 or be used to scale the output voltage and not be equal to C1, C2, C3 and C4. If Cf, C1 and C2 are the same, V=VRDAC+Vref.

Referring now to FIG. 6, the D/A converter of FIG. 3B is shown during an integrating phase for a third digital value (1011). Initially, the switch 16 is closed, the switch 18 is opened and the capacitor C4 is switched by a respective switch to the reference potential, which may be ground. The capacitor C3 is connected to the common node 130 and the capacitors C1 and C2 are connected to Vref. The capacitive portion 110 will be in this configuration when the desired binary value is between 1000 and 1011. One of the resistive switches SW4LSB, SW3LSB, SW2LSB, and SW1LSB is closed to create a voltage divider. In the example shown in FIG. 6, the switch SW4LSB is closed to provide




  
    3
    4
  
  ⁢
  
    
      V
      ref
    
    .
  




A charge is accumulated on the capacitor C3 that is equal to VRDACC3, where VRDAC is the voltage provided by the resistive portion. A charge is also accumulated on capacitors C1 and C2 that is equal to Vref(C1+C2).

During an integrating phase for the third digital value (1011) the switch 16 is opened, the switch 18 is closed and the voltage value is applied to the amplifier 20. Using a charge equalization approach, the total charge before changing the position of the switches 16 and 18 is equal to the total charge after changing the position of the switches 16 and 18:



  
    
      
        Q
        T
      
      =
      
        
          VC
          f
        
        =
        
          
            
              V
              RDAC
            
            ⁢
            
              C
              3
            
          
          +
          
            
              V
              ref
            
            ⁡
            
              (
              
                
                  C
                  1
                
                +
                
                  C
                  2
                
              
              )
            
          
        
      
    
    ;
  




  
    V
    =
    
      
        
          V
          RDAC
        
        ⁢
        
          
            C
            3
          
          
            C
            f
          
        
      
      +
      
        
          V
          ref
        
        ⁢
        
          
            
              
                C
                1
              
              +
              
                C
                3
              
            
            
              C
              f
            
          
          .
        
      
    
  



The value of Cf can be set equal to C1, C2, C3 and C4 or be used to scale the output voltage and not be equal to C1, C2, C3 and C4. If Cf, C1, C2 and C3 are the same, V=VRDAC+2Vref.

Referring now to FIG. 7, the D/A converter of FIG. 3B is shown during an integrating phase for a third digital value (1111). Initially, the switch 16 is closed and the switch 18 is opened. The capacitor C4 is connected to the common node 130 and the capacitors C1, C2 and C3 are connected to Vref. The capacitive portion 110 will be in this configuration when the desired binary value is between 1100 and 1111. One of the resistive switches SW4LSB, SW3LSB, SW2LSB, and SW1LSB is closed to create a voltage divider. In the example shown in FIG. 7, the switch SW4LSB is closed to provide




  
    3
    4
  
  ⁢
  
    
      V
      ref
    
    .
  




A charge is accumulated on the capacitor C4 that is equal to VRDACC4, where VRDAC is the voltage provided by the resistive portion. A charge is accumulated on capacitors C1, C2 and C3 that is equal to Vref(C1+C2+C3).

During an integrating phase for the fourth digital value (1111) the switch 16 is opened, the switch 18 is closed and the voltage value is applied to the amplifier 20. Using a charge equalization approach, the total charge before changing the position of the switches 16 and 18 is equal to the total charge after changing the position of the switches 16 and 18:



  
    
      
        Q
        T
      
      =
      
        
          VC
          f
        
        =
        
          
            
              V
              RDAC
            
            ⁢
            
              C
              4
            
          
          +
          
            
              V
              ref
            
            ⁡
            
              (
              
                
                  C
                  1
                
                +
                
                  C
                  2
                
                +
                
                  C
                  3
                
              
              )
            
          
        
      
    
    ;
  




  
    V
    =
    
      
        
          V
          RDAC
        
        ⁢
        
          
            C
            4
          
          
            C
            f
          
        
      
      +
      
        
          V
          ref
        
        ⁢
        
          
            
              
                C
                1
              
              +
              
                C
                2
              
              +
              
                C
                3
              
            
            
              C
              f
            
          
          .
        
      
    
  



The value of Cf can be set equal to C1, C2, C3 and C4 or be used to scale the output voltage and not be equal to C1, C2, C3 and C4. If Cf, C1, C2, C3 and C4 are the same, V=VRDAC+3Vref.

Referring now to FIGS. 8A and 8B, a nested segmented capacitive-capacitive D/A converter 108 according to the present invention is shown. In FIG. 8A, the output circuit 102 is shown. In FIG. 8B, an exemplary sample and integrate configuration is shown. The capacitive portion 110 operates as described above. For purposes of clarity, the capacitors C1, C2, C3 and C4 have been relabeled C1M, C2M, C3M and C4M. A second capacitive portion 150 is associated with the two least significant bits and includes capacitors C1L, C2L, C3L and C4L. The voltage provided by the LSB capacitive portion 150 is VCDAC. The second capacitive portion 150 also has a sampling and integrating phase as will be described below.
Referring now to FIGS. 8C and 8D, an equivalent circuit of the D/A converter of FIG. 8B during a sampling phase is shown for




  
    V
    CDAC
  
  =
  
    
      
        V
        ref
      
      4
    
    .
  




During sampling phase, the switch 152 is closed and the capacitors C4L, C3L and C2L are connected to a reference potential such as ground. The capacitor C1L is charged to Vref. A charge is accumulated on the capacitor C1L that is equal to VrefC1L.

During the integrating phase, the switch 152 is opened and the capacitors C4L, C3L, C2L and C1L are connected in feedback. The total charge before the switch 152 is opened is the same as the total charge after the switch 152 is opened. Therefore:



  
    
      
        Q
        T
      
      =
      
        
          VC
          T
        
        =
        
          
            
              V
              ref
            
            ⁢
            
              C
              
                1
                ⁢
                L
              
            
          
          =
          
            V
            ⁡
            
              (
              
                
                  C
                  
                    1
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    2
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    3
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    4
                    ⁢
                    L
                  
                
              
              )
            
          
        
      
    
    ;
  




  
    V
    =
    
      
        V
        ref
      
      ⁢
      
        
          
            C
            
              1
              ⁢
              L
            
          
          
            
              C
              
                1
                ⁢
                L
              
            
            +
            
              C
              
                2
                ⁢
                L
              
            
            +
            
              C
              
                3
                ⁢
                L
              
            
            +
            
              C
              
                4
                ⁢
                L
              
            
          
        
        .
      
    
  



Assuming that C1L, C2L, C3L and C4L are equal,





  V
  =
  
    
      
        V
        ref
      
      4
    
    .
  




Referring now to FIG. 8E, an equivalent circuit of the D/A converter of FIG. 8B during a sampling phase is shown for




  
    V
    CDAC
  
  =
  
    
      
        V
        ref
      
      2
    
    .
  




During sampling phase, the switch 152 is closed and the capacitors C4L and C3L are connected to a reference potential such as ground. The capacitors C1L and C2L are charged to Vref. A charge is accumulated on the capacitors C1L and C2L that is equal to Vref(C1L+C2L).

During the integrating phase, the switch 152 is opened and the capacitors C4L, C3L, C2L and C1L are connected in feedback. The total charge before the switch 152 is opened is the same as the total charge after the switch 152 is opened. Therefore:



  
    
      
        Q
        T
      
      =
      
        
          VC
          T
        
        =
        
          
            
              V
              ref
            
            ⁡
            
              (
              
                
                  C
                  
                    1
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    2
                    ⁢
                    L
                  
                
              
              )
            
          
          =
          
            V
            ⁡
            
              (
              
                
                  C
                  
                    1
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    2
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    3
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    4
                    ⁢
                    L
                  
                
              
              )
            
          
        
      
    
    ;
  




  
    V
    =
    
      
        V
        ref
      
      ⁢
      
        
          
            
              C
              
                1
                ⁢
                L
              
            
            +
            
              C
              
                2
                ⁢
                L
              
            
          
          
            (
            
              
                C
                
                  1
                  ⁢
                  L
                
              
              +
              
                C
                
                  2
                  ⁢
                  L
                
              
              +
              
                C
                
                  3
                  ⁢
                  L
                
              
              +
              
                C
                
                  4
                  ⁢
                  L
                
              
            
            )
          
        
        .
      
    
  



Assuming that C1, C2, C3 and C4 are equal,





  V
  =
  
    
      
        V
        ref
      
      2
    
    .
  




Referring now to FIG. 8F, an equivalent circuit of the D/A converter of FIG. 8B during a sampling phase is shown for




  
    V
    CDAC
  
  =
  
    
      
        3
        ⁢
        
          V
          ref
        
      
      4
    
    .
  




During sampling phase, the switch 152 is closed and the capacitor C4L is connected to a reference potential such as ground. The capacitors C1L, C2L and C3L are charged to Vref. A charge is accumulated on the capacitors C1L, C2L and C3L that is equal to Vref(C1L+C2L+C3L).

During the integrating phase, the switch 152 is opened and the capacitors C4L, C3L, C2L and C1L are connected in feedback. The total charge before the switch 152 is opened is the same as the total charge after the switch 152 is opened. Therefore:



  
    
      
        Q
        T
      
      =
      
        
          VC
          T
        
        =
        
          
            
              V
              ref
            
            ⁡
            
              (
              
                
                  C
                  
                    1
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    2
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    3
                    ⁢
                    L
                  
                
              
              )
            
          
          =
          
            V
            ⁡
            
              (
              
                
                  C
                  
                    1
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    2
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    3
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    4
                    ⁢
                    L
                  
                
              
              )
            
          
        
      
    
    ;
  




  
    V
    =
    
      
        V
        ref
      
      ⁢
      
        
          
            
              C
              
                1
                ⁢
                L
              
            
            +
            
              C
              
                2
                ⁢
                L
              
            
            +
            
              C
              
                3
                ⁢
                L
              
            
          
          
            (
            
              
                C
                
                  1
                  ⁢
                  L
                
              
              +
              
                C
                
                  2
                  ⁢
                  L
                
              
              +
              
                C
                
                  3
                  ⁢
                  L
                
              
              +
              
                C
                
                  4
                  ⁢
                  L
                
              
            
            )
          
        
        .
      
    
  



Assuming that C1L, C2L, C3L and C4L are equal,





  V
  =
  
    
      
        3
        ⁢
        
          V
          ref
        
      
      4
    
    .
  




Referring now to FIG. 8G, an equivalent circuit of the D/A converter of FIG. 8B during a sampling phase is shown for VCDAC=Vref. The switch associated with this position may be omitted since this value can be already be obtained by using the next MSB. In this case one of the capacitors may always be connected to ground. If a switch is used, during sampling phase the switch 152 is closed and the capacitors C1L, C2L, C3L and C4L are charged to Vref. A charge is accumulated on the capacitors C1L, C2L, C3L and C4L that is equal to Vref(C1L+C2L+C3L+C4L).
During the integrating phase, the switch 152 is opened and the capacitors C4L, C3L, C2L and C1L are connected in feedback. The total charge before the switch 152 is opened is the same as the total charge after the switch 152 is opened. Therefore:



  
    
      
        Q
        T
      
      =
      
        
          VC
          T
        
        =
        
          
            
              V
              ref
            
            ⁢
            
              (
              
                
                  C
                  
                    1
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    2
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    3
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    4
                    ⁢
                    L
                  
                
              
              )
            
          
          =
          
            V
            ⁡
            
              (
              
                
                  C
                  
                    1
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    2
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    3
                    ⁢
                    L
                  
                
                +
                
                  C
                  
                    4
                    ⁢
                    L
                  
                
              
              )
            
          
        
      
    
    ;
  




  
    V
    =
    
      
        V
        ref
      
      ⁢
      
        
          
            
              C
              
                1
                ⁢
                L
              
            
            +
            
              C
              
                2
                ⁢
                L
              
            
            +
            
              C
              
                3
                ⁢
                L
              
            
            +
            
              C
              
                4
                ⁢
                L
              
            
          
          
            (
            
              
                C
                
                  1
                  ⁢
                  L
                
              
              +
              
                C
                
                  2
                  ⁢
                  L
                
              
              +
              
                C
                
                  3
                  ⁢
                  L
                
              
              +
              
                C
                
                  4
                  ⁢
                  L
                
              
            
            )
          
        
        .
      
    
  



Assuming that C1L, C2L, C3L and C4L are equal, V=Vref.
Referring now to FIGS. 8H and 8I, non-overlapping and overlapping timing diagrams are shown for sampling and integrating phases for LSB and MSB capacitive portions. The timing of the sampling and integrating phases can be non-overlapping as shown in FIG. 8H. Alternately, the sampling phase of the LSB capacitive portion can fully and/or partially overlap the integrating phase of the MSB capacitive portion as shown in FIG. 8I.
Referring now to FIG. 8J, a truth table for the D/A converter is shown. As can be appreciated, the LSB switches can be connected in feedback and/or to ground during the MSB-integrating phase and/or can begin the next LSB sampling phase as described herein.
Referring now to FIG. 9A-9D, additional capacitive and/or resistive DAC portions may be added. In FIG. 9A, an N stage capacitive D/A converter 170 is shown. The converter 170 includes capacitive portions BG1, BG2, . . . , and BGX, which are associated with LSB, next LSB, . . . , and MSB groups. For example, a 6 bit example can include capacitive portions BG1, BG2 and BG3. Each capacitive portion may include four capacitors as shown and described above. Each of the capacitive portions includes sampling and integrating stages that may be non-overlapping and/or overlapping as described above and below.
In FIG. 9B, an N stage capacitive-resistive D/A converter 180 is shown. One or more of the last stages is a resistive portion as described above. In this example, there are X-Y capacitive portions and Y resistive portions, where X and Y are integers greater than zero. When resistive portions are used, the sampling and integrating phases for the last capacitive stage and the final resistive stage can be the same as described above. In FIG. 9C, an exemplary timing diagram shows non-overlapping sampling and integrating phases for additional capacitive stages. In FIG. 9D, an exemplary timing diagram showing fully and/or partially overlapping sampling and integrating phases for additional capacitive stages is shown.
Referring now to FIG. 10, a successive approximation A/D converter 200 is shown. The converter 200 includes a successive approximation register (SAR) 204 or module that contains logic for resolving the digital bits as will be described further below. An output of the SAR 204 is input to decoder module 209 that may include a modified thermometer decoder 210 that communicates with and controls switches SW4MSB, SW3MSB, SW2MSB, and SW1MSB based on MSBs of the output of the SAR. An output of the SAR 204 is input to a thermometer decoder 220 that communicates with and controls switches SW4LSB, SW3LSB, SW2LSB, and SW1LSB based on LSBs in the output of the SAR 204.
During acquisition, the switch 16 is connected to ground. Ends of the capacitors are connected by switches SWMSB to Vin. After acquisition of Vin, the switch 16 is opened and the capacitors are disconnected by switches SWMSB from Vin. The capacitor array is charged with a voltage based on Vin. The capacitors are then connected to ground by switches SWMSB, which drives the common terminal negative to a voltage equal to −Vin.
As the first step in a binary search algorithm, the capacitive and resistive portions are configured to provide 1⁄2Vref as described above. In other words, C4M is connected to the common node, C3M, C2M and C1M are connected to Vref and the switch SW1LSB is closed. For example, if Vin is equal to 3/4Vref, the common terminal will be driven to (−3⁄4Vref+1⁄2Vref)=−1⁄4Vref. When this voltage is compared to ground, the output of the comparator 20 yields a logic ‘1’, implying that Vin is greater than 1⁄2Vref. If Vin is equal to 1⁄4Vref, the common terminal voltage is (−1⁄4Vref+1⁄2Vref)=+1/4Vref, and the output of the comparator 20 is a logic ‘0’. This process continues with the next MSB or LSB depending upon the value of the comparator output until all bits are resolved. While capacitive-resistive implementation is shown, capacitive-capacitive, N-stage capacitive or N-stage capacitive-resistive implementations are also contemplated.
Referring now to FIG. 11A, a pipelined A/D converter 250 is shown. The converter 250 includes a plurality of stages 252-1, 252-2, 252-3 (collectively 252) that are cascaded in series. Each of the course A/D converter stages 252 includes a sample and hold module 254 that samples and holds the analog output signal from a prior stage, a low resolution A/D subconverter module 256 that converts the held analog signal, a low-resolution D/A subconverter module 258 that converts the resulting digital output back into an analog representation, a difference module 260 and an analog interstage difference amplifier module 262 that amplifies the residue. The residue is the difference between the held analog signal and the reconstructed analog signal.
The first stage 252-1 of the pipelined A/D converter 250 operates on a most current analog input sample while the second stage 252-2 operates on the amplified residue of the previous input sample. The concurrency of operations results in a conversion speed that is determined only by the time it takes in one stage.
Referring now to FIG. 11B-11D, ideal and non-ideal residue voltages are shown. In FIG. 11B, an ideal residue voltage is shown. When the input reaches a first decision level of the AND subconverter module 252, the output of the subconverter module switches to its next higher level code causing the output of the D/A subconverter to switch to its next higher level. This in turn causes the amplified residue to drop back to zero.
In actual implementations, however, the components are not ideal and non-uniformity occurs. In FIG. 11C, the residue voltage exceeds the ideal value by a fixed amount. In FIG. 11D, the residue voltage exceeds the ideal residue voltage by a variable amount.
Referring now to FIG. 12A, an analog to digital converter 300 that generates a residue voltage with lower variation according to the present invention is shown. Capacitors C1, C2, C3 and C4 are selectively connected to Vin, a reference potential such as ground, a voltage reference (Vref) and to an output of the opamp 20. In some implementations, C1, C2, C3 and C4 have substantially equal capacitance values.
Referring now to FIGS. 12B-12D, the analog to digital converter of FIG. 12A is shown further. In a sampling phase in FIG. 12B, the switch 16 is closed and the capacitors are connected to Vin. In a residue amplification stage in FIG. 12B for Vin between 0 and




  
    
      C
      1
    
    
      
        C
        1
      
      +
      
        C
        2
      
      +
      
        C
        3
      
      +
      
        C
        4
      
    
  
  ⁢
  
    V
    ref
  




(“A” in FIG. 12D), the switch 16 is opened, the capacitor C1 is connected in feedback arrangement. The capacitors C2, C3, and C4 are connected to the reference potential. A truth table is shown in FIG. 12D.

Referring now to FIG. 13, in a residue amplification stage for Vin between



  
    
      
        C
        1
      
      
        
          C
          1
        
        +
        
          C
          2
        
        +
        
          C
          3
        
        +
        
          C
          4
        
      
    
    ⁢
    
      V
      ref
    
  




  and




  
    
      
        
          C
          1
        
        +
        
          C
          2
        
      
      
        
          C
          1
        
        +
        
          C
          2
        
        +
        
          C
          3
        
        +
        
          C
          4
        
      
    
    ⁢
    
      V
      ref
    
  



(“B” in FIG. 12D), the switch 16 is opened, the capacitor C2 is connected in feedback arrangement and the capacitor C1 is connected to Vref. The capacitors C3 and C4 are connected to a reference potential.

Referring now to FIG. 14, in a residue amplification stage for Vin between



  
    
      
        
          C
          1
        
        +
        
          C
          2
        
      
      
        
          C
          1
        
        +
        
          C
          2
        
        +
        
          C
          3
        
        +
        
          C
          4
        
      
    
    ⁢
    
      V
      ref
    
  




  and




  
    
      
        
          C
          1
        
        +
        
          C
          2
        
        +
        
          C
          3
        
      
      
        
          C
          1
        
        +
        
          C
          2
        
        +
        
          C
          3
        
        +
        
          C
          4
        
      
    
    ⁢
    
      V
      ref
    
  



(“C” in FIG. 12D), the switch 16 is opened, the capacitor C3 is connected in feedback arrangement and the capacitors C1 and C2 are connected to Vref. The capacitor C4 is connected to a reference potential.

Referring now to FIGS. 15 and 16, in a residue amplification stage for Vin between




  
    
      
        C
        1
      
      +
      
        C
        2
      
      +
      
        C
        3
      
    
    
      
        C
        1
      
      +
      
        C
        2
      
      +
      
        C
        3
      
      +
      
        C
        4
      
    
  
  ⁢
  
    V
    ref
  




and Vref (“D” in FIG. 12D), the switch 16 is opened, the capacitor C4 is connected in feedback arrangement and the capacitors C1, C2 and C3 are connected to Vref. Note that because the different capacitors are used as the feedback capacitor during residue amplification, the residue gain can perfectly track the capacitor mismatch. The residue voltage now looks as shown in FIG. 16. There is a variable inter-stage gain and a substantially constant maximum residue voltage.

Referring now to FIGS. 17A-17G, various exemplary implementations of the present invention are shown. Referring now to FIG. 17A, the present invention can be implemented in D/A or A/D converters in a hard disk drive 400. In some implementations, the signal processing and/or control circuit 402 and/or other circuits (not shown) in the HDD 400 may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a magnetic storage medium 406.
The HDD 400 may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links 408. The HDD 400 may be connected to memory 409 such as random access memory (RAM), low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.
Referring now to FIG. 17B, the present invention can be implemented in D/A or A/D converters in a digital versatile disc (DVD) drive 410. The signal processing and/or control circuit 412 and/or other circuits (not shown) in the DVD 410 may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium 416. In some implementations, the signal processing and/or control circuit 412 and/or other circuits (not shown) in the DVD 410 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.
The DVD drive 410 may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links 417. The DVD 410 may communicate with mass data storage 418 that stores data in a nonvolatile manner. The mass data storage 418 may include a hard disk drive (HDD). The HDD may have the configuration shown in FIG. 17A. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′. The DVD 410 may be connected to memory 419 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
Referring now to FIG. 17C, the present invention can be implemented in D/A or A/D converters in a high definition television (HDTV) 420. The HDTV 420 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 426. In some implementations, signal processing circuit and/or control circuit 422 and/or other circuits (not shown) of the HDTV 420 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.
The HDTV 420 may communicate with mass data storage 427 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in FIG. 17A and/or at least one DVD may have the configuration shown in FIG. 17B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′. The HDTV 420 may be connected to memory 428 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The HDTV 420 also may support connections with a WLAN via a WLAN network interface 429.
Referring now to FIG. 17D, the present invention may implement and/or be implemented in D/A or A/D converters in a control system of a vehicle 430, a WLAN interface, mass data storage of the vehicle control system and/or a power supply 433. In some implementations, the present invention implement a powertrain control system 432 that receives inputs from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals.
The present invention may also be implemented in other control systems 440 of the vehicle 430. The control system 440 may likewise receive signals from input sensors 442 and/or output control signals to one or more output devices 444. In some implementations, the control system 440 may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated.
The powertrain control system 432 may communicate with mass data storage 446 that stores data in a nonvolatile manner. The mass data storage 446 may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 17A and/or at least one DVD may have the configuration shown in FIG. 17B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′. The powertrain control system 432 may be connected to memory 447 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The powertrain control system 432 also may support connections with a WLAN via a WLAN network interface 448. The control system 440 may also include mass data storage, memory and/or a WLAN interface (all not shown).
Referring now to FIG. 17E, the present invention can be implemented in D/A or A/D converters in a cellular phone 450 that may include a cellular antenna 451. In some implementations, the cellular phone 450 includes a microphone 456, an audio output 458 such as a speaker and/or audio output jack, a display 460 and/or an input device 462 such as a keypad, pointing device, voice actuation and/or other input device. The signal processing and/or control circuits 452 and/or other circuits (not shown) in the cellular phone 450 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular phone functions.
The cellular phone 450 may communicate with mass data storage 464 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 17A and/or at least one DVD may have the configuration shown in FIG. 17B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′. The cellular phone 450 may be connected to memory 466 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The cellular phone 450 also may support connections with a WLAN via a WLAN network interface 468.
Referring now to FIG. 17F, the present invention can be implemented in D/A or A/D converters in a set top box 480. The set top box 480 receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 488 such as a television and/or monitor and/or other video and/or audio output devices. The signal processing and/or control circuits 484 and/or other circuits (not shown) of the set top box 480 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.
The set top box 480 may communicate with mass data storage 490 that stores data in a nonvolatile manner. The mass data storage 490 may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 17A and/or at least one DVD may have the configuration shown in FIG. 17B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′. The set top box 480 may be connected to memory 494 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The set top box 480 also may support connections with a WLAN via a WLAN network interface 496.
Referring now to FIG. 17G, the present invention can be implemented in D/A or A/D converters in a media player 500. In some implementations, the media player 500 includes a display 507 and/or a user input 508 such as a keypad, touchpad and the like. In some implementations, the media player 500 may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via the display 507 and/or user input 508. The media player 500 further includes an audio output 509 such as a speaker and/or audio output jack. The signal processing and/or control circuits 504 and/or other circuits (not shown) of the media player 500 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.
The media player 500 may communicate with mass data storage 510 that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 17A and/or at least one DVD may have the configuration shown in FIG. 17B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′. The media player 500 may be connected to memory 514 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The media player 500 also may support connections with a WLAN via a WLAN network interface 516. Still other implementations in addition to those described above are contemplated.
Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.

## Claims

1. A pipelined analog-to-digital converter (ADC) comprising:
a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC) that includes:
an amplifier having an input and an output;
N capacitances that are connected in parallel and that include first ends that selectively communicate with said input of said amplifier and second ends;
N switches that selectively connect said second ends of said N capacitances to said voltage input during a first phase, one of said second ends of said N capacitances to said output of said amplifier during a second phase, and others of said second ends of said N capacitances to one of a voltage reference and a reference potential during said second phase, wherein each of said second ends of said N capacitances is selectively connectable to said output of said amplifier; and

a second stage that communicates with said output said amplifier.

2. The pipelined ADC of claim 1 wherein said first phase is a sampling phase and wherein said second phase is a residue amplification phase.

3. The pipelined ADC of claim 1 wherein capacitance values of said N capacitances are substantially equal.

4. A pipelined analog-to-digital converter (ADC) comprising:
a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC) that includes:
an amplifier having an input and an output;
N capacitances that are connected in parallel and that include first ends that selectively communicate with said input of said amplifier and second ends;
N switches that selectively connect said second ends of said N capacitances to said voltage input during a first phase, one of said second ends of said N capacitances to said output of said amplifier during a second phase, and others of said second ends of said N capacitances to one of a voltage reference and a reference potential during said second phase; and

a second stage that communicates with said output said amplifier,
wherein when said input voltage is between zero and a first ratio of a first of said N capacitances divided by a sum of said N capacitances, said first of said N capacitances is connected to said output of said amplifier and others of said N capacitances are connected to said reference potential during said second phase.

5. The pipelined ADC of claim 4 wherein when said input voltage is between said first ratio and a second ratio of a sum of said first and a second of said N capacitances divided by a sum of said N capacitances, said first of said N capacitances is connected to said voltage reference, said second of said N capacitances is connected to said output of said amplifier and others of said N capacitances are connected to said reference potential during said second phase.

6. The pipelined ADC of claim 5 wherein when said input voltage is between said second ratio and a third ratio of a sum of said first, said second and a third of said N capacitances divided by a sum of said N capacitances, said first and said second of said N capacitances are connected to said voltage reference, said third of said N capacitances is connected to said output of said amplifier and others of said N capacitances are connected to said reference potential during said second phase.

7. A pipelined analog-to-digital converter (ADC) comprising:
first stage means for receiving an input voltage signal and that comprises converting means for converting signals that includes:
amplifying means for amplifying and having an input and an output;
N capacitance means for providing capacitance, that are connected in parallel and that include first ends that selectively communicate with said input of said amplifying means and second ends; and
N switching means for selectively connecting said second ends of said N capacitance means to said voltage input during a first phase, one of said second ends of said N capacitance means to said output of said amplifying means during a second phase, and others of said second ends of said N capacitance means to one of a voltage reference and a reference potential during said second phase, wherein each of said second ends of said N capacitance means is selectively connectable to said output of said amplifier; and

second stage means for communicating with said output of said amplifying means of said first stage means.

8. The pipelined ADC of claim 7 wherein said first phase is a sampling phase and wherein said second phase is a residue amplification phase.

9. The pipelined ADC of claim 7 wherein capacitance values of said N capacitance means are substantially equal.

10. A pipelined analog-to-digital converter (ADC) comprising:
first stage means for receiving an input voltage signal and that comprises converting means for converting signals that includes:
amplifying means for amplifying and having an input and an output;
N capacitance means for providing capacitance, that are connected in parallel and that include first ends that selectively communicate with said input of said amplifying means and second ends; and
N switching means for selectively connecting said second ends of said N capacitance means to said voltage input during a first phase, one of said second ends of said N capacitance means to said output of said amplifying means during a second phase, and others of said second ends of said N capacitance means to one of a voltage reference and a reference potential during said second phase; and

second stage means for communicating with said output of said amplifying means of said first stage means,
wherein when said input voltage is between zero and a first ratio of a first of said N capacitances divided by a sum of said N capacitances, said N switching means connect said first of said N capacitances to said output of said amplifier and others of said N capacitances to said reference potential during said second phase.

11. The pipelined ADC of claim 10 wherein when said input voltage is between said first ratio and a second ratio of a sum of said first and a second of said N capacitances divided by a sum of said N capacitances, said N switching means connect said first of said N capacitances to said voltage reference, said second of said N capacitances to said output of said amplifier and others of said N capacitances to said reference potential during said second phase.

12. The pipelined ADC of claim 11 wherein when said input voltage is between said second ratio and a third ratio of a sum of said first, said second and a third of said N capacitances divided by a sum of said N capacitances, said N switching means connect said first and said second of said N capacitances to said voltage reference, said third of said N capacitances to said output of said amplifier and others of said N capacitances to said reference potential during said second phase.

13. A method for generating a residue voltage in a pipelined analog-to-digital converter (ADC) comprising:
providing first and second stages, wherein said first stage receives a voltage input and includes a capacitive ADC including N capacitances;
selectively connecting said second ends of said N capacitances to said voltage input during a first phase;
selectively connecting one of said second ends of said N capacitances to said output of said amplifier during a second phase, wherein each of said second ends of said N capacitances is selectively connectable to said output of said amplifier;
selectively connecting others of said second ends of said N capacitances to one of a voltage reference and a reference potential during said second phase;
selectively connecting said first ends of said N capacitances to an amplifier input; and
connecting an amplifier output to said second stage.

14. The method of claim 13 wherein said first phase is a sampling phase and wherein said second phase is a residue amplification phase.

15. The method of claim 13 further comprising selecting capacitance values of said N capacitances to be substantially equal.

16. A method for generating a residue voltage in a pipelined analog-to-digital converter (ADC) comprising:
providing first and second stages, wherein said first stage receives a voltage input and includes a capacitive ADC including N capacitances;
selectively connecting said second ends of said N capacitances to said voltage input during a first phase;
selectively connecting one of said second ends of said N capacitances to said output of said amplifier during a second phase;
selectively connecting others of said second ends of said N capacitances to one of a voltage reference and a reference potential during said second phase;
selectively connecting said first ends of said N capacitances to an amplifier input;
connecting an amplifier output to said second stage; and
selectively connecting said first of said N capacitances to said output of said amplifier and others of said N capacitances to said reference potential during said second phase when said input voltage is between zero and a first ratio of a first of said N capacitances divided by a sum of said N capacitances.

17. The method of claim 16 further comprising selectively connecting said first of said N capacitances to said voltage reference, said second of said N capacitances to said output of said amplifier and others of said N capacitances to said reference potential during said second phase when said input voltage is between said first ratio and a second ratio of a sum of said first and a second of said N capacitances divided by a sum of said N capacitances.

18. The method of claim 17 further comprising selectively connecting said first and said second of said N capacitances to said voltage reference, said third of said N capacitances to said output of said amplifier and others of said N capacitances to said reference potential during said second phase when said input voltage is between said second ratio and a third ratio of a sum of said first, said second and a third of said N capacitances divided by a sum of said N capacitances.