UNITED STATES


 


A wafer-based monocrystalline silicon photovoltaics
road map: Utilizing 

known technology improvement opportunities for further reductions in 

manufacturing costs

Solar Energy Materials & Solar Cells 114 (2013) 110-135


 


 


Article referenced as support for the following sections:


 


Page 46: Paragraph on Black Silicon






Solar Energy Materials & Solar Cells 114 (2013)
110–135


	
  

 	
  

 	
  

 	
  

 	
  

 
	 

 	 

 	 

 	 

 	 

 
	
  

 	
  

 	
  

 	
  

 	
  

 
	
 

 	
  

 	
 Contents lists available at
 SciVerse ScienceDirect

 

 Solar
 Energy Materials & Solar Cells

 

 journal homepage: www.elsevier.com/locate/solmat

 	
  

 	
 

 
	
  

 	
  

 	
  

 	
  

 	
  

 
	 

 	 

 	 

 	 

 	 

 



A wafer-based
monocrystalline silicon photovoltaics road map: Utilizing known technology
improvement opportunities for further reductions in manufacturing costs


Alan Goodrich*, Peter Hacke,
Qi Wang, Bhushan Sopori, Robert Margolis, Ted L. James, Michael Woodhouse**


The National Renewable Energy Laboratory, Golden, CO USA


	
  

 	
  

 	
  

 
	
 ARTICLE
 INFO

 	
  

 	
 ABSTRACT

 
	 

 	
  

 	 

 
	
 Article history:

 Received 20 July 2012

 Received in revised form

 10 January 2013

 Accepted 22 January 2013

 Available online 9 April
 2013                       

 

 Keywords:

 Crystalline silicon

 Photovoltaics

 Solar energy

 Economics

 	
  

 	
 As
 an initial investigation into the current and potential economics of one of
 today’s most widely deployed photovoltaic technologies, we have engaged in a
 detailed analysis of manufacturing costs for each step within the wafer-based
 monocrystalline silicon (c-Si) PV module supply chain. At each step we find
 several pathways that could lead to further reductions in manufacturing
 costs. After aggregating the performance and cost considerations for a series
 of known technical improvement opportunities, we project a pathway for
 commercial-production c-Si modules to have typical sunlight power conversion
 efficiencies of 19–23%, and we calculate that they might be sustainably sold
 at ex-factory gate prices of $0.60–$0.70 per peak Watt (DC power, current
 U.S. dollars).

           This
 may not be the lower bound to the cost curve for c-Si, however, because the
 roadmap described in this paper is constrained by the boundary conditions set
 by the wire sawing of wafers and their incorporation into manufacturing
 equipment that is currently being developed for commercial-scale production.
 Within these boundary conditions, we find that the benefit of reducing the
 wafer thickness from today’s standard 180 mm to the handling limit of 80 mm
 could be around $0.05 per peak Watt (Wp), when the calculation is
 run at minimum sustainable polysilicon prices (which we calculate to be
 around $23/kg). At that minimum sustainable polysilicon price, we also
 calculate that the benefit of completely eliminating or completely recycling
 kerf loss could be up to $0.08/Wp.

           These
 downward adjustments to the long run wafer price are used within the cost
 projections for three advanced cell architectures beyond today’s standard
 c-Si solar cell. Presumably, the higher efficiency cells that are profiled
 must be built upon a foundation of higher quality starting wafers. The
 prevailing conventional wisdom is that this should add cost at the ingot and
 wafering step—either due to lower production yields when having to sell
 wafers that are doped with an alternative element other than the standard
 choice of boron, or in additional capital equipment costs associated with
 removing problematic boron–oxygen pairs. However, from our survey it appears
 that there does not necessarily need to be an assumption of a higher wafer
 price if cell manufacturers should wish to use n-type wafers derived from the
 phosphorus dopant. And as for making p-type wafers with the traditional boron
 dopant, the potential price premium for higher lifetimes via the magnetic
 Czochralski approach is calculated to be very small, and can ostensibly be
 offset by the higher expected cell efficiencies that would result from using
 the higher quality wafers. With this final consideration, the projected
 minimum sustainable price requirements for three advanced c-Si solar cells
 are incorporated into a final bill of materials for a polysilicon-to-module
 manufacturing facility located within the United States.

 
	
  

 	
  

 	
 

 © 2013 Elsevier B.V. All rights reserved.

 
	 

 	
  

 	 


 



1. Introduction


With
average annual growth rates in excess of 40% over the past decade [1,2], the
success of the PV industry can largely be attributed to the steadfast growth of
wafer-based multicrystalline and monocrystalline silicon. This growth has been
sustained through a powerful combination of three critical competitive
advantages: (1) industry-leading full module area sunlight power conversion
efficiencies (to date, monocrystalline silicon continues to provide the highest
power conversion efficiency among all commercially demonstrated single junction
PV modules [3,4]); (2) product ‘bankability’ from the appropriately qualified
suppliers (with warranties for 80% of original performance after 25 years


_______________

* Corresponding author. Tel.: +1 303 275 4347.

** Corresponding author. Tel.: þ1 720 883 4973.

     E-mail addresses: Alan.Goodrich@nrel.gov (A.
Goodrich), 

Michael.Woodhouse@nrel.gov (M. Woodhouse).


0927-0248/$-see front matter ©
2013 Elsevier B.V. All rights reserved.
 http://dx.doi.org/10.1016/j.solmat.2013.01.030









	
  

 	
  

 
	
 A. Goodrichetal./Solar Energy Materials&Solar Cells
 114 (2013) 110–135

 	
 111

 





Fig. 1. The primary steps of the wafer-based c-Si module supply chain.


of
service now being standard [5]); and (3) a consistent ability to offer
competitively priced modules, which has been enabled through an ability to
realize cost reductions throughout the c-Si module supply chain (see Fig. 1).


          A
significant portion of these cost reductions have come about due to
‘economies-of-scale’ benefits [6]. But there is a point of diminishing returns
when trying to lower costs by simply expanding production capacity. For PV to
sustain its trajectory of cost reductions in both manufacturing and systems, it
will be increasingly important to implement innovations that enable higher
sunlight power conversion efficiencies [7]; and while the advanced cell
architectures needed to achieve these higher efficiencies require a greater
initial capital expenditure in the manufacturing equipment and starting
materials, sufficient gains in efficiency can oftentimes work to offset these
added costs. For wafer-based c-Si there are also multiple pathways to lower
costs further through reductions in the cost of producing the poly-silicon
feedstock, better silicon utilization in wafer fabrication, and through
advances in industrial cell and module assembly processes.


          Separate
from specific technology advancements, there are also pathways to lower future
costs if an industry-wide supply-demand equilibrium can be reached. The prices
for all materials within the supply chain could even approach their minimum
sustainable levels, at the point of a perfectly balanced equilibrium. Finally,
a ‘vertical integration’ strategy—where the buyers and sellers in the supply
chain are united into a single firm or consortium—can also assist in lowering
material transfer prices. Driven by differences in technology focus, regional
differences in electricity and labor rates, and its still small scale relative
to more mature industries, the supply chain for c-Si modules has historically
been comprised of distinct firms specializing in polysilicon feedstock, wafers,
cells or modules. Most recently, however, the vertical integration strategy has
come to play an increasingly evident role, because it can provide several
significant competitive advantages.


          The
principal advantage of global supply-demand equilibrium and the vertical
integration strategy is that they enable better control over the often
volatile, market-driven price demands of upstream suppliers. As an unambiguous
demonstration of this point, one can consider the recent trends and effects of
polysilicon prices. The average spot price that wafer manufacturers had to pay
for this material rapidly rose from around $200/kg in 2007 to highs around
$400/kg in 2008, principally because poly suppliers could readily command the
higher price (due, in no small part, to the sudden increase in demand from so
many rapidly emerging PV companies [8]). Since those times, new polysilicon
factories have come online at a frenetic pace, and the resulting current
oversupply situation has forced polysilicon suppliers to lower spot prices to
less than $20/kg within the past year [9]. Mean-while, global average c-Si
module prices have also recently taken a plunge—from around $4/W in 2008 to
less than $1/W today [10,11]. Given how important the decrease in the price for
poly has been to realizing those dramatic decreases in the total module price,
there is certainly a precedent that—for each player in the supply chain—minimum
sustainable transfer pricing could be one key strategy to survival in a game
that will be won or lost by pennies-per-watt.


          For
many, it seems compelling that PV can provide such valuable contributions to
the dual challenges of carbon mitigation and overall energy security. But, in
addition to the integration challenges associated with its intermittent nature,
there are also a number of economic barriers that must still be overcome before
there can be energy-significant Terawatts adoption levels. Primary among these
economic barriers is that, in most cases, PV is still an overall relatively
expensive choice for power generation.


          With
the recent drops in module and system prices, such economic barriers are
becoming that much less daunting. Under certain conditions (specifically, in
markets where there are high traditional fuel costs and relatively intense
solar irradiation levels), the barrier of a higher levelized cost for
generating electrical power from PV, in comparison to traditional power
generation sources, has even recently been jumped [11–14]. In looking forward,
to understand how PV might go on to become a compelling choice under other
conditions, it becomes necessary to understand just how it compares to the
incumbent energy systems in other applications and locations. With the general
paradigm being that PV must continue to reduce costs even further, in order to become
more economically competitive, it therefore becomes critical to understand just
how low the price for complete systems can be without compromising the
financial viability of all the different players that are involved.


          Though
it is beyond the scope of this paper to address total system costs, and to
suggest a final LCOE number, in the pages below we shall endeavor to derive the
lower limit in price for the module component of PV system costs—for the
specific case of c-Si modules made within the United States from
Czochralski-grown, wire-sawn wafers. For any complete product, its minimum
sustainable price is bound by the sum of the minimum sustainable prices for
every upstream material in the product’s supply chain. Conceptually speaking,
such a lower limit would only be realized once the supply-demand equilibrium
dictates that all materials be sold precisely at their minimum sustainable
prices. Assuming such a scenario, in this paper we shall show how the cost and
price requirements for c-Si modules could evolve over time, after detailing the
cost parameters associated with several representative technology ‘roadmaps’.
We begin with an overview of our modeling methodology, and describe the methods
and assumptions that are used for calculating the minimum sustainable prices of
each node within the c-Si module supply chain.


2. Methods for establishing the minimum sustainable product
prices


For
each of the primary steps within the c-Si supply chain, the structure of our
Microsoft Excel-based cost models is built around the process flow that would
be relevant to the manufacturing process being considered. These process flows
are based upon extensive literature surveys, internal discussions with NREL
researchers, visits to facilities already in place, and through extensive
collaborations with PV researchers and company representatives. With the
process flows in hand, we then aggregate the typical manufacturing cost
considerations for each underlying step, with data that is provided by several
industry collaborators that are involved at each step. These considerations
include the relevant materials and manufacturing equipment costs; operational
costs (which can be calculated after knowing the labor requirements for each
piece of equipment, material yield losses, the total cycle times for each step,
utilities costs, etc.); and the typical costs for financing the initial capital
expenditure in the land, building, and equipment [15]. The specific operational
costs of labor and electricity are









	
  

 	
  

 
	
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 A.Goodrichetal./Solar Energy Materials&Solar Cells 114
 (2013) 110–135

 


estimated
by applying national average rates [16] to the staffing and power requirements
provided by the relevant equipment vendors.


          After
considering the expected throughput, maintenance downtime, etc. for each piece
of equipment needed to execute the model process flow, the total capital
equipment needs are calculated to meet an annual production volume set to meet
the full economies-of-scale benefits for that specific node in the supply chain
(which is, by our analysis of costs as a function of production volume, around
15,000 metric tonnes per year for polysilicon production, tens of millions of
wafers per month in the pulling of ingots and wafering, and 500 MWp(DC)–2
GWp(DC) of annual production for cells and modules). In addition to
purchasing the capital equipment necessary to begin production, the other
upfront capital expenditure that must be included is the cost for the
manufacturing facility, including all of the buildings and land necessary for
housing the manufacturing project. We calculate these facilities-related
expenses in consultation with the equipment vendors and in consultation with
companies already engaged in the related manufacturing activities.


          After
deriving the total initial capital expenditure for the equipment and
facilities, the first derived cost metric of interest is the manufacturing
‘CapEx’, which is calculated by dividing the total initial capital expenditure
by the expected production volume of the model manufacturing facility. In this
way our CapEx costs are expressed on a dollars-per-kg (polysilicon),
dollars-per-area (wafers), or dollars-per-watt (cells and modules) basis.


          In
any typical manufacturing project, however, the total initial capital
expenditure can be shared over a certain length of time—a ‘depreciation
period’—that is set by country-specific tax codes and by an assumed rate of
technology obsolescence. In consideration of these factors, to represent the
averaged depreciation costs we allocate the total initial capital equipment
expenditure over a ten-year, straight-line depreciation schedule in polysilicon
and wafering; a five-year, straight-line schedule in cells; and a seven-year,
straight-line schedule in modules. The average annual depreciation expense for
the building is also calculated by allocating the initial capital expenditure
over a linear depreciation schedule, with an assumed period of 30 years. By
dividing these so-allocated depreciation expenditures by the specified
production volumes, we are then able to represent a second cost metric of
interest—the average depreciation cost—in the same units as the CapEx.


          Within
the final section of our Excel-based models we set up a pro forma discounted
cash flow (DCF) for the model manufacturing facility. The purpose of the DCF
is to provide the necessary framework for deriving the minimum sustainable
prices for each product within the supply chain. Within the DCF, we are able to
account for several additional considerations for manufacturing, such as
inflation and taxes; typical sales, general and administrative (SG & A)
expenses; typical research and development (R & D) expenses; and warranty
coverage [17]. Additionally, because it is a DCF, we have the option of
distributing the initial equipment and facilities expenditures over Modified
Accelerated Cost Recovery System (MACRS) depreciation schedules (with assumed
depreciation periods being the same as those given above for each respective
step in the supply chain). For each product in the c-Si supply chain, the
minimum sustainable price is then calculated on the basis of attaching a
minimum required margin, above the nominal cost of production, to satisfy the
returns on investment that would be required from both debt investors (such as
banks) and equity investors (such as globally-distributed stock-holders). With
the total length of the DCF set by the length of the assumed depreciation
schedule, and the discount rate calculated from these required rates of return,
the minimum sustainable product price is then derived by the iterative
algorithm within Excel called ‘goal seek’, which runs until the net present
value of the free cash flows equals the total initial capital expenditure.


          For
any given manufacturing firm, the required rate of return from investors is
usually derived after carrying out an assessment of the firm’s risk relative to
other investment opportunities. Such an assessment can even be quantified after
knowing the firm’s equity ‘beta’ (a measure of correlation between the
performance of the firm’s stock and the performance of a general global
investment index, such as Standard and Poor’s 500); and after knowing the
firm’s capital financing structure, which consists of both the book value of
debt (BVD) and the market value of equity (MVE). These
risk factors then influence the rates of return required for both debt
financing (KD) and for attracting equity financing (KE).
We use the international capital assets pricing model to derive these debt and
equity rates, and then, by weighting them by their relative contribution to the
overall capital structure of the firm, arrive at a weighted average cost of
capital (WACC) [18]





(1)


          Within
this expression, the ‘leverage ratio’ is the relative amount of debt (i.e., the
BVD/(BVD+MVE) term), and T is the corporate
income tax rate. This tax rate, and the host of risk factors that influence the
expected rates for debt and equity financing, is heavily dependent upon which
country hosts the manufacturing project. For the sake of brevity, within this
paper we limit the estimated WACC (Table 1), leverage ratios, and all other
representative PV manufacturing costs to what would be typical for
manufacturing within the United States, where the average effective corporate
tax rate for publicly traded, non-financial institutions is around 28% [19]. An
additional discussion of how these rates, leverage ratios, and taxes might vary
for an alternative manufacturing site is provided elsewhere [20,21].


          If
a firm is publicly traded, all of the inputs needed for a WACC calculation are
updated daily and are available online [22]. After carrying out the relevant
calculations for several noteworthy U.S.-based players in the c-Si supply
chain, we estimate that a WACC of around 8.6% would have been representative
for the first half of 2012.


          For
several reasons, however, the inputs for a WACC calculation on PV manufacturing
could change over time. For example, if the prices for modules and systems
continue to fall so as to mitigate the industry’s dependence upon subsidies,
and if utilities more widely adopt PV systems because they view them to be a
sensible substitute for their usual choices, then one might expect that the
risks associated with investments into PV companies and installation projects
will eventually become more like the risks associated with investments into
traditional sources for power generation. So assuming that the recent return
requirements of several conventional energy companies might also be
representative of what U.S.


Table 1


WACC
assumptions used within this paper for U.S. c-Si PV manufacturing. The
First-Half (1H) 2012 WACC is used for the benchmarking technology cases shown
throughout this paper; the long-term market WACC assumption will be specified
within the figure legends or captions when it is used. As an important note, we
use the five-year beta when estimating KE in the International CAPM
methodology.


	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	 

 
	
  

 
	
 Weighted
 average cost of capital (WACC) assumptions used for derivations of minimum
 sustainable prices

 
	
  

 
	 

 
	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
  

 	
  

 	
 1H 2012

 	
  

 	
 Long-term

 	
  

 
	
  

 	
  

 	 

 	
  

 	 

 	
  

 
	
 MVE/BVD+MVE

 	
  

 	
 0.60

 	
  

 	
  

 	
 0.70

 	
  

 	
  

 
	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
 Levered cost of equity (KE)

 	
  

 	
 12

 	
 %

 	
  

 	
 7.5

 	
 %

 	
  

 
	
 Leverage ratio BVD/BVD+MVE

 	
  

 	
 0.40

 	
  

 	
  

 	
 0.30

 	
  

 	
  

 
	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
 Levered cost of debt (KD)

 	
  

 	
 4.5

 	
 %

 	
  

 	
 4.5

 	
 %

 	
  

 
	
 Corporate tax rate (T)

 	
  

 	
 28

 	
 %

 	
  

 	
 28

 	
 %

 	
  

 
	
 WACC

 	
  

 	
 8.6

 	
 %

 	
  

 	
 6.2

 	
 %

 	
  

 













	
  

 	
  

 
	
 A. Goodrichetal./Solar Energy Materials&Solar Cells
 114 (2013) 110–135

 	
 113

 


PV
might look like over the long-term [23], we also detail the inputs for our long-term
WACC case in Table 1.


          The
WACC estimates derived in Table 1 are used as the discount rates in our pro
forma approach to estimating minimum sustainable product prices. Because not
even the vertical integration strategy can eliminate the need for every
material within a product’s supply chain to meet a minimum required rate of
return [24], our best-case, long-term minimum sustainable price projections
for complete c-Si modules are built upon the assumption that the transfer
prices for all upstream materials are precisely set to achieve a minimum
required margin, on top of the nominal cost of production, which is calculated
to meet these WACCs. Thus, the values in Table 1 are crucial assumptions that
are compounded within our analysis.


3. Polysilicon feedstock


3.1.
The Siemens process for producing
polysilicon chunk


          The
very first step in the fabrication of a c-Si wafer is the production of
metallurgical grade silicon via the high-temperature reduction of silica (the
source of which is typically lumpy quartz, not sand). With coke serving as the
reducing agent, the process is most typically carried out in an electric arc
furnace with carbon electrodes [25]





          The
elemental purity of this metallurgical grade silicon, which currently sells for
around $2.50/kg, is approximately 98%. But the material purity requirement for
the highest efficiency c-Si devices can approach 99.9999999% (9N). The most
widely used process for the production of the much more pure polysilicon
feedstock material is a chemical vapor deposition (CVD) method called the
Siemens process, whose processing sequence is broadly represented in Fig. 2.


In
order to remove the impurities contained within metallurgical grade silicon,
the first step in the Siemens CVD process involves the production and
distillation of trichlorosilane (TCS). Facilities that manufacture more than
2000 metric tons per annum (MTPA) of polysilicon generally manufacture their
own TCS onsite. The production of TCS can be achieved by the reaction of
metallurgical grade silicon with hydrochloric acid at moderate temperatures.
Most of the impurities that were present within the metallurgical grade Si are
left behind while the TCS is distilled [25]





Solid
polysilicon is then produced in a batch process as TCS is converted over the
surface of silicon rods that have been placed





Fig. 2. Generalized process flow for the production of solar grade polysilicon
feedstock via the Siemens process.


inside
of large bell jars, or ‘Siemens reactors’
as they are com-monly called. These silicon rods—or ‘filaments’—are produced
from ingots made from either the Czochralski
(Cz) or Float Zone (FZ) approaches.
The as-produced filaments of today are typically a 7 mm x 7 mm x 2500 mm
elongated square, which have been sawn lengthwise from the ingots using
slurry-based wire saws. The cropped ingot scrap can be reused for making other
ingots, but, due to inclusions of chemical impurities from the wire-sawing
slurry, and because it remains in the form of a very fine powder that is
extremely difficult to mechanically separate from the SiC based slurry used
during the cutting process, the approximately 10-15% of the ingot removed as
sawing—or ‘kerf—loss has essentially no value. As final steps before the CVD
chamber is sealed, the filaments are mechanically shaped to fit the electrical
contacts made for each, a bridge of filament material is set in place between
each parallel pair, and the native oxide is etched off using a dilute aqueous
HF solution.


          Electrical
current is passed through the resistive U-shaped silicon filaments to reach a
temperature that approaches 1150 0C. This rather high temperature serves to
activate the growth of solid polysilicon, Si (ps),
on the surface of these filaments as a result of the hydrogenation
of TCS with an HCl catalyst. The decomposition of trichlorosilane to produce
dichlorosilane (SiH2Cl2) is one of several side reactions
that also occur in the course of this growth process. Fortunately, this
intermediate can also react to make polysilicon, and so—even though the TCS
stream usually contains 6-9% DCS—most polysilicon producers choose not to
separate the two. This leaves the reaction series to be most generally
described as follows [25,26]:





          A
leading high-pressure 500-MTPA reactor made in 2012 would accommodate 72 rods;
the Siemens process would typically stopped once a diameter of 125 mm is
reached for each. In a reactor of that size, approximately 125 kg of hydrogen
is consumed during each hour of polysilicon growth, and the process is
approximately 20% efficient in its use of TCS for each pass through the
chamber. A total processing time of approximately 60 h per batch is typical,
including a total time of around 24 h for filament placement, oxide etching,
and for harvesting of the U-shaped polysilicon rods. As final steps, the
polysilicon rods are smashed into chunks and packaged in nitrogen- or
argon-filled bags for shipping.


In
order to drive the reaction sequence toward the production of polysilicon, it
is helpful to remove the H2 and SiCl4 as they are
produced within the bell jar. Fortunately, these effluents are actually useful
in that they can be recycled for the production of trichlorosilane (which can,
of course, be used again in later rounds of polysilicon production). The
hydrogenation of silicon tetrachloride, more commonly called the ‘direct
chlorination’ method, is one such pathway





          Or
the H2 and SiCl4 can be reacted with metallurgical grade
Si in the ‘hydrochlorination’ process [26]





          The
yields for the hydrochlorination route are generally more difficult to control
and it is a more technically challenging process. Thus, those companies having
less experience—but also a desire to quickly scale up and establish a presence
in this upstream step of the supply chain—are more likely to adopt the









	
  

 	
  

 
	
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 (2013) 110–135

 


direct
chlorination approach [27]. The direct chlorination method does, however,
require nearly double the capital equipment investment and uses significantly
more energy: 120–200 kWh/kg for direct chlorination versus 65–90 kWh/kg for
hydrochlor-ination [28].


3.2. The fluidized bed reactor (FBR)
process for producing polysilicon


          The
process of polysilicon production via the fluidized bed process is an
altogether physically different approach from the Siemens process [29]. The end
product is also quite different in that polysilicon granules, ranging in size
from 100 to 1500 mm, are produced instead of the much larger chunks [30].


          A
fluidized bed reactor is a cone shaped reaction vessel containing small
crystalline silicon seed particles that are suspended by an upward-flowing
‘fluidizing’ gas. This becomes physically possible once the upward drag force
of the fluidizing gas is approximately equal to the downward gravitational pull
on the particle, based upon its mass (W = mg). At the same time they are being
fluidized, the particles must be heated above the decomposition temperature of
a silicon precursor gas (commonly SiH4) that is introduced into the
vessel. Once the necessary decomposition temperature is reached, with hydrogen
serving as the fluidizing gas purified crystalline silicon layers build up
layer-upon-layer onto the suspended silicon beads. After reaching a size
whereby their weight becomes greater than the upward drag force of the
fluidizing gas, the heavier crystallized Si granules fall to the bottom of the
cone where they are collected.


          There
are several advantages to this approach in that it is much more efficient in
the overall net use of the reactant gases; it does not require the fabrication,
shaping, and placement of crystalline seed filaments; and it requires
significantly less energy, at only around 12–20 kWh/kg [8]. The material form
factor of the FBR granules is also quite advantageous in the subsequent step of
melting polysilicon because the granules can be continuously fed into Cz
pullers to bear up to 3 daughter ingots per initial charge (versus having to
reload polysilicon chunk in single batch processing). In addition, the
semi-continuous feeding of granules enables the semi-continuous feeding of
dopants; and this can be helpful in overcoming the well-known challenges of
uniformly distributing dopants having low segregation coefficients [31]. In
spite of its numerous apparent advantages, how-ever, there are also numerous
technical challenges in qualifying new FBR facilities. In particular, it can be
difficult to manage the heating of the fluidized beads in a controlled manner,
without losing an important temperature differential between the reaction zone
and the walls of the reactor cone [29]. This at least partially explains why
there are currently only a handful of companies that have the technical
capability to provide this FBR material.


3.3. Cost model results for polysilicon production


          In
Fig. 3, the manufacturing cost model results are shown for the two approaches
to polysilicon production most commonly employed within the U.S. In both cases,
the largest expense is calculated to be the average depreciation on the capital
equipment and manufacturing facility (as the basis for our calculations, the
total calculated upfront capital expenditure in the equipment and facilities,
or ‘CapEx’, worked out to be $74/kg of annual production capacity for a Siemens
hydrochlorination facility and $71/kg of annual production capacity for an
FBR-based facility). The greater energy intensity of 90 kWh/kg for the Siemens
hydrochlorination approach, versus 12 kWh/kg for the FBR approach, explains the
differences in energy costs that can be seen in the figure. Within the U.S.,
electricity rates as low as $0.025/kWh (current U.S. dollars) can be had for
industrial customers who are able to locate near hydroelectric dams— currently
the lowest cost method for generating electricity in this country. Not
surprisingly, given the substantial energy requirements, most poly production
within the U.S. occurs near these low-cost electricity sources. Accordingly,
the energy costs represented in Fig. 3 are calculated on the basis of a
$0.025/kWh electricity price assumption. (For all other manufacturing steps in
the c-Si module supply chain, which do not necessarily occur in





Fig. 3. Model results for polysilicon production costs and minimum sustainable
prices, for a U.S.-based 15,000 MTPA production facility with onsite TCS
production. The two most commonly employed methods within the U.S. are shown,
where the minimum sustainable prices were derived using the specified WACC and
Siemens chunk/FBR material ratios. The ‘polysilicon’ and ‘saw wire’ components
correspond to the Cz pulling of ingots and the shaping of filaments. For
several of the major inputs used for the calculations, please also see the
spreadsheet contained within the supplementary information.









	
  

 	
  

 
	
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 114 (2013) 110–135

 	
 115

 


such
locations, we assume an electricity price equal to the U.S. national industrial
average electricity rate of $0.069/kWh [16]).


          While
some analysts believe that polysilicon producers will be forced to lower
long-term contract prices to less than $20/kg by as early as last year [9], by
our estimates price demands below this level are not sustainable over the
long-term. An increased use of the FBR material may appear to provide the most
likely pathway to getting there; however, new FBR facilities are not being
built at a rate that is commensurate with a wholesale replacement of
polysilicon chunk facilities. And so, despite the ostensible cost advantages in
making it, the extent to which the FBR material will contribute to global
polysilicon supplies appears to be limited for at least the foreseeable future.
Per projection from one large polysilicon producer, we assume that its
contribution to global supplies will likely be limited to just 2% in the
short-term, 5% in the mid-term, and 20% over the long-term. After incorporating
these estimated FBR contributions, and after deriving the minimum sustainable
prices needed to meet the mature market WACC, we estimate the long-term minimum
sustainable price for U.S. based polysilicon production to be around $23/kg
(Current U.S.), with an 80/20 mix of Siemens chunk/FBR granules.


4. The Czochralski process for pulling monocrystalline
silicon boules, followed by cropping and wafering


4.1. Technical overview


          The
next step in the c-Si supply chain often takes place in a separate location
from polysilicon feedstock production (even in the case of vertically
integrated firms), and involves melting polysilicon chunks (and FBR granules,
if utilized); forming a Cz boule (or ‘ingot’) from the melt; cropping the
crown, tail, and sides of that ingot into a precise shape that minimizes scrap
losses; and the cross-sectional sawing of the boule into individual wafers.


          This
process is begun by first immersing a rotating crystalline silicon seed crystal
into molten silicon (Tmelting =1410oC). The
seed serves as a template for the growth of a nearly perfect single crystal,
set precisely in length and diameter by the vertical pull rate of the seed from
the melt, the amount of polysilicon that can be melted in the crucible, the
temperature gradient within the crucible, the rotational velocity of the seed,
and the amount of counter-rotation by the crucible [32]. The precise dimensions
of the formed monocrystalline boule are carefully calculated on the basis of
minimizing material scrap losses in the subsequent cropping and wafering steps,
and in consideration of the mechanical fidelity of wafers for all steps through
module assembly.


          In
Fig. 4 a typical process and material flow is shown for producing today’s
standard wafers having a thickness of 180 mm. For making such wafers, the usual
body diameter of an uncropped ingot would be 205 mm, and a representative
length would be around 2100 mm (including the tapered ends of the crown and
tail). Of course, for the purpose of creating uniform wafer sizes the crown and
tail of the ingot cannot be used; they must be cropped off before the wafering
process can begin. After cropping a 2100 mm long ingot with a band saw, the
final length would be about 1700 mm (with 200 mm equally cut off from both the
crown and tail). By sawing off chords of material down the length of the boule,
the cylindrical shape is then sawn into that of an elongated square brick with
rounded corners: a so-called ‘pseudo-square’ shape. After accounting for the
corner losses, the total cross-sectional area of the shaped brick (and,
correspondingly, the pseudo-square shaped wafers that are later used in cell
and module assembly) is most commonly set to a standard 237 cm2,
with a flat-edge width equal to 156 mm.


          The
bulk scrap that is generated during the cuts of the crown and tail, and the
chord scrap, is readily remelted during later rounds of ingot casting (after
being broken into chunks and chemically washed of the native oxide that
develops while the chunks are exposed to air). But, in both the cutting of the
bulk scrap and in the sawing of wafers, the kerf sawdust that is also generated
is generally unusable when the incumbent approach of standard-wire cutting is
employed. With the typical wire diameter of 120 mm producing 130 mm of kerf
loss for each cut, and with the large number of cuts undertaken to produce all
of the wafers that can be taken from a boule, this kerf loss continues to
remain the most significant contribution to the final net material loss in
wafering [33].





Fig. 4. Process and materials flow for standard Cz growth of monocrystalline
silicon ingots and subsequent cropping, squaring, and wafering. Typical
material losses in production are shown on the outside of the processing steps,
where the solid scrap generated through sawing of the boule crown, tail, and
chords is recycled for further ingot pulls; but the kerf loss in sawing is not.
The given ‘Capex’ numbers within each step refer to the associated capital
equipment expenses divided by the annual production capacity of the facility,
with an assumed solar cell power conversion efficiency of 16.7%.









	
  

 	
  

 
	
 116

 	
 A.Goodrichetal./Solar Energy Materials&Solar Cells 114
 (2013) 110–135

 


          Because
this kerf material loss can translate to a significant cost penalty
(particularly when polysilicon prices are high), there remains a strong desire
to eliminate it. Since no wire-sawing process can completely eliminate at least
some amount of sawdust; perhaps it could be just as well to recycle the kerf.
For this purpose, one promising trend to have recently surfaced in ingot
cropping, squaring and wafering is to switch from the current industry-standard
steel cutting wires to cutting wires that have industrial-grade diamond
particles attached to them. By using such wires, the diamonds can serve as the
abrasive elements for the cutting, thereby replacing the suspension of SiC particles
that serve as the abrasive elements in the incumbent standard-wire cutting
approach. This is advantageous in terms of the cutting fluid chemistry: Because
the SiC particles used in standard cutting must typically be distributed as a
slurry with polyethylene glycol, the diamond-wire approach offers a more likely
pathway to kerf recycling because the cutting fluid can instead be a simple
aqueous surfactant solution—thus yielding a kerf material that possesses a
greatly reduced chemical contamination [34–36]. The benefits of diamond-wire
sawing do not stop there, however, as it also offers a longer wire life, a
faster cutting rate and lower cost for the cutting fluid. In the next section
we quantify how these benefits might lead to a reduction in total wafer
manufacturing costs.


4.2. Cost analyses of ingot casting and wafering


          In
Fig. 5, we present wafer production costs for the first half of 2012 (leftmost
bar), and the calculated future costs for producing, cropping, shaping, and
wafering standard monocrystalline silicon ingots.


          The
labor costs for wafer production are calculated to be substantial. This is
because so many of the steps in wafering are currently difficult to automate.
First, the cropped and shaped bricks are manually glued to a glass substrate
before being placed into the wafering machine. After the brick is cut, the
wafers are released from the glass by immersing the entire unit in an aqueous
solution formulated to dissolve the glue. The result is a stack of thin wafers
that adhere to each other by virtue of the solution’s surface tension. To
separate the wet wafers from one another, without incurring high mechanical
yield losses due to wafer breakage, requires a level of dexterity that has so
far been most easily achieved not by robots but by human hands. And so, with
relatively high labor rates, the labor cost for the wafer singulation step in
particular is calculated to be nontrivial for a U.S.-based wafer manufacturing
facility.


          From
the first half 2012 case represented in the leftmost bar in Fig. 5, if the
technical improvement opportunities described in the last section could be
successfully demonstrated in commercial production then there could be a trend
towards lower wafer manufacturing costs. In addition to implementing these
technologies in wafer production, a long-term reduction in the price for
polysilicon—to something more like its minimum sustainable price—would also
provide a very obvious benefit toward reducing the costs for making wafers.


          Over
the course of 2011, the global monthly average spot price for polysilicon
varied between $80/kg and $30/kg. Meanwhile, typical contract prices were
around $50/kg [8]. After an aggressive





Fig. 5. Estimated current cost and minimum sustainable price (in $/m2)
for producing standard wafers via the Cz pulling of silicon ingots and
subsequent cropping and wafering (leftmost bar). The waterfall chart then
quantifies the specific cost reduction opportunities–and a cost penalty–for
each implemented technology described in the text. The modeled facility size is
set for an annual production level of 120 million wafers per year in the 1 H
2012 case, and 480 million wafers per year in the long-term case.









	
  

 	
  

 
	
 A. Goodrichetal./Solar Energy Materials&Solar Cells
 114 (2013) 110–135

 	
 117

 


worldwide
build-out of polysilicon plants, in 2012 poly suppliers had to offer
significantly lower prices. At the beginning of the year, typical expectations
for spot prices were around $27/kg and typical contract prices were around
$41/kg [37]. At the 50%/50% spot/contract prices that wafer manufactures
typically work with, at the start of 2012 the blended price for polysilicon
would then have been around $34/kg for global wafer production—still notice-ably
higher than the $24 and $23/kg minimum sustainable poly-silicon prices derived
in Fig. 3. If the final blended polysilicon price to wafer manufacturers could
drop to those minimum sustainable levels, relative to a $34/kg blended poly
price there could be a total reduction in materials cost that would work out to
around $12/m2 of wafers produced. As foreshadowed in the
Introduction, to obtain such minimum sustainable prices in long-term blended
supply contracts may require something like a vertical integration strategy—in
addition to globally stable poly prices.


          Another
pathway to wafer cost reductions could be through an increased use of FBR
polysilicon granules. While it is currently not possible to rely exclusively
upon FBR granules in the pulling of Cz ingots—because current equipment
configurations require that the larger Siemens-based chunks be present in the
initial material loading and melting steps—their increased use in this step of
the supply chain enables the effective uptime of the capital equipment to be
improved through semi-continuous feeding. This then enables a decline in the
overall depreciation expense because the effective ‘uptime’ of the equipment is
improved. However, the benefit is not calculated to be that much. Relative to
the bench-mark case of just one daughter ingot per initial charge if solely
using polysilicon chunk, if three daughter ingots per initial charge could be
achieved then the associated savings could be around $0.35/m2 of
wafers produced.


          In
Table 2 we highlight the major cost-of-ownership considerations for both
today’s standard wire approach as well as diamond-wire sawing. Although the
cost-per-meter of the diamond wire is higher than the standard cutting wire, by
utilizing the diamond-wire approach there may be substantial benefits in the
final net cost for producing wafers. Before consideration of the additional
potential benefit of kerf recycling, the diamond-wire approach may enable an
overall savings in wafer manufacturing of around 15% (if the cost of diamond
wire can fall to within twice the cost of standard wire, and assuming equal
capital equipment costs). If diamond-wire sawing also leads to kerf recycling,
an additional cost reduction of up to $15/m2 may also become
possible, depending upon the final costs for the recycling process. (Because
the costs for kerf recycling are not currently known, within the Supplementary
Information we provide a curve showing the sensitivity of wafer costs to the
costs for kerf recycling).


          The
contribution of future wafer costs to total future module manufacturing costs
is generally expected to be lower because the silicon utilization—that is, the
grams of silicon needed per Watt of solar cells produced—is expected to improve
as cell efficiencies rise and as the wafer thickness is reduced. As cell
efficiencies greater than 20% have already been demonstrated on sub-50 mm
substrates [38–40], it may even seem that this could happen at any time. But
beginning with wafering—and also continuing into cell and module assembly—moving
down from today’s standard wafer thickness of 180-mm to something much thinner
is quite challenging for currently available sawing and handling equipment. The
principal challenge is that, for wafering and for all downstream steps, when
using today’s manufacturing equipment the mechanical yield losses generally
increase as the wafer thickness is reduced—and can ultimately become quite
intractable for wafer thicknesses below about 80 mm [41].


Table 2


          Cost
of ownership assumptions for the standard and diamond-wire saw approaches to
cropping and wafering monocrystalline silicon boules.


	
  

 	
  

 	
  

 
	 

 
	
  

 
	
 Cost of
 ownership input assumptions for the standard-wire and diamond-wire approaches
 to cropping, squaring and wafering monocrystalline silicon ingots

 
	
  

 
	 

 
	
  

 	
  

 	
  

 
	
  

 	
 Standard
 wire

 	
 Diamond-wire

 
	 

 	 

 	 

 
	
 Wire diameter

 	
 120 mm

 	
 120 mm

 
	
 Kerf loss per cut

 	
 130 mm

 	
 130 mm

 
	
 Cutting rate (mm/min)

 	
 0.37

 	
 1.1

 
	
 Cutting fluid and cost

 	
 SiC in PEG $1.40/

 	
 Water with surfactant

 
	
  

 	
 kg - $2.00/kg

 	
 ($0.39/1000 l)

 
	
 Wire cost

 	
 $2.80/km

 	
 $5.60/km

 
	
 Wire life (cm2 of wafers produced per meter of wire)

 	
 24

 	
 80

 
	 

 	 

 	 

 


          To
partially address this yield loss challenge, the area of the wafer can be
reduced while the thickness is reduced. The current guideline is that once the
thickness of a wire-sawn wafer is reduced to 140 mm, the boule diameter and final
cross-sectional area of a wire-sawn ingot should be reduced from a standard 205
mm (237 cm2) to 165 mm (155 cm2). While the guidelines
for boule diameter for wafers having a thickness between 80 and 140-mm are less
well known, under the best of circumstances it may be possible to make wafers
having the same 155 cm2 area. It may also be possible to achieve a
condition of mass balance in that the length of the ingot can be increased, as
the diameter is reduced, in order to fully utilize the material capacity of the
Cz crucible. Additionally, the vertical pull rate can also be slightly
increased when making a smaller diameter boule [42]. (From the data provided by
a relevant equipment supplier, the achievable vertical pull rate of the boule
body is calculated to be around 43 mm/h for 237 cm2 wafers, and
around 49 mm/h for 155 cm2 wafers). Even so, there is an overall net
cost penalty associated with the smaller area wafers because there is an
overall lower through-put in the Cz pullers and in the sawing equipment. After
accounting for these factors, with the relevant collaborator-provided inputs
this small-area penalty is calculated to be around $6/m2.


          There
are, of course, several other ideas beyond what we have outlined that also seek
to improve the net silicon utilization. These include ideas such as the
epitaxial growth and lift-off of film silicon, cast wafers, exfoliated wafers,
ion-based cleaving approaches for wafer separation from an ingot, etc. [43].
Each of these approaches would have its own proprietary cost structure for
wafer production, in addition to other considerations for how such wafers would
integrate into the overall c-Si supply chain. Knowing that there are other
approaches to wafer production that are being considered, it is worth noting to
the reader that the wafering cost estimates that have been presented are only
for the technology cases that have been described.


5. Cells


5.1. The standard monocrystalline silicon solar cell


          The
majority of c-Si solar cell production is currently based upon a very
standardized process that is intended to make a p-/n-electrical junction on the
entire front surface of the wafer and a full-area aluminum-based metallization
on the back [44]. A representative series of steps for making such cells is
shown in Fig. 6.


          First,
because wafers are typically received from multiple supply sources, and because
they can be damaged during sawing and shipping, all incoming wafers should be
tested to ensure that they would provide a foundation for acceptable cell
efficiencies. Specifically, for the purposes of wafer metrology, measurements
of the minority charge-carrier lifetimes would be quite informative [45]. But
due to an anticipated slowdown in manufacturing throughput if every single wafer
was to be tested—primarily









	
  

 	
  

 
	
 118

 	
 A.Goodrichetal./Solar Energy Materials&Solar Cells 114
 (2013) 110–135

 





Fig. 6. Process flow for fabricating a standard c-Si solar cell.


because
it can be difficult and time-consuming to decouple the effects of surface
recombination from bulk recombination when interpreting such measurements—it
has so far proven elusive to cost-effectively standardize the in-line metrology
of all as-cut, unpassivated wafers immediately after they are taken out of the
box [46,47]. While this is rapidly changing, particularly in the more
state-of-the-art cell manufacturing facilities, in the current standard process
as-received wafers are more simply and quickly screened for their dimensions
and for any physical damage. Most commonly, the standard process typically
employs rapid throughput wafer-imaging systems that detect the defect states
associated with microcracks (by mapping attenuations in IR transmission), and
reject any wafers containing microcracks that are too large.


          Because
the wire sawing process is extremely abrasive, if left untreated an as-received
c-Si wafer would retain a high density of unpassivated surface defects that
would actively facilitate electron–hole recombination in an illuminated cell.
To ameliorate this problem, and to partially remove the microcracks at the
surface that might compromise the wafer’s resilience to breakage during
handling in cell processing [35], as the second step in the standard process a
wet bench chemical treatment is utilized to etch away between 5 and 15 mm of
saw damage from the top surface of the wafer. This is typically achieved by
exposing the wafers to an aqueous solution of NaOH or KOH with IPA. With the
alkali metal only being a spectator ion, the etching reaction proceeds as
follows [48]:





          The
etch rate of this chemical reaction is different for different crystallographic
orientations. Due to these anisotropic differences in etch rates, the
originally flat wafer surface is etched into a morphology of pyramids having a
random distribution in size. Fortuitously, these pyramids can provide the
foundation for front-surface light trapping [49]. At the conclusion of this wet
bench chemical processing step the surface is then ready for the formation of
the topside p-/n- electrical junction.


          In
a well designed solar cell, the surface and bulk electric fields should work to
usher all of the photogenerated electrons and holes towards their appropriate
electrical contacts. This is most generally achieved by establishing a p-/n-
junction across the region that absorbs the most light. The standard c-Si solar
cell is generally made with a boron doped (p-type) base wafer. The formation of
the n-doped region—the so-called the ‘emitter’ region—is formed over the entire
topside of the wafer as the doping characteristics are inverted from p- type
into n- type by the high-temperature drive-in of phosphorus [50]. In this step,
the wafers are exposed to phosphorus oxychloride (POCl3) gas within
a quartz tube furnace and then heated to a high temperature, typically between
800 and 900 1C, in order to activate the diffusion of phosphorous into the
wafer.


          During
this diffusion step, the surface of a POCl3 treated wafer becomes
glassy. Because this amorphous layer makes it difficult to make a good
electrical contact to the bulk silicon, and because its properties change after
being exposed to moisture, it is generally necessary to include another
processing step for the removal of this thin phosphosilicate glass (PSG) layer.
For this purpose, an HF dip is typically used. So that only one p-/n-junction
is formed at the top of the solar cell, another treatment commonly called ‘edge
isolation’ is also typically carried out. The purpose of the edge isolation
treatment is to remove the shallow phosphorus diffusion that creeps onto the
wafer edges and back-side, which is unavoidable even though it was only the
topside that was primarily exposed within the tube furnace [51]. In the wet
bench chemical approach to edge isolation, the same manufacturing tool can be
used as for PSG removal.


          While
the random pyramid surface texturing is helpful, deposit-ing an additional
layer that possesses a sufficiently different index of refraction from silicon
can help to reduce the reflection of light even further. As a standard
material, hydrogenated silicon nitride (SiNx:H) is able to serve as
such an antireflection (AR) coating. The plasma-enhanced chemical vapor
deposition (PECVD) approach is currently the most widely employed method for
depositing this material. In this process, the AR coating is formed during the
plasma-activated reaction between silane (SiH4) and ammonia (NH3)
gases that are introduced into the reactor chamber.


          Because
it has generally been more cost-effective than vacuum-based metallization
approaches like evaporation or sputtering, the screen printing of Ag and Al
pastes for the formation of the front and rear electrical contacts has been in
use by the c-Si industrial community since the 1970s [52]. In this process a
conveyer belt moves c-Si wafers along a queue where they are picked up, either
by a robotic or human arm, and placed onto a printing table. An H-pattern
screen that is mounted in an aluminum frame is then overlain on the frontside
of the cell and the metallization paste is squeegeed over the wafer surface
with a defined pressure. In today’s screen printers this handling and printing
process can be repeated at an impressive net rate of 1–2 s per wafer, including
time for wafer placement and removal. After the front-side screen-printing, the
wafers are moved into a low-temperature ("200 1C) drying oven, and the wafer is
then moved on to another table for a three-step printing sequence of the rear
side Al paste and Ag/Al rear busbars. At the end of the printing steps, in
order to drive off the undesired additives used to make the metal pastes, the
entire cell assembly is typically co-fired at around 8101C [53]. At this temperature, lead borosilicate glass frit (PbO–B2O3–SiO2)
contained within the Ag paste etches through the SiNx:H layer
to form a direct bond and electrical contact with the underlying emitter
region.









	
  

 	
  

 
	
 A. Goodrichetal./Solar Energy Materials&Solar Cells
 114 (2013) 110–135

 	
 119

 


          As
the final step in the standard c-Si solar cell processing sequence, the
current–voltage (J–V) characteristics are measured for each cell that is
produced on the line. In order to minimize current mismatch losses between
cells when they are series-connected into modules, they are binned according to
their current density at maximum power point.


5.2. Introduction of potential pathways to improve
efficiencies beyond the standard c-Si cell


          While
the standard approach to cell processing has been the dominant manufacturing
strategy for quite some time, it is increasingly clear that it will become
necessary to lower costs even further, in order to remain competitive within
the future landscape of PV. For all steps within the c-Si supply chain as well
as at the installed systems level, there is little choice but to call upon
gains in efficiency in order to achieve these ends—and it appears that the
standard cell processing approach will ultimately not be able to deliver the
20–25% power conversion efficiencies that other industrially-relevant manufacturing
processes are capable of delivering [54].


          To
define this important consideration, the efficiency of a solar cell is most
generally calculated as follows:





(9)


where
AM 1.5 represents a modeled profile for the number of photons expected for each
wavelength within the solar spectrum after it passes through the earth’s
atmosphere. By carefully specifying the atmospheric conditions in an
internationally standardized way, which falls within the expectations of
sunlight received at mid latitude on a clear day, the total integrated energy
content of this modeled profile can be set equal to 1 kW/m2. The FF,
Jsc, and Voc represent the respective efficiency
parameters of fill factor (unitless), short-circuit current density (in A/m2,
or mA/cm2), and open-circuit voltage (in Volts). The product of
these three gives the maximum power under standard test conditions. For c-Si,
in consideration of the absorption profile of the semi-conductor in comparison
to the AM 1.5 spectrum, as well as the factors that limit the Voc
and FF, the full efficiency potential under standard test conditions is around
29% for a 100-mm
wafer [55]. 


          If
it assumed that the solar cell follows ideal diode behavior with superposition,
the Voc parameter can be analyzed after knowing the inputs for Eq.
(10), where n, k, and q are constants at a fixed temperature [56]:





(10)


          As
Eq. (10) shows, maximizing the Voc implies maximizing the Jsc,
while at the same time also minimizing the J0.


          This
J0 parameter—most commonly called the saturation, or recombination,
current density—is a broad representation of the overall net rate of
electron-hole recombination within a solar cell. While the theoretical limits
to the J0 and Voc in a c-Si absorber are estimated to be
around 0.27 fA/cm2 and 0.845 V [54], the measured values for a
standard cell are noticeably different from these. There is a long list of
causes: radiative, conduction-band to valence-band recombination (i.e.,
emission); defect-mediated recombination on the front, edge, and back surfaces
(which is but one form for Shockley–Read–Hall, or SRH, recombination); SRH
recombination from states generated by bulk defects; metal-to-silicon contact
recombination; p-/n- electrical junction (or ‘depletion layer’) recombination;
Auger recombination; and the list goes on. In the end, the lower limit to the J0
is set by the radiative recombination term because, at the thermodynamic limit
of a perfect detailed balance, the rate of electron–hole pairs being put back
into the solar cell must equal the rate that is generated by light absorption
[55]. (For a more complete description of this lower limit, and for a history
of c-Si technology development, please see Ref. [57].)


          As
for the other, non-radiative, sources for recombination, there are a multitude
of potential remedies that are commonly recognized. We introduce several of
them in Table 3.


          By
calling upon the same underlying assumptions used to derive the open-circuit
voltage expression, it is also possible to simplify the discussion of the
short-circuit current to the following [56]:





(11)


where
the QE(l) term, called the external quantum efficiency, is the probability for
generating and collecting an electron at the specified wavelength of incident
light. In the typical reference case, the maximum possible current (i.e., at
short-circuit condition) of the solar cell can then be derived by integrating
these probabilities over the entire AM 1.5 spectrum. As it is for the Voc,
there are architecture-specific origins for the observed losses in the Jsc
of a standard c-Si solar cell. Several ideas for improving them are captured in
Table 3. 


          In
arranging the table some of the major technical improvement opportunities that
are known are organized into three general technology groups. The first
difference between these technology groups is in the choice of base doping
within the wafer: p-type for Group 1, and n-type for Groups 2 and 3. The
hypothetical cells for each technology group capture several of the currently
known opportunities for creating more efficient c-Si devices and, in principle,
could be made with equipment that is currently available for industrial-scale
manufacturing. Nonetheless, the model cell architectures, the underlying
efficiency assumptions, and following processing flows associated with each
have not necessarily been commercially demonstrated in their entirety, and were
explicitly designed for cost-modeling purposes only.


5.3. Technology group 1: front-side metallization on a
p-type Cz wafer (20–22% cell efficiency)





5.3.1. Front metal contact buried into the wafer with a
locally diffused emitter


          The
highest efficiency c-Si solar cell to date, at 25% [93], is based upon an
architecture called the Passivated Emitter Rear Locally-diffused (PERL) cell.
The record efficiency mark for this cell has been in place since 1999, and,
although it is cost-prohibitive to precisely replicate all aspects of the PERL
cell, several of its underlying concepts









	
  

 	
  

 
	
 120

 	
 A.Goodrichetal./Solar Energy Materials&Solar Cells 114
 (2013) 110–135

 


Table 3


Overview
of several technical improvement opportunities, organized by technology groups,
that are available to improve the efficiency of c-Si cells and modules. The
assumed cell-to-module derate is 89% for the calculation of the module
efficiencies shown in parentheses at the bottom of the table, although this
value may be improved with changes to the assumed standard module design.


	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
 Cell per

 formance 

 parameters

 	
 2011
 Standard cell 

 (p-type base)

 	
 Technology
 Group 1 

 (p-type base)

 	
 Technology
 Group 2 

 (n-type base)

 	
 Technology
 Group 3 

 (n-type base)

 
	 

 	 

 	 


 	 

 	 

 
	
 Short-circuit

 	
 35

 	
 38

 	
 41

 	
 40

 
	
 current
 density:

 JSC (mA/cm2)

 	
  

 	
 •

 	
 Backside optical mirror
 [58]

 	
 •

 	
 Reduce front-side shadowing
 losses by moving contacts to the back [62]

 	
 •

 	
 3 Develop a TCO
 with reduced free-carrier absorption [54,66]

 
	
  

 	
  

 	
 •

 	
 Higher aspect ratio front
 gridlines [59]

 	
 •

 	
 Improved light trapping
 through novel surface texturing and higher internal light reflection [63,64]

 	
 •

 	
 3 Develop a
 heterojunction window layer with reduced absorption [66]

 
	
  

 	
  

 	
 •

 	
 Buried front metal
 contacts[60]

 	
 •

 	
 Lightly doped FSF [65]

 	
  

 	
  

 
	
  

 	
  

 	
 •

 	
 Selectively diffused
 emitter junctions [61]

 	
 •

 	
 SiO2 passivation[65]

 	
  

 	
  

 
	 

 	 

 	 

 	 

 	 



 	 

 	 

 	 

 
	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
 Open-circuit

 	
 0.62

 	
 0.70 [67]

 	
 0.74

 	
 0.75 [68]

 
	
 voltage: VOC

  (V/cell)

 	
  

 	
 •

 	
  Selectively diffused emitter junctions[61]

 	
 •

 	
 Ion implantation for precise
 control of dopant profiles [73–75]

 	
 •

 	
 Use n-type wafers with ms
 minority carrier lifetimes [78]

 
	
  

 	
  

 	
 •

 	
  Improve wafer quality: alternative dopants or
 magnetic Cz [69–71]

 	
 •

 	
 Use tightly focused
 metal-to-Si contacts in order to reduce contact recombination losses [76,77]

 	
 •

 	
 a-Si:H/c-Si heterojunction
 surface passivation [81]

 
	
  

 	
  

 	
 •

 	
  Improve surface and bulk passivation [62,72]

 	
 •

 	
 Use n-type wafers with
 minority carrier lifetimes approaching 10 ms [78]

 	
  

 	
  

 
	
  

 	
  

 	
  

 	
  

 	
 •

 	
 Improve back, front, and
 edge surface passivation [55,79,80]

 	
  

 	
  

 
	 

 	 

 	 

 	 

 	 

 	 

 	 

 	 

 
	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
 fill
 factor: FF (%)

 	
 78

 	
 80

 	
 82

 	
 80

 
	
  

 	
  

 	
 •

 	
  Improve conductivity (s) through electroplating [82]

 	
 •

 	
 Reduce resistive (I2R)
 losses, without compromising optical losses, by covering more solar cell area
 in a back-contact scheme [54]

 	
 •

 	
 Use n-type wafers with ms
 minority carrier lifetimes [78]

 
	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
 •

 	
 a-Si heterojunction surface
 passivation [54]

 
	
  

 	
  

 	
 •

 	
 Develop and improve new
 metal and selective emitter paste chemistries [83,84]

 	
  

 	
  

 	
 •

 	
 Use a TCO for
 charge-carrier transport and anti-reflection coating, and develop a new one
 with a higher electrical conductivity [85]

 
	
  

 	
  

 	
 •

 	
 Selectively diffused
 emitter junctions [61]

 	
  

 	
  

 	
  

 	
  

 
	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
 AM 1.5
 power

 	
 17% cells

 	
 20–22%
 [86–89] (18.7%)

 	
 25% [90]
 (22.4%)

 	
 24%
 [91,92] (21.4%)

 
	
 conversion

 	
  (14.5%

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	
 efficiency
 (%):

 	
 modules)

 	
  

 	
  

 	
  

 	
  

 	
  

 	
  

 
	 

 	 

 	 

 	 

 	 

 	 

 	 

 	 

 













	
  

 	
  

 
	
 A. Goodrichetal./Solar Energy Materials&Solar Cells
 114 (2013) 110–135

 	
 121

 


are
clearly appearing within many of the new equipment designs and industrial research and development programs
[87,89,94]. Because the cell is also based upon a boron doped (p-type) base, making it quite amenable to
the standard industrial cell processing approaches already in place, we have
included an industrially scalable derivative of
the PERL architecture as part of our c-Si roadmap.


          While
not the only contributor to the high cell efficiency, the PERL concept
incorporates the idea of a heavily doped emitter region that is narrowly
focused at the point of contact between Si and the frontside metal, in addition
to a lightly doped region over the entire wafer front surface [95]. Today this
design is more commonly called a ‘selective’, rather than a ‘locally diffused’,
emitter; and it possesses several advantages over the standard cell
architecture—primarily in optimizing the electrical connection between the
frontside metal and silicon without also creating unnecessarily high rates of
recombination over the unmetallized regions of the wafer’s front surface
[50,96]. This selective emitter profile is achieved by creating two different
doping densities within the cell: n-type doping (with carrier concentrations, Nd, on the order of 1019cm-3)
over the entire wafer front surface, and n+
doping (Nd " 1020cm-3)
directly at the line of contact between the metal and the narrow emitter
region. In comparison to the standard emitter profile, this selective emitter
doping profile makes it possible to establish an electric field within the
device that more efficiently ushers photogenerated electrons and holes toward
their appropriate electrodes—while also greatly reducing the probability for
recombination as the charge carriers move between the silicon and the metal
electrodes [97]. The overall expected result when employing such a design is a
lowered value in the overall J0 (and,
therefore, a correspondingly higher Voc), as well as a slight
benefit to the Jsc of
the cell due to a higher quantum efficiency of blue photons [61,98].


          There
are numerous manufacturing processes currently under development that can
deliver cells of this type. These include the industrially-relevant options of
either screen-printing dopant pastes [84,98], or using the laser-assisted
doping of a wafer from a stream of H3PO4 [99,100], to
form the n+ region. As for how they might be implemented, we have incorporated
either nominally cost-equivalent option as a step within a process flow
designed around an industrially scalable derivative of the PERL cell (Fig. 7).
While not used within our specific process flow, there are also other options
for making selective emitter contacts, including a heavy doping of the entire
wafer frontside (followed by selective etch-back of the cell’s surface in all
regions except where the metal contacts are to be printed), or screen-printing
a heavily doped silicon nanoparticle ink [101].


          In
creating the process flow for Technology Group 1, it is assumed that standard
cell processing steps 1–5 could be retained. That is, standard cell processing
steps 1–4 could be called upon to establish light n doping of the wafer front
surface; and step 5 could be called upon for incorporation of SiNx:H (because, as in the standard
cell, this material is beneficial as an anti-reflection coating and for
mitigating Jo due to
front-surface recombination [54,102]).


          After
the PECVD step, it could then be appropriate to form a network of trenches in
the silicon wafer with a laser ablation step. In this process, a focused laser
that is powerful enough to create localized heating above the melting
temperature of both silicon (Tmelting=1410 1C) and silicon
nitride (Tmelting=1900
1C) is used to create a pattern of trenches having a precisely set depth
and width [99,103]. Such an ablation process may create a thin layer of damage
on the walls of the groove, however, which should be removed with something
like a NaOH etch. (Otherwise, if left untreated, dislocations in the local
crystal structure that are generated by the lasers can potentially glide into
the bulk during subsequent thermal processing steps.) We have included this
laser damage removal step as step 7.


          The
laser groove is envisioned to be advantageous for either the printed dopant
paste or aqueous-based approaches to emitter drive-in, primarily because it
also establishes a pathway to higher aspect ratio grid lines on the front of
the cell—a benefit we discuss next. It is worth noting that steps 6 and 8 would
likely require separate laser stations.





Fig. 7. Model process flow for fabrication of Technology Group 1 cells.









	
  

 	
  

 
	
 122

 	
 A.Goodrichetal./Solar Energy Materials&Solar Cells 114
 (2013) 110–135

 


5.3.2. Moving from screen-printing to electroplating for
front-side metallization


          For
the most part, there appears to be little rush to replace the standard
screen-printing of Ag. It is, after all, a commercially proven, high-throughput
process with good alignment control and low wafer breakage rates. Just as
importantly, it also provides a metal contact having reliable adhesion to the
solar cell over the entire lifetime of the module. Yet there are multiple reasons
as to why this approach to frontside metallization is ultimately unsustainable.


          One
commonly expressed reason is that, at some point, the c-Si technology may
eventually become a victim of its own success, in that the demand for Ag from
it alone may drive its price to an unacceptably high level. Without confirming
or denying that particular line of conjecture, the question does need to
consider that there will more than likely be a noticeable decline in the
required grams-of-Ag-per-watt in c-Si manufacturing, because there are other
approaches to metallization—beyond just simple screen-printing—that can replace
a lot of the Ag with much cheaper metals.


          The
next step of our model process flow incorporates the light-induced plating approach
for depositing a copper-alloy grid on top of an electroless seed of nickel
[60,104,105]. This metal layer stack could conceivably move c-Si cells away
from the full screen-printing of silver and toward the more scalable
alternative of a primarily Cu-based metallization. Even if this choice is
developed, as it already has been within the integrated circuits industry, we
have included the Ni layer to be but one example of a material that will likely
be needed for adhesion, to prevent the diffusion of Cu into the cell (which is
detrimental to the reliability [106]), and to also serve as an electrical
channel for the deposition of a Cu alloy from solution.


          In
the first step of this method, a very narrow seed and barrier layer around 5 mm
in width (much more narrow than today’s usual full Ag line widths of 60–100 mm), and around 1.0 mm in height would be deposited in the trenches
via electroless plating, screen-printing, ink jet printing, or aerosol printing
[59,82]. (Our cost calculations for this step of the process flow are based
upon an electroless plating of the barrier layer, with SiNx:H serving as a built-in dielectric
plating mask.) The light induced electroplating process could then conceivably
be used to thicken the line, either with the same metal, or, if need be, with a
different metal (such as a Cu-alloy). This elegant plating process is driven by
employing the photovoltaic effect for a cell immersed in an electroplating
bath: after applying the necessary reduction potential and exposing the cell to
light, the photogenerated electrons flow to the surface and then into metal
ions within the surrounding solution [86,87]. The plating process continues
until the desired line conductivity (cross-sectional area) is reached, with
current cycle times being just a few minutes per cell [67,107]. As to what
metals could be used within the alloy, per the model provided by a relevant
equipment supplier, our specific cost-of-ownership estimates for such a plating
process are based upon a three bath sequence that produces layer thick-nesses of 3.0 mm for Cu, 3.0 mm for Sn, and 8.0 mm for Ag.


          The
light-induced plating approach has been used for quite some time in several
higher efficiency cell designs because it has demonstrated an absolute
efficiency improvement of at least 0.3–0.5% over screen printing [108]. One of
the main contributors to the efficiency improvement has been that this approach
to metallization can produce much narrower completed line widths of around
30–50 mm
[82,87,108]. This is advantageous in reducing losses to the Jsc due
to shadowing and reflection of light from the frontside metal. But using
narrower metallization lines does require using either a higher density of grid
lines on the wafer surface, or lines with a higher aspect ratio, in order to
limit resistive losses and to move the same amount of photocurrent as the wider
screen-printed lines. It is on this point that the laser groove serves yet
another purpose. Controlled by the trench depth and width, the height: width
metallization aspect ratio can be moved from around 1:4 to 1:2, and so the line
conductivity can be improved while also reducing the total amount of dead area
on the cell [86,87]. As final notes in addressing the replacement of
screen-printing with a laser-buried groove in the Technology Group 1 cells,
this concept has also been shown to reduce the area-dependent contact
recombination losses between metals and silicon [82]. Moving away from the
dielectric glass frit that is contained within Ag paste should also lead to
lower overall series resistance losses within the grid array [83].


5.3.3. Improved front- and back-side surface passivation,
back surface field, and backside mirror


          With
little time to lose, immediately after a solar cell absorbs light it is
necessary to drive the photogenerated electrons and holes towards their
appropriate electrode terminals before they recombine [109,110]. The average
time that is available to move a given charge carrier—before a recombination
process would be expected to occur—is called the charge carrier lifetime (t).
The corresponding average distance that the charge carrier will be able to
travel during that time is called the diffusion length (Ld). Ld is related to the lifetime by (Dt)1/2, where D, the diffusion
coefficient, is around 30 cm2/s for a minority carrier electron
within the bulk of a p-type c-Si wafer [111], and around 11 cm2/s
for a minority carrier hole within the bulk of an n-type c-Si wafer [112].


          Over
the course of their transitory lifetime, mobile charge carriers will spend relatively
more time either diffusing through the bulk of the wafer or in navigating the
wafer surfaces. The relative amount of time spent at either depends upon the
bulk diffusion length and the wafer thickness and size (in essence, for a given
diffusion length, the thinner and smaller in area the wafer is, the more
relative time a charge carrier will spend near the front, back, and edge
surfaces). While they are on the surface, the mobile charge carriers must
traverse a thicket of dangling bonds and other defects that can capture them
and trap them in place—at least until they either escape the trap and move onto
the next one, or until another oppositely charged carrier happens to come along
and the process of recombination occurs. The best strategies for keeping charge
carriers away and free from these traps are: (i) to create an electrical
potential energy barrier (specifically, a space-charge region around the p-/n-
electrical junction and a back surface field) in order to repel a chosen charge
carrier away from the surface in the first place; (ii) to reduce the rate of
surface recombination by reducing the concentration of one charge carrier type
at the surface; and (iii) to passivate all dangling bonds and defect states to
the fullest extent possible [102].


          Whether
or not one has been successful in this regard can be inferred from measurements
of the surface recombination velocity (SRV), which is parameterized separately
for the front and back. There are several built-in features within a standard
cell that lower the SRV to a level such that it can operate at least reasonably
well. The p-/n- junction on the wafer front surface is
the first such feature. By inverting the doping characteristics from p-type into n-type, the process of POCl3
diffusion creates a wafer front surface where the concentration of one charge
carrier (electrons) is significantly higher than the other (holes). After the
electrons migrate down their concentration gradient—from the sur-face into the
bulk—the resulting vacancies, or ‘holes’, that are left behind are positively
charged, and this creates an internal electric field within the solar cell
which works to repel charge carriers of one particular type (in this case,
other incoming holes) away from the surface [56]. With a lower surface
concentration of one particular charge carrier in the electron–hole
recombination pair, the overall rate of surface recombination is thus lowered.
On top of this junction, the SiNx:H anti-reflection coating also
helps to significantly lower the front SRV, from "250,000 cm/s to "40,000 cm/s,
by passivating surface defects and dangling bonds [113].









	
  

 	
  

 
	
 A. Goodrichetal./Solar Energy Materials&Solar Cells
 114 (2013) 110–135

 	
 123

 


          There
is also another built-in surface passivation on the back-side of the standard
c-Si cell called the high-low junction—named because the Si at the back region
is locally doped by Al to a higher, p+,
doping level (Nh+ "3
x 1018 cm-3) in comparison to the bulk of the base wafer (Nh+ "
1-2 x 1016 cm-3) [114]. As in the case of the emitter
junction (at least in the sense of the surface and the bulk possessing
different carrier concentrations), this high-low scheme establishes another
type of ‘charge carrier mirror’, or ‘back surface field’, which works to repel
minority carriers away from the rear surface of the wafer [56,115]. In the
absence of additional layers to passivate surface defects, however, the typical
back SRV realized for a full-area Al back surface field (BSF) in industrial
production is still very high, at around 1000 cm/s. With optimization, a simple
full-area Al BSF might be able to deliver a back surface SRV around 200 cm/s
[114,116].


          To
quote the publication directly: ‘the major advantage of the PERL cells is
passivation of most of the cell surface areas’ [95]. Even before the champion
PERL cell result, the first achievements of efficiencies greater than 20% can
also largely be attributed to the implementation of more effective passivation
techniques [117,118]. In light of this extremely important efficiency improve-ment
parameter, our roadmap and cost models incorporate enhanced backside
passivation techniques, beyond the simple full area Al BSF, for a more
efficient Technology Group 1 type of cell. As a minimum requirement, the
achievement of > 20% cell efficiencies may very well require that the total
back SRV be on the order of just 5-10 cm/s. Meanwhile, the front SRV achieved
with SiNx:H still appears to be acceptable for the purpose of achieving such
cell efficiencies [102].


          The
necessarily lower back SRV could be achieved by employ-ing the field-effect
passivation approach, whereby additional fixed negative charges are brought
into place on the wafer back surface. This could be achieved by depositing an
additional dielectric layer(s) between the Si and Al BSF [119]. There seem to
be numerous approaches, all of them industry-relevant, for achieving such an
end. The first option is to simply heat a wafer to high temperature in the
presence of oxygen. A thick layer of SiO2 would then be produced on
all wafer surfaces, as it was in the original PERL cell [95]. While not
demonstrated at large produc-tion volumes, a lower temperature alternative to
achieving an SRV similar to SiO2 is by the atomic layer deposition
of Al2O3 [120,121]. This is not the only low temperature
option, however. Each one capable of being deposited by industrial PECVD tools,
there are at least three other dielectric materials that can also achieve
similarly low back SRV: SiNx:H [102,122], undoped (intrinsic) a-Si:H
[102], and SiC [123, 124]. Another approach for a Technology Group 1 type of
cell might be to try some combination of the above, as is done in the
industrial passivated emitter rear cell (i-PERC) that uses an SiO2/SiNx:H
stack [72,119].


          For
the sake of brevity, our costs modeling results and process flow for Technology
Group 1 are limited in scope to the choice of a backside dielectric passivation
layer deposited by PECVD. This choice seems logical to us because, with regards
to SiO2 being deposited in a high-temperature furnace, there are
known material instability problems for standard B-Cz wafers under high tempera-ture oxidizing conditions (which the PERL cell
did not suffer because it utilized a float zone wafer) [60,125].
Furthermore, the potential need for additional masking steps only seems to
complicate matters for a marginal improvement in SRV [102,126]. Finally, p-type
Cz wafers in particular are
difficult to passivate uniformly with SiO2 under industrial
processing conditions [127]. As for the ALD approach, it is certainly
intriguing and may be a topic for future research.


          Among
the options available for the PECVD approach, it is not entirely clear at this
time which material would be best. Without commenting further on the choice of
a-Si (a perfectly viable option, which we address within the Technology Group HIT), SiNx:H
appears to be a good choice because it is a decent surface passivation layer
and it can also serve as a backside mirror of light [58]. As yet another
option, SiC is also an excellent passivation layer, as well as backside optical
reflection layer, that can be doped to assist with the overall cell mechanics
of bringing holes to the cell’s back surface [124]. Finally, either choice can
ostensibly offer similar solutions to the problem of wafer bowing during the Al
firing step [86]. Without having to decide between the two any further, they
both appear to be essentially equivalent because they essentially utilize the
same capital equipment, have similar thicknesses, and can both be made from
precursors with similarly low costs.


          The
final steps of our modeled Technology Group 1 process flow enable ohmic contact
between the silicon wafer and Al. For this there are two conceivable options:
either open the dielectric with a laser first, and then screen-print the Al; or
screen-print the Al directly on the dielectric first, and then use a laser to
drive metal melt-through [128–130]. Both options are estimated to be margin-ally
cost-equivalent, and only require that around 1% of the area on the backside of
the wafer be contacted by the metal (which is beneficial for making a backside
mirror of light, and in preventing wafer bowing). Within our process flow, we
have also assumed that, due to the Al–Si eutectic that is formed during
co-firing, an additional laser damage removal step will not be needed [115].


5.3.4. On the need for improved material
quality within the base wafer


          Boron
has a long history as the dopant of choice for standard silicon wafers because
its high segregation coefficient works to produce ingots having a very
reproducible and uniform distribution of dopant atoms along the entire length
of the boule [131]. This remains a highly desirable material property for wafer
manufacturers who must sell their product with a specified base resistivity,
which is principally set by the dopant concentration within the wafer. How-ever,
the inherent efficiency limitations for cells made with the standard B-Cz
wafers have been known for quite some time [132].


          The
first complication with standard B-Cz can be understood from how a dopant atom
incorporates itself into the silicon lattice, because each site that must
accommodate a dopant atom is a disturbance to the symmetry of the crystal. Even
though the concentration of these asymmetries is usually extremely low (on the
order of ppm), if the difference in size between the dopant atom and silicon is
significant enough, the process of recombination can be accelerated over a
network of the asymmetries, or ‘misfit dislocations’, that propagate throughout
the bulk of a wafer [133]. To begin understanding how these misfit dislocations
might vary depending upon the choice of dopant, the atomic radius of silicon is
1.18 A—and this can be compared to that of phosphorus, with an atomic radius of
1.06 A; gallium, with an atomic radius of 1.22 A; and boron, with an atomic
radius of 0.88 A [70,134].


          The
symptoms of increased bulk recombination—be it from misfit dislocations or
other factors—can be diagnosed from measurements of minority charge carrier
lifetimes. By these measurements, a few general patterns can be gleaned from
the published literature: both before and after a typical cell processing
sequence, as well as after illumination, Ga-doped Cz wafers (Ga-Cz) will retain
lifetimes on the order of hundreds of microseconds [70,135]; P-doped Cz wafers
will retain lifetimes on the order of milliseconds under the same stresses
[125,133]; but the lifetimes of the traditional B-Cz wafers will rapidly decay
from the hundreds of microseconds to the tens of microseconds [125,136–138].


          A
careful reading of the same literature, however, also highlights a second and
more significant explanation for the observed changes in carrier lifetimes
within B-Cz wafers. During the Cz pulling of ingots, it is unavoidable that
oxygen from the silica-based crucible is released into the melt, where it is
strongly attracted to boron. As the melt









	
  

 	
  

 
	
 124

 	
 A. Goodrichetal./Solar Energy Materials&Solar Cells 114
 (2013) 110–135

 


solidifies
during the pull, these boron–oxygen pairs can remain in place within the
crystal lattice. By first observing that the presence of oxygen very much
coincides with the light-induced carrier lifetime degradation effect seen in B-Cz wafers, and then by carefully
monitoring the concentration of both the boron and oxygen species within a
defined ensemble of wafers, it can be seen that the lifetime degradation
typically seen in B-Cz wafers is
due more to the presence of oxygen than it is due to the presence of boron
[125,139]. To quantify the experimental observations, the concentration of the
metastable boron–oxygen complexes that lead to the lifetime degradation
depends quadratically on the concentration of oxygen and linearly on the
concentration of boron [140].


          To
stick with the boron dopant, but to also mitigate the deleterious effects of
boron–oxygen complexes, it is generally helpful to use wafers with the lowest
concentration possible for both species [141,142]. To offer a reduced
concentration of boron, cell manufacturers could conceivably adopt higher
resistivity wafers. But there is a very narrow limit to how far this can be
exploited because there is a tradeoff in the form of an increased Jo—and a correspond-ingly lower
Voc and FF—as it becomes
increasingly difficult to achieve acceptable ohmic contact resistance between
high resistivity silicon and metal electrodes [113,143]. As for how to reduce
the concentration of interstitial oxygen, the currently best-known solu-tions
seem to involve alternative approaches to crystal growth—the foremost being
either the float zone (Fz), or magnetically confined Czochralski (M-Cz)
techniques [70,71,144]. These alternative approaches to crystal growth offer a
reduced concentration of interstitial oxygen, either because they do not use a
silica-based crucible (Fz), or because there is better control of the
convection currents within the silicon melt that are exposed to the crucible
(M-Cz) [30]. Either approach can deliver wafers with lowered oxygen content,
and, depending upon the base resistivity, stabilized carrier lifetimes ranging
from the hundreds of microseconds to several milliseconds [69,70,135,145].
However, even though the original PERL cell was built upon a Fz base wafer, the
M-Cz option is currently the more commercially relevant because Fz ingots are
significantly more expensive to produce and have traditionally been limited to
a much smaller diameter [146].


5.4. Technology group 2: the interdigitated back contact
(IBC) c-Si solar cell ("25% cell efficiency)





5.4.1. On the benefits and requirements of making a c-Si
solar cell with hidden metal electrodes


          One
of today’s more esthetically pleasing PV modules has no obvious metal
connections on top of or between the cells. Even to a layperson this design
makes sense because there should be increased absorption in the solar cell by
eliminating frontside metal grid shading—and indeed the relative gain in Jsc to be enjoyed by
eliminating these optical shadowing losses is a notice-able 5–10% (depending
upon the finger and busbar layout for the front-contacted cell [61]). As
another, not-so-obvious benefit of this design, by locating the metal contacts
on the back there can also be a much greater emitter-to-metal area coverage.
This helps mitigate FF losses, because there can be an overall lower series
resistance without also increasing optical shading and reflection losses at the
same time. But, in terms of enabling the full efficiency potential of c-Si in
commercial-production, there are other advantages to this architecture that are
just as hidden as the metal contacts.


          In
a rear-contacted solar cell, charge carriers generated from the absorption of
light near the front surface of the wafer—as most are—must traverse the entire
wafer thickness in order to reach the interdigitated array of metal electrode
terminals and p-/n- electrical junctions that are located
on the back. With corresponding lifetime requirements in excess of 2 ms for
today’s typical wafer thickness [65], and with a requirement that the wafers be
obtained from industry-relevant manufacturing methods, this currently limits
the wafer choice to just one option: those with an n-type (phosphorus) base
made by the Cz approach [54,78,147]. This is because, although the M-Cz option
can greatly reduce the concentration of problematic boron–oxygen complexes,
and the Ga-Cz option can offer light-stabilized lifetimes on the order of
hundreds of microseconds, largely due to a much lowered sensitivity to residual
metallic and carbon impurities it is still the P-doped Cz option that most
consistently delivers wafers having light- and temperature-stabilized carrier
lifetimes on the order of milliseconds [88,141,148].


          Because
the carrier diffusion lengths for an optimized back-contact solar cell do have
to be so high, free charge carriers within these cells will spend more time
interacting with all of the wafer’s surface areas [80]. This makes
consideration of the total SRV even more critical for an IBC cell than for cells
made with a lower lifetime base material. Most generally because of the
stability of n-type wafers under high temperature oxidizing conditions—
especially relative to the standard B-Cz wafers—this requirement can be easily
addressed by utilizing the excellent dielectric sur-face passivation properties
of SiO2 [79], which affords uniform coverage over the entire wafer
front, back, and edge surfaces in one simple thermal processing step. On the
front of an IBC cell, after establishing a front surface field via approaches
such as light POCl3 diffusion [97,149], a SiNx:H on SiO2 stack can
provide three advan-tages: very high quality surface passivation, high
transparency to sunlight, and excellent antireflection properties. On the back
of the cell, an optically thick layer of Si/SiO2 on a back metal
stack provides very high reflectivity due to the very low refractive index of
SiO2 (n=1.46)
[63,64,86,126]. Finally, due to the proximity of the emitter and base contacts
within the backside array, in an IBC cell a material that is capable of
electrically isolating each n++
and p+ diffusion
should be also be present in order to mitigate current leakage—yet another need
that can be met with SiO2 [88,150].


          In
consideration of the ability of P-doped Cz wafers to use SiO2 for
all of these purposes, and in consideration of the fact that it can be
deposited very easily and cheaply in industrially scalable processes, we have
incorporated a thermal oxidation step within our process flow used to model the
costs of IBC cells (Fig. 8). Most of the concepts and processing steps that we
apply are similar in nature to those discussed within the Standard and
Technology Group 1 sections. Significantly, however, we have called upon a
different procedure (step 5) for the drive-in of additional P dopant atoms in
order to make the n++
diffusion region.


          Because
the electrical connections to the base (back surface field) contacts must also
be incorporated into the same area that









	
  

 	
  

 
	
 A. Goodrichetal./Solar Energy Materials&Solar Cells
 114 (2013) 110–135

 	
 125

 





Fig. 8. Modeled process flow for fabrication of the Technology Group 2 (IBC)
c-Si solar cells.


would
otherwise be fully available for collecting and moving charge carriers to the
emitter contacts, the total area available for the capture of the all-important
minority charge carriers is reduced for an IBC cell relative to a
front-contacted cell. For the case of an n-type
base, this means there is a reduction in the probability for capturing minority
carrier holes, before they recombine with majority carrier electrons, because
there is less area with which to do the capturing. This is a problem more
generally called ‘electrical shading’ and, if not handled appropriately, it
can noticeably compromise the efficiency gains that are enjoyed by an IBC cell
by virtue of the fact that it eliminates optical shading losses [76,77].


          To
address this efficiency loss mechanism, the general goal should be to maximize
the total area of the p+
emitter diffusions while minimizing the total area of the n++ base diffusions. Moreover,
this must also be achieved within an interdigitated array having base diffusion
line widths that are as narrow as possible, and with an optimized spacing
[88,151,152]. To achieve the very narrow, very precise, and high aspect ratio
base diffusion profiles that may be needed for this optimization, we make an
accommodation within our process flow that the n++
diffusion in a fully-optimized IBC cell may require something beyond simply
exposing wafers to POCl3 and/ or screen-printing a dopant paste. Our
cost modeling analysis is based upon a compilation of manufacturing costs
related to the dry and in-line process of precision patterned ion implantation
[73–75], which has already been commercially developed for the much more
technologically complex integrated circuits industry [153], and which is just
now being developed to achieve wafer throughputs that are relevant to the PV
industry [154].


5.5. Technology group 3: the heterojunction with intrinsic
thin layer (HIT) cell ("24% cell efficiency)





          As
the final cell architecture considered within this roadmap, we consider cells
which utilize very thin a-Si:H layer stacks on









	
  

 	
  

 
	
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Fig. 9. Model process flow for fabrication of a bifacial Technology Group 3
(HIT) cell.





Fig. 10. Sensitivity of minimum sustainable wafer prices to changing ingot wafer
yields and initial capital equipment outlay, based upon 1 H 2012 polysilicon
prices (blended price of $35/kg) and the wafering cost analysis outlined in
Section 4. The horizontal dashed line represents the baseline (180-mm) B-Cz wafers shown in Fig. 5.


n-type
wafers to provide surface passivation, emitter formation, and a back surface
field [81]. Not only have these ‘HIT’ cells achieved commercial-production
efficiencies that are a close second to the IBC cells [155], they can also
offer some compelling benefits at the LCOE level as well. First, high Voc HIT cells offer a
temperature coefficient that can be slightly lower than the IBC cells, and
almost half that of a standard c-Si cell [92]. Second, HIT cells easily offer the
possibility to realize bifacial structures, which can lead to greater total
harvesting of solar power over a system’s lifetime [156]. HIT cells offer
another potential benefit in that they can be fabricated using a very simple
processing sequence that can be carried out—in its entirety—below 200 1C
[112,157].


          A
typical architecture for HIT cells is shown above, and a representative
sequence for fabricating them is shown in Fig. 9. When fabricating these p-/i- and i-/n-
stacks, the thickness of the intrinsic and doped a-Si:H layers must be
carefully optimized with two conflicting requirements. On the one hand, the Voc and FF generally increase
as the front layer stack is increased, and then levels off at around 20 nm
total thickness. As a tradeoff, because of undesired absorption in the a-Si:H
layers, the Jsc gradually
decreases for all total layer thicknesses greater than around 5 nm [158]. This
preference for the minimum allowable a-Si:H layer stack thickness stems from
the fact that it is generally more advantageous to allow the sequence of light
absorption and charge carrier separation to occur within the crystalline
wafer—rather than within the amorphous layer—because the material defect
density is significantly higher in a-Si:H [157,159,160]. On the bottom of the
wafer, excellent surface passivation is provided by a back surface field that
can be formed









	
  

 	
  

 
	
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 114 (2013) 110–135

 	
 127

 


by
depositing an n-doped a-Si:H layer on top of an intrinsic a-Si:H layer, with a
combined optimal thickness for these two layers somewhere in the range of 20–50
nm. Without knowing what the actual layer thicknesses need to be on either side
of an optimized HIT cell, we have expressed these ranges in Fig. 9 and use the
middle values for each within our cost models.


          Because
the chemical processing sequence that takes place immediately before the a-Si:H
deposition is critical to obtaining a high Voc,
the exact recipe and processing details of this step in the HIT process flow is
one of the more proprietary trade secrets in PV. In laboratory-level research,
a wet chemical bath treatment called the ‘RCA clean’ is typically employed
[161]. But this specific cleaning process would likely be too expensive for mass
production of solar cells [160]. While not having the exact recipe that is
used to fabricate the most efficient HIT devices, we assume that some form of
wet bench treatment is nevertheless still necessary immediately prior to the
intrinsic a-Si:H layer deposition. We base our cost estimates for this step in
the process flow upon the single step of HF oxide removal (step 3), after the
description given in [162].


          One
of the last steps for fabricating a HIT cell is to deposit a transparent
conducting oxide (TCO) layer, which is step 6 in our model process flow [160].
The first purpose of this layer is to facilitate better charge carrier
collection (because a-Si:H has a very low lateral mobility for free
charge-carriers, but a TCO on its surface can greatly assist in shuttling
mobile charge carriers to the metal electrodes with low series resistance
losses). The second purpose of the TCO is to serve as an AR coating. While
fulfilling its dual purposes, the exact thickness and conductivity the TCO layer
should be optimized towards the best-possible cell efficiencies. This typically
means that consideration of the optical clarity and AR properties leads to very
thin layers having a less-than-optimal conductivity (because a ‘transparent’
electrode generally inhibits the complete passage of light to some degree, and
because this parasitic absorption is most significantly influenced by the
thickness and the free-carrier concentrations within the layer [163]). While
there may be several material options for the TCO, the better-known solutions
at present are indium tin oxide (ITO) or zinc oxide doped with either boron or
aluminum. While it is worth noting that other deposition techniques such as
chemical vapor deposition may also present opportunities for forming TCO
materials on HIT cells, our specific process flow calls for ITO deposited by
sputtering—mainly to highlight that the calculated costs for using this very
thin layer of a precious material are probably lower than one might think.


          The
metallization of HIT cells can most simply be achieved through the standard
process of screen-printing, and indeed this is presumably how it is most
frequently done in commercial production. However, the a-Si:H layers cannot be
taken to a deposition temperature above 200 1C, and this requirement then
excludes the use of the standard screen-printed metal pastes. This requirement
for low-temperature metallization can be a significant drawback for HIT cells,
as the total amount of the low-temperature paste that is needed is greater
because the resistivity is a factor of two to four times higher than the
standard pastes. Meanwhile, the price for the low temperature pastes, at around
$1700/kg, is also notably higher than the price for the standard pastes, at
around $1300/kg (2012 U.S.). These dual factors— metallization price and
resistivity—present some severe cost hurdles for HIT cells when the standard
process of screen-printing is employed. For this reason, and because we have
also called upon the same path for the Technology Group 1 and IBC cells,
towards the end of our HIT process flow we call upon the lower cost
metallization process of electroplating a Cu-alloy on top of an electroless
seed of Ni. To prevent uniform plating of metal over the entire surface of the
TCO, we have also included an additional low-cost patterning step in the
process [164]. For our purposes this is assumed to be screen-printing of a
resist mask, followed by its removal in an industry standard solution.


          The
next reasonable question then becomes the cost for the electroplating sequence
relative to the cost of screen-printing copious amounts of expensive silver. In
the next section, we address this question and other questions that might
naturally arise for the different cell designs that have been presented.


5.6. Cells cost analysis: the overall results and some
specific points of note


5.6.1. On the potential price premium for higher lifetime
wafers


          To
begin a discussion on costs, because the two are so intimately related it is
first necessary to provide some necessary disclaimers on the assumed
efficiencies. A significant assumption underlying the efficiency projections
shown in Table 3 is that the higher efficiency cells must be built upon a
foundation of higher quality starting material than the standard B-Cz wafers.
In total, a full 1–2% improvement in the absolute efficiency, above the
standard cell, may be possible solely due to the utilization of higher lifetime
wafers [88, 135].


          The
conventional thinking is that, in order to provide higher lifetime wafers to
cell manufacturers, for one of two reasons there should be an attached price
premium—either because wafer manufacturers must charge more because they will
have suffered higher yield losses in the alternative dopants case, or because
of additional capital equipment and energy costs if they were to attach
magnetic systems to Cz pullers.


          Allow
first for some explanation of what is meant by ‘higher yield losses in the
alternative dopants case’.


          The
traditional boron dopant, with a relatively high segregation coefficient of
0.8 [42], has an inherent propensity to dis-tribute very well during the
process of pulling a Cz boule.
This then directly leads to variations in base resitivity that are typically
very low, at less than 0.5 Wcm, for all wafers taken along the entire length of
the boule [135,144]. In the absence of additional sorting steps to more
carefully bin wafers by their base resistivities, by virtue of their being
taken from different parts of a boule, this low variation enables a
corresponding consistency in current and voltage for essentially all cells made
from all as-received B-Cz wafers.
The desire to have this consistency is certainly clear (it is, to begin,
crucial for reducing the cell-to-module derate), and it is in this respect that
the yield loss for wafers made with the B dopant is nominally zero.


          But
not everything is ideal for the B-Cz wafers because they are, to one degree or
another, vulnerable to problems associated with metastable boron–oxygen
complexes. One demonstrated solution to this problem is to use alternative
dopants—such as Ga for making p-type wafers or P making for n-type wafers. With
lower segregation coefficients, however, these alternative dopants do not
distribute as uniformly as boron does—leading directly to greater axial
variations in base resistivity, and, potentially, corresponding yield losses
because not every wafer is usable to cell manufacturers. Quantifying these
yield losses would require knowing the average number of wafers per ingot that
are unsellable, based upon how the average resistivity varies for wafers taken
from different sections of all produced ingots, and exactly what range of base
resistivities cell manufacturers are interested in buying. For the standard cell
made with p-type wafers, the allowable range of base wafer resistivity is
generally anywhere between 0.5 and 3 W cm [142]. While such a range is easily
achieved with the boron dopant, this desired resistivity range would correspond
to a wafer yield loss of around 25% for a Ga-doped Cz ingot produced by single charge loading and without
semi-continuous feeding [144,165].









	
  

 	
  

 
	
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          To
partially offset this material yield loss in wafering, the head, tail, and
chord scrap of an ingot made with a low segregation coefficient dopant can
still be recycled for later rounds of Cz
ingot pulling. While incorporating this partial material recovery into the
wafering cost model, in Fig. 10 we display the sensitivity of minimum
sustainable wafer prices to the material yield loss in the wafers-only section
of the ingot. For a 25% wafer loss, by our analysis a maximum increase in wafer
price of around 10% would be necessary.


          Since
Phosphorus has a much higher segregation coefficient than Gallium (0.35 versus
0.008 [135]), a less than 25% yield loss would be expected for the P-doped Cz wafers. As an additional consideration
for selling such n-type wafers,
the allowed base resistivity can actually be unique for each c-Si cell
manufacturing process—with a much broader range of 2–10 O cm allowed for cells
made on an n-type base [78,149,166]. In that case, such an allowable range
would translate to no yield loss, and therefore no necessary price premium, for
the doping of Cz ingots with
Phosphorous. Of course, this explanation does not exactly match the historical
pricing trends where there was a price premium for n-type wafers. But it is a consensus echoed by every
interviewed industry collaborator: any price premium that may have existed for
the n-type Cz wafers was simply a result of their
being a product for a ‘niche market’, and not because there is some upstream
loss in wafer yield.


          For
the purpose of characterizing the costs associated with the magnetically
confined Cz process, the lower
curve in Fig. 10 corresponds to the relationship between minimum sustainable
wafer prices and any additional capital equipment and energy costs that may
exist for the Cz pulling of
ingots. The baseline wafer price, equal to $76/m2, was derived in
Fig. 5. The first calculated small revision upwards in cost—the higher
y-intercept of around $2/m2—is due to the additional energy
requirements of a typical M-Cz
system. This price correction is based upon an aggressive assumption that 1980
kWh of additional electricity would be required for each 2.158 long, 205 mm diameter
boule that is produced (and detailed in Section 4).


          With
respect to the additional capital equipment costs for the M-Cz attachment, the necessary wafer price
is estimated to have a linear dependence. From a survey on crystal growth equipment,
we gathered that the applicable M-Cz
pullers came with an additional median cost of around $200,000 (current U. S.),
although it could be twice that much for the more expensive option that
employed superconducting magnets [146,167]. By our sensitivity analysis the
additional capital equipment costs over that range would translate to an
additional price premium of $3–$6/m2 of wafers produced. At 20% cell
efficiency, this would translate to a cost penalty of just $0.01–$0.03/W.


          Ultimately,
all signs are that any additional costs that might be associated with
fabricating higher lifetime wafers are probably quite small. For making p-type
wafers, it would also appear to be a difficult decision between using an
alternative dopant such as Gallium—with its potentially compromised wafer
yield—versus making a bigger investment in the capital equipment and energy
inputs for M-Cz. (Although, for
any yield loss expected to be greater than around 20%, there may be an
advantage in paying that little extra for the M-Cz upgrade—instead of being
left to wonder just what to do with all those boxes filled with unsellable
wafers.)


5.6.2. Some statements on the overall cells cost analysis


          In
Fig. 11, the results are shown for the projected manufacturing costs of the
Technology Groups 1–3 cells, with the cost-of-ownership models for each step of
the process flows shown in Figs. 7–9. (Please see the supplementary information
for a breakdown of costs for each step). In the long-term case it is assumed
that the n-type wafer price is $22/ m2, corresponding to the


80-mm kerfless wafers shown in Fig. 5. That is, it
is assumed that there will be no long-term price premium for those wafers due
to potential yield losses in wafering. In order to attach the potential price
premium for higher lifetime p-type wafers, the wafering cost model was rerun at
the 80-mm
thickness. The curves for those thinner wafer curves were similar to Fig. 10
and showed a marginal penalty of just $1–$2/m2 for the M-Cz option. This less than $0.01/W penalty
is included within the projected costs for the Technology Group 1 cells shown
in Fig. 11. For all cell types, the results shown assume that the yields in
cell manufacturing are constant—even for the case of thinner wafers.


          The
IBC cells appear to have the highest total expected depreciation expense;
however, the difference becomes significantly reduced for similarly sized
wafers. This is because the modeled process flows for the Technology Groups 1
and 2 are actually very similar, and because the effective throughput of the
cell manufacturing equipment is estimated to be lower for smaller area wafers
(if equipment is sold based upon throughputs measured in the number of wafers
per hour, then for a given production volume more pieces of equipment must be
purchased in order to handle more smaller area wafers). This is why, for the
sake of comparison, we include a case that might be made for the Technology
Group 1 cells to be fabricated on 160 mm wafers.


          In
further regards to the depreciation expense for the IBC cells, we also
calculate that the capital costs for the ion implantation tools may not be as
significant as one might think. With a wafer throughput of roughly 1100 wafers
per hour for a roughly $1.5 million machine, by our calculations ion
implantation contributes less than $0.02/W to the total manufacturing cost for
our model IBC cells.


          In
light of the compelling efficiency for the HIT cells, and by virtue of the fact
that they have a very simple manufacturing process, it comes as no surprise
that they are also calculated to have a very competitive manufacturing cost.
But that calculated result is contingent upon the replacement of the
screen-printed, low-temperature Ag pastes with an electroplated Cu alloy.


          Because
the processing temperatures for HIT cells must generally be kept below 250 1C,
the cocktail of binders within the low-temperature metallization pastes differ
from the binders that can be used in the standard metallization pastes (which
can be made from materials that are more easily removed at the typical 800–900
1C temperatures endured during a standard co-firing step [160,163]). This
currently leaves the low-temperature metallization with a compromised
resistivity (typically between 15–25 mW per square for 25 mm of planar paste thickness) relative to the
standard Ag pastes (typically between 4 and 5 mW per square for 10 mm of planar paste
thickness) [168]. To overcome the higher resistance within the low-temperature
paste, but to still keep the I2R losses constant, there are several
approaches that can be employed: use gridlines with a greater cross-sectional
area; use more tightly spaced gridlines (although this comes with a trade-off
in that more busbars are needed, and in optical shading), and use smaller
diameter wafers.


          By
our calculations, to achieve a similar resistivity it is still necessary to
deposit around four times as much low-temperature paste per unit area of
manufactured cells—even when using 155 cm2 wafers instead of 237 cm2
wafers, and even when employ-ing an optimized metallization geometry.
Considering the $1700/kg price for the low-temperature paste versus $1300/kg
for the standard paste, and with a total baseline material requirement of
around 200 mg of Ag paste for the frontside grid and rear busbars for every 17%
efficient 237 cm2 cell made in the standard process [169,170], a
quadrupling in the area-based paste requirement would









	
  

 	
  

 
	
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 114 (2013) 110–135

 	
 129

 





Fig. 11. Cost model results for cells for the Standard and Technology Groups 1–3
cells. Top: cell costs derived with typical 2012 wafer thicknesses (shown at
the bottom of each bar), and the wafer prices depicted in Fig. 10. Bottom:
estimated cell-processing costs with either the 80-mm or the 160-mm wafers, where all cells are made from $23/
kg polysilicon and the future-case wafer price premiums mentioned in the text.
The WACC used for assigning the required margin is 8.6% in the 2012 scenario
and 6.2% in the long-term scenario.


then
work out to a metallization cost disadvantage of around $0.17/W for the 24%
efficient 155 cm2 HIT cells.


          This
certainly helps to explain why the HIT cells in particular could benefit from
alternative metallization schemes. With the requirement that any alternative
metallization scheme must still be a low-temperature process, it is perhaps
logical that it would be most beneficial for HIT cells to call upon the process
of electroplating. This process was also used as a metallization procedure in the
Technology Group 1 and IBC cell models; but, in the case of the HIT cells there
would have to be an additional masking step in order to carry out the
electroplating within a precise pattern (otherwise, without a mask, there would
be metal deposited over the entire surface of the TCO). The relevant
cost-of-ownership model that we were provided for the screen-printing of a
masked resist would be expected to add around $0.01/W for both the front and
rear sides. Presumably there should also be a mask removal step, but—if it can
be done with an industry standard resist stripping solution—this is also a
conceivably very cheap step (so cheap, in fact, that even in tandem with
chemical edge isolation the two-step wet bench process would only cost around
$0.02/W total).


          To
conclude the discussion on cells, several of the cell processing flows
referenced the PECVD deposition of SiNx:H,
Si:C, or a-Si:H layers. The sputtering of ITO was also mentioned. For all of
these layers, we find that the depreciation expense is relatively consistent
over the range of projected thicknesses. This is because the total cycle times
depend more upon the longer steps of wafer handling and pump-down than the
total times required for depositing even the thickest layers. We also find that
the sputtered ITO layer in the HIT cell is more affordable than one might
think. Primarily because









	
  

 	
  

 
	
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 A.Goodrichetal./Solar Energy Materials & Solar Cells
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it
is a very thin layer, our estimated net material costs for sputtering 75 nm of ITO from a rotary target are less than
$0.02/W for each side of the bifacial cell. Knowing this, and knowing
that the electroplating of Cu on a HIT
cell has recently been demonstrated [164], from a costs standpoint it
would be a pretty tight contest between all three of these modeled c-Si solar
cell architectures.


6. Modules


          In
the final step of the c-Si supply chain, completed cells are incorporated into
modules by first electrically connecting cells together into strings with conductive
solder and tabbing ribbons. The ends of those strings are then soldered onto
bussing ribbons. To protect this assembly from the elements, it is encased
within a top-bottom stack of encapsulant films—typically ethyl vinyl acetate,
or ‘EVA’—that have been melted (Tmelting
"145-160 0C)
and vacuum-laminated onto the array. During this encapsulation step, the
assembly is also bonded to a sheet of front glass and to a backside film or
glass with a tape that is dispensed around the perimeter of the module. An
aluminum frame is also oftentimes fit around the perimeter of the module—with
the benefits that it can be used to protect the module edges, to provide a
connection point for electrical grounding, to support snow and wind loads, and
to make the module installation an overall easier process. (The frame is,
however, a relatively expensive component, and there is still an open debate
within the industry for how to realize those same benefits at a reduced cost.)


          The
array of bussing ribbons connected to the ends of each series of strings is
then crimped towards a through hole in the module backsheet film. The bussing
ribbons are connected to bypass diodes, which are housed inside an electrical
junction box, or ‘J-box’. The purpose of these bypass diodes is to prevent excessive
reverse current flow and power consumption in cells that may be receiving
different amounts of sunlight, such as when the module might be partially
covered with snow, dust, or leaves, or by some other obstruction [171]. As a
final step in module assembly, the ‘J-box’ is set in place with adhesive
sealant on the bottom of the backside film.


          The
materials and equipment for this final step of the supply chain have become
fairly standardized over the years. In Table 4, we detail the typical costs for
these materials in early 2012, roughly averaged over numerous conversations
with c-Si module


Table 4


Balance-of-materials costs for c-Si module manufacturing,
aggregated from several suppliers for each. The module dimensions are assumed to
be 1.65 m x 1.20 m for the large-area (237 cm2) cells used for the 180- or 160-mm thick Standard and Tech Group 1 designs (which
corresponds to 72 cells per module), and 2.26 m2 for the small-area (155 cm2)
cells used for the 140- or 80-mm thick Tech Groups 1-3
designs (which corresponds to 128
cells per module).


	
  

 	
  

 
	 

 	 

 
	
 Balance of
 material costs for modules

 	
  

 
	 

 	 

 
	
 Material

 	
 First half
 2012 costs

 
	 

 	 

 
	
 Long-term cell prices (See Fig. 11)

 	
 $0.77-$0.41/Wp

 
	
 Stringing and tabbing ribbons, metal solder and busing ribbons

 	
 $2.50/module

 
	
 J-box containing the bypass diodes

 	
 $5.00/module

 
	
 J-box sealant, bonding tape, printed module sticker label and bus bar
 covers

 	
 $1.50/module

 
	
 Aluminum frame

 	
 $20/module

 
	
 EVA (2 sheets needed)

 	
 $3.50/m2 for
 each sheet

 
	
 Backsheet film (Polyvinyl fluoride, and/ or UV- and
 chemically-stabilized polyethylene terephthalate)

 	
 $8/m2

 
	
 Premium front glass: 3.2 mm, low [Fe], tempered, with AR coating

 	
 $16/m2

 
	
 Estimated module materials costs

 	
 $1.08–$0.61/Wp

 
	 

 	 

 


manufacturers
and their primary material suppliers. In consideration of the optical
properties that may be needed within the front glass in order to achieve the
target module efficiencies (i.e., in an effort to reduce the amount of
parasitic light absorption from certain contaminants such as Fe), and to ensure
the mechanical robustness of modules, we have assumed that the highest quality
front glass might be needed. There are certainly cheaper types of glass that
are available, however. (Please see the supplementary information for other
possible front glass cost assumptions).


          Within
the industry, an intensive effort is underway to identify lower cost module
materials and processes. But the adoption of these new approaches is tempered
by a very clear need to maintain product bankability. This makes it unlikely
that these materials will be significantly changed for at least the foreseeable
future. Over the long-term, however, it is possible that the movement to thin
or ultrathin wafers may necessitate that the final module materials be modified
or even incorporated into wafer handling and cell processing, as many of the
ideas that have surfaced for reducing wafer thickness frequently hinge upon the
need to use the final module materials as a mechanical support and/or
electrical conduit for the more delicate wafers. For exam-ple, the front
glass/encapsulation combination may need to serve as an adhesive support for
wafer bonding and cleavage from an epitaxial substrate; or a conductive film,
paste, or epoxy may be needed to electrically connect very thin cells, should
the stresses of conventional tabbing and stringing prove to be devastating
[172–175].


          Without
knowing the exact characteristics and purposes of these next-generation module
materials, it is correspondingly, difficult to speculate on what their
associated costs might be. Thus, as things stand, there is little choice but to
assume the same balance of module materials costs shown in Table 4 within the
long-term module price projections shown in Fig. 12. With the balance of module
materials constant across all technologies, it is the difference in cell
efficiencies that explains the final—very subtle—differences in costs in
dollars-per-watt terms. Within the figure, the minimum required margins for
meeting a 6.2% WACC are also included for each cell type, and this is why the
costs shown in Table 4 are slightly lower than the final minimum sustainable
module price numbers seen within Fig. 12.


7. Conclusions


          The
analysis described in this paper is limited in scope to the Cz approach for
making crystalline silicon ingots and the wire sawing of wafers. As a major
step for reducing costs within this infra-structure, the complete elimination
of kerf loss could prove to be a very fruitful endeavor, yielding as much as
$15/m2 in savings. One possibility for wafer manufacturers to
realize these savings may be through the recycling of kerf after switching from
standard-wire sawing to diamond-wire sawing. Within this scope of c-Si manufacturing,
there is also a generally held boundary condition that the wafer thickness must
be 80-mm or
greater [41]. If manufacturers at all steps of the supply chain can
successfully operate at this wafer thickness, at minimum sustainable
polysilicon prices we calculate a cost benefit of around $9/m2 of
wafers produced, relative to the materials cost for producing today’s standard
180-mm wafers. But the
calculus of wafer thickness must also consider that the mechanical yields for
all steps in the supply chain can vary as a function of thickness, that there
might have to be modifications to the capital equipment at each step, and that
there can be problems with wafer bowing. As there have been historical
disadvantages associated with each of these considerations as the wafer
thickness is reduced, and knowing that the total potential savings for the 180-
versus 80-mm
wafers works out to just $0.04–$0.05/W, in the









	
  

 	
  

 
	
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 114 (2013) 110–135

 	
 131

 





Fig. 12. Top: Cost model results for completed modules: a compilation of
estimated costs for manufacturing standard modules and advanced modules within
the full c-Si supply chain, assuming all products are transferred at minimum
sustainable prices. The numbers underneath each cell type indicate the assumed
module efficiency and wafer thickness for each. The long-term scenario reflects
the projected costs and prices for modules made with cells on 80-mm wire-sawn kerfless wafers at minimum
sustainable polysilicon prices (see Figs. 5 and 11). Bottom:
efficiency-adjusted module prices for the different cell types, in
consideration of balance-of-systems savings (HIT and IBC) or costs (Standard
and Technology Group 1). For a rationale of these efficiency adjustments,
please see Ref. [176]. The BOS efficiency adjustments to the module prices are
normalized against the 20% module efficiency targeted within the U. S.
Department of Energy’s SunShot Initiative [177].


end
it is still unclear just how rapidly such drastically thinner wafers will be
adopted.


          We
have discussed some of the available opportunities for moving standard c-Si
solar cells toward higher sunlight power conversion efficiencies. The advanced
cell architectures needed to achieve these higher efficiencies would likely
require a greater initial capital equipment expenditure and higher materials
costs on a piecemeal basis; but by our calculations the resulting efficiency
improvements could very well translate to lower total module manufacturing
costs on a dollars-per-watts basis. With three advanced cell architectures in
hand, and with best-case wafer prices, we project that c-Si modules made from
wire-sawn wafers within the United States could conceivably move from 14.5–22%
efficiency and $1.10–$1.45/W mini-mum sustainable prices at the beginning of
2012 to 19–23% efficiency and $0.60–$0.70/W prices over the long-term. This
estimate supports the rigorous derivation of future c-Si module prices from
experience-based learning curves—where the ‘long-term’ price potential was
estimated by Nemet to be around $0.65/W [6]. But, while we deliberately shy
away from attaching specific dates to our guess of when the ‘long-term’ module
price might be equal to the actually sustainable module price, with a globally
strong demand for more PV deployment, and with all of the research and
development occurring









	
  

 	
  

 
	
 132

 	
 A.Goodrichetal./Solar Energy Materials&Solar Cells 114
 (2013) 110–135

 


in
c-Si, it may very well prove to be long before the ‘optimistic’ date of 2027
derived from his curve labeled the ‘aggressive scenario’.


Acknowledgments


          We
would like to acknowledge the following individuals for helpful comments,
corrections, and contributions during the preparation of this manuscript:Allen
Barnett (The Universities of Delaware and New South Wales), John Benner
(Stanford University), Tonio Buonassisi (The Massachusetts Institute of
Technology), Denis De Ceuster (TetraSun), Charles Gay (Applied Materials),
Martin Green (The University of New South Wales), Steven Hegedus (The
University of Delaware), Stefan Ko'stner (Max Planck Institute), Sarah Kurtz
(NREL), Minh Le (The U.S. Department of Energy), Margaret Mann (NREL), Robin
Newmark (NREL), John Lushetsky (The U. S. Department of Energy), Douglas Powell
(The Massachusetts Institute of Technology), Hans J Queisser (Max Planck
Institute), Ramamoorthy Ramesh (The U. S Department of Energy and The
University of California, Berkeley), Doug Rose (SunPower), Oliver
Schultz-Wittmann (TetraSun), Ron Sinton (Sinton Instruments), and Richard
Swanson (SunPower).


          We
would also like to thank our many industry collaborators who provided the cost
data that made this manuscript possible, as well as those who served for SOLMAT
as anonymous reviewers. SolMat Editor: Greg Smestad, Graphics Artis): Alfred
Hicks, Technical Publications Editor (NREL): Kendra Palmer.t (NREL).


Appendix A. Supporting information


          Supplementary
data associated with this article can be found in the online version at
http://dx.doi.org/10.1016/j.solmat.2013.01.030.


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