# Patent

## Title
Switched mode assisted linear regulator with AC coupling with capacitive charge control

## Abstract

The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator include configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. In one embodiment, the linear amplifier is AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control. In another embodiment, the amplifier includes separate feedback loops: an external relatively lower speed feedback loop may be configured for controlling signal path bandwidth, and an internal relatively higher speed feedback loop may be configured for controlling output impedance bandwidth of the linear amplifier.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
Priority is hereby claimed under USC§119(e) to U.S. Provisional Application 61/681,901 (Texas Instruments docket TI-88379P, filed Aug. 10, 2012), and to U.S. Provisional Application 61/681,880 (Texas Instruments docket TI-88381P, filed Aug. 10, 2012).


BACKGROUND
1 Technical Field
This Patent Disclosure relates generally to hybrid or composite amplifier/regulator architectures that combine a switched mode amplifier/regulator and a linear amplifier/regulator, also referred to as a linear assisted switched mode or a switched mode assisted linear architectures.
2 Related Art
In one application for hybrid architectures, a hybrid regulator includes a switched mode converter (or switched converter) and a linear amplifier coupled in parallel at a power output node, and cooperatively controlled to supply regulated load voltage and load current. In such hybrid regulators, the higher bandwidth but less efficient linear amplifier supplies the higher frequency content of the output power, while the more efficient but lower bandwidth switched converter provides the lower frequency content.
One application for a hybrid regulator is as an envelope modulated power supply for an RF (radio frequency) power amplifier (PA). Envelope modulation/tracking improves power amplification efficiency for high peak-to-average power ratio (PAR) signals such as typical of mobile RF communications—envelope modulated regulators dynamically control the RF PA supply voltage, tracking PA output power variations/requirements.
Design parameters for an envelope modulated/tracking power supply include noise, distortion and bandwidth. Noise and distortion generated by the envelope modulator and injected into the PA supply pin will transfer to the PA output spectrum. Envelope modulator bandwidth will typically be significantly higher than the baseband signal bandwidth. For hybrid regulator architectures, a significant noise source is switching noise from the switched mode converter, and an important design criteria is to reduce small signal output impedance of the linear amplifier over the operational bandwidth of the envelope modulator (the output impedance bandwidth).
Hybrid regulators can be configured with the linear amplifier AC coupled to the power output node. The linear amplifier is only required to supply AC content of the load voltage—the DC average voltage at the output of the regulator is maintained on the AC coupling (DC-decoupling) capacitor.
While this Background information is presented in the context of regulated power supplies for power amplifier applications, this Patent Disclosure is not limited to such applications, but is more generally directed to hybrid architectures that include a switched mode converter and a linear amplifier.
BRIEF SUMMARY
This Brief Summary is provided as a general introduction to the Disclosure provided by the Detailed Description and Figures, outlining various aspects, features and advantages of the disclosed invention, and should not be interpreted as identifying key elements of the invention, or otherwise defining the scope of the invention that is the subject of this Patent Disclosure, aspects of which are defined by the Claims.
The Disclosure describes apparatus and methods for adapting a switched mode assisted linear (SMAL) amplifier architecture as a regulator supplying a regulated dynamic load voltage and an associated load current to a dynamic load characterized by a signal (dynamic) bandwidth. The SMAL amplifier/regulator architecture includes a switched mode converter (switched converter or switcher) coupled to a (linear) amplifier at a supply node that is coupled to the load. The SMAL amplifier/regulator is configured for, and characterized by a signal path bandwidth, which can be less than the signal bandwidth of the dynamic load.
In one embodiment, a SMAL regulator according to aspects of the invention is configured with the amplifier coupled to the supply node through a coupling capacitor, and implements a methodology for AC coupling with capacitive charge control, including: (a) in response to a dynamic input signal, supplying from the amplifier the corresponding regulated load voltage based on the signal path bandwidth; (b) in response to a switching control signal with a switcher bandwidth that is less that the signal path bandwidth, supplying from the switcher to the supply node a switcher load current based on the switcher bandwidth; and (c) supplying from the amplifier circuit, through the coupling capacitor to the supply node, an amplifier load current corresponding to the load current not supplied by the switcher load current. The methodology further includes: (a) establishing a current control loop that provides the switching control signal, and a nested charge control loop that introduces into the current control loop an offset corresponding to a difference between a voltage across the coupling capacitor and a predetermined DC-average coupling capacitor voltage; and (b) in response to a non-zero offset, providing a corresponding adjusted switching control signal such that the switcher supplies a corresponding adjusted switcher load current, causing the amplifier to output an adjusted amplifier load current with a non-zero average corresponding to the non-zero offset, thereby adjusting the voltage on the coupling capacitor to the predetermined DC-average coupling capacitor voltage.
Other aspects and features of the claimed invention will be apparent to those skilled in the art from the following Disclosure.



BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B illustrate an example RF transmitter system including a power amplifier (PA), and including an envelope modulator configured to supply envelope modulated power to the PA that tracks power variations/requirements of the PA.
FIG. 2 illustrates an example embodiment of a SMAL (switched mode assisted linear) regulator, such as for application as an envelope modulator/supply for an RF PA, including a switched mode converter configured to supply load current, and a linear amplifier (DC coupled to the switched converter) configured to supply regulated load voltage, and to supply load current not supplied by the switched converter.
FIG. 3 illustrates, for the SMAL regulator embodiment illustrated in FIG. 2, example waveforms for: (a) in an upper plot, PA load/supply voltage VPA tracking PA output power variations/requirements, and (b) in the lower plot, associated PA load current IPA, together with separate plots for ISW load current supplied by the switched mode converter, and additional IOP load current required to be supplied by the linear amplifier.
FIG. 4 illustrates an example embodiment of a SMAL regulator in which the linear amplifier is AC coupled to a switched mode converter configured as a current supply, and in which the switching (current) control loop is configured to effectively control the linear amplifier to provide capacitive charge control for the coupling capacitor.
FIGS. 5A and 5B illustrate respectively an example embodiment of, and an equivalent circuit for, an alternate SMAL regulator in which the linear amplifier is AC coupled to a switched mode converter configured as a voltage supply (supplying current through an output inductor), and in which the switching (voltage) control loop is configured to effectively control the linear amplifier to provide capacitive charge control for the coupling capacitor.
FIG. 6 illustrates an example alternate embodiment of SMAL regulator in which a linear amplifier is AC coupled to a switched mode converter, and in which capacitive charge control is implemented by a capacitive charge control loop controlling a transistor coupled to the linear amplifier side of the coupling capacitor.
FIG. 7A illustrates an example embodiment of a SMAL regulator including a linear amplifier design with decoupled output impedance and signal path bandwidth, including a local/internal (higher speed) feedback loop configured for increased output impedance bandwidth, and an external feedback network configurable to establish signal path bandwidth independent of output impedance bandwidth.
FIG. 7B illustrates an example alternate embodiment of the SMAL regulator of FIG. 7A, in which the switched mode converter is coupled directly to the local/internal feedback loop of the linear amplifier, reducing parasitic trace inductance (coupled, for an example IC implementation, to a dedicated IN_SW pin).
FIG. 8 illustrates the relationship between closed-loop output impedance (ZOUT) and frequency.



DETAILED DESCRIPTION
This Description and the Figures disclose example embodiments and applications that illustrate various features and advantages of the invention(s) that is(are) the subject of this Patent Disclosure, aspects of which are defined by the Claims. Known circuits, functions and operations are not described in detail to avoid unnecessarily obscuring the principles and features of the invention.
This Disclosure describes embodiments of a hybrid amplifier/regulator architecture according to the invention, implemented as a switched mode assisted linear (SMAL) regulator supplying a regulated dynamic load voltage and an associated load current to a dynamic load characterized by a signal (dynamic) bandwidth. Embodiments of the SMAL regulator include a switched mode converter (switched converter or switcher) coupled to a (linear) amplifier at a supply node that is coupled to the load. The SMAL amplifier/regulator is configured for, and characterized by a signal path bandwidth, which can be less than the signal bandwidth of the dynamic load, and is configured such that linear amplifier sets the regulated (dynamic) load voltage, and the switched converter (characterized by a switcher bandwidth less than the signal path bandwidth) supplies lower frequency load current, while the (higher bandwidth) linear amplifier supplies load current not supplied by the switched converter. Example embodiments of the SMAL regulator are described in the context of an example application as an envelope modulated (tracking) power supply for an RF power amplifier (PA). The terms envelope modulation and envelope tracking are used interchangeably.
In brief overview, embodiments of the SMAL regulator according to the invention are configured with the amplifier coupled to the supply node through a coupling capacitor, and implement AC coupling with capacitive charge control, wherein: (a) the amplifier circuit, in response to a dynamic input signal, supplies the corresponding regulated load voltage based on the signal path bandwidth; (b) the switcher circuit, in response to a switching control signal with a switcher bandwidth that is less than the signal path bandwidth, supplies a switcher load current based on the switcher bandwidth; and (c) the amplifier circuit supplies through the coupling capacitor an amplifier load current corresponding to the load current not supplied by the switcher load current. The switcher circuit includes: (a) a current control loop configured to provide the switching control signal to control the switcher circuit to supply the switcher load current; and (b) a nested charge control loop configured to introduce into the current control loop an offset corresponding to a difference between a voltage across the coupling capacitor and a predetermined DC-average coupling capacitor voltage; (c) such that, in response to a non-zero offset, the current control loop provides a corresponding adjusted switching control signal. In response to the adjusted switching control signal, the switcher circuit supplies a corresponding adjusted switcher load current, causing the amplifier circuit to output an adjusted amplifier load current with a non-zero average corresponding to the non-zero offset, thereby adjusting the voltage on the coupling capacitor to the predetermined DC-average coupling capacitor voltage. For other embodiments, the SMAL regulator can be configured such that: (a) the current control loop can maximize the switcher load current, such that the amplifier load current is minimized; (b) the signal path bandwidth can be less than the signal bandwidth; and (c) the current control loop can implement hysteretic control with a predetermined hysteretic window, and wherein the charge control loop is configured to introduce an offset to the hysteretic window corresponding to the predetermined coupling capacitor voltage.
RF Envelope Modulation. In an RF transmitter using envelope modulation, the supply voltage provided to a PA is dynamically modulated to correspondingly track output power variation required by the PA. Envelope modulation provides significant efficiency improvement for high peak-to-average power ratio (PAR) signals typical of RF communications (such as used in mobile handsets and base stations).
FIG. 1A is a functional illustration of an example RF transmitter system 10 including an RF power amplifier 11 and an RF baseband subsystem 13 commonly referred to as an RFIC (RF integrated circuit). RFIC 13 generates a baseband signal x(t), which is up-converted 15 to RF, and then amplified by the PA (such as for driving an RF antenna).
Envelope modulator 100 supplies power to the PA (the PA supply rail), modulating supply voltage in response to an envelope signal e(t) from RFIC 13. The envelope tracking signal e(t) tracks output power variations/requirements of the PA as determined by RFIC 13. That is, RFIC 13 splits the baseband signal between two separate paths: an envelope tracking signal e(t) that carries envelope (magnitude) information, and a constant magnitude signal x(t), that carries phase information:

e(t)=|s(t)|  (1)

x(t)=s(t)/|s(t)|  (2)

These two signals are merged by the PA. Because the operation in (1) is nonlinear, even though s(t) is bandwidth limited, the envelope signal e(t) will not be, and as a result, the envelope modulation bandwidth typically will be significantly larger than the signal path bandwidth.

FIG. 1B illustrates an alternate embodiment of the RF transmitter system 10 that includes a low pass filter 17 after RFIC 13. The low pass filter can be configured to reduce the bandwidth of the envelope signal e(t) input to envelope modulator 100. Symbol adjustment 19 prior to up-conversion/mixing 15 can be used to compensate for latency introduced by the low pass filter.
This alternate embodiment represents design trade-offs in terms of overall efficiency of the RF transmitter system 10, including the envelope modulator 100. For example, reducing the bandwidth of envelope modulator 100 (that is, reducing the bandwidth of the envelope tracking signal e(t) input to the envelope modulator) sacrifices some PA efficiency in that the tracking bandwidth of the PA supply voltage is reduced, but is advantageous in terms of improved envelope modulator efficiency. Including symbol adjustment in the x(t) signal path will increase signal path bandwidth, and therefore will increase the bandwidth requirement of the upconverter/mixer and the input to the PA.
Other advantages of limiting envelope tracking bandwidth include reduced receive band noise, and reduced PA gain error. RX band noise is noise measured at the output of the PA within the receive band of the RF transceiver—by reducing the envelope tracking bandwidth, the envelope modulator will introduce less noise and/or distortion, reducing RX band noise. PA gain error is proportional to the difference between the envelope tracking signal through the envelope modulator and the actual envelope tracking signal—if envelope tracking bandwidth is reduced, PA gain error is reduced, reducing RX band noise.
SMAL Regulator-DC Coupled. FIG. 2 illustrates an example embodiment of a SMAL regulator 200 configured to provide regulated power to a load—load voltage VPA and load current IPA. SMAL regulator 200 includes a linear amplifier 210 and a switched mode converter 230, with an associated switching controller 250, configured as a current supply. Linear amplifier 210 and switched mode converter 230 are parallel coupled at a current summing output node PAOUT (coupled to the supply pin of a power amplifier). For this example embodiment, the linear amplifier is DC coupled to the PAOUT node.
The linear amplifier stage 210 supplies a dynamic load voltage VPA in response to a dynamic input voltage VIN. An example application for SMAL regulator 200 is as an envelope modulated supply for an RF PA (FIG. 1A), such that the dynamic input voltage VIN is an envelope tracking signal (from an RFIC) and the SMAL regulator supplies dynamic regulated load voltage VPA, and the required load current IPA, to the PA,
Linear amplifier 210 is configured to provide voltage regulation, setting the dynamic load voltage VPA supplied to the PA. Linear amplifier also supplies the required load current IOP not supplied by switched converter 230. SMAL regulator 200 can be configured to maximize the ISW load current from switched converter 230 (current supply), thereby minimizing the IOP load current required to be supplied by linear amplifier 210. In this configuration, a lower bandwidth switched converter supplies lower frequency ISW load current, and a higher bandwidth linear amplifier supplies higher frequency IOP load current, such that ISW+IOP at the PAOUT node supplies the IPA load current required by the PA.
An example embodiment of linear amplifier 210 is described below (FIGS. 7A and 7B), including configuring the linear amplifier to establish the signal path bandwidth for SMAL regulator 200, and including decoupling the configuration of signal path bandwidth from the configuration of output impedance bandwidth. Decoupling output impedance bandwidth from signal path bandwidth enables the output impedance bandwidth to be maximized relatively independently of signal path bandwidth, an important advantage because, in addition to supplying higher frequency load current (IOP), linear amplifier 210 can be configured to reject switching noise and ripple generated by switched converter 230.
The example embodiment of switched converter 230 is implemented as a buck converter configured as a current supply/source. Switched converter 230 includes a buck inductor 231, but does not include the output capacitor of a conventional buck voltage regulator. In effect, linear amplifier 210 replaces the conventional buck output capacitor. This example converter topology is a design choice, and alternative implementations of the switched converter include boost, buck-boost and flyback.
According to conventional buck converter design, a controlled modulator circuit 233 controls gate drivers 235 for buck switches (FETs) M1/M2. A switching controller 250 is configured to control the switching duty cycle of the switched converter 230.
Switching controller 250 is implemented with a hysteretic voltage comparator 251. One input to comparator 251 is derived from the IOP load current supplied by the linear amplifier 210, and the other input is a predetermined offset VOFFSET. As illustrated, IOP/N from the linear amplifier is converted to a voltage by a resistor 255, and low pass filtered 257 to reduce switching frequency. For the example embodiment, IOP/N is provided by one of the N output transistors of linear amplifier 210, so that the IOP load current supplied by the linear amplifier is formed by N−1 of the N output transistors.
Switching controller 250 can be configured to optimize efficiency of SMAL regulator 200 in supplying power to the PA, which typically results from maximizing the ISW component of the IPA load current supplied by switched converter 230 (subject to bandwidth limitations), and correspondingly minimizing the IOP load current required to be supplied by the linear amplifier 210 (and therefore power dissipation in the linear amplifier). That is, the ISW current sourced/sunk by switched converter 230 is maximized, and the IOP current required to be sourced/sunk by linear amplifier 210 is minimized, such that the higher speed but less efficient linear amplifier delivers the higher frequency IOP content of the dynamic IPA load current, while the more efficient but lower bandwidth switched converter provides the lower frequency ISW content. Typically, this efficiency optimization results from setting the VOFFSET input to comparator 251 to zero.
For the example buck implementation of switched converter 230, bandwidth is limited primarily by the maximum current slew rate through the buck inductor 231 (with inductance L) given by

Rising Slew Rate=(VCC−VPA)/L 

Falling Slew Rate=−VPA/L 

linear amplifier 210 then dynamically sources/sinks the difference between the required IPA load current and the ISW load current supplied by switched converter 230. The inductance of the buck inductor represents a design trade-off.

FIG. 3 illustrates, for SMAL regulator 200, example waveforms for: (a) in the upper plot, VPA load voltage tracking PA output power variations/requirements, as set by the linear amplifier, and (b) in the lower plot, associated IPA load current (ISW+IOP), together with separate plots for the lower frequency ISW load current supplied by the switched converter, and the higher frequency IOP load current required to be supplied by the linear amplifier. Note that based on the dynamic requirements of the IPA load current and the bandwidth limitations of the switched converter, both the linear amplifier and the switched converter can source and sink current.
Referring to FIG. 2, as noted, SMAL regulator 200 and linear amplifier 210 can be configured with a signal path bandwidth that is significantly higher than the bandwidth of the switched converter 230. For example, an implementation of a SMAL regulator according to this Disclosure can be configured for a signal path bandwidth in the range of 20 MHz with a converter switching frequency in the range 1-15 MHz (depending on passive components and signal characteristics).
AC Coupling With Capacitive Charge Control. FIGS. 4, 5 (A/B) and 6 illustrate embodiments of a SMAL regulator in which the linear amplifier is AC coupled to the PAOUT node through an AC coupling (DC decoupling) capacitor CAC. For each embodiment, the coupling capacitor CAC is coupled between the linear amplifier output and the PAOUT node, within the (external) feedback loop of the linear amplifier.
With AC coupling, a predetermined DC-average voltage is maintained on the CAC coupling capacitor, and the linear amplifier supplies the AC content of the VPA load voltage supplied by the SMAL regulator (PAOUT supply node). The IOP load current supplied by the linear amplifier is coupled through the CAC coupling capacitor to the PAOUT node, so that, to maintain the predetermined DC-average voltage on CAC, the steady-state average current through the CAC coupling capacitor is zero.
The SMAL regulator can be configured to control the average current input from the linear amplifier into the coupling capacitor CAC to maintain a predetermined DC-average voltage on CAC: (a) example embodiments in FIGS. 4 and 5A/B illustrate a SMAL regulator in which the switched mode converter stage includes a capacitive charge control loop that controls the ISW load current to effectively control the output current of the linear amplifier, and (b) an alternate example embodiment in FIG. 6 illustrates a SMAL regulator in which the linear amplifier stage includes a charge control transistor with associated capacitive charge control, configured to control the current output from the linear amplifier into the coupling capacitor.
For the example embodiments, CAC capacitance can be relatively large (for example, in the range of 5-10 uF). In this configuration, the CAC coupling capacitor is not designed to filter switching noise/ripple from switched converter, but instead acts as a DC voltage level shifter, storing a predetermined DC-average of the VPA output voltage. The predetermined level of the DC-average voltage on the CAC coupling capacitor can be set from a register or by calculation from one or more registers.
FIG. 4 illustrates an example embodiment of a SMAL regulator 400 in which a linear amplifier 410 is AC coupled to the PAOUT node through an AC coupling capacitor CAC. A switched mode converter 430 includes a switching controller 450 with nested control loops, including a VCAC control loop 455 configured to effect capacitive charge control.
Functionally, VCAC control loop 455 introduces a VCAC offset into an ISW control loop (IOP/N) that controls the ISW load current supplied by switched converter 430. Responsive to the VCAC offset, switched converter 430 correspondingly adjusts the ISW load current such that the linear amplifier 410 adjusts its ILA output current to a non-zero average. As a result, the voltage on the CAC coupling capacitor changes based on the average current through the CAC coupling capacitor to the PAOUT node, charging/discharging the coupling capacitor CAC to maintain the DC-average voltage VCAC.
A design consideration for the AC coupled embodiment of the SMAL regulator 400 is establishing the DC-average voltage VCAC relative to the supply voltage of linear amplifier 410. For purposes of illustration, ignoring the DC-average voltage VCAC, SMAL regulator 400 can supply an output voltage above supply (for example, battery) voltage so long as the signal peak-to-peak amplitude is less than the supply voltage. For example, for a supply voltage of 2.5V, boosting the LA supply rail would not be required if the PA load voltage VPA swings from 2V to 3.6V because the signal peak-to-peak amplitude (1.6V in this example) is below the 2.5V supply voltage (and will remain so as long as the supply voltage remains above 1.6V with appropriate headroom). That is, for the AC coupled example embodiment, the design constraints at the LA are that both VPP (peak-to-peak), and VPA-DC (average VPA output voltage) must be less than the supply voltage by some headroom (in some embodiments, VPA-DC could be zero volts). Thus, AC coupling provides a degree of design freedom in specifying a maximum PA load voltage VPA without requiring boosting the supply rail of the linear amplifier 410. Specifically, VPK can be greater than the supply voltage as long as the VPP and VPA-DC constraints are observed. Contrast the example DC coupled implementation illustrated in FIG. 2 in which VPK is constrained.
Switching controller 450 is configured to control the switched converter (buck) 430, both (a) for steady-state operation, to supply ISW load current that minimizes the IOP load current required to be supplied by linear amplifier 410, and (b) as necessary, to adjust ISW to cause the linear amplifier to output a non-zero-average ILA output current that, in addition to supplying the required IOP load current, changes/discharges the coupling capacitor CAC to maintain the DC-average VCAC coupling capacitor voltage.
Switching controller 450 includes a hysteretic current comparator 451 that defines an ISW/IOP hysteretic window. Hysteretic current comparator 451 receives inputs derived from two (nested) control loops: (a) an ISW control loop based on IOP/N corresponding to the IOP load current supplied by linear amplifier 410, and (b) the VCAC control loop 455 based on the voltage across the coupling capacitor CAC. Referring to FIG. 2, the VCAC control loop basically replaces the VOFFSET input to the hysteretic voltage comparator 251.
The ISW control loop operates to drive the buck switched converter to supply ISW load current to minimize the IOP load current from the linear amplifier by maintaining IOP/N (averaged by low pass filtering within the ISW/IOP hysteretic window. As a result, the linear amplifier outputs (steady-state) a zero-average output current ILA, coupled through the coupling capacitor CAC to the PAOUT summing node as the IOP load current supplied by linear amplifier 410.
The VCAC control loop 455 is implemented with a transconductance (gm) amplifier 457. The VCAC control loop introduces a VCAC charge control offset into the ISW/IOP hysteretic window, corresponding to the predetermined coupling capacitor voltage VCAC. Transconductance (gm) amplifier 457 provides a current input to the hysteretic comparator 451 proportional the voltage across the CAC coupling capacitor referenced to VCAC:gm*[VPA−(VLA+VCAC)]. That is, the VCAC offset introduced by the VCAC control loop corresponds to the difference between (a) VPA, the PA load voltage, and (b) (VLA+VCAC), the linear amplifier output voltage VLA plus the predetermined coupling capacitor voltage VCAC. Low pass filtering these inputs reduces the requirement for high frequency common mode rejection.
When the voltage on the CAC coupling capacitor deviates from the predetermined VCAC, the ISW/IOP hysteretic window is offset (VPA−(VLA+VCAC) is non-zero), so that the ISW control loop operates to drive switched converter 430 to output an ISW load current that causes the linear amplifier to correspondingly output a non-zero-average ILA current. This non-zero-average ILA, in addition to providing the IOP load current through the coupling capacitor CAC, charges/discharges CAC to VCAC, i.e., until [VPA−(VLA+VCAC)] is zeroed. At that point, the nested ISW control loop continues steady-state operation to drive switched converter 430 to supply ISW load current that minimizes the IOP load current required to be supplied by linear amplifier 410. For this steady-state operation (with VCAC on the CAC coupling capacitor), the linear amplifier outputs a zero-average ILA current through CAC to the PAOUT summing node as the IOP load current.
For example, assume that switched converter 410 is sourcing current when the IOP load current provided by linear amplifier (LA) 410 is greater than 50 mA, and sinking current when IOP is below 50 mA, so that the ISW/IOP hysteresis window is +50/−50 mA (zero-average ILA current). If the DC average of VPA is above (VLA+VCAC), then an offset current of gm times [VPA−(VLA+VCAC)] is input to the hysteretic comparator. If, for example, this current is 20 mA, then the new ISW/IOP hysteretic window is +70/−30 mA, and the new LA non-zero-average ILA output current is approximately 20 mA, gradually charging CAC to increase voltage on the coupling capacitor, until the predetermined voltage VCAC is reached (when VPA−(VLA+VCAC) is zero).
FIGS. 5A and 5B illustrate respectively an example alternate embodiment of, and an equivalent circuit for, a SMAL regulator 500 with AC coupling, adapted for high frequency applications. Linear amplifier 510 is AC coupled through a coupling capacitor CAC to the PAOUT node. For this embodiment, switched mode converter 530 is implemented as a buck voltage supply, including in addition to a buck inductor 531 a buck output capacitor 532. A switching controller 550 provides voltage control to the buck converter 530, which includes a large output inductor 539 that converts the buck voltage supply to a current supply for the ISW load current. Switching controller 550 includes a VCAC control loop 455 configured to effect capacitive charge control.
Functionally, VCAC control loop 555 introduces a VCAC offset into an ISW control loop (VIN) that controls the ISW load current supplied by switched converter 530. Responsive to the VCAC offset, switched converter 530 correspondingly adjusts the ISW load current, current such that the linear amplifier 510 adjusts its ILA output current to a non-zero average. As a result, the voltage on the CAC coupling capacitor changes based on the average current through the CAC coupling capacitor to the PAOUT node, charging/discharging the coupling capacitor CAC to maintain the DC-average voltage VCAC.
Switching controller 550 includes a combiner 551 that receives two signal inputs: (a) an ISW control signal based on the target voltage VIN also input to linear amplifier 510, and (b) a VCAC control signal from VCAC control loop 555 based on the voltage across the CAC coupling capacitor.
For the ISW control signal, the target voltage VIN is averaged by a low pass filter 553, and provides an ISW control input to the switched converter 530 that corresponds to the VPA load voltage set by linear amplifier 510. The ISW control input to switched converter 530 operates to control the supply voltage on the buck output capacitor 532 such that the resulting ISW load current through the output inductor 539 causes the linear amplifier to output (steady-state) a zero-average ILA output current. The ILA output current is coupled through the CAC coupling capacitor to the PAOUT summing node as the IOP load current required to be supplied by the linear amplifier 510.
VCAC control loop 555 is implemented with a voltage amplifier 557 followed by a compensation network 559. The resulting VCAC control signal introduces a VCAC charge control offset signal corresponding to a predetermined coupling capacitor voltage VCAC. The output from amplifier 557 is proportional the voltage across the CAC referenced to VCAC: [VPA−(VLA+VCAC)]. That is, the VCAC offset control signal introduced by the VCAC control loop corresponds to the difference between (a) VPA, the PA load voltage, and (b) (VLA+VCAC), the linear amplifier output voltage VLA plus the predetermined coupling capacitor voltage VCAC. Low pass filtering these inputs reduces the requirement for high frequency common mode rejection.
When the voltage on the CAC coupling capacitor deviates from the predetermined VCAC, the VCAC offset control signal from the VCAC control loop 555 [VPA−(VLA+VCAC)] will be non-zero. The resulting ISW control signal and VCAC offset control signal are combined by the combiner 551, driving switched converter 530 to adjust the load current ISW, and thereby cause linear amplifier 510 to output a non-zero-average ILA current corresponding to [VPA−(VLA+VCAC)]. This non-zero-average ILA, in addition to providing the load current IOP, charges/discharges the CAC coupling capacitor to VCAC, i.e., until [VPA−(VLA+VCAC)] is zeroed. At that point, the ISW control signal (corresponding to the low pass filtered target voltage VIN) continues steady-state operation in driving switched converter 530 to supply load current ISW that minimizes the IOP load current from linear amplifier 510. The linear amplifier outputs a zero-average ILA current corresponding to the IOP load current, through the CAC coupling capacitor to the PAOUT summing node.
FIG. 5B illustrates an AC equivalent circuit of the embodiment of SMAL regulator 500 illustrated in FIG. 5A, approximating switched mode converter (buck) 530 as a voltage controlled voltage source. The transfer function of the control loop is given by




  
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All quantities are shown in FIG. 5B except RC which is the ESR of the coupling capacitor CAC (designated C in the transfer function) and RL which is the ESL of L. Poles and zeros are: P1=0; P2=−RL/L; P3=−2πf3 dB; P4=−1/C1R11; Z1=−1CRC; Z2=−1/(C1(R12+R11)). For example: (P2) assuming ESR of 100 mOhm and L of 100 uH, this pole can be located at 160 Hz; (P3) this pole can provide additional freedom to filter out any high frequency noise across the capacitor C, caused by the linear amplifier current; (P4) this pole can provide additional freedom to filter out any high frequency noise across the capacitor C, caused by the linear amplifier current; (Z1) assuming ESR of 20 m Ohm and C of 50 uF, this zero can be located at 166 kHz (very high frequency pole); (Z2) this zero can be set to stabilize the loop and increase phase margin.

FIG. 6 illustrates an example embodiment of an alternate SMAL regulator architecture 600 with AC coupling, in which capacitive charge control is implemented in the linear amplifier stage. Specifically, linear amplifier stage 610 includes a VCAC (charge) control transistor M3 and associated VCAC control circuit 660. For the example embodiment, VCAC control transistor M3 is an operating mode transistor operated in the linear region to provide capacitive charge control—in another operating mode not the subject of this Patent Disclosure, is used to ground the coupling capacitor (with the linear amplifier is disabled).
SMAL regulator 600 includes a switched converter 630 implemented as a buck current supply. The buck switched converter 630 is coupled through a buck inductor 631 to the PAOUT node.
A switching controller 650 is configured to control switched converter 630 to supply ISW load current that minimizes the IOP load current required to be supplied by linear amplifier 610. Switching controller 650 includes a hysteretic current comparator 651 that defines an ISW/IOP hysteretic window. The hysteretic current comparator 651 receives an IOP/N input derived from an ISW control loop based on a current IOP/N corresponding to the IOP load current supplied by linear amplifier 610. This IOP/N input is compared to a zero reference corresponding to the DC average of the IOP load current (for AC coupled implementations, zero). The ISW control loop operates to drive switched converter 630 to supply ISW load current to minimize the IOP load current from the linear amplifier by maintaining IOP/N (low pass filtered) within the ISW/IOP hysteretic window. As a result, linear amplifier 610 outputs (steady-state) a zero-average output current ILA, coupled through the CAC coupling capacitor to the PAOUT summing node as the IOP load current supplied by the linear amplifier 610.
VCAC control loop 660 includes cascade differential amplifiers 661 and 662, configured to implement VCAC control based on the voltage across the CAC coupling capacitor. The output of amplifier 662 provides a VCAC control signal to the M5 control gate.
VCAC control loop 660 can be represented as [VPA−(VLA+VCAC)], or for the configuration of FIG. 6, [(VPA−VLA)−VCAC)]. That is, the amplifiers 661/662 generate the VCAC control signal which corresponds to the voltage across the coupling capacitor (VPA−VLA) relative to the predetermined DC-average voltage VCAC. In particular, feedback ensures that VCAC applied to the negative input of amplifier 662 will appear across the CAC coupling capacitor, which allows precise control of the VCAC coupling capacitor voltage.
When the voltage on the CAC coupling capacitor deviates from the predetermined VCAC (non-zero [(VPA−VLA)−VCAC)]) the VCAC control signal from VCAC control loop 660 (amplifier 662) controls M3 to effect charging/discharging the coupling capacitor CAC, until [(VPA−VLA)−VCAC)] is zeroed. The separate ISW control loop 650 continues steady-state operation, driving switched converter 630 to supply ISW load current that minimizes the IOP load current required to be supplied by the linear amplifier 610. In this steady-state case (with VCAC on the CAC coupling capacitor), linear amplifier 610 outputs a zero-average ILA current through CAC to the PAOUT summing node as the IOP load current.
Decoupling Output Impedance and Signal Path Bandwidth. FIGS. 7A and 7B illustrate example embodiments of SMAL regulator 700 in a system configuration with a power amplifier 701 (such as for use in the RF transmitter system illustrated in FIG. 1A/B). SMAL regulator 700 includes linear amplifier 710 and a switched mode converter 730, parallel coupled at an output node PAOUT to PA 701. Control for the switched mode converter is integrated with the switched mode converter and not separately illustrated (compare, for example, controller 250 in FIG. 2).
As illustrated, the example embodiments of SMAL regulator 700 are configured with DC coupling (such as also illustrated in FIG. 2), with appropriate modification, the Description related to these embodiments would also apply to AC coupled embodiments/implementations.
As illustrated, linear amplifier 710 and switched converter 730 are implemented as separate integrated circuits (ICs)—a SMAL regulator according to this Disclosure can be adapted to a single-IC implementation. System interconnect will necessarily include trace inductance that can impact operation at higher frequencies (discussed in connection with the embodiment in FIG. 7B).
SMAL regulator 700 supplies to the PA (PAOUT) regulated voltage VPA and current IPA. In accordance with this Disclosure, (a) PA load voltage VPA is dynamically set by the linear amplifier 710, and (b) PA load current IPA is supplied by linear amplifier 710 with primary current assist supplied by switched converter 730. Switched converter 730 is configured to supply lower frequency ISW load current, and the linear amplifier 710 is configured to supply IOP load current not supplied by the switched converter (i.e., sourcing/sinking PA load current IPA not supplied by the switched converter). ISW and IOP summed at the PAOUT supply node.
Linear amplifier 710 outputs voltage VLA and current ILA. For the example DC coupled implementations, output voltage VLA corresponds to the regulated load voltage VPA supplied to PA 701, and output current ILA corresponds to the load current IOP supplied by the linear amplifier. For the example IC implementations, VLA and ILA are available at an output pin OUT_PA.
The linear amplifier design 710 can be configured for decoupling output impedance and signal path bandwidth, enabling signal path bandwidth to be established relatively independent of output impedance bandwidth. The linear amplifier includes a local/internal (higher speed) feedback loop configured for controlling output impedance bandwidth, and a global/external feedback network configurable to independently establish signal path bandwidth. As used in this Disclosure, output Impedance bandwidth refers to the bandwidth over which the output impedance of a SMAL regulator remains low relative to the frequencies of interest and the load.
FIG. 8 illustrates the relationship between closed-loop output impedance (Zout) and frequency—this description will be in the context of a negative feedback operational amplifier which corresponds in relevant respects to a linear amplifier such as used in a SMAL regulator according to this Disclosure. The closed-loop output impedance Zout is characterized by a low resistance RDC at lower frequencies where the amplifier has significant loop gain. At higher frequencies, the amplifier loop gain drops and output impedance Zout increases. A design parameter is the zero dB crossing frequency f0dB (ZCF), defined as the frequency at which system output impedance rises to zero dB-ohms (1 ohm in non-dB units).
In the context of the example RF application, the higher the ZCF for the output impedance of the linear amplifier, the higher the output impedance bandwidth, and the lower the RX band noise at a power amplifier. That is, a linear amplifier with a high ZCF relative to the RF frequencies of interest is advantageous in actively rejecting high-frequency voltage disturbances introduced internal to a SMAL regulator by the switched mode converter, or externally from the dynamic PA load (noise output from the PA supply pin). Thus, it can be advantageous to increase output impedance bandwidth (increase ZCF) to reduce RX band noise. However, a design trade-off can be to reduce signal path bandwidth to increase efficiency (that is, limiting signal path bandwidth to the bandwidth requirement for envelope tracking) and/or increase design flexibility (such as by reducing design complexity).
FIGS. 7A/7B include a high level functional illustration of a linear amplifier design 710, including decoupling output impedance bandwidth from signal path bandwidth. Specific implementations of a linear amplifier for use in a SMAL regulator according to this Disclosure represent a design choice, and other amplifier architectures are adaptable as a linear amplifier according to this Disclosure, including implementing design alternatives and/or trade-offs to improve efficiency under different operating conditions and for different applications.
Referring to FIG. 7A, linear amplifier 710 receives a differential envelope tracking signal (VCON+/−), such as from an RFIC (this differential signal corresponds to VIN in FIGS. 2, 4, 5A/5B and 6). In response, linear amplifier 710 supplies a regulated, single-ended load voltage VPA (VLA) to the PA 701.
Linear amplifier 710 includes both an internal (higher speed) feedback loop 711 configured for reducing output impedance at the frequencies of interest, and an external (lower speed) feedback network 713 configured to establish signal path bandwidth. For the illustrated IC implementation, the external feedback network 713 is connected to PAOUT, between the FB and OUT_PA pins.
The local/internal (higher speed) feedback loop 711 enables increased output impedance bandwidth. The internal feedback loop 711 reduces output impedance at higher frequencies, increasing zero crossing frequency (ZCF in FIG. 8), and thereby increasing output impedance bandwidth. A capacitive divider network 715 at the inverting VCON-input to linear amplifier 710 can be used to provide further control at higher frequencies.
The global/external feedback network 713 can be configured to establish signal path bandwidth, including optimizing SMAL regulator 700 for reduced signal path bandwidth leading to increased efficiency. For example, using relatively large resistive values in the external feedback loop 713 will slow the feedback loop, and reduce signal path bandwidth, without appreciably affecting output impedance bandwidth for the frequencies of interest. In addition, a parallel resistance 717 can be used to stabilize the external feedback loop 713 at high frequencies by shorting the (trace) inductance in the feedback loop between the OUT_PA and FB pins, thereby improving phase margin.
FIG. 7B illustrates an example alternate embodiment of the SMAL regulator 700 of FIG. 7A, in which switched converter 730 is connected at the output of the linear amplifier 710, effectively at the local/internal feedback loop 711, reducing parasitic trace inductance between switched converter 730 and linear amplifier 710. For the example IC implementation, switched converter 730 connects to a separate IN_SW pin of linear amplifier 710. With this system interconnect configuration, the PAOUT node is effectively at the linear amplifier, reducing the affects of trace inductance (distortion caused by switching and ripple noise).
Example embodiments of the switched mode assisted linear amplifier/regulator architecture have been described in the context of an example application as an envelope modulated (or tracking) power supply for an RF power amplifier. Other applications for a SMAL amplifier/regulator architecture according to this Disclosure include audio power supplies, audio amplifiers (with integrated power) and power line communications.
The Disclosure provided by this Description and the Figures sets forth example embodiments and applications, including associated operations and methods, that illustrate various aspects and features of the invention. These example embodiments and applications may be used by those skilled in the art as a basis for design modifications, substitutions and alternatives to construct other embodiments, including adaptations for other applications, Accordingly, this Description does not limit the scope of the invention, which is defined by the Claims.

## Claims

1. A circuit for supplying a regulated load voltage and associated load current to a dynamic load characterized by a signal bandwidth, comprising:
a switched mode assisted linear (SMAL) regulator including an amplifier circuit and a switched mode converter (switcher) circuit coupled in parallel at a supply node coupled to the load, the amplifier circuit coupled to the supply node through a coupling capacitor;
The SMAL regulator configured to supply the regulated load voltage and load current based on a signal path bandwidth, wherein:
the amplifier circuit, in response to a dynamic input signal, supplies the corresponding regulated load voltage based on the signal path bandwidth;
the switcher circuit, in response to a switching control signal with a switcher bandwidth that is less than the signal path bandwidth, supplies a switcher load current based on the switcher bandwidth; and
the amplifier circuit supplies through the coupling capacitor an amplifier load current corresponding to the load current not supplied by the switcher load current; and

the switcher circuit including:
a current control loop configured to provide the switching control signal to control the switcher circuit to supply the switcher load current; and
a nested charge control loop configured to introduce into the current control loop an offset corresponding to a difference between a voltage across the coupling capacitor and a predetermined DC-average coupling capacitor voltage;
such that, in response to a non-zero offset, the current control loop provides a corresponding adjusted switching control signal;

such that, in response to the adjusted switching control signal, the switcher circuit supplies a corresponding adjusted switcher load current, causing the amplifier circuit to output an adjusted amplifier load current with a non-zero average corresponding to the non-zero offset, thereby adjusting the voltage on the coupling capacitor to the predetermined DC-average coupling capacitor voltage.

2. The circuit of claim 1, wherein the current control loop is further configured to maximize the switcher load current, such that the amplifier load current is minimized.

3. The circuit of claim 1, wherein the signal path bandwidth is less than the signal bandwidth.

4. The circuit of claim 1, wherein the current control loop implements hysteretic control with a predetermined hysteretic window, and wherein the charge control loop is configured to introduce an offset to the hysteretic window corresponding to the predetermined coupling capacitor voltage.

5. The circuit of claim 1, wherein the switcher circuit includes switching control circuitry configured to provide the switching control signal, the switching control circuitry comprising:
a hysteretic comparator configured to establish as hysteretic window, and coupled to receive (i) a current control signal corresponding to the amplifier load current, and (ii) an offset signal;
current control circuitry configured to establish the current control loop and generate the current control signal; and
charge control circuitry configured to establish the charge control loop and generate the offset signal;
wherein the amplifier circuit and the switcher circuit are operable to maintain the current control signal within the hysteretic window; and
wherein the hysteretic comparator is responsive to the offset signal to introduce a corresponding offset to the hysteretic window.

6. The circuit of claim 1, wherein the switcher circuit is configured as a voltage supply, including:
an output capacitor storing a controlled voltage; and
an output inductor coupled between the output capacitor and the supply node, such that the controlled voltage on the output capacitor is converted into the switcher load current supplied by the switcher circuit to the supply node.

7. A system, comprising:
a power amplifier coupled to receive a dynamic input signal with a signal bandwidth, and configured to output an amplified signal corresponding to the input signal, the power amplifier including a supply input;
a switched mode assisted linear (SMAL) regulator including an amplifier and a switched mode converter (switcher) coupled in parallel at a supply node, the amplifier coupled to the supply node through a coupling capacitor, the supply node coupled to the supply input of the power amplifier;
the SMAL regulator configured to supply a regulated load voltage and an associated load current to the power amplifier based on a signal path bandwidth, wherein:
the amplifier, in response to the input signal, supplies the corresponding regulated load voltage based on the signal path bandwidth;
the switcher, in response to a switching control signal with a switcher bandwidth that is less than the signal path bandwidth, supplies a switcher load current based on the switcher bandwidth; and
the amplifier supplies an amplifier load current corresponding to the load current not supplied by the switcher load current; and

the switcher including:
a current control loop configured to provide the switching control signal to control the switcher to supply the switcher load current; and
a nested charge control loop configured to introduce into the current control loop an offset corresponding to a difference between a voltage across the coupling capacitor and a predetermined DC-average coupling capacitor voltage;
such that, in response to a non-zero offset, the current control loop provides a corresponding adjusted switching control signal;

such that, in response to the adjusted switching control signal, the switcher supplies a corresponding adjusted switcher load current, causing the amplifier to output an adjusted amplifier load current with a non-zero average corresponding to the non-zero offset, thereby adjusting the voltage on the coupling capacitor to the predetermined DC-average coupling capacitor voltage.

8. The system of claim 7, wherein the current control loop is further configured to maximize the switcher load current, such that the amplifier load current is minimized.

9. The system of claim 7, wherein the signal path bandwidth is less than the signal bandwidth.

10. The system of claim 7, wherein the current control loop implements hysteretic control with a predetermined hysteretic window, and wherein the charge control loop is configured to introduce an offset to the hysteretic window corresponding to the predetermined coupling capacitor voltage.

11. The system of claim 7, wherein the switcher includes switching control circuitry configured to provide the switching control signal, the switching control circuitry comprising:
a hysteretic comparator configured to establish as hysteretic window, and coupled to receive (i) a current control signal corresponding to the amplifier load current, and (ii) an offset signal;
current control circuitry configured to establish the current control loop and generate the current control signal; and
charge control circuitry configured to establish the charge control loop and generate the offset signal;
wherein the amplifier and the switcher are operable to maintain the current control signal within the hysteretic window; and
wherein the hysteretic comparator is responsive to the offset signal to introduce a corresponding offset to the hysteretic window.

12. The system of claim 7, wherein the switcher is configured as a voltage supply, including:
an output capacitor storing a controlled voltage based on the switching control signal; and
an output inductor coupled between the output capacitor and the supply node, such that the controlled voltage on the output capacitor is converted into the switcher load current supplied by the switcher to the supply node.

13. A method for supplying a regulated load voltage and associated load current to a dynamic load characterized by a signal bandwidth, the method operable with a switch mode assisted linear (SMAL) regulator including an amplifier and a switched mode converter (switcher) coupled in parallel at a supply node coupled to the load, the amplifier circuit coupled to the supply node through a coupling capacitor, the SMAL regulator characterized by a signal path bandwidth, the method comprising:
in response to a dynamic input signal, supplying from the amplifier the corresponding regulated load voltage based on the signal path bandwidth;
in response to a switching control signal with a switcher bandwidth that is less that the signal path bandwidth, supplying from the switcher to the supply node a switcher load current based on the switcher bandwidth; and
supplying from the amplifier circuit, through the coupling capacitor to the supply node, an amplifier load current corresponding to the load current not supplied by the switcher load current;
establishing a current control loop that provides the switching control signal, and a nested charge control loop that introduces into the current control loop an offset corresponding to a difference between a voltage across the coupling capacitor and a predetermined DC-average coupling capacitor voltage; and
in response to a non-zero offset, providing a corresponding adjusted switching control signal such that the switcher supplies a corresponding adjusted switcher load current, causing the amplifier to output an adjusted amplifier load current with a non-zero average corresponding to the non-zero offset, thereby adjusting the voltage on the coupling capacitor to the predetermined DC-average coupling capacitor voltage.

14. The method of claim 13, wherein the switcher is controlled to maximize the switcher load current, such that the amplifier load current is minimized.

15. The method of claim 13, wherein the signal path bandwidth is less than the signal bandwidth.

16. The method of claim 13, wherein the switcher load current is controlled within a predetermined hysteretic window, and wherein the offset adjusts the hysteretic window corresponding to the predetermined coupling capacitor voltage.

17. The method of claim 13, wherein the switcher is configured as a voltage supply, including:
an output capacitor storing a controlled voltage; and
an output inductor coupled between the output capacitor and the supply node, such that the controlled voltage on the output capacitor is converted into the switcher load current supplied by the switcher to the supply node.