Conference Paper

NREL/CP-520-46304

July 2009

Degradation and CapacitanceVoltage Hysteresis in CdTe 

Devices 

Preprint 

D.S. Albin, R.G. Dhere, S.C. Glynn, J. Del Cueto, 

and W.K. Metzger

National Renewable Energy Laboratory

Presented at the 2009 SPIE Optics+Photonics Meeting

Reliability of Photovoltaic Cells, Modules, Components and Systems II

Proceedings of SPIE, Vol. 7412

San Diego, California

August 2-6, 2009
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1 

Degradation and Capacitance-Voltage Hysteresis in CdTe Devices

D.S. Albin*a, R.G. Dherea, S.C. Glynna, J.A. del Cuetoa, and W.K. Metzgera 

a

National Renewable Energy Laboratory, 1617 Cole Blvd., Denver, CO, USA 80401 

ABSTRACT

CdS/CdTe photovoltaic solar cells were made on two different transparent conducting oxide (TCO) structures in order to 

identify differences in fabrication, performance, and reliability. In one set of cells, chemical vapor deposition (CVD)

was used to deposit a bi-layer TCO on Corning 7059 borosilicate glass consisting of a F-doped, conductive tin-oxide 

(cSnO2) layer capped by an insulating (undoped), buffer (iSnO2) layer. In the other set, a more advanced bi-layer 

structure consisting of sputtered cadmium stannate (Cd2SnO4; CTO) as the conducting layer and zinc stannate (Zn2SnO4; 

ZTO) as the buffer layer was used. CTO/ZTO substrates yielded higher performance devices however performance 

uniformity was worse due to possible strain effects associated with TCO layer fabrication. Cells using the SnO2-based 

structure were only slightly lower in performance, but exhibited considerably greater performance uniformity. When 

subjected to accelerated lifetime testing (ALT) at 85 - 100 oC under 1-sun illumination and open-circuit bias, more 

degradation was observed in CdTe cells deposited on the CTO/ZTO substrates. Considerable C-V hysteresis, defined as 

the depletion width difference between reverse and forward direction scans, was observed in all Cu-doped CdTe cells. 

These same effects can also be observed in thin-film modules. Hysteresis was observed to increase with increasing 

stress and degradation. The mechanism for hysteresis is discussed in terms of both an ionic-drift model and one 

involving majority carrier emission in the space-charge region (SCR). The increased generation of hysteresis observed

in CdTe cells deposited on CTO/ZTO substrates suggests potential decomposition of these latter oxides when subjected 

to stress testing.

Keywords: CdTe solar cell, capacitance-voltage hysteresis, DLTS, transient ion drift, reliability, degradation

1. BACKGROUND

CdS/CdTe solar cell stability has been an important area of focus. The detrimental effects of localized shunts [1] 

and micro-nonuniformities [2], improved reliability by mitigating Cu diffusion using Te and O [3], the relative effects 

of different back contact structures [4], and most recently, the determination of degradation activation energies 

identifying both Cu and S diffusion [5] have been discussed. In the latter study, higher activation energy mechanisms 

were shown to dominate lower energy processes, e.g., the heavily studied effects associated with Cu diffusion. 

Degradation was shown to be stress temperature dependent (Fig. 1(a)). The lower degradation activation energy (Ea ~ 

0.63 eV) measured at higher temperatures (100 – 120 oC) was attributed to Cu-diffusion (Ea reported as 0.67 eV [6]) 

from the heavily Cu-doped back contact. The mechanism responsible for the higher measured activation energy (Ea ~ 

2.94 eV) seen at lower temperatures (60 – 80 oC) was perplexing until scanning electron microscopy (SEM) showed the 

formation of Kirkendall voids in the CdS with increasing stress. At this point, it was suggested that bulk S-diffusion (Ea

reported as 2.8 eV [7]) into the CdTe from the CdS was responsible for this mechanism. Sulfur out-diffusion from the 

CdS layer also helped explain the results of a correlation analysis (Fig. 1(b)) in which changes in cell performance (η%) 

were plotted as a function of changes in 2nd level metrics (open-circuit voltage (Voc), short-circuit current density (Jsc), 

and fill factor (FF).

As shown in Fig. 1(b), changes in performance were well-correlated (R2 = 1 being perfect) with FF change at all 

temperatures. This correlation was observed to increase with increasing stress temperature. At a stress temperature of 

120 oC, nearly all (97.3%) the observed variation in efficiency could be explained by considering FF alone. Cu diffusion 

from the back contact was determined to be a major contributor to degradation. With shorter stress times, improvements 

in FF observed at all stress temperatures were quantitatively related by Ea = 0.67 eV. At higher temperatures, where 

degradation is dominated by Cu diffusion, increased space-charge recombination reduced Voc and FF. 

*

david_albin@nrel.gov; phone 1 303 384-6550; fax 1 303 384-7600; www.nrel.gov
2 

The effects of sulfur out-diffusion are perhaps best understood by considering cells stressed at lower temperatures. 

The moderate correlation with Jsc seen at lower stress temperatures (where S diffusion dominates) decreases with 

increasing temperature. The performance change with Jsc in this case was not always negative, i.e., improvements in 

performance were correlated with improvements in Jsc. The latter improvements in Jsc could be due to the reduced 

optical attenuation presented by thinner CdS (i.e., due to S-outdiffusion). Thus, it is shown how an energetically less 

favorable (S diffusion with Ea ~ 2.8-2.9 eV) mechanism, can dominate more favorable ones (Cu diffusion; Ea ~0.63-0.67 

eV), if in fact that mechanism occurs at a critical location in the cell (the junction in this case). We would even suggest, 

that degradation mechanisms originating at the junction are perhaps even more damaging than those that originate 

elsewhere (i.e., at the back contact).

Figure 1. Arrhenius figure (a) showing two different activation energies associated with CdTe stress testing. Correlation data (b) 

pertaining to performance change (delta Eff) vs. changes in Voc, Jsc, and FF as a function of stress temperature.

In ref [5], the CdS/CdTe cells were deposited by chemical bath deposition (CBD) and close spaced sublimation 

(CSS) respectively on Corning borosilicate (7059) glass substrates which had previously been coated by chemical-vapor 

deposited (CVD) SnO2 using a tetramethyltin (TMT) precursor. The SnO2 structure consisted of a bilayer configuration 

in which a F-doped, conductive cSnO2 layer was deposited first, followed by an undoped, intrinsic, iSnO2 buffer layer. 

In this paper, the stress tolerance of CdS/CdTe cells grown by identical semiconductor layer processes (and identical 

back contact fabrication) using both this TMT-CVD SnO2 bilayer construction (cSnO2/iSnO2) and a more advanced, 

sputtered conducting Cd2SnO4 (CTO) and resistive Zn2SnO4 (ZTO) buffer layer will be discussed. The latter 

transparent-conducting-oxide (TCO) is arguably the most important technology partition (along with back contact 

variations) in the superstrate CdTe field. SnO2 is a proven and cost-effective TCO while CTO/ZTO layers are well 

known to have yielded the highest CdS/CdTe starting cell efficiencies to date [8]. The relative performance metrics of 

CdS/CdTe cells using SnO2 and the more advanced CTO/ZTO layers is shown in Fig. 2.

 Figure 2. Total-Area Efficiency (%) vs. (a) Voc, (b) Jsc, and (c) FF for CdS/CdTe cells fabricated from bilayer SnO2 (dots) and 

CTO/ZTO (open-circles) transparent conducting oxide layers

The initial performance data shown in Figure 2 consists of a set of (447) SnO2-based and (62) CTO/ZTO-based cells 

fabricated at NREL over the course of several years of research and reflects the variation in performance resulting from 

(a) (b)
3 

routine variations in processing. Several comments are noteworthy. First, higher performance in CTO/ZTO cells is due 

to improvements in Jsc and FF only. There is no indication that Voc improves when using the CTO/ZTO structure. In a 

CTO/ZTO/CdS/CdTe structure, the CdS layer is observed to diffuse into both the ZTO and CdTe layers while in 

cSnO2/iSnO2/CdS/CdTe structures, CdS diffuses primarily into the CdTe alone [8]. A major advantage of this enhanced 

interdiffusion is the increased adhesion the CdS/CdTe stack has to the substrate which allows higher CdCl2 anneal 

temperatures and longer times. CdTe cells grown on CTO/ZTO substrates thus have considerably higher (~2.2 ns) 

minority carrier lifetimes than similar cells grown on SnO2-based substrates (<1 ns). Another benefit related to 

increased interdiffusion is the resultant thinning of the CdS layer which can improve Jsc. The majority of the Jsc benefit 

however, is due to the higher transmission of the CTO/ZTO stack relative to cSnO2/iSnO2. Light transmission through 

the TCO/glass substrates alone can explain improvements in current of up to 1.5 mA/cm2 when using CTO/ZTO-based 

substrates. 

A final observation from Figure 2 is that CTO/ZTO cells can exhibit extremely poor performance that is rarely 

observed when using SnO2-based TCOs. Some of these “outliers” will be discussed subsequently. Regardless, the use 

of CTO/ZTO layers obviously improves initial cell performance.

Though the initial benefits of CTO/ZTO TCO layers are well known, there is a paucity of knowledge concerning the 

relative stability of these materials when used in cells. In 2004, a preliminary determination of the dry heat stability (85 

oC, room-temperature humidity ~ 3% RH) of a number of CTO/ZTO and SnO2-based CdTe cells was performed 

(CTO/ZTO cells provided by X. Wu). Uncertainty regarding whether these cells were optimized to minimize edge 

shunts prevented an open discussion of the results. Re-evaluation of that data, as well as its relevance to this paper, 

justifies presenting the results at this point.

Figure 3 shows the one-way analysis of variance (ANOVA) in degradation of Voc, Jsc, FF, and η% (delta Voc, delta 

Jsc, delta FF, and delta Eff respectively) measured in 14 stressed CTO/ZTO and 7 SnO2 based cells after 521 hrs of dry 

heat ALT.

Figure 3. ANOVA of changes in (a) Voc, (b) Jsc, (c) FF, and (d) η% measured during dry heat (85 oC) stress testing of CdS/CdTe 

cells grown on CTO/ZTO (X’s) and SnO2-based (circles) substrates

The ANOVA “diamonds” represent group means (center horizontal line) and 95% confidence intervals (CI) of the 

mean (min and max vertical extent of the diamond) degradation observed in cells deposited on CTO/ZTO and SnO2-

based substrates. Statistically significant differences between groups (CTO/ZTO and SnO2-based cells) exist when the 

95% CIs do not overlap. After 521 hours, the mean change in Voc, Jsc, FF, and η% for CTO-based cells were measured 

as -12.5%, -6.0 %, -16.2%, and -30.8% respectively. For SnO2-based cells these same changes were -5.2%, +2.2%, -

8.8%, and -11.6%. Differences in Voc, Jsc, and η% degradation based on CTO-type were clearly shown to be 

significant. Shunting (determined by the inverse-slope of the current-voltage curve at V=0 in the dark) was only 

observed in 1 out of 14 CTO/ZTO cells after 521 hrs of stress and is therefore not relevant as originally suspected. 

(a) (b)

(c) (d)
4 

2. EXPERIMENTAL PROCEDURE

Techniques for depositing the CdS/CdTe layers were presented previously [9]. The basic structure is that of a 

borosilicate (7059) superstrate design in which light passes through a glass/TCO construction (either 7059/cSnO2/iSnO2

or 7059/CTO/ZTO), where it is then absorbed in the n-(CdS)/p-(CdTe) heterojunction. For this study, the chemical-bath 

deposited CdS layer thickness was ~ 80 nm while the CSS deposited CdTe thickness was ~ 8 μm. After the CdTe 

deposition, the finished structure was exposed to vapor CdCl2 (VCC) in an oxygen/helium ambient (100 Torr O2 + 400 

Torr He). SnO2-based cells were CdCl2-treated at either 400 or 405 oC for 5 m. CTO/ZTO-based cells were treated at 

either 400 oC/5 m or 410 oC/10 m. Prior to the back contact step, CdTe surfaces were treated with a NP etch in order to 

form a beneficial, Te-rich layer and to remove surface oxides [10]. Back contacts concluded with the application of a 

relatively thick layer (~50–100 μm) of graphite paste containing CuxTe and HgTe dopants followed by a similarly thick, 

final conducting layer of Ag paste. A narrow (~1 mm) margin of CdTe surrounding the perimeter of the dopant/Ag 

paste contact was used to reduce edge shunting. 

SnO2 layers were again grown by TMT-CVD. The cSnO2 and iSnO2 layers were 500 and 100 nm thick 

respectively. The resulting sheet resistance was measured at ~ 9 ohms/sq. The CTO and ZTO layers were sputtered 

onto unheated substrates to a thickness of 320 and 150 nm respectively. Conditions for sputtering these oxide layers can 

be found in ref [8]. After each sputter deposition, the oxide layer was annealed in 30 Torr He for 15 min at 650 oC with 

the oxide film in contact with a CdS/borosilicate plate (i.e., a “close-proximity” anneal). This anneal has a pronounced 

effect on the CTO layer. There is a large structural change associated with the films transitioning from an amorphous to 

polycrystalline state. A large decrease in volume is observed, i.e., film thickness decreases by about 10%. The optical 

band gap of the CTO layer also increases from about 3.0 eV to 3.5 eV with a several order drop in resistivity to ~1.8 x 

10-4 Ω⋅cm. The buffer layers were harder to characterize due to their thickness and high resistance. The iSnO2 and ZTO 

layers (after anneal) have resistivities of about 1-10 Ω⋅cm and contribute little additional absorption loss to the oxide 

layer stack.

Performance data using standard current versus voltage (J-V) scans were made on cells after fabrication (t = 0) and 

during stress testing with a current-calibrated Oriel solar simulator. Capacitance-voltage (C-V) measurements (dark at 

room temperature) were performed on half the stressed cells using an Agilent 4294A Precision Impedance Analyzer 

operated manually at 100 kHz with a 50 mV oscillation voltage. Capacitance data was collected by scanning voltage in 

two directions. Immediately upon applying a voltage of +0.5 V forward bias, capacitance was measured as voltage was 

quickly swept (~3 s) in a “reverse” direction to -1.5 V where it was held for exactly 5 min. During the subsequent 

“forward” sweep back to +0.5 V, capacitance data was again collected. C-V data for these two directions will 

subsequently be referred to as “rev” and “fwd” scans. The rationale for using “two-way” directional scans will be 

discussed shortly.

Accelerated lifetime test (ALT) conditions have been described before [5]. In short, cells were placed, glass-side 

up, under an Atlas CPS+ solar light source (~AM 1.5; 1-sun) in machined Al blocks designed to keep the cells at Voc

bias. Cell temperature was set at 100 oC. At times equal to 1, 4.4, 10, 28, 73, and 115 hrs cells were removed and 

allowed to relax in the dark for 12-24 hrs. After quick measurements of J-V and C-V, cells were again placed under 

stress. Sometime after the last measurement at T=115 hrs, the temperature controllers failed (over a weekend) resulting 

in excessive heating and destruction of cells. The actual test temperature of 100 oC is suspect (temperatures may have 

been higher) particularly near the conclusion of the test. Regardless, the design of the Al blocks at least assures us that 

cells were tested at the same temperature.

3. RESULTS AND DISCUSSION

The performance of cells fabricated for this study at t = 0 (initial data) is shown in Table 1. Two different 

CTO/ZTO and cSnO2/iSnO2 substrates were used and are appended “_1” & “_2”. Each substrate was approximately 

1.5” x 1.5” in size and provided 8 individual cells. The uniformity in performance of the cells grown on the SnO2-based 

substrates was very good as expected. The mean values for Voc, Jsc, FF, and η% as a function of CdCl2 temperature (400 

oC vs. 405 oC) were 0.824 vs. 0.830 volts, 22.7 vs. 23.1 mA/cm2

, 69.9 vs. 70.7 %, and 13.1 and 13.6 % respectively. 

ANOVA differences in all but FF were statistically significant at the 95% confidence level. A similar analysis between 
5 

“_1” and “_2” substrates showed no difference between substrate. The uniformity in performance for the cells grown on 

the CTO/ZTO substrates was considerably worse. Cells grown on the CTO/ZTO_1 substrate were nearly all dead due to 

essentially no current. For the cells grown on CTO/ZTO_2, FF appears to be the primary reason for performance 

variation. This CTO/ZTO substrate yielded the highest efficiency cell of the study (η% = 14.5%)

Table 1. Initial (t=0) cell performance metrics 

Figure 4 shows the J-V curves for one of the “dead” cells grown on CTO/ZTO_1 (T452_A1) compared with two 

cells from CTO/ZTO_2 showing the wide variation in performance (T453_A1 and T453_B2) observed when using this 

particular CTO/ZTO substrate. 

Figure 4. Initial (t=0) J-V characteristics for CTO/ZTO cells 
6 

Series resistance, Rs, is obviously the reason for the large variation in initial cell performance for these CTO/ZTO 

cells. In our experience, such a large variation in initial cell performance among cells that have been identically 

processed had never been seen when using SnO2-based substrates, which indicates the Rs variation is purely specific to 

the CTO/ZTO substrates alone. At first glance, the root cause would not appear to be CTO compositional fluctuations. 

According to the combinatorial study by Li et al. [11], resistivity varies less than an order magnitude across the entire 

CdO-SnO2 pseudobinary. Though these films were deposited by CVD, this suggests that the observed variations in Rs are 

not due to compositional variations. Also, since the ZTO thickness is only 150 nm thick, even magnitude changes in 

buffer layer resistivity should not impact Rs in these devices. Typical values for cell Rs are on the order of 1-2 Ω⋅cm2 [5]. 

The contribution to Rs for a 150 nm thick ZTO layer with resistivity of 10 Ω⋅cm is only 1.5 x 10-4 Ω⋅cm2

. Rather, 

examination of devices under an optical microscope show that very small “micro” cracks in the CTO were likely 

responsible for very high conductive sheet resistance, and thus, high Rs. The origin of this “cracking” is currently under 

investigation. One possibility is the strain introduced by volume shrinkage during the 650 oC post-deposition anneal.

Because of these problems with CTO/ZTO uniformity, the number of cells for available stress testing was greatly 

reduced. Table 1 identifies the (4) CTO/ZTO and (4) cSnO2/iSnO2 cells that were subsequently chosen for stress testing 

(ALT). J-V measurements were performed on all stressed cells, while C-V measurements (also indicated in Table 1) 

were performed on half this set.

The variation in performance metrics during ALT are shown in Figure 5. Changes in performance are normalized to 

measurements performed at t=0 (initial data). All data for stressed CTO/ZTO (solid lines) and SnO2 (dashed lines) based 

cells are shown in Figure 5. Data with symbols correspond to cells in which additional C-V measurements were made. 

As discussed previously, decreases in performance correlated well with decreases in FF. In general, Figure 5 shows 

more degradation in cells using the CTO/ZTO layers corroborating the earlier study performed in 2004. However, the JV curves show that the mechanism of degradation appears to be different relative to the earlier study.

Figure 5. Percent changes in (a) Voc, (b) Jsc, (c) FF, and (d) η% during ALT at T~100 oC 

Figure 6 compares very representative J-V curve changes with stress for CTO/ZTO cells from these two 

independent studies. CTO/ZTO cells made in this study show considerably less Voc degradation than those from the 

earlier study. Large initial drops in Voc (~15-20%) were observed in all 14 CTO/ZTO cells from the 2004 study at which 

point, degradation shifted to one involving a decrease in FF. No such shift in degradation was observed in this study. 

(a) (b)

(c) (d)
7 

Rather, both Voc and FF appear to degrade concurrently. Also, the overall degradation observed in the 2004 study was 

considerably more even though a lower stress temperature was used. After 100 hrs of stress, the overall performance of 

CTO/ZTO cells from the 2004 study (T = 85 oC) had decreased approximately 20-30% while in this study (T = 100 oC), 

the drop in performance was only about 15-20%.

Figure 6. Representative changes in J-V data with stress time (t in hours) observed in this (a) and the earlier 2004 (b) ALT study of 

CdTe cells grown on CTO/ZTO substrates

In addition to differences in Voc and FF degradation, increased shunting with stress was observed in (3) out of (4) 

CTO/ZTO cells stressed in this study while only (1) out of (14) cells from the 2004 study showed any increase in shunt 

resistance. The lack of any significant increase in Rs for the cells from either study also implies that the Rs nonuniformity observed in the as-grown (t=0) case was a function purely of fabrication and not a stability concern.

Since details concerning the fabrication of the earlier CTO/ZTO cells measured in 2004 were incomplete, it is 

difficult to ascertain why these cells degraded differently. In the present study, the CdS film was grown by CBD. It is 

not clear whether this was the case for the earlier study. One known difference between these sets of devices concerns 

the CSS CdTe deposition itself. In this study, H2 anneals of the glass/CTO/ZTO/CdS stack prior to CdTe deposition 

were avoided. This was based upon previous knowledge that H2 anneals were potentially detrimental to SnO2-based 

substrates [12]. Indeed the highest efficiency achieved at NREL using a SnO2-based substrate (Voc = 0.83 Volts, Jsc = 

24.7 mA/cm2, FF = 74.8, and η% = 15.4) used a CdTe deposition process intentionally modified to avoid this H2 anneal 

step [9]. In the earlier 2004 ALT study, it is almost certain that H2 anneals were used prior to the CSS CdTe deposition 

since these anneals do not appear to impact the initial performance of CTO/ZTO cells. 

It is clear that cell processing has a profound affect not only on the rate of degradation but also on how it manifests. 

This is important. One should not consider degradation as purely representative of the materials involved. One also 

needs to consider the more subtle details associated with fabrication, and possibly, the techniques used to deposit those 

layers. This point is even more poignant when considering the results shown in ref [12]. In this study, the susceptibility 

of SnO2-based layers to reduction in H2 was demonstrated to be process dependent. SnO2 films sputtered onto unheated 

substrates were more prone to reduction than similar materials deposited by CVD onto heated substrates.

This paper will now conclude with a discussion of features observed in C-V measurements made during ALT. C-V 

is commonly used to determine doping profiles in solar cells. Historically, they have also been used to quantify mobile 

ionic charge, particularly Na+

, Li+, and K+ in the dielectric SiO2 layer of metal-oxide field effect devices, by measuring 

field-induced, C-V hysteresis [13]. More recently, capacitance transients were used by Enzenroth et al. [14] and 

Lyubomirsky, et al. [15] to determine the diffusion parameters of mobile ions in CdTe and CuInSe2 cells and materials 

based upon a transient ion drift (TID) technique developed by Heiser and Mesli [16]. In particular, Enzenroth et al., 

used the TID approach to associate an increase in mobile Cui

+ as a function of Cu added during cell fabrication. C-V 

measurements are also, now being used to study transients in monolithic, series-connected CdTe and CuInSe2-based thin 

film modules [17]. C-V hysteresis in modules is not only relevant to understanding product reliability, but also in 

developing pre-measurement, stabilization procedures for base lining the performance of these products.

(a) (b)
8 

In order to capture some of the potential ramifications of C-V hysteresis in this study, we elected to collect C-V data 

during ALT using both rev (+0.5 V to -1.5 V) and fwd (-1.5V to +0.5V) scans. A key requirement of any measurement 

made during ALT is that the measurement be quick enough so as not to introduce unintentional relaxation effects during

long-term stress testing. Another requirement is that the technique “does no harm”. The “two-way” scan C-V approach 

described earlier is quick, requiring ~ 10 min. to perform for each cell tested which made it amenable to measurements 

performed as part of a basic ALT protocol. Also, because cell bias is maintained constant only during negative 

voltages, potentially damaging forward currents at positive bias (and possible cell damage due to heating) were 

minimized. Finally, the technique is performed at room temperature. Since ALT measurements traditionally use 

temperature as an accelerant, any quantification of performance change during ALT should avoid thermal heating, and 

possibly cooling. In retrospect, a more useful two-direction scan technique might avoid the use of forward-bias entirely. 

An explanation for this will be presented in due course.

Representative C-V data collected as a function of scan direction is shown in Figure 7 below for cells made when 

both Cu is added and not added as a constituent of the graphite paste contact respectively. Figure 7(a) displays the 

charge density as a function of depletion width, Wd that would be calculated from C-V data assuming the commonly 

used, one-sided, n+/p junction model (Mott-Schottky plot). Figure 7(b) is the same data showing only Wd plotted as a 

function of reverse-bias. In the latter case, no junction model is assumed as Wd is inversely proportional to the measured 

capacitance, and thus, is a “purer” representation of the data. 

Figure 7. C-V data plotted assuming a 1-sided junction (a) showing charge density vs. depletion width, and (b) as simply depletion 

width vs. reverse bias voltage.

Figure 7 clearly demonstrates how the introduction of Cu into CdTe as a function of cell fabrication affects the 

space-charge region (SCR). The strong decrease in Wd (as Cu is added) reflects an increase in ionized acceptor 

concentration, Na

- in the CdTe possibly as CuCd or as a paired, defect complex. Ref [15] discusses many of the defects 

(both acceptor and donor-like) that may form. The decrease in Wd, since it can be so easily explained by active doping, 

is not too surprising. What is less obvious is the large degree of hysteresis associated with the introduction of Cu. When 

Cu is not intentionally added (i.e., Cu is well-known to be a naturally occurring, trace impurity in CdTe), we see little 

indication of hysteresis within the accuracy of the measurement technique. This has been confirmed in every cell made 

in which Cu was intentionally absent. The presence of Cu introduces significant hysteresis in which Wd measured 

during the second (fwd) scan is always lower than the value of Wd determined during the first (rev) scan. Hysteresis in 

C-V measurements on polycrystalline thin film cells has also been reported by others [18, 19] in which the authors 

associated hysteresis with the presence of deep states.

The TID explanation for the hysteresis proceeds as follows. The cell is biased in the dark at point A (+0.5V forward 

bias) in Figure 7. The bias is immediately decreased to -1.5V (point B’; reverse bias) and the C-V data collected. In this 

A

B’

(a) (b) “hysteresis”

B’’
9 

sense, we are effectively probing the cell SCR with any mobile ions (presumably Cui

+

) in an “equilibrium” or “relaxed” 

state. At point B’, the cell bias of -1.5V is held for exactly 5 min. During this time, the capacitance is observed to 

increase, with a corresponding decrease in Wd (point B’’). The TID model suggests that as Cui

+ (a donor-like defect) 

moves towards the back contact, the screening effect it has on negatively-charged, ionized acceptors is removed such 

that the SCR charge density must increase, and Wd decrease in order to maintain charge-neutrality. Thus, the change in 

depletion width can be explained by assuming mobile, positively charged ions. 

From an electronic perspective, the same C-V hysteresis can be explained by considering majority carrier trap 

emission within the CdTe space-charge. This effect is shown in Figure 8, in which reverse-bias results in the raising of 

electron energies in the CdTe relative to the window (n) layers.

Figure 8. CdS/CdTe band structure during voltage sweep v = 0 (left) to v = -1.5V at t = 0+ (middle) and t > 0 (right). The depletion 

width initially increases then decreases as holes are emitted from the CdTe space-charge region.

When the cell bias is changed from v = 0 to a reverse bias as shown in Figure 8, the depletion width increases since 

the negative-charge of the SCR is initially screened, not by mobile Cui

+ ions, but rather by holes initially occupying deep

states in the CdTe. Given adequate time, these holes are emitted into the valence band where they are quickly removed 

by the field. Cell capacitance increases with time as holes are emitted, and again, Wd decreases. The hole emission 

relaxation time τem associated with this capacitance increase is given by [20]:

[( ) ]

p th V

VT

em N

EE kT

υσ

τ exp − / = (1)

where ET and EV are the trap and valence band energies, σp and υp are the hole capture cross section and thermal velocity 

respectively, and NV is the valence band density of states. Note that for large values of ET – EV (expected in wide band

gap materials like CdTe) relaxation times on the order of minutes are possible.

Relaxation times associated with the capacitance increase from B’ to B’’ shown in Figure 7 are this order of 

magnitude. Figure 9 shows a characteristic relaxation curve typical of how capacitance increases at point B.

Figure 9. Typical capacitance relaxation observed when holding cells at a 

reverse-bias of – 1.5 V reflected as a decrease in Wd (Figure 7) pt B’ B’’.
10

 

At this point, we have two plausible explanations for the C-V hysteresis observed in this study. Each is based upon 

a different mechanism. The TID approach [16] associates the magnitude of hysteresis with an increase in free ions 

within the CdTe. The electronic model implies an increase in deep states with increasing hysteresis. Fortunately, 

techniques for discerning these two mechanisms have been suggested. For example, the ratio of relaxation times 

associated with the capacitance change during zero-bias and reverse-bias states (what is referred to as ionic filling and 

accumulation in [16]) should equal the ratio (qVrev/kT) where Vrev is the reverse-bias applied to the cell. This ratio 

should be much greater than unity. This determination however requires C-V voltages ≤ 0 volts, i.e., ion motion is fieldassisted only during the reverse-bias. Another way to assert ionic behavior is to determine the voltage dependence of 

relaxation when changing the cell bias from Vrev to zero. For ionic effects, the relaxation time should be a function of 

reverse-bias as ions are forced to thermally diffuse longer distances. This is argued as not being so for electronic 

processes.

In two studies involving both CdTe films [14] and single crystals [15], data was given to suggest the validity of Cui

+

ion migration as responsible for C-V hysteresis. In retrospect, the two-direction C-V scan technique used to monitor 

degradation in this study should have avoided positive voltages. A better procedure would have involved using voltage 

scans between 0 volts and different reverse-biases while also measuring the capacitance transient at each extreme point. 

Such a technique would allow for better interpretation of the data while at the same time not compromising the integrity 

of the ALT study. Positive voltages inject minority carriers into the CdTe which complicates the data analysis. Though 

useful for Mott-Schottky studies, positive biases are not necessary for determining either trap or mobile ion 

concentrations.

In order to quantify the observed changes in C-V during ALT, we arbitrarily define the C-V hysteresis obtained in 

our measurements as the difference in depletion width observed at v = 0, i.e., Wd,rev – Wd,fwd as shown in Figure 7. A plot 

of this value with stress (Figure 10) for the cells whose general degradation characteristics are shown in Figure 5 shows 

an interesting correlation with performance degradation.

Figure 10. Depletion width hysteresis plotted as a function of ALT stress for CdTe devices grown on both CTO/ZTO and 

cSnO2/iSnO2 glass substrates

As cells degrade, there is a near monotonic increase in hysteresis. The Cu-doped, graphite paste contacts contain 

ample Cu to source Cu well beyond the termination of back contact fabrication. For example, a typical Cu-containing 

paste contains approximately 0.25 gms of Cu1.4Te for each 10 grams of carbon electrodag. Approximating the molecular 

weight of the electrodag to that of carbon, and assuming an approximate electrodag thickness of 100 microns (commonly 
11

observed in cross-sectional images) and a CdTe thickness of 10 microns, the potential at% ratio of Cu to Cd is on the 

order of 0.10. Only a fraction of this Cu is introduced into the CdTe film during routine back contact processing. The 

presence of this “infinite Cu source” would explain the observed increase in hysteresis observed in the cSnO2/iSnO2 cells 

as Cu diffuses continuously, during the course of ALT, into the CdTe film. However, since the CTO/ZTO cells share 

the same paste contact and back contact processing, the greater rate of hysteresis increase seen for these latter cells in 

Figure 10 suggests an additional source of ion contamination. The only real difference between the CTO/ZTO and 

SnO2-based devices is indeed the TCO stannate layers. 

There are three generally accepted methods by which conductivity is improved in these stannate structures. The 

spinel structure (composed of 32 close-packed oxygen atoms) contains 64 and 32 possible tetrahedral and octahedral 

interstitial sites of which only 1/8 and 1/2 of these sites are occupied by cations. In the inverse-spinel Cd2SnO4 structure, 

the 8 tetrahedral sites are occupied entirely by Cd2+, while the 16 octahedral sites are shared equally by Cd2+ and Sn4+. 

The most intuitive mechanism by which to improve CTO conductivity is to introduce additional Cd interstitials. 

Another possibility is to introduce oxygen vacancies though the formation energy may be too high. Finally, n-type 

conductivity in CTO can be achieved by the replacement of an octahedrally coordinated Cd2+ with Sn4+ [21]. The latter, 

combined with basic thermodynamics would explain a consistent observation concerning CTO and ZTO films. CTO 

films can exhibit high conductivities, yet, ZTO films are always very resistive. Thermodynamically, Zn is a strong 

reducing agent and will reduce both SnO2 and CdO, i.e., the Zn—O bond is favored. At the same time, SnO2 is 

favorable relative to CdO. In CTO and ZTO structures, it is therefore, thermodynamically possible that Sn4+ will tend to 

replace octahedrally coordinated Cd2+ ions (i.e., conducting CTO), and unfavorable that it will replace similarly 

coordinated Zn2+ ions (i.e., resistive ZTO).

It was at first suspected that the complex defect chemistry of CTO and ZTO films as well as their formation could 

be responsible for the larger degradation observed in CTO/ZTO devices. For example, these films were sputtered onto 

unheated substrates and then converted by a high temperature CdS proximity anneal. The films undergo considerable 

modification during this step. It would be presumptuous to assume that post-annealed films are entirely single phase and 

crystalline, and void of secondary phases. Also, the strongly reducing nature of Zn should always be suspect due to its 

high chemical potential. Zn, after all, is regularly used as a catalyst to reduce and subsequently remove SnO2 from glass 

during routine cleaning procedures. The decomposition of either CTO or ZTO would however not be expected to affect 

cell performance much. Again, it has been reported that large variations in CTO stoichiometry only affect resistivity 

slightly [11] and as discussed previously, any change in ZTO resistivity would be over-shadowed by the already high 

resistivity of the CdTe itself. This is also corroborated by the lack of any significant increase in series resistance 

observed with stress in these cells as shown in Figure 6. However, changes in CTO and ZTO film composition might 

manifest electronically by either introducing additional mobile ions into CdTe as well as additional deep states during 

ALT. The fact that there is no clear mechanism by which the addition of mobile ions from the CTO and ZTO layers 

would degrade performance indeed does suggest that it is rather, the formation of deep states, and not mobile ions, that 

may be responsible for the degradation observed in this study. The formation of deep states, and thus increased 

recombination will directly impact the performance of CdTe solar cells.

4. CONCLUSIONS

CdS/CdTe cells deposited on CTO/ZTO transparent conducting oxides show greater initial performance relative 

to more conventional SnO2-based substrates due to the superior optical and electrical properties of the oxide layers and 

the ability of using more rigorous CdCl2 processing. Open-circuit voltage is not observed to increase when using the 

CTO/ZTO substrates. Performance uniformity when using the CTO/ZTO substrates was a problem however. When 

exposed to accelerated lifetime testing under 1-sun illumination, Voc bias, and both 85 °C and 100 °C stress 

temperatures, the CTO/ZTO cells did not perform as well as similar devices grown on SnO2-based substrates though the 

mechanism of degradation is suspected to be strongly determined by how the subsequent CdS/CdTe cells were grown. 

Considerable C-V hysteresis was observed in Cu-doped CdTe cells. Degradation in cells correlates well with an 

increase in this hysteresis. The hysteresis itself can be explained by either ionic motion of free charge in the CdTe, or 

majority carrier (hole) emission and charging of deep states in the CdTe space-charge region. Performance degradation 

could not be explained simply by considering the motion of ions. Rather, it is suggested, that ultimately, the formation 

of additional deep states, perhaps through the decomposition of unstable CTO and/or ZTO layers, may be responsible for 

the increased degradation observed in CTO/ZTO cells.
12

5. ACKNOWLEDGEMENTS 

This work was supported by the U.S. Department of Energy under Contract No. DOE-AC36-08G028308 with 

the National Renewable Energy Laboratory (NREL). The authors thank Dr. Jian Li for discussions concerning 

admittance spectroscopy, Dr. Tim Gessert for better understanding the stannate sputtering process, and finally, Dr. 

Xiaonan Li for her knowledge regarding the variations in CTO electrical properties with composition.

6. REFERENCES 

[1] McMahon, T. J., Berniard, T. J., and Albin, D.S., “Nonlinear shunt paths in thin-film CdTe solar cells,” J. Appl. 

Phys. 97, 054503, (2005).

[2] Karpov, V.G., Compaan, A.D., and Shvydka, D., “Effects of nonuniformity in thin-film photovoltaics,” Appl. Phys. 

Lett., 80(22), 4256-4258 (2003).

[3] Albin, D.S., Demtsu, S.H., and McMahon, T.J., “Film thickness and chemical processing effects on the stability of 

cadmium telluride solar cells,” Thin Solid Films, 515, 2659-2668 (2006).

[4] Demtsu, S.H., Albin, D.S., Pankow, J.W., and Davies, A., “Stability study of CdS/CdTe solar cells made with Ag 

and Ni back-contacts”, Sol. Energy Mat. & Solar Cells, 90, 2934-2943 (2006).

[5] Albin, D.S., “Accelerated Stress Testing and Diagnostic Analysis of Degradation in CdTe Solar Cells,” in 

[Reliability of Photovoltaic Cells, Modules, Components, and Systems], ed. N.G. Dhere, SPIE, ISBN 

9780819472687, vol. 7048, DOI 10.1117/12.795360 (2008).

[6] Woodbury, H., Aven, M., "Some Diffusion and Solubility Measurements of Cu in CdTe,” J. Appl. Phys. 39(12), 

5485-5488 (1968).

[7] McCandless, B., Engelmann, M., and Birkmire, R., "Interdiffusion of CdS/CdTe thin films: Modeling x-ray 

diffraction line profiles," J. Appl. Phys. 89(2), 988-994 (2001).

[8] Wu, X., "High efficiency polycrystalline CdTe thin-film solar cells," Solar Energy 77, 803-814 (2004).

[9] Rose, D.H., Hasoon, F.S., Dhere, R.G., Albin, D.S., Ribelin, R.M., Li, X.S., Mahathongdy, Y., Gessert, T.A., and 

Sheldon, P., “Fabrication Procedures and Process Sensitivities for CdS/CdTe Solar Cells,” Prog. Photovolt: Res. 

Appl. 7, 331-340 (1999).

[10] Levi, D., Albin, D., and King, D., “Influence of Surface Composition on Back-contact Performance in CdTe/CdS 

PV Devices,” Prog. Photovolt: Res. Appl. 8, 591-602 (2000).

[11] Li, X., Gessert, T.A., and Coutts, T., “The properties of cadmium tin oxide thin-film compounds prepared by linear 

combinatorial synthesis,” Appl. Surf. Science 223, 138-143 (2004).

[12] Albin, D., Rose, D., Dhere, R., Niles, D., Swartzlander, A., Mason, A., Levi, D., Moutinho, H., and Sheldon, P., 

“Tin Oxide Stability Effects – Their Identification, Dependence on Processing and Impacts on CdTe/CdS Solar Cell 

Performance,” in [NREL/SNL Photovoltaics Program Review], eds. C.E. Witt, M. Al-Jassim, and J.M. Gee, AIP 

Conference Proceedings 394, 665-681 (1997).

[13] Snow, E.H., Grove, A.S., Deal, B.E., and Sah, C.T., “Ion Transport Phenomena in Insulating Films,” J. Appl. Phys. 

36(5), 1664-1673 (1965).

[14] Enzenroth, R.A., Barth, K.L., and Sampath, W.S., “Transient Ion Drift Measurements of Polycrystalline CdTe PV 

Devices,” 4th IEEE – World Conference Photovoltaic Energy Conversion (WCPEC), Hawaii, 449-452 (2006).

[15] Lyubomirsky, I., Rabinal, M.K., and Cahen, D., “Room-temperature detection of mobile impurities in compound 

semiconductors by transient ion drift,” J. Appl. Phys. 81(10), 6684-6691 (1997).

[16] Heiser, T., and Mesli, A., “Determination of the Copper Diffusion Coefficient in Silicon from Transient Ion-Drift,”

Appl. Phys. A 57, 325-328 (1993).

[17] Del Cueto, J.A., Deline, C.A., Albin, D.S., Rummel, S.R., and Anderberg A., “Striving for a standard protocol for 

preconditioning or stabilization of polycrystalline thin film photovoltaic modules,” ibid. these proceedings. [18] Wimbor, M., Romeo, A., and Igalson, M., “Electrical characterization of CdTe/CdS photovoltaic devices,” OptoElectronics Review 8(4), 375-377 (2000)

[19] Hegedus, S.S., and Shafarman, W.N., “Thin-Film Solar Cells: Device Measurements and Analysis,” Prog. 

Photovolt: Res. Appl. 12, 155-176 (2004).

[20] Schroder, D.K., in [Semiconductor Material and Device Characterization], John Wiley & Sons, (1990).

[21] Zhang, S.B., Wei, S., “Self-doping of cadmium stannate in the inverse spinel structure,” Appl. Phys. Lett. 80, 1376-

1378 (2002).
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Degradation and Capacitance-Voltage Hysteresis in CdTe Devices

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14. ABSTRACT (Maximum 200 Words)

CdS/CdTe photovoltaic solar cells were made on two different transparent conducting oxide (TCO) structures to identify 

differences in fabrication, performance, and reliability. In one set of cells, chemical vapor deposition (CVD) was used to deposit a 

bi-layer TCO on Corning 7059 borosilicate glass consisting of a F-doped, conductive tin-oxide (cSnO2) layer capped by an 

insulating (undoped), buffer (iSnO2) layer. In the other set, a more advanced bi-layer structure of sputtered cadmium stannate 

(Cd2SnO4; CTO) as the conducting layer and zinc stannate (Zn2SnO4; ZTO) as the buffer layer was used. CTO/ZTO substrates 

yielded higher performance devices; however, performance uniformity was worse due to possible strain effects associated with 

TCO layer fabrication. Cells using the SnO2-based structure, only slightly lower in performance, exhibited considerably greater 

performance uniformity. When subjected to accelerated lifetime testing at 85 - 100oC under 1-sun illumination and open-circuit 

bias, more degradation was observed in CdTe cells deposited on the CTO/ZTO substrates. Considerable C-V hysteresis, defined 

as the depletion width difference between reverse and forward direction scans, was observed in all Cu-doped CdTe cells. 

Hysteresis increases with increasing stress and degradation; the mechanism is discussed for an ionic-drift model and one 

involving majority carrier emission in the space-charge region. 

15. SUBJECT TERMS

PV; CdTe; solar cell; capacitance-voltage; hysteresis; DLTS; transient ion drift; reliability; degradation; 

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