Theory and Operation of Cold Field-effect Transistor (FET) 

External Parasitic Parameter Extraction 

by Benjamin D. Huebschman, Pankaj B. Shah, and Romeo Del Rosario 

ARL-TR-4812 May 2009 

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Army Research Laboratory 

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ARL-TR-4812 May 2009 

Theory and Operation of Cold Field-effect Transistor (FET) 

External Parasitic Parameter Extraction 

Benjamin D. Huebschman, Pankaj B. Shah, and Romeo Del Rosario 

Sensors and Electron Devices Directorate, ARL 

Approved for public release; distribution unlimited. 
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Theory and Operation of Cold Field-effect Transistor (FET) External Parasitic 

Parameter Extraction 

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Benjamin D. Huebschman, Pankaj B. Shah, and Romeo Del Rosario 

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14. ABSTRACT 

The design of monolithic microwave integrated circuits (MMIC) is dependent on the ability to generate accurate device 

models. Prior knowledge of the external parasitic components is required to determine the small-signal model of the intrinsic 

device. In this report, we describe a technique and its implementation for extracting external device parasitics. The term cold 

field-effect transistor (FET) refers to measurements taken when the drain is at the same voltage as the source. 

15. SUBJECT TERMS

FET, gate extension, small-signal model 

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Benjamin D. Huebschman 

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iii 

Contents 

List of Figures iv

1. Introduction 1

2. Theory 1

2.1 Reverse Bias: Shunt Parasitic Capacitor Extraction........................................................2 

2.2 Forward Bias: Series Parasitic Capacitor Extraction ......................................................3 

3. Measurement Procedure and Software Operation 6

3.1 System Hardware ............................................................................................................7 

3.2 Procedures .......................................................................................................................8 

4. Results 11

5. Conclusions 13

6. References 15

Distribution List 16 
iv 

List of Figures 

Figure 1. External parasitic equivalent circuit model. ....................................................................2 

Figure 2. (a) Simplified equivalent circuit model of the reverse biased device and (b) with 

series components removed. ......................................................................................................2 

Figure 3. Admittance matrix equivalent circuit model. ..................................................................3 

Figure 4. High frequency model of the forward-biased device. .....................................................4 

Figure 5. High frequency model of the forward-biased device with parasitic capacitances 

deembeded. ................................................................................................................................5 

Figure 6. Impedance matrix equivalent circuit model. ...................................................................5 

Figure 7. Flow chart for cold FET programs (a) instrument control (b) parasitic capacitance 

calculation (c) series parasitic calculation. ................................................................................7 

Figure 8. Block diagram of the cold FET measurement system.....................................................7 

Figure 9. ADS circuit used to compare measured data with the model for the reverse biased 

device. ......................................................................................................................................11 

Figure 10. Reverse biased measured and modeled S-parameters compared (a) S11 and S12

and (b) S22 and S21....................................................................................................................12 

Figure 11. ADS circuit used to compare measured data with the model for the forwardbiased device............................................................................................................................12 

Figure 12. Forward biased measured and modeled S-parameters compared (a) S22 and S21 

(b) S11 and S12. .........................................................................................................................13 
1 

1. Introduction 

Existing semiconductor models are based primarily on modeling the active components of the 

intrinsic device (1). The design of monolithic microwave integrated circuits (MMIC) is 

dependent on the ability to generate accurate device models. In order to accurately model the 

intrinsic device, one needs a mechanism for extracting external parasitics. A well-known 

procedure for measuring external parasitics has been implemented with a modification (1–3). 

The results observed from using the extraction technique suggest that it is a reliable method for 

determining parasitic elements. 

2. Theory 

The difficulty in determining the component values of the equivalent circuit model of either a 

large-signal model or a small-signal model comes from ambiguity. For the purposes of this 

report, the term ambiguity, in the general case, refers to a calculated result that may result from 

several different inputs. In the specific case, ambiguity refers to a set of scattering parameters 

(S-parameters) that could be the result of different equivalent circuits or multiple instantiations 

of a single equivalent circuit using different sets of component values. The key to eliminating 

ambiguity and solving for a single unique solution is being able to perform experiments capable 

of isolating different parts of the circuit model so that they can be measured separately. This is 

done by applying a bias to a device that causes it to behave in a predictable manner. Outside of 

the normal operating regime of the device, a high electron mobility transistor (HEMT) can be 

forced to behave as either a short circuit or an open circuit. Figure 1 shows the model for the 

external parasitics that is used in this report and the equivalent circuit models currently under 

development at the U.S. Army Research Laboratory (ARL) (1). 
2 

Figure 1. External parasitic equivalent circuit model. 

The intrinsic device model is not relevant to the topic of this report and as such is treated as a 

black box. During the cold field-effect transistor (FET) measurements, the source and the drain 

are both held at zero volts. When biased in this manner, the device behaves like a diode. 

2.1 Reverse Bias: Shunt Parasitic Capacitor Extraction 

The device is reversed biased by setting the drain and source to zero volts and applying a 

negative voltage to the gate. When the device is reversed biased, the intrinsic device smallsignal low frequency behavior can be modeled as an open circuit. In this case the diode is 

reverse biased. This setup allows the equivalent circuit model to be represented as a set of 

capacitors in parallel, as shown in figure 2. 

 (a) (b) 

Figure 2. (a) Simplified equivalent circuit model of the reverse biased device and (b) with series 

components removed. 

Cpdds

Cpdgs

D

S

Cpdgd

G

Rg Rd

Rs

Lg Ld

Ls Cpdds

Cpdgs

D

S

Cpdgd

G

Rg Rd

Rs

Lg Ld

Ls Cpdds

Cpdgs

D

S

Cpdgd

Intrinsic 

Device

G
3 

The circuit then becomes a three-terminal system connected by shunt capacitors. The equivalent 

Y-parameter model is shown in figure 3 (4). 

Figure 3. Admittance matrix equivalent circuit model. 

The procedure for calculating the parasitic capacitances is shown below: 

1. Apply a sufficiently negative bias to the device to pinch off the gate and drain. 

2. Measure the S-parameters of the device. 

3. Convert the S-parameters into admittance parameters. 

4. Calculate the parasitic capacitances using the admittance parameters. 

Equations 1–3 are used to calculate the parasitic capacitance for a given set of admittance 

parameters: 

Im( ) 12



Y Cpgd   (1) 

Im( ) Im( ) 11 12

 

Y Y Cpgs   (2) 

Im( ) Im( ) 22 12

 

Y Y Cpds   (3) 

2.2 Forward Bias: Series Parasitic Capacitor Extraction 

The procedures for extracting the series parasitic component values from the forward-biased 

device are analogous to those for the reversed-biased device but are more complicated and 

include several additional considerations. When the device is forward biased, the intrinsic 

device behaves like a short circuit. Measurement has shown that at high frequencies, a residual 

gate capacitance is present on the device and must be included in the model when extracting 

the parasitics. Figure 4 shows the model used to extract parasitics when the device is 

forward biased. 

-Y12

Y11 +Y12 Y22 +Y12
4 

Figure 4. High frequency model of the forward-biased device. 

The procedure for calculating the parasitic capacitances is as follows: 

1. Apply a positive voltage to the gate to drive sufficient current through the device to put the 

diode into the “on” state but not enough current to damage the device. 

2. Measure the S-parameters of the device. 

3. Convert the S-parameters to Y-parameters. 

4. Subtract the shunt parasitic capacitances. 

5. Convert the S-parameters to Z-parameters. 

6. Calculate the component values of the series elements. 

In step 4, the admittance of the shunt capacitors are subtract from the extrinsic Y-parameters. 

The equations used for subtracting the Y-parameters are shown below: 

( ) Y11  Y11  i Cpgs Cpgd   (4) 

( ) Y22  Y22  i Cpds Cpgd   (5) 

Y Y i Cpgd 21  21    (6) 

Y Y i Cpgd 12  12    (7) 

Rg Rd

Rs

Lg Ld

Ls Cpdds

Cpdgs

D

S

Cpdgd

G

Cg
5 

Following this, the admittance parameters with the parasitic capacitances removed are converted 

into impedance parameters. The equivalent circuit with the parasitic capacitance removed is 

shown in figure 5. 

Figure 5. High frequency model of the forward-biased 

device with parasitic capacitances deembeded. 

This model shows a three-terminal passive device. A well-known technique for determining the 

Z-parameters of such a system is shown in figure 6 (4). 

Figure 6. Impedance matrix equivalent circuit model. 

From this, we can determine the impedance parameters of the model. Equations 8–10 show how 

to calculate the impedance parameters of the model in figure 5 (2): 

gs

sg sg C

j LLjRRz )( 11



  (8) 

 2112  s  LjRzz s (9) 

 ) ( 22   sd    LLjRRz sd (10) 

Z11 - Z12 Z22 - Z12

Z12
6 

Based on these equations, the parameter values can be calculated: 

 ) Re( 12 R z s  (11) 

g Rs R  Re(z11)  (12) 

d Rs R  Re(z22 )  (13) 



Im( ) 12 z Ls  (14) 

d Ls

z L   

Im( ) 22 (15) 

gs

g s C

L z L 2

11 Im( ) 1

     (16) 

The term Cgs must be determined by a separate procedure. There are several useful techniques 

for calculating Cgs. One can calculate Cgs using a polynomial fit function on the reactive 

component of the impedance. We have developed a technique that uses differentiation to isolate 

elements that have different frequency dependence. Others have used knowledge of the 

fabrication process to estimate Cgs. This component can also be determined by examining the 

resonance properties of that branch of the T junction. 

3. Measurement Procedure and Software Operation 

We implemented the cold FET method in the Radio Frequency (RF) Test lab. Figure 7 

shows a graphic representation in flow chart form of the programs used to perform the cold 

FET measurement. 
7 

 (a) (b) (c) 

Figure 7. Flow chart for cold FET programs (a) instrument control (b) parasitic capacitance 

calculation (c) series parasitic calculation. 

3.1 System Hardware 

We used the ARL load pull system depicted in figure 8 to perform the cold FET measurements. 

Figure 8. Block diagram of the cold FET measurement system. 

In order to perform the required measurements for the cold FET test, the test system must be able 

to apply a bias to the device, measure the current, and measure the S-parameters. The bias 

controls the operating regime of the device under test (DUT). The current must be monitored in 

order to tell when the device is sufficiently forward biased so the diode junction is in the “on” 

Start

Apply Reverse 

Bias

Measure

S-parameters

Stop

Measure

S-parameters

Apply Forward 

Bias

Record

S-parameters

Record

S-parameters

Start

Convert

S to Y

parameters

Stop

Start

Calculate

Series Parasitics

Stop

Convert

S to Y

parameters

Deembed

Parasitic 

Capacitances

Convert

Y to Z

parameters

Calculate

Parasitics

Capacitances

Read 

S-parameters 

from file

Output 

Parasitics

Capacitances

Read 

S-parameters 

from file

Output 

Series Parasitics

Gate Power Supply

Agilent 4142B 

SMU 41421B 18 

Bias Tee 

Agilent 

11612V K62 

Force Sense GNDU

Bias Tee 

Pico Pulse Lab 

334294 

Force Sense

Vector Network Analyzer

Agilent PNA E8364A 

Gate Power Supply

Agilent 4142B 

SMU 41421B 18 

DUT
8 

state. The S-parameters are used to measure the high frequency model of the device. In our 

setup, the voltage and current were both provided and measured by an HP4142B power supply. 

The S-parameters were measured using an Agilent E8364A. 

The hardware is connected to a computer from where the instruments are externally controlled. 

We used the programs written for the scripting language program MATLAB to control the 

experiment and record the measurements. We recorded the data into a series of files, and then 

analyzed this data using different algorithms, as well as implemented the data in MATLAB and 

calculated and recorded the values for the parasitic elements. 

3.2 Procedures 

Prior to performing the experiment, we calibrated the Vector Network Analyzer (VNA) using the 

thru, reflect, line (TRL) calibration procedure. The DUT is placed on the test station and the 

probes are landed on the device. 

The function that controls the instruments that perform the measurements during the cold FET 

test is Measure_Gate_Data. 

The format for the function is as follows: 

[Ig] = Measure_Gate_Data(Dev_name, Max_gate_power, Max_gate_V, Min_gate_V) 

The inputs are as follows: 

Dev_name (Text string) The device name is a text string that used is in generating the 

output files. 

Max_gate_power (Milliwatts, floating point decimal number) This is the maximum power 

that is allowed to pass through the device before the experiment is 

terminated. 

Max_gate_V (Volts, floating point decimal number) This is upper limit of the voltage 

sweep. 

Min_gate_V (Volts, floating point decimal number) This is lower limit of the voltage 

sweep. 

The outputs are as follows: 

Ig (Milliamps, floating point decimal vector) This is a vector that consists of 

the gate current for each voltage measure. 

The function generates two types of output files: 

• %Dev_name_VDS0.0_VGS#.#.s2p: This file records the measured S-parameters for a 

given bias in touchstone format. 
9 

• % Dev_name_Gate_IV.dcp: This file records the gate current and voltage of the device 

over the range of the voltage sweep. 

An example usage of the function would take the following form: 

[Ig] = Measure_Gate_Data(‘Dev_1_test_1’, 0.1, 3, -5) 

The function begins by biasing the device to the minimum voltage. The S-parameters at this bias 

are measured and recorded in a file. The voltage is increase incrementally. Once the voltage 

passes positive one volt, the program begins measuring and recording the forward bias Sparameter measurements. The sweep terminates when the DC power being dissipated exceeds 

the maximum power or when the voltage reaches the maximum voltage. 

At the successful conclusion of the program, S-parameter files in touchstone format for different 

biases are written to the hard drive, and a file containing the current-voltage parameters is 

generated. 

At this point the measurements are completed and the data must be analyzed. The S-parameters 

are uploaded into MATLAB and two separate functions are used to calculate the values of the 

parasitic elements of the DUT. 

The first function has the format shown below and is used to compute the parasitic capacitances 

from the negatively biased S-parameters: 

[Cpgd, Cpds, Cpgs] = extract_pad_cap(S,Start_freq,Stop_freq) 

The inputs are as follows: 

S (S-parameters, N×5 complex floating point decimal matrix) This input 

contains the S-parameters in touchstone format for the reversed biased DUT. 

Start_freq (GHz, floating point decimal) This is the lowest frequency in the S-parameters 

that is used in the calculations. 

Stop_freq (GHz, floating point decimal) This is the highest frequency in the 

S-parameters that is used in the calculations. 

The outputs are the parasitic capacitances: 

Cpgd (Farads, floating point decimal) This is the gate drain parasitic capacitance. 

Cpds (Farads, floating point decimal) This is the drain source parasitic capacitance. 

Cpgs (Farads, floating point decimal) This is the gate source parasitic capacitance. 

An example usage of the function would take the following form: 

[Cpgd, Cpds, Cpgs] = extract_pad_cap(S_pinch_off,.2,1); 
10 

The other function has the format shown below and is used to compute the parasitic capacitances 

from the negatively biased S-parameters: 

[Rs, Rg, Rd, Ls, Lg, Ld] = extract_L_R(S,Start_freq,Stop_freq, Cpgd, Cpds, 

Cpgs)

The inputs are as follows: 

S (S-parameters, N×5 complex floating point decimal matrix) This input 

contains the S-parameters in touchstone format for the forward-biased DUT. 

Start_freq (GHz, floating point decimal) This is the lowest frequency in the S-parameters 

that is used in the calculations. 

Stop_freq (GHz, floating point decimal) This is the highest frequency in the 

S-parameters that is used in the calculations. 

Cpgd (Farads, floating point decimal) This is the gate drain parasitic capacitance. 

Cpds (Farads, floating point decimal) This is the drain source parasitic capacitance. 

Cpgs (Farads, floating point decimal) This is the gate source parasitic capacitance. 

The outputs are the series parasitic values: 

Rs (Ohms, floating point decimal) This is the series source parasitic resistance. 

Rg (Ohms, floating point decimal) This is the series gate parasitic resistance. 

Rd (Ohms, floating point decimal) This is the series drain parasitic resistance. 

Ls (Henries, floating point decimal) This is the series source parasitic inductance. 

Lg (Henries, floating point decimal) This is the series gate parasitic inductance. 

Ld (Henries, floating point decimal) This is the series drain parasitic inductance. 

An example usage of the function would take the following form: 

[Rs, Rg, Rd, Ls, Lg, Ld] = extract_L_R(S_forward, 20,38, Cpgd, Cpds, Cpgs);

These functions calculate the parasitic parameter values in the manner described in section 2. 
11 

4. Results 

The procedure was performed on a number of devices. The values of the components in the 

equivalent circuit model were extracted and S-parameters for the equivalent circuit model were 

calculated. A representative example of these calculations is presented. We used Agilent’s 

Advanced Design System (ADS) computer aided design program to compare measured data with 

modeled data. Figure 9 shows the circuit used to compare the reverse bias measured data with 

the modeled data. 

S-Parameter Simulation

Linear Frequency Sweep

S2P

SNP1

File="C:\users\default\ModelData\S_pinch_off.s2p"

1 2

Ref

S_Param

SP1

Step=100 MHz

Stop=20.0 GHz

Start=1.0 GHz

S-PARAMETERS

Term

Term3

Z=50 Ohm

Num=3

Term

Term4

Z=50 Ohm

Num=4

C

C3

C=6.67085e-14

C

C1

C=1.0655e-13

C

C2

C=1.1467e-13

Term

Term2

Z=50 Ohm

Num=2

Term

Term1

Z=50 Ohm

Num=1

Figure 9. ADS circuit used to compare measured data with the model for the reverse biased device. 

Figure 10 shows the comparison of the measured and modeled data from 1 to 20 GHz. 
12 

freq (1.000GHz to 20.00GHz)

S(3,4)S(1,2)S(3,3)S(1,1)

Input Reflection Coefficient

freq (1.000GHz to 20.00GHz)

S(4,3)S(2,1)S(4,4)S(2,2)

Input Reflection Coefficient

 (a) (b) 

Figure 10. Reverse biased measured and modeled S-parameters compared (a) S11 and S12 and (b) S22 and S21. 

Note: The lower numbered (1,2) S-parameters are modeled and higher numbers (3,4) are measured. 

The circuit used to model the forward-biased devise is shown in figure 11. 

Linear Frequency Sweep

S-Parameter Simulation

S2P

SNP1

File="C:\users\default\ModelData\S_forward.s2p"

1 2

Ref

S_Param

SP1

Step=100 MHz

Stop=40.0 GHz

Start=10.0 GHz

S-PARAMETERS

R

R1

R=2.5622 Ohm {t}

L

L1

R=

L=2.1096e-011 H {t}

C

C2

C=1.1467e-013 {t}

L

L2

R=

L=2.3308e-011 H

L

L3

R=

L=6.1786e-013 H

R

R2

R=2.1918 Ohm

R

R3

R=1.1611 Ohm

C

C7

C=5.8855e-013 F

C

C3

C=6.67085e-14

C

C1

C=1.0655e-13

Term

Term3

Z=50 Ohm

Num=3

Term

Term4

Z=50 Ohm

Num=4

Term

Term2

Z=50 Ohm

Num=2

Term

Term1

Z=50 Ohm

Num=1

Figure 11. ADS circuit used to compare measured data with the model for the forward-biased device. 
13 

The measured S-parameters for the forward-biased device are compared to those of the modeled 

device in figure 12 from 10 to 40 GHz. The frequency ranges shown in figures 10 and 12 were 

selected to be where the parasitics being measured would have the largest effect. These are low 

frequencies for capacitors and high frequencies for inductors. 

We calculated the error by taking the absolute value of the difference between measured and 

calculated values divided by the absolute value of the measured value. The average error for S11

and S22 for the reverse bias model was less than 6%. The error for the S11 and S22 for the forward 

bias model was less than 7%. The forward and reverse transmission parameters (S12 and S21) 

were higher but on average less than 15%. The magnitude of the transmission parameters was 

much smaller than the reflection coefficients. This aspect makes them more susceptible to 

measurement errors. These errors are from the directly extracted values, and we have 

successfully reduced these values by using optimization algorithms. Optimizing the parasitic 

elements together with the small-signal model of the device resulted in errors of less than 

a few percent. 

freq (10.00GHz to 40.00GHz)

S(4,3)S(2,1)S(4,4)S(2,2)

Input Reflection Coefficient

freq (10.00GHz to 40.00GHz)

S(3,4)S(1,2)S(3,3)S(1,1)

Input Reflection Coefficient

 (a) (b) 

Figure 12. Forward biased measured and modeled S-parameters compared (a) S22 and S21 (b) S11 and S12. 

Note: The lower numbered (1,2) S-parameters are modeled and higher numbers (3,4) are measured. 

5. Conclusions 

The ability to isolate and determine the parasitic capacitances of a device under test is a crucial 

step in generating either small-signal or large-signal device models. We have implemented a 

well-known parasitic extraction algorithm that determines the component values of a device 

model that reliably reproduce the measured data. Our technique builds upon existing parasitic 
14 

extraction algorithms by numerically determining the residual intrinsic device gate 

capacitances. This technique has been fully automated and can be integrated into other 

model generation procedures. 

The software used to perform the measurements and calculations describe in the report is 

available upon request for use in the interest of the Government on a case-by-case basis as 

determined by the authors. 
15 

6. References 

1. Golio, J. M. Microwave MESFETs & HEMTs; Artech House, 1991. 

2. Shealy, J. R.; Wang, J.; Brown, R. Methodology for Small-signal Model Extraction of 

AlGaN HEMTs. IEEE Trans. Electron Devices July 2008, 55 (7), 1603–1613. 

3. Chigaeva, E.; Walthes, W.; Wiegner, D.; Grözing, M.; Schaich, F.; Wieser, N.; Berroth, M. 

Determination of Small-signal Parameters of GaN-based HEMTs. Proceedings 

IEEE/Cornell Conf. High Performance Devices, 2000, 115–122. 

4. Pozar, David. Microwave Engineering; Wiley, 1997. 
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