# Patent

## Title
Method of fabricating power transistor with protected channel

## Abstract

A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. application Ser. No. 12/353,866, filed Jan. 14, 2009, which claims priority to U.S. Provisional Application Ser. No. 61/021,009, filed on Jan. 14, 2008, the entire contents of which are incorporated by reference.


BACKGROUND
The present disclosure relates to semiconductor devices.
Voltage regulators, such as DC to DC converters, are used to provide stable voltage sources for electronic systems. Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC to DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage signal, and filtering the high frequency input voltage signal to generate the output DC voltage. Specifically, the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit. An output filter, typically including an inductor and a capacitor, is coupled between the input voltage source and the load to filter the output of the switch and thus provide the output DC voltage. A controller, such as a pulse width modulator or a pulse frequency modulator, controls the switch to maintain a substantially constant output DC voltage.
LDMOS transistors are used in switching regulators as a result of their performance in terms of a tradeoff between their specific on-resistance (Rdson) and drain-to-source breakdown voltage (BVd—s). On-resistance (Rdson) versus the long-term reliability of device is another performance tradeoff.
Referring to FIG. 1, a conventional LDMOS transistor 300 includes a p-type substrate 302 in which is formed a high-voltage n-type well (HV n-well) 304. In the HV n-well are a source region 310 with an n-doped n+ region 312, a p-doped p+ region 314, and a p-doped p-body diffusion (p-body) 316, a drain region 320 with an n-doped n+ region 322 and a more lightly doped n-type doped drain (NDD) 324, and a gate 330 with a gate oxide 332 and a polysilicon layer 334.
In this conventional LDMOS design, a region 340 in the NDD under the gate 330 that is between the n+ region 312 and the HV n-well 304 experiences the highest electrical field due to the depletion region that is developed to support the high drain voltage potential. Because the region 340 is in the current path during the conduction state, significant engineering effort has been made to minimize this high-resistance region. However, minimizing the high-resistance region further increases the electrical field gradient and can result in a high impact ionization rate. Thus, in a conventional LDMOS design, region 340 is the location where device breakdown happens during the off-state.
When breakdown happens at the region 340, a large quantity of holes and electrons are generated in this region 340. These carriers can easily get trapped in the drain-side gate oxide of the device due to their high energy, and cause intrinsic device characteristic degradation and long-term reliability problem such as FET on-resistance degradation. One technique used to avoid intrinsic breakdown in the power LDMOS device is to include a second device with lower breakdown voltage in parallel with the LDMOS device to clamp the drain voltage of LDMOS device. However, such an approach results in a complex system and higher component count and cost.
SUMMARY
In one aspect, a transistor includes a p-type substrate having a p-type body, an n-well formed in the substrate, a source formed in the n-well, a drain formed in the n-well and spaced apart from the source, a channel region for current flow from the drain to the source, a gate to control channel formation in the channel region between the source and the drain, and a breakdown region in the high-voltage n-well outside the channel region. The source includes a p-doped p-body, a p-doped p+ region within the p-body, and a first n-doped n+ region within the p-body. The drain includes a second n-doped n+ region. The breakdown region is between the p-body and the p-type body of the substrate. The channel region has an intrinsic breakdown voltage, and the breakdown region has an extrinsic breakdown voltage lower than the intrinsic breakdown voltage.
In another aspect, a transistor includes a p-type substrate having a p-type body, an n-well formed in the substrate, a source formed in the n-well, a drain formed in the n-well and spaced apart from the source, a channel region for current flow from the drain to the source, a gate to control channel formation in the channel region between the source and the drain, and a breakdown region in the high-voltage n-well outside the channel region. The source includes a p-doped p-body, a p-doped p+ region within the p-body, and a first n-doped n+ region within the p-body. The drain including a second n-doped n+ region. The breakdown region is between the second n-doped n+ region and the p-type body of the substrate. The channel region has an intrinsic breakdown voltage, and the breakdown region having an extrinsic breakdown voltage lower than the intrinsic breakdown voltage.
Implementations of either of the above aspects may include one or more of the following features. A field oxide on the substrate may surround the n-well and extend over a portion of the n-well. The field oxide may extends over a portion of the p-body. The drain may include an n-doped region that surrounds and is more lightly doped than the second n-doped n+ region. The field oxide may extend over a portion of the n-doped region. The first n-doped n+ region may abut the p+ region. The channel may extend along a first direction and the breakdown region may extend along a second direction perpendicular to the first direction. The intrinsic breakdown voltage may be not more than about 10% greater than the extrinsic breakdown voltage. The intrinsic breakdown voltage may be about 1-2 volts greater than the extrinsic breakdown voltage. The drain may be a distributed drain with a plurality of drain regions each including the second n-doped n+ region, and the gate may include a plurality of gates lines to control a plurality of depletion regions between the source and the drain regions. The source may be a distributed source with a plurality of source regions each including the p-body, the p+ region and the second n-doped n+ region, and the gate may include a plurality of gates lines to control a plurality of depletion regions between the source regions and the drain.
In another aspect, a transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
Implementations may include one or more of the following features. The drain may be a distributed drain with a plurality of drain regions each including the first impurity region, the source may be a distributed source with a plurality of source regions each including the second impurity region, and the gate may include a plurality of gates lines to control a plurality of depletion regions between the source regions and the drain regions. The plurality of drains and the plurality of sources may be arranged in alternating rows. The rows may extend along a first direction, and the breakdown region in the high-voltage well may extend along a second direction perpendicular to the first direction. The breakdown region in the well may be at an end of the rows. The drain may be a distributed drain with a plurality of drain regions each including the first impurity region, and the gate may include a plurality of gates lines to control a plurality of depletion regions between the source and the drain regions. The source may be a distributed source with a plurality of source regions each including the second impurity region, and the gate may include a plurality of gates lines to control a plurality of depletion regions between the source regions and the drain. The substrate may be a p-body substrate and the well may be an n-body well. The first impurity region may be an n-doped n+ region n+ and the second impurity region may be an n-doped n+ region n+. The source may include a p-doped p+ region. The source may include a p-doped p-body, the first impurity region and the p-doped p+ region formed within the p-body. The breakdown region in the high-voltage well may be located adjacent the p-body. The drain may include a n-doped region that surrounds and is more lightly doped than the second n-doped n+ region. A field oxide on the substrate may surround the n-well and may extend over a portion of the p-body. A field oxide on the substrate may surround the high-voltage well and may extend over a portion of the high-voltage well. The intrinsic breakdown voltage may be not more than about 10% greater than the extrinsic breakdown voltage. The intrinsic breakdown voltage may be about 1-2 volts greater than the extrinsic breakdown voltage. The gate may include a first conductive region and a second conductive region electrically isolated and independently biased from the first conductive region, the first conductive region to control channel formation over a p-body in the source, the second conductive region to control an electric potential in the region of intrinsic breakdown.
In another aspect, a method of fabricating a transistor includes selecting dimensions and concentrations for impurity regions in a source and a drain of the transistor, selecting an n-well concentration of an n-well in which the source and drain will be formed, selecting a distance between the impurity regions of source and the drain, determining an intrinsic breakdown voltage of a channel between the source and the drain from the dimension, concentrations, distance and n-well concentration, and selecting a width of a portion of the n-well extending past the source to provide such that the portion of the n-well has an extrinsic breakdown voltage lower than the intrinsic breakdown voltage.
Implementations may include one or more of the following. The substrate may be implanted with the impurity regions having the selected dimensions and concentrations and implanted with the n-well having the selected n-well concentration and width.
Implementations may include one or more of the following advantages. When breakdown occurs, electron-hole pairs generated by impact ionization may be located away from the intrinsic channel region. As a result, FET on-resistance need not degrade as a result of avalanche breakdown. This may be achieved without sacrificing significant silicon area.
The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.



DESCRIPTION OF DRAWINGS
FIG. 1 is a cross-sectional view of a conventional LDMOS transistor.
FIG. 2 is a plan view of an implementation of an LDMOS transistor.
FIGS. 3A, 3B and 3C are cross-sectional views of the LDMOS transistor of FIG. 2.
FIG. 4 is a cross-sectional view of another implementation of an LDMOS transistor.



Like reference symbols in the various drawings indicate like elements.
DETAILED DESCRIPTION
In general, this disclosure concerns a power device with inherent self-protection capability. That is, the device is designed such that when breakdown occurs, electrode-hole pairs generated by impact ionization will occur away from the intrinsic channel region (the explicit current path from the n+ of the drain to the n+/p+ of the source).
In general, the power device takes advantage of the fact that power-LDMOS is not a one-dimensional device in the application. In particular, the device can be designed so that the channel follows a first path (e.g., in a first direction), whereas breakdown occurs along a second path (e.g., in a perpendicular second direction).
FIG. 2 is a plan view of an LDMOS device 100. The LDMOS transistor 100 includes a p-type substrate 102 in which is formed a high-voltage n-type well (HV n-well) 104. In the HV n-well are source regions 110 and drain regions 120 separated by gates 130. The source regions 110 can be extended, with a length LS along the gate that is greater than their width WS in the orthogonal direction. Similarly, the drain regions 120 can be extended, with a length LD along the gate that is greater than their width WD in the orthogonal direction. The dimensions can be measured from the boundaries of the highly doped regions.
The source regions 110 and drain regions 120 can be arranged in alternating rows, each row separated by a gate 130. Although only one drain region 120 is illustrated, the pattern could repeat with more than one drain region 120. Similarly, although only two source regions 110 are illustrated, the pattern could repeat with more than two source regions 110. Also, there could be two drain regions 120 disposed on opposite sides of a single source region 110. In operation, current flows from the drain to the source (as shown by the arrows) through the channel that extends along the length of the gate. In some implementations, the length of the source region is equal to the length of the drain region.
FIG. 3A is a cross-sectional view that is parallel to the width of the source and drain regions. Each gate 130 includes a gate oxide layer 132 and a conductive layer 134, e.g., a polysilicon layer, over the oxide layer 132. In some implementations, the gate oxide can include a thicker region closer to the adjacent drain 120 and a thinner region closer to the adjacent source 110. Each gate can be tied to a common control voltage.
The source region 110 includes an n-doped n+ region 112, a p-doped p+ region 114, and a p-doped p-body diffusion (p-body) 116. Both the n+ region 112 and the p+ region 114 are surrounded by the p-body 116. The n+ region 112 and p+ region 114 abut, with the n+ region closer to the drain region 120. The p-body 116 has a lower concentration of impurities than the p+ region 114. The p-body 116 and the n+ region 112 (e.g., a shallow doped region implanted before the oxide sidewalls) can extend under the gate oxide 132, with the p-body extending farther than the n+ region. Electrical connection to the n+ region 112 and p+ region 114 can be made by contact pads 136 (see FIG. 2) in an overlying metal layer. In some implementations, individual contact pads contact both the n+ region 112 and p+ region 114.
The drain region 120 includes an n-doped n+ region 122 and a more lightly doped n-body doped drain (NDD) 124. The n+ region 122 is surrounded by the NDD 124. The NDD can extend under the gate oxide 132. Electrical connection to the n+ region 122 can be made by contact pads 138 (see FIG. 2) in an overlying metal layer.
The HV n-well 104 has a lower concentration of impurities than the n+ regions 112, 122 and the NDD 124.
FIG. 3B is a partial cross-sectional view parallel to the length of the source, e.g., parallel to the gate line, that passes through the p+ region 114. The p-body 116 can extend farther than the p+ region 114 in the direction parallel to the gate line. Similarly, the HV n-well 104 can extend farther than the p-body 116 in the direction parallel to the gate line.
A portion of the substrate outside the active area can be covered by a field oxide 150. Both the p-body 116 and the HV n-well 104 can extend beneath the field oxide 150 in the region proximate the source 110. The field oxide 150 can completely surround the HV n-well 104. Although not illustrated, a conductive contact can be placed in direct contact with the p-type substrate 102 to provide a substrate electrode at a location beyond the field oxide 150.
As shown, a termination region 140 includes a portion of the HV n-well 104 that is sandwiched between the p-body 116 and the p-type substrate 102. Since this is at the lateral edge of the source region 110 (as opposed to the edge abutting the gate 130), this region does not serve as a channel.
FIG. 3C is a partial cross-sectional view parallel to the length of the drain, e.g., parallel to the gate line, that passes through the n+ region 122. The NDD 124 can extend farther than the n+ region 122 in the direction parallel to the gate line. Similarly, the HV n-well 104 can extend farther than the NDD 124 in the direction parallel to the gate line.
As noted above, a portion of the substrate outside the active area can be covered by a field oxide 150. Both the NDD 124 and the HV n-well 104 can extend beneath the field oxide 150 in the region proximate the drain 120.
As shown, a termination region 142 includes a portion of the HV n-well 104 that is sandwiched between the NDD 124 and the p-body substrate 102. Since this is at the lateral edge of the drain region 110 (as opposed to the edge abutting the gate 130), this region does not serve as a channel.
The device is engineered so that the drain to body extrinsic breakdown voltage (e.g., from the p-body to the p-type body of the substrate, e.g., along the 3B-3B cross-section) is slightly lower than the intrinsic breakdown voltage of the device (through the channel, e.g., along the 3A-3A cross-section). The width WHV of HV n-well 104 between the p-body 116 and the p-body substrate 102, along with the concentrations of the various impurity regions, can be selected so that the breakdown voltage in the termination region 140 is lower than the breakdown voltage in the channel. Alternatively or in addition, the width WHV of HV n-well 104 between the NDD 124 and the p-body substrate 102, along with the concentrations of the various impurity regions, can be selected so that the breakdown voltage in the termination region 142 is lower than the breakdown voltage in the channel, so that extrinsic breakdown voltage (e.g., from the NDD to the p-type body of the substrate, e.g., along the 3C-3C cross-section) is slightly lower than the intrinsic breakdown voltage of the device. By doing so, when breakdown happens, electron-hole pairs generated by impact ionization will be located away from the intrinsic channel region. As a result, FET on-resistance will no longer degrade as a result of avalanche breakdown.
In addition, although FIGS. 3B and 3C illustrate the breakdown regions 140 and 142 on the sides of the source and drain, respectively, that run perpendicular to the gate line, the breakdown region could be under the gate 134, but still not in the intrinsic channel, e.g., the breakdown region could be in a portion of the HV n-well 104 that is between NDD 124 and adjacent P-body 114, but not between the n+ region 122 of the drain 120 and the adjacent n+ region 114 of the source 110, or in a portion of the HV n-well 104 that underlies the gate 134 but is not between the NDD 124 and P-body 114. Moreover, for the outermost source or drain region in the array, it might be possible to create a breakdown region on the side of the source or drain that runs parallel to the gate line 134 but is farther from the gate and associated channel.
As a first order estimation, the difference in breakdown voltage (delta-BV) between the extrinsic path and the intrinsic path can be determined by the product of the maximum current in a breakdown event and the series resistance of the extrinsic breakdown path. The difference in breakdown voltage (delta-BV) can be selected to be less than 10% of the extrinsic breakdown voltage. For example, if the breakdown voltage for a device is about 30 volts, then the concentrations and dimensions of the implanted regions can be selected such that the extrinsic breakdown voltage is about 30 volts and the intrinsic breakdown voltage is about 32 volts. Thus, this new methodology of device engineering achieves self-protection on the device, at a slight cost of delta-BV (1 ̃2V) in the breakdown voltage value but without sacrificing any significant silicon area.
One example of an approach to achieve this intrinsic and extrinsic breakdown voltage difference is described as follows. The intrinsic breakdown voltage can be engineered to the value of desired breakdown by the well-known practices in power LDMOS design. While the extrinsic breakdown voltage in this particular device structure can be tuned to the value of desired breakdown voltage minus delta-BV by adjusting the width of high-voltage N-well sandwiched between two P-type regions at the same potential.
FIG. 4 illustrates another implementation in which each gate region 130 includes two electrically isolated gates 130a, 130b, that can be biased to different potentials. Each gate 130a, 130b includes a gate oxide layer 132 and a conductive layer 134, e.g., a polysilicon layer, over the oxide layer 132. The gates 130a, 130b can extend in parallel. The gate 130a closer to the source 110 is positioned over the portion of the p-body 116 that projects past the n+ region 112, and thus can control channel formation through the p-body 116. The gate 130b closer to the drain is positioned over a portion of the NDD 124 that extends past the n+ region 122 and over the remainder of the channel (which can be undoped except for the HV N-well 104), and thus can control the voltage potential in the region of intrinsic breakdown. Thus, selection of the voltages on the gates 130a, 130b permits selection of both the breakdown voltage value and the location of the breakdown.
A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, although P-type body and P-type substrate are described, the P-type substrate could be replaced by other available P-type implantation. Accordingly, other embodiments are within the scope of the following claims.

## Claims

1. A method of fabricating a transistor, comprising:
selecting dimensions and concentrations for impurity regions in a source and a drain of the transistor;
selecting an n-well concentration of an n-well in which the source and drain will be formed;
selecting a distance between the impurity regions of source and the drain;
determining an intrinsic breakdown voltage of a channel region between the source and the drain from the dimensions, concentrations, distance and n-well concentration;
selecting a width of a portion of the n-well extending past the source to provide such that the portion of the n-well has an extrinsic breakdown voltage lower than the intrinsic breakdown voltage.

2. The method of claim 1, further comprising implanting the substrate with the impurity regions having the selected dimensions and concentrations and implanting the substrate with the n-well having the selected n-well concentration and width.

3. The method of claim 2, wherein the substrate has a p-type body, and implanting the substrate with the impurities regions includes implanting a p-doped p-body in a source region, implanting a p-doped p+ region within the p-body, implanting a first n-doped n+ region within the p-body, and implanting a second n-doped n+ region in a drain region.

4. The method of claim 3, wherein the portion of the n-well is between the p-body and the p-type body of the substrate outside the channel region.

5. The method of claim 3, wherein the portion of the n-well is between the second n-doped n+ region and the p-type body of the substrate outside the channel region.

6. The method of claim 3, comprising forming a gate to control channel formation in the channel region between the source and the drain.

7. The method of claim 6, comprising depositing a field oxide on the substrate surrounding the n-well and extending over a portion of the n-well.

8. The method of claim 7, wherein the field oxide is deposited to extend over a portion of the p-body.

9. The method of claim 6, wherein implanting the substrate with the impurity regions includes forming the drain as a distributed drain with a plurality of drain regions each including the first impurity region, forming the source as a distributed source with a plurality of source regions each including the second impurity region, and wherein forming the gate comprises forming a plurality of gates lines to control a plurality of depletion regions between the source regions and the drain regions.

10. The method of claim 9, comprising forming the plurality of drains and the plurality of sources arranged in alternating rows.

11. The method of claim 10, wherein the rows extend along a first direction, and the portion of n-well extends along a second direction perpendicular to the first direction.

12. The method of claim 10, wherein the portion of the n-well is at an end of the rows.

13. The method of claim 3, wherein implanting the substrate with the impurities regions includes implanting an n-doped region in the drain that surrounds and is more lightly doped than the second n-doped n+ region.

14. The method of claim 13, wherein the first n-doped n+ region is deposited to abut the p+ region.

15. The method of claim 3, comprising implanting the impurity regions such that the channel region extends along a first direction and the portion extends along a second direction perpendicular to the first direction.

16. The method of claim 1, wherein the dimensions, concentrations, distance and width are selected such that the intrinsic breakdown voltage is not more than about 10% greater than the extrinsic breakdown voltage.

17. The method of claim 1, wherein the dimensions, concentrations, distance and width are selected such that the intrinsic breakdown voltage is about 1-2 volts greater than the extrinsic breakdown voltage.