# Patent

## Title
Cross-point memory bias scheme

## Abstract

The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.

## Background
FIELD
The present disclosure relates to a bias scheme for a cross-point memory.
BACKGROUND
Phase change memory is a memory device which typically uses a chalcogenide material for the memory elements. A memory element is the unit that actually stores information. In operation, the phase change memory stores information on the memory element by changing the phase of the memory element between amorphous and crystalline phases. The chalcogenide material may exhibit either a crystalline or an amorphous phase, exhibiting a low or high conductivity. Generally, the amorphous phase has a low conductivity (high impedance) and is associated with a reset state (logic zero) and the crystalline phase has a high conductivity (low impedance) and is associated with a set state (logic one). The memory element may be included in a memory cell that also includes a selector, i.e., a select device coupled to the memory element. The select devices are configured to facilitate combining a plurality of memory elements into an array.
Phase change memory elements may be arranged in a cross-point memory array including row address lines and column address lines arranged in a grid. The row address lines and column address lines, called word lines (WLs) and bit lines (BLs), respectively, cross in the formation of the grid and each memory cell is coupled between a WL and a BL where the WL and BL cross (i.e., cross-point). It should be noted that row and column are terms of convenience used to provide a qualitative description of the arrangement of WLs and BLs in cross-point memory.
A memory cell (e.g., a target memory cell) may be selected by applying bias voltages to the WL and BL that cross at the target memory cell, i.e., WL select voltage, VSELWL, and BL select voltage, VSELBL, respectively. A resulting target cell differential bias voltage (VT—SEL=VSELBL−VSELWL) across the memory element is configured to be greater than a threshold select voltage (Vt) for the memory element. It is desirable that VT—SEL be large enough to reliably select the target cell but not so large as to inadvertently select other cells, particularly non-target cells included in the selected WL or selected BL.
One technique configured to ensure that VT—SEL is large enough while avoiding selecting non-target cells is to apply a debias (“C-cell bias”) voltage to deselected WLs and/or deselected BLs. C-cell bias is configured to reduce or maintain a bias voltage across non-target cells below Vt when an increased VT—SEL is applied to the target cell. The increased VT—SEL is configured to increase the likelihood that the target cell will be selected. Continuously maintaining C-cell bias (i.e., whether or not a memory access has been initiated) increases leakage current in a cross-point array and increases idle current draw and idle power consumption.
Another technique that is configured to ensure that VT—SEL is large enough while avoiding selecting non-target cells, enables C-cell bias for every memory cell selection operation. This technique is configured to avoid increasing leakage current and/or idle current draw but incurs a relatively high energy cost due to charging and discharging associated with establishing and removing the C-cell bias for every memory cell operation. Relatively large bus structures may be necessary to accommodate rapid charging of C-cell bias and/or relatively long delay times may be experienced to allow time enough for all of the memory cells to achieve C-cell bias prior to selecting the target cell.



BRIEF DESCRIPTION OF DRAWINGS
Features and advantages of the claimed subject matter will be apparent from the following detailed description of embodiments consistent therewith, which description should be considered with reference to the accompanying drawings, wherein:
FIG. 1 illustrates a system block diagram consistent with several embodiments of the present disclosure;
FIG. 2 illustrates an example portion of a cross-point memory array including a target cell, A cells, B cells and C cells consistent with one embodiment of the present disclosure; and
FIG. 3 illustrates a flowchart of operations for selectively applying a C-cell bias consistent with various embodiments of the present disclosure.



Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.
DETAILED DESCRIPTION
Generally, this disclosure describes a system and method configured to expand an operation window of a cross-point memory array while minimizing effects on power, energy, die size and/or latency. The system and method are configured to attempt to select a target cell by applying a nominal bias voltage VT—SEL—nominal across the target cell without applying a C-cell bias and to detect whether or not the target cell has been selected. If the target cell has not been selected, then the C-cell bias may be applied and a bias voltage applied to the target cell may be increased by an amount related to the C-cell bias. The C-cell bias is configured to increase the operation window for the target cell when a selection threshold voltage Vt is greater than VT—SEL—nominal. Thus, the C-cell bias may be applied “on-demand”, thereby avoiding increasing idle power consumption associated with continuously applied C-cell bias and avoiding relatively high energy costs associated with applying C-cell bias for every memory cell selection operation.
A selection threshold for a memory cell in the reset state is higher than a selection threshold for a memory cell in the set state. C-cell bias may typically be applied in write operations since read operations are configured to select memory cells in the set state and to avoid selecting cells in the reset state. In other words, a generally lower VT—SEL may be used for read operations than is used for write operations.
FIG. 1 illustrates a system block diagram 100 consistent with several embodiments of the present disclosure. The system 100 includes a processor 102, a memory controller 104 and a memory array 106. The processor 102 is coupled to the memory controller 104 by bus 108. Processor 102 may provide read and/or write requests including memory address(es), and/or associated data to memory controller 104 and may receive read data from memory controller 104. It should be noted that system 100 is simplified for ease of illustration and description.
Memory array 106 corresponds to at least a portion of a phase change cross-point memory and includes a plurality of word lines 115, a plurality of bit lines 117 and a plurality of memory cells, e.g., memory cell 107. Each memory cell is coupled between a word line (“WL”) and a bit line (“BL”) at a cross point of the WL and the BL. Each memory cell includes a memory element configured to store information and may include a memory cell select device coupled to the memory element. Select devices may include ovonic threshold switches, diodes, bipolar junction transistors, field-effect transistors, etc. Memory array 106 is configured to store binary data and may be written to (i.e., programmed) or read from.
Memory controller 104 includes memory controller module 110, WL control module 114 and BL control module 116. Memory controller module 110 is configured to perform operations associated with memory controller 104. For example, memory controller module 110 may manage communications with processor 102. Memory controller module 110 may be configured to identify one or more target WLs associated with each received memory address. Memory controller module 110 is configured to manage operations of WL control module 114 and BL control module 116 based, at least in part, on the identified target WL.
WL control module 114 may include a C-cell bias module 120. WL control module 114 is configured to receive target WL address(es) from memory controller module 110 and to select one or more WLs for reading and/or writing operations. WL control module 114 may be configured to select a target WL by coupling VSELWL (i.e., WL select bias voltage) to the target WL and may be configured to deselect a WL by coupling a WL deselect bias voltage VDESWL to the WL. WL control module 114 may be coupled to a plurality of WLs 115 included in memory array 106. Each WL may be coupled to a number of memory cells corresponding to a number of BLs 117.
BL control module 116 may include a C-cell bias module 124 and/or a sense module 126. BL control module 116 is configured to select one or more BLs for reading and/or writing operations. BL control module 116 may be configured to select a target BL by coupling VSELBL (i.e., BL select bias voltage) to the target BL and may be configured to deselect a BL by coupling a BL deselect bias voltage VDESBL to the BL. WLs and BLs that are not selected may be coupled to deselect bias voltages, i.e., VDESWL and VDESBL, respectively. Nominally, VDESWL and VDESBL are zero.
FIG. 2 illustrates an example portion of a cross-point memory array 200 including a target cell (i.e., cell T), A-cells, B-cells and C-cells consistent with one embodiment of the present disclosure. For example, the portion of the cross-point memory array 200 may correspond to memory array 106 and cell T may correspond to cell 107 of FIG. 1. The example 200 includes a selected WL 202, a selected BL 204, a plurality of deselected WLs 206 and a plurality of deselected BLs 208. Example 200 includes one target cross-point memory cell T, a plurality of A-cells that are included in the selected WL 202 and a plurality of B-cells that are included in the selected BL 204. Example 200 further includes a plurality of C-cells (cross-points of deselected WLs 206 and deselected BLs 208).
The bias voltage across each of the A-cells is VA=VDESBL−VSELWL. The bias voltage across each of the B-cells is VB=VSELBL−VDESWL. The bias voltage across each of the C-cells is VC=VDESWL−VDESBL. Nominally, VDESWL and VDESBL are zero and VSELWL and VSELBL are configured to select a target cell without also selecting an A-cell and/or a B-cell. C-cell bias corresponds to adjusting VDESWL and/or VDESBL to allow VT—SEL to increase (VT—SEL=VSELBL−VSELWL) while maintaining VA and/or VB at their nominal values (that are less than Vt). Vt is a target cell selection threshold voltage. In other words, VT—SEL may be increased by increasing VSELBL and/or decreasing VSELWL but increasing VSELBL without changing VDESWL may cause VB to increase and decreasing VSELWL without changing VDESBL may cause VA to increase. C-cell bias is utilized to adjust VDESWL and/or VDESBL to maintain VA and/or VB below Vt when VT—SEL is increased.
A difference between VT—SEL and a maximum of VA, VB and VC corresponds to the operation window. C-cell bias may thus be utilized to increase the operation window by allowing VT—SEL to increase while maintaining VA and VB at or near their nominal values. In other words, since VA, VB and VC are configured to be less than Vt for proper operation (i.e., selecting only target cell(s)), allowing VT—SEL to increase while maintaining VA and VB at or near their nominal values increases the operation window.
WL control module 114 and BL control module 116 are configured to identify a target cell, e.g., cell T, for a memory access operation, e.g., in response to an input from processor 102 and/or memory controller module 110. WL control module 114 and BL control module 116 are configured to select target cell T by applying VSELWL and VSELBL to a selected WL, e.g., WL 202, and the selected BL, e.g., BL 204, respectively, thereby applying VT—SEL across cell T. If VT—SEL is greater than or equal to the target cell select threshold voltage Vt then cell T may be selected.
Sense module 126 is configured to determine whether or not a target cell, e.g., cell T, is selected. When a memory cell is selected, the memory cell transitions from an OFF state to an ON state and a cell impedance state transitions from a relatively high impedance (e.g., greater than about 10 Mega-ohms (MΩ)) state to a relatively low impedance (e.g., less than about 10 kilo-ohms (kΩ)) state. When the impedance state of the memory cell is relatively low, the memory cell is “selected”. Thus, sense module 226 may be configured to determine whether a target cell, e.g., cell T, has been selected based, at least in part, on the impedance state of the memory cell. For example, sense module 226 may be configured to sense a current through cell T (e.g., current directly or a voltage drop across a sense resistor). Thus, sense module 226 may determine that a cell is selected if the sensed current and/or voltage increases indicating that the impedance has decreased (for a fixed supply voltage).
If sense module 126 determines that cell T has been selected, memory access operation(s) (e.g., read and/or write) on cell T may proceed. If, after applying VT—SEL, sense module 126 determines that cell T has not been selected, C-cell bias module 120 is configured to apply C-cell bias to deselected WL(s) (e.g., deselected WL(s) 206) and/or C-cell bias module 124 is configured to apply C-cell bias to deselected BL(s) (e.g., deselected BL(s) 208). C-cell bias may be achieved by increasing VDESWL and/or decreasing VDESBL from their nominal value (e.g., zero) so that VC increases correspondingly. WL control module 114 and/or BL control module 116 may then be configured to increase VT—SEL by increasing VSELBL and/or decreasing VSELWL by an amount related to the C-cell bias voltage VC. The increased VT—SEL is configured to select cell T (i.e., is configured to be greater than or equal to Vt) and the memory access operation may then proceed.
It may be appreciated that the selection threshold voltage Vt for each memory cell in a cross-point array may vary due, at least in part, to variation in material properties and/or other characteristics of cross-point memory cells. For example, variation in Vt of a cell may be due to geometric variation in the cell shape (e.g., thickness, width, length). Variation in cell shape may result in a variation in Vt in the range of +/−10% of a nominal Vt value. In another example, for some types of memory cells, over time, Vt may increase due to drift and/or decrease due to thermal crystallization of the cell.
For example, Vt for a specific memory cell may have a value between a minimum threshold voltage Vt—MIN and a maximum threshold voltage Vt—MAX. For example, a sampling of a number of memory cells may yield a distribution of Vt values between Vt—MIN and Vt—MAX. Initially, VT—SEL may be set to a nominal value (e.g., VT—SEL—nominal) based, at least in part, on the distribution of Vt values. For example, VT—SEL—nominal may be set to a value of Vt that is greater than, e.g., approximately 50% of the Vt values of the distribution of Vt values. In another example, VT—SEL—nominal may be set to a value of Vt that is greater than, e.g., approximately 80% of the Vt values of the distribution of Vt values. In this example, C-cell bias may be triggered in approximately 20% of the attempts to select a target memory cell (for write operations). The specific setting for VT—SEL—nominal may be selected based, at least in part, on characteristics of the distribution of Vt values. In operation, C-cell bias may be triggered at a frequency related to the distribution. For example, relatively low trigger rates, e.g. less than 1%, may be possible.
If, during operation, VT—SEL set to VT—SEL—nominal does not result in the target cell being selected, VT—SEL may be set to a value greater than or equal to Vt—MAX in order to select the target cell. C-cell bias voltage VC may then be related to a difference between Vt—MAX and VT—SEL—nominal. For example, VC may be equal to Vt—MAX VT—SEL—nominal.
As described herein, VC=VDESWL−VDESBL, thus, C-cell bias may be achieved by increasing VDESWL and/or decreasing VDESBL. For example, to achieve VC of 2 volts, C-cell bias may be applied to a single side of the deselected cells, e.g., VDESWL may be increased to +2 volts and VDESBL may be maintained at zero volts. Of course, a single sided C-cell bias may be similarly achieved by decreasing VDESBL to −2 volts and maintaining VDESWL at zero volts. In another example, C-cell bias may be implemented as a dual-sided balanced approach, e.g., VDESWL may be increased to +1 volt and VDESBL may be decreased to −1 volt to achieve VC of 2 volts.
The single-sided approach is configured to switch voltage to and/or select half of the WLs and BLs as compared to the double-sided approach and, thus, may result in a relatively smaller switching energy cost associated with establishing the C-cell bias. One bias voltage source may be utilized to establish the single-sided C-cell bias compared to the double-sided approach which may rely on two bias voltage sources. The one bias voltage source may be implemented using an existing voltage source depending on the value of the bias voltage. Using an existing voltage source may reduce C-cell bias cost (e.g., die size, energy consumption, complexity).
Applying the C-cell bias when a target cell with VT—SEL set to VT—SEL—nominal is not selected (i.e., when an increased operation window may be necessary) is configured to result in a relatively low average energy compared to approaches that either always apply C-cell bias to all cells all the time or apply C-cell bias during operation of each of the memory cells. For example, C-cell bias may be applied during operation of approximately 20% of the memory cells, consistent with the present disclosure. Thus, idle power draw by C-cell bias may be avoided and energy “cost” associated with C-cell bias may be limited to only those cells that are not selected with VT—SEL—nominal. A maximum current draw associated with a C-cell setup may be limited and a low latency C-cell setup may be allowed since only a few memory cells may utilize the C-cell bias in a specific memory access operation. A bus expansion configured to rapidly establish C-cell bias may thus be avoided.
Table 1 illustrates some example C-cell biasing schemes. In the table, V is volts and VT—SEL is the bias voltage applied to the target cell.















TABLE 1





Scheme
VSELWL
VSELBL
VDESWL
VDESBL
VA
VB
VC
VT_SEL







Zero Bias C-cell
−4 V
+4 V
  0 V
0 V
4 V
4 V
0 V
 8 V


C-cell bias, Balanced WL & BL
−5 V
+5 V
+1 V
−1 V  
4 V
4 V
2 V
10 V


C-cell bias, WL Only
−4 V
+6 V
+2 V
0 V
4 V
4 V
2 V
10 V


On Demand, Expanded window










For Vt ≦ 8 V
−4 V
+4 V
  0 V
0 V
4 V
4 V
0 V
 8 V


For 8 V < Vt ≦ 10 V

+6 V
+2 V
0 V
4 V
4 V
2 V
10 V









The Zero Bias C-cell scheme illustrates example WL and BL voltages and resulting cell bias voltages for C-cell bias of zero, i.e., no C-cell bias. Thus, the target cell may be selected when VT—SEL≧8 volts and Vt is 8 volts. The C-cell Bias with Balanced WL and BL corresponds to increasing VDESWL and decreasing VDESBL equally (i.e., balanced) to achieve the C-cell bias. The C-cell Bias, WL Only scheme is configured to increase only VDESWL to achieve the C-cell bias and increase the target cell bias voltage, VT—SEL.
The rows in the table below On Demand, Expanded window illustrate an example that corresponds to an embodiment consistent with present disclosure. In this example, when Vt is less than or equal to 8 volts and VT—SEL is 8V without C-cell bias (i.e., the target cell is selected without applying C-cell bias), C-cell bias is not applied. Continuing with this example, when Vt is greater than 8 volts and less than or equal to 10 volts, a C-cell bias of 2V may be achieved by increasing VDESWL to +2V and VSELBL may then be increased to +6V to achieve a VT—SEL of 10V. Of course, the a C-cell bias of 2V may be similarly achieved by decreasing VDESBL to −2V and VSELWL may be decreased to −6V to achieve a VT of 10V in order to select the target cell. Thus, consistent with the present disclosure, C-cell bias may be applied “on demand” and the operation window may be increased for those memory cell(s) that are not selected in response to VT—SEL bias voltage set to VT—SEL—nominal.
FIG. 3 illustrates a flowchart 300 of operations for selectively applying a C-cell bias consistent with various embodiments of the present disclosure. The operations may be performed, for example, by a memory controller, e.g., memory controller 104, including WL control module 114 and BL control module 116. Flowchart 300 depicts exemplary operations configured to selectively establish C-cell bias. In particular, flowchart 300 depicts exemplary operations configured to initiate selecting a target cell without C-cell bias and to establish C-cell bias if the target cell is not selected, as described herein.
Operations of flowchart 300 may begin start at operation 302. Selection of a target cell (T) may be initiated at operation 304. Whether the target cell has been selected may be determined at operation 306. If the target cell has not been selected, C-cell bias may be established at operation 308. The target cell may then become selected at operation 310. Program flow may then proceed to operation 312. If the target cell has been selected, a memory access operation may be performed at operation 312. For example, the memory access operation may include a read and/or a write (i.e., programming) operation. Program flow may then end at operation 314.
Thus, the operations of flowchart 300 are configured to attempt to select a target cell without C-cell bias and to establish C-cell bias if the attempt to select the target cell is not successful. C-cell bias may thus be established “on demand”.
While FIG. 3 illustrates various operations according one embodiment, it is to be understood that not all of the operations depicted in FIG. 3 are necessary for other embodiments. Indeed, it is fully contemplated herein that in other embodiments of the present disclosure, the operations depicted in FIG. 3 and/or other operations described herein may be combined in a manner not specifically shown in any of the drawings, but still fully consistent with the present disclosure. Thus, claims directed to features and/or operations that are not exactly shown in one drawing are deemed within the scope and content of the present disclosure.
As used in any embodiment herein, the term “module” may refer to an app, software, firmware and/or circuitry configured to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on non-transitory computer readable storage medium. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices.
“Circuitry”, as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smart phones, etc.
In some embodiments, a hardware description language may be used to specify circuit and/or logic implementation(s) for the various modules and/or circuitry described herein. For example, in one embodiment the hardware description language may comply or be compatible with a very high speed integrated circuits (VHSIC) hardware description language (VHDL) that may enable semiconductor fabrication of one or more circuits and/or modules described herein. The VHDL may comply or be compatible with IEEE Standard 1076-1987, IEEE Standard 1076.2, IEEE1076.1, IEEE Draft 3.0 of VHDL-2006, IEEE Draft 4.0 of VHDL-2008 and/or other versions of the IEEE VHDL standards and/or other hardware description standards.
Thus, a system and method configured to initiate selection of a target cell without C-cell bias and to establish C-cell bias if the target cell is not selected has been described. The system and method are configured to attempt to select the target cell with a nominal bias voltage and to determine whether or not the target cell has been selected. If the target cell has not been selected, the system and method are configured to establish a C-cell bias and to then increase the target cell bias voltage an amount corresponding to the C-cell bias voltage to increase the operation window. Thus, C-cell bias may be implemented to increase the operation window when needed.
According to one aspect there is provided an apparatus. The apparatus includes a memory controller that includes a word line (WL) control module and a bit line (BL) control module. The memory controller is configured to initiate selection of a target memory cell. The apparatus further includes a sense module configured to determine whether the target memory cell has been selected and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.
According to another aspect there is provided a method. The method includes initiating, by a memory controller, selection of a target memory cell, determining, by a sense module, whether the target memory cell has been selected and establishing, by a C-cell bias module, a C-cell bias if the target cell is not selected.
According to another aspect there is provided a system. The system includes a processor, a cross-point memory array that includes a target memory cell, a target word line (WL) and a target bit line (BL). The target memory cell is coupled between the target word line and the target bit line. The system further includes a memory controller configured to initiate selection of the target memory cell. The memory controller includes a WL control module and a BL control module, a sense module configured to determine whether the target memory cell has been selected and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.
Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

## Claims

1. An apparatus comprising:
a memory controller comprising a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell at least in part by coupling the target memory cell to a target memory cell select bias voltage, VT—SEL;
a sense module configured to determine whether the target memory cell has been selected by the coupling of the target memory cell to VT—SEL; and
a C-cell bias module configured to establish a C-cell bias when the sense module determines that the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

2. The apparatus of claim 1, wherein the C-cell bias module is configured to adjust at least one of a WL deselect bias voltage and a BL deselect bias voltage to establish the C-cell bias.

3. The apparatus of claim 1, wherein the memory controller is configured to increase VT—SEL when the sense module determines that the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

4. The apparatus of claim 1, wherein the WL control module is configured to apply a WL select bias voltage, VSELWL, to a target WL and the BL control module is configured to apply a BL select bias voltage, VSELBL, to a target BL to initiate selection of the target memory cell, wherein VT—SEL corresponds to a difference between VSELBL and VSELWL.

5. The apparatus of claim 4, wherein the WL control module is configured to adjust VSELWL to increase VT—SEL by an amount related to the C-cell bias when the target cell is not selected by the coupling of the target memory cell to VT—SEL.

6. The apparatus of claim 4, wherein the BL control module is configured to adjust VSELBL to increase VT—SEL by an amount related to the C-cell bias when the target cell is not selected by the coupling of the target memory cell to VT—SEL.

7. A method comprising:
initiating, by a memory controller, selection of a target memory cell at least in part by coupling the target memory cell to a target memory cell select bias voltage, VT—SEL;
determining, by a sense module, whether the target memory cell has been selected by the coupling of the target memory cell to VT—SEL; and
establishing, by a C-cell bias module, a C-cell bias when the sense module determines that the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

8. The method of claim 7, further comprising:
adjusting, by the C-cell bias module, at least one of a WL deselect bias voltage and a BL deselect bias voltage to establish the C-cell bias.

9. The method of claim 7, further comprising:
increasing, by the memory controller, VT—SEL by an amount related to the C-cell bias when the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

10. The method of claim 7, wherein initiating selection of the target memory cell comprises:
applying, by a WL control module, a WL select bias voltage, VSELWL, to a target WL, and
applying, by a BL control module, a BL select bias voltage, VSELBL, to a target BL,
wherein a difference between VSELBL and VSELWL corresponds to VT—SEL.

11. The method of claim 10, further comprising:
adjusting, by the WL control module, VSELWL to increase VT—SEL by an amount related to the C-cell bias when the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

12. The method of claim 10, further comprising:
adjusting, by the BL control module, VSELBL to increase VT—SEL by an amount related to the C-cell bias when the target cell is not selected by the coupling of the target memory cell to VT—SEL.

13. The method of claim 7, further comprising:
performing, by the memory controller, at least one of a read operation and a write operation on the target memory cell.

14. A system comprising:
a processor;
a cross-point memory array comprising a target memory cell, a target word line (WL) and a target bit line (BL), the target memory cell coupled between the target word line and the target bit line; and
a memory controller configured to initiate selection of the target memory cell, the memory controller comprising:
a WL control module and a BL control module, a sense module configured to determine whether the target memory cell has been selected by the coupling of the target memory cell to a target memory cell select bias voltage VT—SEL, and
a C-cell bias module configured to establish a C-cell bias when the sense module determine that the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

15. The system of claim 14, wherein the C-cell bias module is configured to adjust at least one of a WL deselect bias voltage and a BL deselect bias voltage to establish the C-cell bias.

16. The system of claim 14, wherein the memory controller is configured to increase VT—SEL by an amount related to the C-cell bias when the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

17. The system of claim 14, wherein the WL control module is configured to apply a WL select bias voltage, VSELWL, to a target WL and the BL control module is configured to apply a BL select bias voltage, VSELBL, to a target BL to initiate selection of the target memory cell, wherein a difference between VSELWL and VSELBL corresponds to VT—SEL.

18. The system of claim 17, wherein the WL control module is configured to adjust VSELWL to increase the VT—SEL by an amount related to the C-cell bias when the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.

19. The system of claim 17, wherein the BL control module is configured to adjust VSELBL to increase VT—SEL when the target memory cell is not selected by the coupling of the target memory cell to VT—SEL.