Capacitive Discharge Circuit for Surge 

Current Evaluation of SiC

by Mark R. Morgenstern

ARL-TN-0376 November 2009

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Army Research Laboratory

Adelphi, MD 20783-1197

ARL-TN-0376 November 2009

Capacitive Discharge Circuit for Surge 

Current Evaluation of SiC

Mark R. Morgenstern

Sensors and Electron Devices Directorate, ARL

Approved for public release; distribution unlimited. 
ii

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1. REPORT DATE (DD-MM-YYYY)

November 2009

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Summary

3. DATES COVERED (From - To)

Q1 2009

4. TITLE AND SUBTITLE

Capacitive Discharge Circuit for Surge Current Evaluation of SiC

5a. CONTRACT NUMBER

5b. GRANT NUMBER

5c. PROGRAM ELEMENT NUMBER

6. AUTHOR(S)

Mark R. Morgenstern

5d. PROJECT NUMBER

5e. TASK NUMBER

5f. WORK UNIT NUMBER

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)

U.S. Army Research Laboratory

ATTN: RDRL-SED-P

2800 Powder Mill Road

Adelphi, MD 20783-1197

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 REPORT NUMBER

ARL-TN-0376

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13. SUPPLEMENTARY NOTES

14. ABSTRACT

The power components branch has constructed an apparatus used for surge current testing of prototype semiconductor switch 

devices. The test apparatus is small-scale. It provides a 1 J pulse at a 5-25μS pulse width. Shoot-through is a concern in many 

of the power conversion applications and the pulse provided by this apparatus can provide a very useful model of what device 

behavior to expect when shoot-through currents occur. Other device characteristics that can also be measured with this 

apparatus are: maximum current rise rate, forward transconductance, high voltage blocking, required gate charge, and safe 

operating area.

15. SUBJECT TERMS

Surge, current, evaluation, silicon carbide, switches

16. SECURITY CLASSIFICATION OF: 

17. LIMITATION

 OF 

 ABSTRACT

UU

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 OF 

 PAGES

10

19a. NAME OF RESPONSIBLE PERSON

Mark R. Morgenstern

a. REPORT

Unclassified

b. ABSTRACT

Unclassified

c. THIS PAGE

Unclassified

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(301) 394-5532

Standard Form 298 (Rev. 8/98)

Prescribed by ANSI Std. Z39.18
iii

List of Figures

Figure 1. Schematic of the capacitive discharge circuit. See figure 6 for circuit of V2..................1

Figure 2. Sample test subjects – 4 HSiC MOSFETS provided by Cree Inc. 20 A MOSFET on 

left, 5 A MOSFET on right........................................................................................................2

Figure 3. Peak surge current of 5 A 4 HSiC MOSFET shown in figure 2. .....................................2

Figure 4. Parallel discharge capacitors on bottom of test board. .....................................................2

Figure 5. Parallel load resistors on top of test board. Test subject is clipped to test board on 

lower left. ...................................................................................................................................2

Figure 6. Gate drive circuit used in ring down circuit of figure 1. ..................................................3
iv

INTENTIONALLY LEFT BLANK.
1

In recent years there has been widespread interest in developing SiC semiconductor technology 

for power electronics applications. This interest is due to wide band gap and other superior 

characteristics such as high temperature operation and the ability to handle large current 

densities. The purpose of the apparatus described in this report is to measure the response of SiC 

semiconductor devices to current surges in the on state and high blocking voltages in the off 

state. These measurements allow us to evaluate certain device characteristics critical to 

understanding how a prototype SiC semiconductor switch will operate in real power electronics 

applications. One example of this might be using a surge current pulse to represent an expected 

“shoot-through” current in a half bridge inverter. There are other device characteristics that can 

be evaluated using the circuit in figure 1 and by varying the time, current and voltage parameters 

of the figure 3 waveform, as well as gate bias. These indicate maximum current rise rate, forward 

transconductance, high voltage blocking, required gate charge, and safe operating area.

In the circuit of figure 1, the capacitor (C1) trickle charges through Rc and D1. During discharge,

Rc and D1 prevent oscillations from occurring between C1 and line inductance between Vdc and 

Rc. Rl provides a reasonably low resistance, while L1 (intrinsic in the connections ~100 nH) 

spreads the discharge to occur in the 5–25 μS time range.

L_line

50uH

1 2

Rc

100k

C1

2uF

D1

0

Rg

1

L1

100nH

1 2

Rl

.25

0

Signal ground floats with

respect to zero source

ground in rest of circuit

S

G D

0

V1

0-1000Vdc

V2

+

-

+

-

Ev aluated Switch

Figure 1. Schematic of the capacitive discharge circuit. See figure 6 for circuit of V2.

During the process of trouble shooting and refining this apparatus, 5 A 4 HSiC SiC MOSFETS 

provided by Cree (figure 2 – right), were evaluated at a surge current of 180A (36 times the 

continuous current rating of the parts as seen in figure 3) at a gate bias of 30V. However, at a 

gate bias of 15 V, a maximum surge current of only 70 A was achieved. Fast switching at high 

currents requires aggressive gate drive (figure 6). The capacitive discharge circuit (figures 1, 4, 

and 5) will be used to evaluate 20 A parts (figure 2 – left) similar to the parts mentioned above,
2

as well as evaluate and compare different types of SiC switches for best suitability in high power 

conversion applications. 

0

20

40

60

80

100

120

140

160

180

200

0 5 10 15 20 25 30 35 40 45

Time (μS)

Ipk (A)

0

20

40

60

80

100

120

140

160

180

200

0 5 10 15 20 25 30 35 40 45

Time (μS)

Ipk (A)

Figure 5: Ipk of 5A DMOSFET with gate bias of 30 V

0

20

40

60

80

100

120

140

160

180

200

0 5 10 15 20 25 30 35 40 45

Time (μS)

Ipk (A)

0

20

40

60

80

100

120

140

160

180

200

0 5 10 15 20 25 30 35 40 45

Time (μS)

Ipk (A)

Figure 5: Ipk of 5A DMOSFET with gate bias of 30 V

Figure 2. Sample test subjects – 4 HSiC MOSFETS 

provided by Cree Inc. 20A MOSFET on 

left, 5A MOSFET on right.

Figure 3. Peak surge current of 5A 4 HSiC 

MOSFET shown in figure 2.

Figure 4. Parallel discharge capacitors on bottom of 

test board. 

Figure 5. Parallel load resistors on top of test board. 

Test subject is clipped to test board on 

lower left.

Note: As can be seen in figures 4 and 5, the test board is arranged so that inductance is minimal and the current 

rise times from each capacitor are as close to overlapping as practical.
3

U1

HFBR2521

RL

VCC

GND

VO

U2

HCNW3120

NC1

AN

CAT

NC2

VCC

VO

NC3

VEE

U3

IRF9540

G

D

S

U4

IRF540

G

D

S

r1

300

+5V

C1

1uF

V+

VC2

10uF

C3

10uF

Optical Input

D1

C4

.01uF

0

D3

D2

TO DUT.

Figure 6. Gate drive circuit used in ring down circuit of figure 1. 

Note: This circuit is V2 of figure 1. U1 provides the optical isolation necessary to float the entire gate drive while 

U2 provides level shifting needed for variable positive and negative gate rails, and U3 and U4 provide the fast 

current rise times necessary for surge current testing. Series gate resistor is external and is not shown in figure 6.

The capacitive discharge circuit, although it is very simple, can provide valuable information 

about the likely behavior of SiC MOSFET switches in power electronics applications. That 

information gives demonstrations of power electronics applications where SiC MOSFET 

switches are used (or any MOSFET switch with limited published data) a higher likelihood of 

success.
4

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ADELPHI, MD 20783-1197

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