# Patent

## Title
System and apparatus for clock retiming with catch-up mode and associated methods

## Abstract

An apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal.

## Background
TECHNICAL FIELD
The disclosure relates generally to clock signal conditioning and, more particularly, to system and apparatus for clock retiming with catch-up mode in some embodiment, and associated methods.
BACKGROUND
Combining digital logic and radio-frequency (RF) circuits on the same integrated circuit (IC), or even printed circuit board (PCB), introduces the likelihood of the digital logic interfering with radio operations. More specifically, the energy of the interference at certain frequencies, such as harmonics of the digital clock frequency, can appear to an RF receiver as an in-band signal that may interfere with actual incoming (or even transmitted) radio signals at or near those frequencies. Several conventional techniques exist for combating the interference, are known to persons of ordinary skill in the art, and are therefore briefly described below.
FIGS. 1A-1B show, respectively, a conventional digital synchronizer used to modulate digital clock edges, and associated timing signals. As seen in FIG. 1B, although the average frequency of the resulting FRETIMED clock is not altered, edges of that clock are moved to align with edges of FLO. Doing so changes the harmonics of the resulting digital clock to generate less interference in an RF band based on FLO. The retimed output can exhibit shorter times between adjacent edges than the original clock. The minimum retimed edge-to-edge delay for the example above is given by:




  
    T
    
      MIN
      
        RETIMED
        
          E
          ⁢
          
            
          
          ⁢
          2
          ⁢
          E
        
      
    
  
  =
  
    
      INT
      ⁡
      
        (
        
          
            T
            
              MIN
              
                CLK
                
                  E
                  ⁢
                  
                    
                  
                  ⁢
                  2
                  ⁢
                  E
                
              
            
          
          ·
          
            F
            LO
          
        
        )
      
    
    
      F
      LO
    
  




where TMIN_CLK—E2E is the minimum edge-to-edge time for the clock frequency, FCLK, and FLO represents a local oscillator frequency of an RF receiver. Because of the integer function, INT( ), which truncates its parameter to an integer smaller than or equal to the parameter, the minimum retimed edge-to-edge time is generally less than the original edge-to-edge time. If the duty-cycle of the original clock is not close to 50%, and the FLO is not very much larger than FCLK, the retimed edge-to-edge time can be significantly shorter than TMIN_CLK—E2E. This may result digital logic running from the retimed clock and having critical signal paths between registers clocking on opposite clock edges to be capable of running at a much faster speed than if running from the original clock, FCLK. The digital logic's increased frequency may increase both power and area (on an IC) of the digital logic.

SUMMARY
According to an exemplary embodiment, an apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal.
According to another exemplary embodiment, an apparatus includes a first circuit that operates in response to a first signal, and a second circuit that operates selectably in response to a second signal or a retimed version of the second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes the second signal to generate the retimed version of the second signal, and manages transition of operation of the second circuit in response to the second signal or the retimed version of the second signal without generating glitches and missing or extra cycles in the retimed version of the second signal.
According to another exemplary embodiment, an apparatus includes a circuit that operates selectably in response to a signal or a retimed version of the signal. The apparatus further includes a signal retiming circuit that manages transition of operation of the circuit in response to the retimed version of the signal to operation of the circuit in response to the signal by using a catch-up mode.



BRIEF DESCRIPTION OF THE DRAWINGS
The appended drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope of the application or the claims. Persons of ordinary skill in the art appreciate that the disclosed concepts lend themselves to other equally effective embodiments. In the drawings, the same numeral designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks.
FIGS. 1A-1B illustrate, respectively, a conventional synchronizer and its associated timing diagram.
FIG. 2 depicts a system according to an exemplary embodiment.
FIG. 3 shows an exemplary embodiment that includes RF circuitry and digital circuitry.
FIG. 4 depicts a signal retiming circuit according to an exemplary embodiment.
FIG. 5 illustrates a timing diagram for the exemplary embodiment in FIG. 4.
FIG. 6 depicts a signal retiming circuit according to another exemplary embodiment.
FIG. 7 illustrates a timing diagram for entry into retimed mode for an exemplary embodiment.
FIG. 8 shows a timing diagram for exiting retimed mode for an exemplary embodiment.



DETAILED DESCRIPTION
The disclosed concepts relate generally to reference or source signal (e.g., clock signal) conditioning, for example, in apparatus or systems that combine RF circuitry (e.g., receiver, transmitter, transceiver) with digital logic circuitry (e.g., processors, microcontroller units (MCUs), and the like). More specifically, the disclosed concepts provide system, apparatus, and methods for clock signal retiming and, in some exemplary embodiments, providing a catch-up mode.
For example, when used in conjunction with RF circuitry, the disclosure describes techniques for reducing interference (e.g., radio interference) generated by a digital clock by retiming edges of the digital clock to fall on cycle boundaries of a local oscillator (LO) used by the RF circuitry. Furthermore, exemplary embodiments provide mechanisms for management of transitions between a raw clock and a retimed version of that clock while maintaining a specified minimum edge-to-edge time and period for the resulting output clock, as well as a catch-up mode, as desired.
As noted above, exemplary embodiments provide a mechanism and related techniques for retiming clock signals in order to reduce or eliminate interference between a digital circuit, such as a circuit having a clock signal, and another circuit, for example a signal processing circuit, that is susceptible to interference, for example, an RF circuit. Interference reduction is accomplished by retiming a signal (e.g., a clock signal) in the digital circuit with a signal in the other circuit (e.g., an LO signal).
FIG. 2 illustrates a system 100 according to an exemplary embodiment. System 100 includes a circuit partition 103 and a circuit partition 109. A link 127 couples circuit partition 103 to circuit partition 109. Link 127 may include a coupling mechanism, such as a bus, a desired number of conductors (e.g., traces in an IC or in or on a PCB), etc. Circuit partitions 103 and 109 may communicate one or more signals via link 127.
Circuit partition 103 includes digital circuit 106. Digital circuit 106 includes digital signal source 115. Without loss of generality, this disclosure may refer to digital signal source 115 as a source of a clock signal, FCLK. As persons of ordinary skill in the art understand, however, digital signal source 115 may constitute other types of circuitry or generate signals known by other names.
Circuit partition 109 includes signal processing circuit 112. Signal processing circuit 112 includes a signal source 121 coupled to other circuitry or processing circuitry 124, for example, circuitry that performs analog or digital or mixed-signal signal processing on one or more signals (not shown). Signal source 121 provides a signal to processing circuitry 124. Processing circuitry 124 uses the signal received from signal source 121 perform the signal processing on the one or more signals (not shown).
Digital circuit 106 includes signal retiming circuit 118. Signal retiming circuit 118 retimes the digital signal provided by digital signal source 115 with the signal provided by signal source 121 (e.g., by communicating the signal provided by signal source 121 to digital signal retiming circuit 118 via link 127). As a result of the retiming of digital signal provided by digital signal source 115, interference between circuit partitions 103 and 109 is reduced or eliminated. The retimed digital signal may be used by digital circuit 106 to perform operations, for example, use the retimed digital signal as a clock signal to perform digital logic operations.
For example, in exemplary embodiments, circuitry in circuit partition 109 (e.g., signal processing circuit 112) may operate on one or more analog or mixed-signal signals. By their nature, such signals (and the circuitry that processes them) may be susceptible to interference, such as interference generated by digital signal source 115. The retiming operation (and the use of the retimed signal, as noted above), reduces or eliminates the interference.
In exemplary embodiments, signal retiming circuit 118 retimes the edges of the output signal of digital signal source 115 to fall on cycle boundaries of the output signal of signal source 121. In other exemplary embodiments, signal retiming circuit 118 provides for management of transitions between the output signal of digital signal source 115 and a retimed version of that output signal while maintaining a specified minimum edge-to-edge time and period for the resulting retimed signal. In yet other exemplary embodiments, management of the transitions (entry and exit from retimed or retiming mode) includes performing the retiming operation such that: (a) entry into and exit from the retimed mode is accomplished without generating output glitches, missing clock cycles or extra clock cycles; and (b) exit from the retimed mode includes a catch-up mode, as described below in detail.
In some embodiments, circuit partition 109 may include RF circuitry. As noted above, the RF circuitry might constitute receiver, transmitter, or transceiver circuitry. FIG. 3 shows an exemplary embodiment in which circuit partition 109 includes RF circuitry.
In exemplary embodiments, such as the embodiment shown in FIG. 3, RF circuitry 124 uses antenna 130 to communicate wirelessly with a receiver, transmitter, or transceiver. RF circuitry 124 may include receive functionality, transmit functionality, or both (i.e., transceiver functionality).
More specifically, RF circuitry 124 may include one or more of mixers, down-converters, up-converters, low-noise amplifiers, power amplifiers, etc. One or more of the circuits in RF circuitry 124 use the output signal FLO of LO 121 to perform their functions. For example, a mixer or down-converter may use signal FLO.
Similar to FIG. 2, circuit partition 103 in FIG. 3 includes digital circuit 106. Digital circuit 106 includes digital signal source 115, such as a source of a clock signal, FCLK. Without loss of generality, digital circuit 106 may include in exemplary embodiments one or more processors, microprocessors, MCUs, digital signal processors (DSPs), baseband processor circuitry (e.g., to operate in conjunction with RF circuitry 124) and the like.
In some embodiments, digital circuit 106 includes an MCU (not shown in FIG. 3). The MCU couples to RF circuitry 124 via link 127. The MCU may facilitate operation of RF circuitry 124, act as a host to RF circuitry 124, or perform operations on output signals of RF circuitry 124, etc., as desired. For example, digital circuit 106 may include circuitry for performing baseband operations such as frame synchronization, encryption or decryption, data interleaving and de-interleaving, bit stuff and de-stuffing, packet assembly and disassembly, error detection and correction, and transmission and reception scheduling.
As noted, circuit partition 109 includes signal processing circuit 112, including RF circuitry 124. In addition, circuit partition 109 may include circuitry that performs analog or digital or mixed-signal signal processing on one or more signals (not shown). Digital circuit 106 includes signal retiming circuit 118. Signal retiming circuit 118 retimes the clock signal FCLK provided by digital signal source 115 with the signal (FLO) provided by LO 121 (e.g., by communicating the signal provided by signal source 121 to digital signal retiming circuit 118 via link 127).
As a result of the retiming of the digital signal provided by digital signal source 115, interference between circuit partitions 103 and 109 is reduced or eliminated. The retimed digital signal may be used by digital circuit 106 to perform operations, for example, by using the retimed digital signal as a clock signal to perform digital logic operations.
For example, in exemplary embodiments, circuitry in circuit partition 109 (e.g., signal processing circuit 112 and/or RF circuitry 124) may operate on one or more analog or mixed-signal signals. By their nature, such signals (and the circuitry that processes them) may be susceptible to interference, such as interference generated by digital signal source 115. The retiming operation (and the use of the retimed signal, as noted above), reduces or eliminates the interference.
In exemplary embodiments, signal retiming circuit 118 retimes the edges of the output signal of digital signal source 115 to fall on cycle boundaries of the output signal of signal source 121. In other exemplary embodiments, signal retiming circuit 118 provides for management of transitions between the output signal of digital signal source 115 and a retimed version of that output signal while maintaining a specified minimum edge-to-edge time and period for the resulting retimed signal. In yet other exemplary embodiments, management of the transitions (entry and exit from retimed or retiming mode) includes performing the retiming operation such that: (a) entry into and exit from the retimed mode is accomplished without generating output glitches, missing clock cycles or extra clock cycles; and (b) exit from the retimed mode includes a catch-up mode, as described below in detail.
Note that reference to circuit partitions (e.g., circuit partitions 103 and 109) does not necessarily denote physical partitioning of circuitry. In some exemplary embodiments, circuit partitions 103 and 109 may be included or fabricated within an IC. The circuitry may be on the same die, and may or may not have physical portioning (e.g., fabricated in different parts of the die, or may be partitioned from a signal flow perspective, or both).
In other exemplary embodiments, circuit partitions 103 and 109 may be included or fabricated within an IC, but on separate die, for example, in a multi-chip module (MCM) arrangement. In this situation, the circuit partitions are more physically separated than if fabricated on the same die. The circuit partitions may or may not be partitioned from a signal-flow perspective, as desired.
In other exemplary embodiments, circuit partitions 103 and 109 may be fabricated on a PCB, for example, two ICs on a PCB. In this case, the circuit partitions are separated or partitioned physically by virtue of residing in two physical packages. The circuit partitions may or may not be partitioned from a signal-flow perspective, as desired.
One aspect of the disclosure relates to providing a retimed signal that has desired or prescribed timing characteristics. FIG. 4 depicts an exemplary embodiment that provides such functionality.
A block diagram of a signal retiming circuit 118 according to an exemplary embodiment is illustrated in FIG. 4. Signal retiming circuit 118 can provide a desired minimum amount of time in the edge-to-edge transitions and a minimum period for the retimed signal, e.g., the output signal (FOUT) of signal retiming circuit 118 (see FIGS. 2 and 3).
Referring to FIG. 4, signal retiming circuit 118 includes a limit counter 137 that runs from or is clocked by the FLO signal. Limit counter 137 includes control circuitry and a counter having a desired number of bits, for instance three bits in the example shown in FIG. 4. If enabled via enable signal EN, limit counter 137 measures the number of FLO periods during which the FRETIMED clock is either high or low, and associated logic circuitry prevents a change in the FRETIMED output until the FRETIMED signal has been high or low for at least a given number of FLO periods.
The number of FLO periods for which the FRETIMED signal has been high or low is prescribed by a LIMIT input to limit counter 137. In the example shown in FIG. 4, the LIMIT signal is a 3-bit word, having bits 0 through 2.
Use of limit counter 137 provides a retimed signal that has both a minimum edge-to-edge time and a minimum period in the retimed output. As long as the minimum edge-to-edge time is less than one-half the period of FCLK, the retiming circuit continues to provide a retimed signal with the characteristics described above.
Flip-flops 140 and 149 provide a synchronizer function. A hold multiplexer (“MUX”) 143 is added between flip-flops 140 and 149 to hold or freeze the retimed output until limit counter 137 detects that the time between edges of the retimed output has reached the value LIMIT. Limit counter 137 signals this event to hold MUX 143 via select signal 150.
The circuit in FIG. 4 also allows selecting as the output signal, FOUT, either the original clock signal, FCLK, or the retimed clock signal, FRETIMED. Specifically, using select signal 153, limit counter 137 may control MUX 146 to provide either the FCLK signal (exit or cease the retiming or retimed mode) or the FRETIMED signal (enter or use the retiming or retimed mode). Depending on the nature of the circuits operating from the FOUT signal, transitions between FRETIMED and FCLK may or may not be allowed to generate glitches or extra clock cycles. If glitches are allowed, the control to MUX 146 can change at any time with respect to the phase of the inputs of MUX 146. If glitches are not allowed, limit counter 137 can, for example, change the state of the control to MUX 146 only with the other inputs to MUX 146 are both at logic low or both at logic high.
Although the embodiment in FIG. 4 shows one flip-flop 140 before hold MUX 143, two or more flip-flops in cascade may be used to reduce the likelihood of a metastability fault in the circuit. In addition, hold MUX 143 before flip-flop 149 can be replaced with other circuits to allow the output state of flip-flop 149 to be held, for example by using a clock-gating circuit.
FIG. 5 illustrates a timing diagram for the circuit in FIG. 4. Note that, in addition to clock signal FCLK, LO signal FLO, and the FRETIMED signal for the circuit of FIG. 4, for comparison purposes FIG. 5 also includes the FRETIMED signal (labeled “FRETIMED (prior art”) of the conventional circuit shown in FIG. 1.
Referring to FIG. 5, note that in the example shown, the duty-cycle of FCLK is well below 50%. Due to the relatively low duty-cycle, the conventional retiming method discussed above in connection with FIG. 1 generates some edge-to-edge times as low as one FLO period, such as the time period labeled “T1” in FIG. 5.
As noted above, however, the circuit shown in FIG. 4 measures the width of the retimed high and low times (using the signal labeled “Count,” which represents the state of the counter in limit counter 137), which eliminates the relatively short edge-to-edge times in the retimed signal, FRETIMED. In the example shown in FIG. 5, the edge-to-edge times have a minimum of two FLO periods, by adding the time periods indicated by “T2” and “T3” in the figure.
Note that although the exemplary embodiment in FIG. 4 incorporates a single “LIMIT[2:0]” value, other embodiments may support, for example, one limit value used during low outputs, and a second limit value used during high outputs. Such a scheme allows the minimum high and low durations to be configured to different values. In addition, exemplary embodiments may include multiple counters and limits, including a limit to set the minimum period generated at the output, as desired.
Another aspect of the disclosure relates to entering and exiting retimed mode without generating output glitches, missing clock cycles or extra clock cycles. In some applications, such as when an integrated RF circuitry is frequently enabled and disabled, it may be desirable to operate some logic circuitry from FCLK when the RF circuitry is disabled, and operate the logic circuitry from FRETIMED when enabled. One advantage of operating logic circuitry from FCLK relates to power savings. Often the FLO clock used during retiming is generated by a high-frequency oscillator or clock generator, which requires relatively high amounts of power to operate. When FLO is not used by the retiming circuit (for example when the original FCLK is used), power can be reduced by disabling the source of FLO.
In some applications, it may also be desirable that entering and exiting retimed mode not affect the average frequency of the generated digital clock. For example, it is generally undesirable for the number of digital clock cycles received during a long period of time to depend on how many times the RF circuitry is enabled or disabled. Such dependency would cause errors in digital timers, baud-rate generators, etc.
Exemplary embodiments allow for “clean” transitions into and out of retimed mode, i.e., without generating glitches, missing clock cycles or extra clock cycles, relative to the raw input clock, for example, FCLK. Because of the delay generated by the synchronizing flip-flops 140 and 149 (see FIG. 4), the retimed clock signal, FRETIMED, lags in time the input clock signal, FCLK.
Depending on the duty-cycle of the FCLK signal, the ratio of the frequencies of FCLK and FLO, and the number of synchronizing flip-flops used, the time lag can be large enough to cause the logic high duration of the FRETIMED and FCLK signals to sometimes not overlap. For an example, see FIG. 5, where the first retimed output stretched by the limit counter happens to rise after the falling edge of its associated FCLK cycle.
Because the frequency or duty-cycle of the FCLK signal may not be well controlled in some applications, it may be undesirable to assume these input and output clocks overlap, making it potentially hazardous (from a noise or glitch perspective) to simply change the select control of MUX 146 (see FIG. 4). Signal retiming circuits according to exemplary embodiments make a transition at their outputs from the FCLK signal to the FRETIMED signal (entering retimed mode) in a glitch-free manner, without making assumptions about the overlap of the two signals that may or may not be valid.
Exemplary embodiments provide this feature by performing a logic OR operation on a force-to-one blanking signal and an output signal of the MUX in the output path of the retiming circuit, as FIG. 6 shows. More specifically, limit counter 137 provides a signal FORCE1 to OR gate 160. MUX 146 drives another input of OR gate 160.
FIG. 7 illustrates a timing diagram for entry into retimed mode for the exemplary embodiment of FIG. 4.
When the EN signal (provided to limit counter 137) is detected high, digital logic circuitry in limit counter 137 asserts the FORCE1 signal (to logic high or 1, for normal logic) on or shortly after a subsequent rising edge of FCLK, and de-asserts FORCE1 on or shortly after the next rising edge of FRETIMED. The state of FCLK is detected by the digital logic circuitry in limit counter 137 using the flip-flop labeled “U3,” which combined with flip-flop U1 serves as a synchronizer. While FORCE1 is asserted high, the output FOUT is also forced high by OR gate 160. The delay between this subsequent rising edge of FRETMED and de-assertion of FORCE1 should be long enough to allow the rising edge of FRETIMED to propagate to OR gate 160. This allows the FORCE1 signal to de-assert without causing a glitch at the output of OR gate 160 since the FRETIMED signal causes OR gate 160 to continue to output a logic high signal until the following falling edge of FRETIMED.
As a consequence, the control circuitry in limit counter 137 may switch the output MUX (i.e., MUX 146 in FIG. 6) selection while FORCE1 is high (indicated by the time period labeled “T1” in FIG. 7) without generating a glitch at the output. Since the FRETIMED signal lags FCLK, the extended high period at the output (FOUT) serves to correct for this lag without generating a glitch, missing clock cycles, or extra clock cycles.
A number of variations are possible and contemplated in exemplary embodiments. For example, some embodiments may generate a FORCE0 signal (not shown) feeding an AND gate (not shown) at the output rather than an OR gate. In such embodiments, the FORCE0 signal would drive low on or shortly after a falling edge of FCLK and return high on or shortly after a falling edge of FRETIMED, thereby forcing the output low while the MUX selection (i.e., MUX 146) is changed. Similar to above, the delay between this subsequent falling edge of FRETMED and de-assertion of FORCE0 should be long enough to allow the falling edge of FRETIMED to propagate to the AND gate. This allows the FORCE0 signal to de-assert without causing a glitch at the output of the AND gate since the FRETIMED signal causes the AND gate to continue to output a logic low until the following rising edge of FRETIMED. Furthermore, exemplary embodiments may vary the time at which the FORCE1 or FORCE0 signal is asserted and de-asserted (as well as the time the control to MUX 146 is changed) as long as the generated output, FOUT, maintains a continuous logic high or logic low state during the illustrated “T1” period, depending on whether an OR gate or AND gate is used, to allow transition from FCLK to FRETIMED to be made without generating a glitch at the output of the retiming circuitry.
Another aspect of the disclosure relates to exiting retimed mode without generating a glitch, missing clock cycles or extra clock cycles. When exiting retimed mode, the output (FOUT) is switched from the FRETIMED signal to the FCLK signal. Since the FRETIMED signal lags the FCLK signal, using a technique similar to entering retimed mode, e.g., generating an appropriate FORCE1 logic-high pulse, may generate an output clock cycle whose period is shorter than that of the FCLK signal (shorter by roughly the amount of lag between the FCLK and FRETIMED signals), or may cause the resulting output to miss a clock cycle entirely.
Thus, rather than simply using a FORCE1 signal, a “catch-up” mode is provided. In the catch-up mode, the FRETIMED signal is temporarily altered to have a frequency higher than the FCLK signal. Doing so causes the lag between the FCLK and FRETIMED signals to eventually reduce to zero, and even causes FRETIMED to eventually lead FCLK.
More specifically, in exemplary embodiments, to exit retimed mode, limit counter 137 (see FIGS. 4 and 6) employed in retimed mode, i.e. the counter used to limit the minimum retimed clock low and high times, may be used. Thus, limit counter 137 may be used to not only alter the timing characteristics of the retimed signal (as described above), but also to facilitate implementing the catch-up mode.
When exiting retimed mode, however, limit counter 137 is used to generate fixed low and high times (i.e., the periods of time during which the FRETIMED signal has logic low and logic high values, respectively) independent of the edges of the FCLK signal. The fixed low and high times generate a FRETIMED period less than the period of FCLK. As a result, the FRETIMED signal will catch-up to the FCLK signal in phase.
Whether catch-up has occurred is detected by sampling the FCLK signal on edges of the FRETIMED signal (or on edges of the FLO signal that correspond to edges of the FRETIMED signal, given that the FRETIMED signal makes transitions on the edges of the FLO signal). In exemplary embodiments, flip-flops 140 and 163 and signal 166 are used by the control circuitry in limit counter 137 to perform the sampling operation. Flip-flops 140 and 163 serve as a synchronizer to safely sample FCLK on edges of FLO.
Note that FIG. 6 shows merely one example of how the sampling operation may be performed. A variety of alternatives are contemplated in exemplary embodiments. As one example, an alternative to flip-flop 140, such as a register clocked by the FRETIMED signal or a gated version of the FLO signal may be used, as desired.
In exemplary embodiments, detection of whether the FRETIMED signal has “caught up” with the FCLK signal may be performed by the control circuitry in limit counter 137. More specifically, when the control circuitry in limit counter 137 samples the FCLK signal as logic high on a rising edge of the FRETIMED signal, followed by sampling the FCLK signal as logic low on the next rising edge of the FRETIMED signal, it has detected that the FRETIMED signal now leads the FCLK signal. In other words, the FRETIMED signal has caught up with the FCLK signal.
Once catch-up has been detected, a variety of techniques may be used in exemplary embodiments to switch the output MUX 146 so as to provide the FCLK signal rather than the FRETIMED signal as signal FMUX. As merely one example, the FORCE1 signal may be used, similar to the technique employed to enter retimed mode, described above.
FIG. 8 shows a timing diagram for exiting retimed mode for an exemplary embodiment. Sometime after limit counter 137 detects that the EN input signal has a logic low value, the generated FRETIMED signal enters catch-up mode. In the example shown in FIG. 8, during catch-up the FRETIMED signal has fixed generated low and high times of two FLO periods, as indicated in the time period labeled “T1.”
A variety of techniques exist for defining the fixed low and high times are contemplated in exemplary embodiments. For example, in some embodiments, the fixed times can be defined by one or more of the LIMIT values provided to limit counter 137.
As another example, the fixed times may be provided via a value dedicated to catch-up mode.
At the time indicated by “t1” in FIG. 8, the control circuitry in limit counter 137 samples the FCLK signal as logic high on the rising edge of the FRETIMED signal. At the time indicated by “t2” in FIG. 8, the control circuitry in limit counter 137 samples the FCLK signal as logic low on the rising edge of the FRETIMED signal. This sequence indicates that the FRETIMED signal now leads the FCLK signal in phase.
To make a transition of the output signal (FOUT) from the FRETIMED signal to the FCLK signal, the control circuit in limit counter 137 freezes the state of the FRETIMED signal. The control circuit in limit counter 137 also adds a delay of two cycles of the FLO signal, as indicated by the LIMIT input for the example in FIG. 8, at which time the select signal provided to output MUX 146 is changed. As a consequence, the output signal of MUX 146 and, hence, the output signal FOUT, switches from the FRETIMED signal to the FCLK signal.
Because the FRETIMED signal provided to output MUX 146 is at logic high, the selection change does not cause a glitch at the output of MUX 146 (or the output signal, FOUT). More specifically, if the FCLK signal is still at logic high when the select signal to output MUX 146 is changed, the output FMUX will remain at logic high. Conversely, if the FCLK signal is at logic low when the select signal to output MUX 146 is changed, the output FMUX will immediately go to a logic low value.
Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown might depict mainly the conceptual functions and signal flow. The actual circuit implementation might or might not contain separately identifiable hardware for the various functional blocks and might or might not use the particular circuitry shown. For example, one may combine the functionality of various blocks into one circuit block, as desired. Furthermore, one may realize the functionality of a single block in several circuit blocks, as desired. The choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation. Other modifications and alternative embodiments in addition to those described here will be apparent to persons of ordinary skill in the art. Accordingly, this description teaches those skilled in the art the manner of carrying out the disclosed concepts, and is to be construed as illustrative only.
The forms and embodiments shown and described should be taken as illustrative embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts without departing from the scope of the disclosed concepts in this document. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described here. Moreover, persons skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the disclosed concepts.

## Claims

1. An apparatus comprising:
analog or mixed-signal circuitry operating in response to a first signal;
digital circuitry operating in response to a second signal; and
a signal retiming circuit, comprising first and second flip-flops selectably coupled in a cascade configuration, generating the second signal to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of an output signal of a digital signal source to fall on cycle boundaries of the first signal.

2. The apparatus according to claim 1, wherein the signal retiming circuit further comprises a limit counter coupled to the second flip-flop.

3. The apparatus according to claim 1, wherein the analog or mixed-signal circuitry comprises radio-frequency (RF) circuitry.

4. The apparatus according to claim 3, wherein the first signal comprises a local oscillator (LO) signal.

5. The apparatus according to claim 1, wherein the output signal of the digital signal source comprises a clock signal, and wherein the second signal comprises a retimed clock signal.

6. The apparatus according to claim 1, wherein the analog or mixed-signal circuitry resides in a first circuit partition and the digital circuitry resides in a second circuit partition.

7. The apparatus according to claim 6, wherein the first and second partitions are physically partitioned.

8. The apparatus according to claim 6, wherein the first and second partitions reside within an integrated circuit (IC).

9. An apparatus comprising:
a first circuit that operates in response to a first signal;
a second circuit that operates selectably in response to a second signal or a retimed version of the second signal; and
a signal retiming circuit that retimes the second signal to generate the retimed version of the second signal, and manages transition of operation of the second circuit in response to the second signal or the retimed version of the second signal without generating glitches and missing or extra cycles in the retimed version of the second signal, the signal retiming circuit comprising first and second flip-flops selectably coupled in a cascade configuration.

10. The apparatus according to claim 9, wherein the signal retiming circuit further comprises a limit counter coupled to the first and second flip-flops.

11. The apparatus according to claim 9, wherein the analog or mixed-signal circuitry comprises radio-frequency (RF) circuitry, and wherein the first signal comprises a local oscillator (LO) signal.

12. The apparatus according to claim 11, wherein the second circuit comprises a microcontroller unit (MCU).

13. The apparatus according to claim 12, wherein the RF circuitry and the MCU are fabricated within an integrated circuit (IC).

14. The apparatus according to claim 9, wherein the second signal comprises a clock signal, and wherein the retimed version of the second signal comprises a retimed clock signal.

15. An apparatus comprising:
a circuit that operates selectably in response to a signal or a retimed version of the signal; and
a signal retiming circuit that manages transition of operation of the circuit in response to the retimed version of the signal to operation of the circuit in response to the signal by using a catch-up mode, the signal retiming circuit comprising a first flip-flop selectably coupled to a second flip-flop.

16. The apparatus according to claim 15, wherein in the catch-up mode, the retimed version of the signal is altered to reduce a lag between the signal and the retimed version of the signal.

17. The apparatus according to claim 15, wherein the retimed version of the signal is generated with fixed periods of time where the retimed version of the signal has logic low and logic high values.

18. The apparatus according to claim 15, wherein the signal retiming circuit samples the signal at times corresponding to edges of the retimed version of the signal to determine whether catch-up has occurred.

19. The apparatus according to claim 15, wherein the signal retiming circuit manages transition of operation of the circuit in response to the signal or the retimed version of the signal without generating glitches and missing or extra cycles in the retimed version of the signal.

20. The apparatus according to claim 15, wherein the signal retiming circuit further comprises a limit counter coupled to the second flip-flop.