NREL is a national laboratory of the U.S. Department of Energy, Office of Energy 

Efficiency & Renewable Energy, operated by the Alliance for Sustainable Energy, LLC.

Contract No. DE-AC36-08GO28308

Effect of Hysteresis on 

Measurements of Thin-Film Cell 

Performance 

David Albin and Joseph del Cueto

Presented at the Reliability of Photovoltaic Cells, Modules, 

Components, and Systems III: SPIE Conference 

San Diego, California

August 3-5, 2010

Conference Paper

NREL/CP-5200-48996

March 2011
NOTICE

The submitted manuscript has been offered by an employee of the Alliance for Sustainable Energy, LLC 

(Alliance), a contractor of the US Government under Contract No. DE-AC36-08GO28308. Accordingly, the US 

Government and Alliance retain a nonexclusive royalty-free license to publish or reproduce the published form of 

this contribution, or allow others to do so, for US Government purposes.

This report was prepared as an account of work sponsored by an agency of the United States government. 

Neither the United States government nor any agency thereof, nor any of their employees, makes any warranty, 

express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of 

any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately 

owned rights. Reference herein to any specific commercial product, process, or service by trade name, 

trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, 

or favoring by the United States government or any agency thereof. The views and opinions of authors 

expressed herein do not necessarily state or reflect those of the United States government or any agency thereof.

Available electronically at http://www.osti.gov/bridge

Available for a processing fee to U.S. Department of Energy

and its contractors, in paper, from:

U.S. Department of Energy

Office of Scientific and Technical Information

P.O. Box 62

Oak Ridge, TN 37831-0062

phone: 865.576.8401

fax: 865.576.5728

email: mailto:reports@adonis.osti.gov

Available for sale to the public, in paper, from:

U.S. Department of Commerce

National Technical Information Service

5285 Port Royal Road

Springfield, VA 22161

phone: 800.553.6847

fax: 703.605.6900

email: orders@ntis.fedworld.gov

online ordering: http://www.ntis.gov/help/ordermethods.aspx

Cover Photos: (left to right) PIX 16416, PIX 17423, PIX 16560, PIX 17613, PIX 17436, PIX 17721

Printed on paper containing at least 50% wastepaper, including 10% post consumer waste.
*

david_albin@nrel.gov; phone 1 303 384-6550; fax 1 303 384-7600; www.nrel.gov

1 

Effect of Hysteresis on Measurements of Thin-Film Cell Performance

David Albin* and Joseph del Cueto

National Renewable Energy Laboratory, 1617 Cole Blvd., Denver, CO, USA 80401 

ABSTRACT

Transient or hysteresis effects in polycrystalline thin film CdS/CdTe cells are a function of pre-measurement voltage 

bias and whether Cu is introduced as an intentional dopant during back contact fabrication. When Cu is added, the 

current-density (J) vs. voltage (V) measurements performed in a reverse-to-forward voltage direction will yield higher

open-circuit voltage (Voc), up to 10 mV, and smaller short-circuit current density (Jsc), by up to 2 mA/cm2

, relative to 

scanning voltage in a forward-to-reverse direction. The variation at the maximum power point, Pmax, is however small. 

The resulting variation in FF can be as large as 3%. When Cu is not added, hysteresis in both Voc and Jsc is negligible

however Pmax hysteresis is considerably greater. This behavior corroborates observed changes in depletion width, Wd, 

derived from capacitance (C) vs voltage (V) scans. Measured values of Wd are always smaller in reverse-to-forward 

voltage scans, and conversely, larger in the forward-to-reverse voltage direction. Transient ion drift (TID) 

measurements performed on Cu-containing cells do not show ionic behavior suggesting that capacitance transients are 

more likely due to electronic capture-emission processes. J-V curve simulation using Pspice shows that increased 

transient capacitance during light-soak stress at 100 oC correlates with increased space-charge recombination. Voltagedependent collection however was not observed to increase with stress in these cells.

Keywords: CdTe solar cell, transient capacitance, DLTS, transient ion drift, reliability, degradation, voltage-dependent 

collection

1. INTRODUCTION

Transient and metastable effects in polycrystalline thin film modules significantly affect module performance 

measurements. Storage conditions concerning light-exposure, bias, and temperature can change not only power, but also 

measurements of open-circuit voltage (Voc), short-circuit current-density (Jsc), and fill-factor (FF) [1]. The magnitude of 

these effects is observed to vary as modules undergo accelerated lifetime testing [2]. Uncertainty regarding premeasurement conditions during module shipment and storage and the resulting effect on performance justifies the need 

for stabilization procedures prior to module performance measurements during qualification and field-test studies.

Recent research has concentrated on studying the nature of transients in capacitance-voltage (C-V) measurements 

applied to small-area CdTe devices [3] as well as production-sized CdTe and Cu(In,Ga)Se2 modules [2]. These studies 

involve measuring the capacitance as a function of sequential forward-to-reverse (termed a “rev” direction) and reverseto-forward (termed a “fwd direction) voltage scans with a 5 m hold at reverse-bias. In [3], CdS/CdTe devices were 

fabricated on two, uniquely different transparent conducting oxides (TCOs) in which the durability of the device under 

1-sun, Voc bias, 100 oC stress testing was notably affected by the TCO type. The rate of degradation observed in 

CdS/CdTe devices fabricated on insulating zinc-stannate (ZTO)/cadmium stannate (CTO) TCO/Corning 7059

borosilicate glass substrates was in general, greater relative to identically fabricated CdS/CdTe devices fabricated on 

more traditional, undoped, insulating tin-oxide (iSnO2)/F-doped conductive tin-oxide (cSnO2) TCO/borosilicate glass 

substrates. Depletion width (Wd = [ε⋅A]/C where ε is the dielectric permittivity, A is the cell area) hysteresis (defined as 

the difference in Wd measured at V=0 between fwd and rev voltage scans) was observed to correlate strongly with 

performance during stress testing. The variation in Wd hysteresis with stress time as well as the correlation of this 

capacitance-derived measurement with both Voc and FF measured during stress is shown in Figure 1. The increased 

hysteresis seen in Fig. 1(a) paralleled decreased performance during stress. The reasonably good correlation of 

hysteresis with both Voc and FF (shown in Fig. 1(b) and 1(c) respectively) is also apparent.
2 

The linear correlation coefficient, R2

, of Voc with hysteresis for CTO/ZTO cells #1 and #2, and SnO2 cells #1 and 

#2, were 0.98, 0.46, 0.75, and 0.82, respectively. Similar correlations for FF were 0.99, 0.58, 0.63, and 0.87 

respectively. When analyzed without considering hysteresis, i.e., based on either Wd,fwd or Wd,rev separately, correlations 

were not nearly as high and tended to show non-monotonic behavior.

The origin of this capacitance hysteresis was not substantiated. From an electronic perspective, hysteresis could be

explained by considering majority carrier trap emission within the CdTe space-charge region. Depletion widths 

measured during a rev-voltage scan will initially be higher since the negative space-charge (i.e., Na

-

) region of the CdTe 

is screened by holes occupying deep states in the band gap. At a fixed reverse bias (1.5 V in [3]), some deep states fall 

below the Fermi level and the resulting, time-dependent hole emission (or electron capture) will reduce this screening 

causing Wd to decrease. The subsequent fwd-direction voltage scan (-1.5 V to +0.2 V) captures this reduced value of Wd

such that hysteresis, Wd,rev–Wd,fwd is positive. This filling and emptying of deep states gives rise to capacitance transients 

which are fundamental to deep level transient spectroscopy (DLTS) measurements. Based upon this model, hysteresis is 

proportional to the density of deep states within the CdTe space-charge undergoing capture-emission processes, and an 

increase in hysteresis would represent an increase in electronic traps with stress.

Another mechanism for hysteresis, based upon transient ion drift (TID) was also presented. This seemed plausible 

given the previous reports of TID behavior in both polycrystalline CdTe [4] and CuInSe2 [5] devices which themselves 

were based upon earlier works by Heiser and Mesli [6] and subsequently, Lyubomirsky, et al. [7]. In the TID model for

hysteresis, the higher Wd measured during the rev-voltage scan is due to the screening of the space-charge region, not by 

holes, but rather by positively charged Cu-interstitial donors, Cui

+

. Again, at a fixed reverse bias of 1.5 V, these donors 

are attracted toward the back contact, away from the space-charge, with the same net effect, i.e., a decrease in Wd again 

0.8

0.7

0.6

0.5

0.4

0.3

Wd,rev - Wd,fwd (um)

0 20 40 60 80 100

Stress Time, hrs

 CTO/ZTO #1

 CTO/ZTO #2

SnO2 #1

SnO2 #2

(a)

0.78

0.79

0.8

0.81

0.82

0.83

Voc (volts)

0.2 0.4 0.6 0.8

Wd_rev - Wd_fwd

(b)

60

65

70

FF %

0.2 0.4 0.6 0.8

Wd_rev - Wd_fwd

(c)

Figure 1. Variation of C-V hysteresis with stress 

time (a) for CdS/CdTe devices deposited on either 

CTO/ZTO or SnO2-based TCO/glass substrates 

and subsequent correlations of (b) Voc and (c) FF 

with hysteresis. Hysteresis is defined as the 

difference in Wd measured at V = 0 between rev 

and fwd voltage scans. 
3 

due to reduced screening. However, according to Heiser and Mesli, the transients observed in TID are distinguishable 

from those in TID. Referring to the capacitance change occurring at reverse and positive bias as accumulation (Cui

+

accumulating towards the back contact) and flattening (Cui

+ re-distribution towards the space-charge) processes

respectively, they note that relaxation times at reverse and forward bias levels, τa and τf, should follow the relationship

τf / τa > 1 and be reverse bias dependent, that is, the ratio should increase with increasing reverse-bias. This was argued 

as not the case for DLTS processes where the capture rate is much higher than the emission rate, and generally 

independent of reverse bias. The C-V technique described in [3] unfortunately did not record decay rates at either +0.2 

or -1.5 V. It was stated however, that there was no obvious mechanism by which an increase in mobile ions (as 

explanation for the increased hysteresis shown in Fig. 1) would degrade performance, but rather, the formation of deep 

states and possibly increased recombination that would most likely decrease performance during stress testing.

This paper reports on a modification of the C-V technique used in [3] such that capacitance response is measured 

during the initial reverse-bias pulse (τa) and a subsequent, relaxation bias at V=0 (τf). By repeating this measurement at 

progressively increasing reverse-bias levels, the voltage-dependence of the term τf / τa can be determined. The effect of 

the strong variation in Wd with voltage-scan direction shown in Fig. 1(a) on the J-V characteristics of cells with and 

without Cu as an intentional dopant is also shown. Finally, further insight regarding the mechanism of degradation 

reported in [3] is ascertained using PSpice modeling of device J-V characteristics measured during stress. 

2. EXPERIMENTAL PROCEDURE

Cell Fabrication

The structure and fabrication history of CdS/CdTe cells used in this study is discussed in reference [3]. The basic 

structure is that of a Corning 7059 borosilicate glass superstrate design in which light passes through a glass/TCO/buffer

construction (either 7059/cSnO2/iSnO2 or 7059/CTO/ZTO), where it is then absorbed in the n-(CdS)/p-(CdTe)

heterojunction. A schematic of the different layers comprising the device is shown in Fig. 2.

Figure 2. CdS/CdTe device superstrate structure. The TCO layer is either CTO or nSnO2 while the corresponding 

buffer is either ZTO or iSnO2. 

The CTO/ZTO and SnO2-based TCOs were deposited by sputtering and low-pressure, chemical vapor deposition. 

The cSnO2 and iSnO2 layers were deposited onto bare glass substrates heated to 550 oC using tetramethyltin, 

bromotrifluoromethane (CBrF3), and oxygen. The CBrF3 provides the fluorine dopant for the cSnO2 layer alone. The 

cSnO2 and iSnO2 layers were 500 and 100 nm thick respectively. The resulting sheet resistance of this bi-layer stack 

measures ~ 9 Ω /sq. The CTO and ZTO layers were sputtered onto unheated substrates to a thickness of 320 and 150 nm 

respectively. After each sputter deposition, the amorphous oxide layers were annealed in 30 Torr He for 15 min at 650 

oC with the oxide film in contact with a CdS film/Corning 7059 glass plate (i.e., a “close-proximity” anneal). During the 

subsequent anneal, the optical band gap of the CTO layer increases from about 3.0 eV to 3.5 eV with a several order 
4 

magnitude drop in resistivity to ~1.8 x 10-4 Ω⋅cm. The CTO layer exhibits some crystallization during this postdeposition anneal. The iSnO2 and ZTO buffer layers (after anneal) are insulating with a resistivity of around 1-10 Ω⋅cm 

and contribute little additional absorption loss to the oxide layer stack. The CdS layer is grown by chemical bath 

deposition at ~90 oC to a thickness of approximately 80 nm. The CdTe layer is deposited onto the 

CdS/buffer/TCO/glass substrate in a close-spaced sublimation (CSS) arrangement where the CdTe source and substrate 

temperatures are 660 and 625 oC respectively. An ambient of 15 torr He and 1 torr O2 is used during CSS. After the 

CdTe deposition, the CdTe/CdS/buffer/TCO/glass structure was then exposed to vapor CdCl2 treatments in an 

oxygen/helium ambient (100 Torr O2 + 400 Torr He). Prior to the back contact application, CdTe surfaces were etched 

in a nitric-phosphoric acid solution in order to form a beneficial, Te-rich layer and to remove surface oxides [8]. Back 

contacts concluded with the application of a relatively thick layer (~50–100 μm) of graphite paste containing CuxTe and 

HgTe dopants followed by a similarly thick, final conducting layer of Ag paste. Cells without intentional Cu dopant use 

only the graphite paste. A narrow (~1 mm) margin of CdTe surrounding the perimeter of the dopant/Ag paste contact 

was used to reduce edge shunting.

J-V and C-V Measurements

Performance data using standard current versus voltage (J-V) scans were made on cells after fabrication (t = 0) and 

during stress testing (t > 0) with a current-calibrated Oriel solar simulator. In an attempt to average out J-V transients 

due to pre-bias and voltage scan directions, the voltage applied across the probes is routinely swept continuously from a 

fwd-bias to rev-bias in a saw-tooth fashion while Kelvin probes are lowered onto the front and back contacts of the 

device. With probes attached, and after the next subsequent voltage sweep, current as a function of voltage is collected 

first in the dark from fwd to rev-bias. The simulator shutter is then opened, exposing the cell to a pre-calibrated 1-sun 

irradiance spectrum with the photocurrent measured during the subsequent fwd to rev-scan. In this fashion, transients 

are managed and repeatable measurements of performance are obtained for monitoring relative degradation during stress 

testing. A small indium pad is placed between the back contact and Kelvin probe to minimize potential damage to the 

cell by the sharp probe tips. To ascertain what effect the hysteresis in depletion width shown in Fig. 1(a) has on cell 

performance, this voltage sweeping technique was not used. Rather, cells were first biased at -1.5 V for 5 m in the dark, 

at which point the current was measured as the voltage was swept from -1.5 V to +0.2 V. At +0.2 V, the cell was then 

placed in the dark for an additional 5 m, and the light photocurrent was measured as the voltage was scanned from +0.2

V to -1.5 V.

Capacitance-voltage (C-V) measurements (dark at room temperature) were performed using an Agilent 4294A 

Precision Impedance Analyzer operated at 100 kHz with a 50 mV oscillation voltage. The capacitance is relatively 

insensitive to frequency at 100 kHz. Unlike in [3], a Labview program was used to automate data collection to insure 

repeatability. The same bi-directional voltage scan used in [3] was replicated except that three successive loops in 

voltage between V=0 and increasing reverse biases of -1.0, -2.0, and -3.0 V were performed with capacitance transient 

data collected at the termination of each voltage scan. After some experimentation, a pause time of 20 m was used to 

collect transient data at each terminating voltage. This is twice as long as the collection time used in reference [4] and 

was determined to be adequate for obtaining linear fits of ln [∆C] functions with time for calculating relaxation time 

constants. The relaxation time constants for τa and τf were determined respectively, using the following relationships:





 



−= −∞

−∞

a

t

CC

tCC

τ exp )0()(

)()( (1)





 





−= ∞−

∞−

f

t

CC

CtC

τ exp )()0(

)()( (2)

where C(t), C(0), and C(oo) equal the capacitance as a function of time, as well as the capacitance at the beginning and 

end of each 20 m transient measurement period. The resulting capacitance change with time for a representative Cucontaining cell is shown in Fig. 3.
5 

Figure 3. Capacitance versus time for a three cycle loop with progressively increasing rev-bias voltage. 

The increasing capacitance during the accumulation period, where the cell is subjected to a reverse bias pulse, 

corresponds to a value for Wd which decreases with time (C increases). C(0) and C(oo) in equation (1) correspond to the 

capacitance measured at t = 0 and 1200 s (20 m). The voltage is then swept to V = 0 capturing the hysteresis discussed 

in [3]. The voltage is maintained at this level for an additional 20 m where Wd increases (C decreases). C(0) and C(oo) 

in equation (2) corresponds to the capacitance measured at t=1200+ and 2400 s.

Accelerated lifetime test (ALT) conditions have been described before [3]. In brief, cells were placed, glass-side up, 

under an Atlas CPS+ solar light source (~AM 1.5; 1-sun) in machined Al blocks designed to keep cells at Voc bias. Cell 

temperature was set to 100 oC. At times equal to 1, 4.4, 10, 28, 73, and 115 hrs, cells were removed and allowed to 

stabilize in the dark for 12-24 hrs. After measurements of J-V and C-V, cells were again placed under stress. Sometime 

after the last measurement at t=115 hrs, the temperature controllers failed (over a weekend) resulting in excessive 

heating and destruction of cells. The actual test temperature of 100 oC is suspect (temperatures may have been higher) 

particularly near the conclusion of the test. Regardless, the design of the Al blocks at least assures us that cells were 

tested at the same temperature.

J-V Curve Modeling

PSpice simulations provide a near-quantitative method for determining losses in devices as a function of stress. In 

Fig. 4, a parallel combination of forward-biased diodes is used to independently simulate recombination currents in the 

quasi-neutral (JQNR) and space-charge (JSCR) regions. Back contact behavior is represented by a parallel combination of a 

reverse-biased diode (represented by the leakage current Jb) and a shunt conductance (1/Rb) that was previously used to 

model the J-V characteristics of contacts commonly observed in 1st quadrant J-V behavior [9]. The theoretical basis for 

the two-diode model as a general expression for the current produced in a solar cell can be found in reference [10].

Figure 4. Two-diode solar cell discrete element circuit model.
6 

Losses associated with any of the circuit elements shown in Fig. 4 can be determined by comparing J-V curves 

before and after some change in the cell. For example, Fig. 5 demonstrates a nearly exact fit for a 14.4% cell in which 

the following parameters were determined: Jp = 0.024409 A/cm2

, J01 = 0.5e-16 A/cm2, J02 = 2e

-09 A/cm2

, Rs = 1.9 

ohm*cm2

, Rsh = 200k ohm*cm2, Jb = 6e-02 A/cm2, and Rb = 1.5 ohm*cm2. The “loss” associated with this cell, relative to 

a theoretical, maximum performance cell can be determined by generating the latter J-V curve as shown in Fig. 5 in 

which J01 and J02 are both set to ideal values of 1e-20, Rs 0, Rsh oo, and Jb and Rb are removed from the model. The 

corresponding ideal cell has J-V parameters of Voc ~ 1.095 V, Jsc ~ 24.4 mA/cm2

, FF ~ 89.0, and efficiency of ~23.8% 

suggesting the performance entitlement of this technology if processing induced “losses”, in particular those resulting in 

high recombination currents can be eliminated. This approach has recently been used to explain general degradation 

mechanisms in CdS/CdTe devices as a function of stress [11].

Figure 5. PSpice simulation of a high-efficiency CdS/CdTe device and the potential improvement in J-V behavior if all 

losses are removed (ideal cell). 

A major weakness of PSpice, however, is its inability to adequately determine voltage-dependent collection losses

since Jp in the PSpice model is constant, and not a function of voltage. Thus, superposition is guaranteed. The high 

degree of superposition between the light and dark J-V curves for the ideal cell shown in Fig. 5 was obtained simply by 

setting Jp=0 in the dark J-V simulation. In general, polycrystalline thin film solar cells do not demonstrate this degree of 

superposition [12]. However, as discussed in reference [11], the differences between actual J-V data and the PSpice 

simulations can be used to determine this voltage-dependent photocurrent loss. The value of Jp is set to the current 

measured at the greatest value of reverse-bias. Rs is then determined by dV/dJ in the first quadrant. As long as roll-over 

is not extreme (Jb approaching zero), this value can be determined. Rsh is subsequently determined by using the value of 

dV/dJ at V=0 from the dark J-V curve since there is nothing to suggest a photo-active shunt conductance. The remaining 

parameters JQNR and JSCR are then adjusted to fit Voc. When performed in this manner, the actual J-V photocurrent will 

generally be lower than the simulated value since the latter again assumes a constant value of Jp. The difference between 

these two curves represents the voltage-dependent loss.

3. RESULTS AND DISCUSSION

Pre-bias Effects on Cell Performance

Fig. 6 shows how pre-biasing the cell at either 1.5 V reverse bias and 0.2 V forward bias can affect the J-V 

characteristics of cells with and without intentional Cu added as a dopant to the graphite paste contact described 

previously. The behavior shown in Fig. 6 is representative of the 16 cells (8 each with and without Cu) fabricated for 

this measurement.
7 

Figure 6. Representative variation in cell J-V curve behavior based upon pre-measurement bias and sweep direction for 

CdS/CdTe cells without (a) and with (b) intentional Cu added as a dopant.

Voc and Jsc were strongly impacted by pre-measurement bias and sweep direction only for devices that contained Cu. 

At the same time, the behavior at Pmax (where J-V curves cross) was significantly less. Scanning the cell in a fwd 

direction from an initial reverse bias — where C-V data would suggest a smaller Wd — caused a strong reduction in Jsc

(1-2 mA/cm2

) and increase in Voc (5-10 mV). The net effect on FF is an increase of 1-3% points. This is similar to the 

increase in FF observed in testing CdTe modules when tracing current-voltage from V=0 (Isc) to Voc (see for example 

Fig. 5 in reference [1]). This overall behavior is consistent in devices where voltage-dependent collection limits 

performance. Voc and Jsc transients for cells not containing Cu were negligible, though a slight J-V curve hysteresis near 

Pmax was observed. FF was slightly less in cells not containing Cu when scanning voltage in the fwd direction. It should 

be noted that the distinction between cells “containing” and “not containing” Cu refers only to whether Cu was 

intentionally added during back contact processing. Cu may exist as a trace impurity in cells not intentionally doped 

with Cu, and thus the reason for the very slight hysteresis observed here in J-V measurements and in the C-V data 

presented earlier in [3].

TID measurements

Using the C-V technique described earlier to collect capacitance transient response at V=0 and progressively

increasing values of reverse bias, equations (1) and (2) were employed to determine relaxation time constants in cells 

containing Cu. Capacitance transients in cells without Cu are too small to differentiate from noise in such 

measurements. Shown in Fig. 7 are the ln (∆C) functions plotted as a function of time and the corresponding relaxation 

time constants for accumulation (τa) occurring during the reverse-bias pulse (7(a)) and flattening (τf) at V = 0 (7(b)) for 

each of the three reverse-bias voltage levels studied. The latter values were determined from the inverse slope of the 

curves between t= 200 and 800 s. These measurements were performed for several cells containing Cu. The example 

shown here is representative of the overall behavior and will be used for this discussion. The ratio τf / τa with increasing 

reverse bias is shown to equal 0.85, 0.79, and 0.72 in this case. This behavior does not meet either of the two primary 

criteria for identifying ionic drift as discussed previously. Thus, at this point, it does not appear that the hysteresis 

observed in these cells has an ionic basis though this work is somewhat preliminary. For example, frequency domain 

measurements might be used to selectively freeze out ionic processes.

(a) (b)
8 

Figure 7. Transient capacitance response during the accumulation (a) and flattening (b) processes occurring at reversebias and V=0 conditions respectively.

J-V Curve Modeling

J-V curves corresponding to cells CTO/ZTO #1 and SnO2 #1 from Fig. 1 at t = 0 and t = 115 hrs were fit using the 

PSpice technique described previously. Actual and simulated J-V data for the CTO/ZTO and SnO2 cells are shown in 

Fig. 8(a) and 8(b) respectively. The current density axis has been adjusted to magnify the difference observed between

simulated and actual photocurrents. The difference between actual and fit graphs represent the additional current loss 

not determined by the discrete element model of Fig. 4. In each case, Rsh was determined by the behavior of the dark JV curve at V = 0 (not shown). 

Figure 8. Comparison of actual J-V data and PSpice simulated data for unstressed (t=0) and stressed (t=115 hrs) 

CTO/ZTO-based (a) and SnO2-based (b) cells.

The circuit model fit parameters for the simulated J-V curves are summarized in Table 1. Times are given in hrs, 

current density is expressed in A/cm2

, and resistive terms given in Ω⋅cm2. The primary reason for the greater rate of 

degradation in the CTO/ZTO cells appears to be due to both increased shunting (lower Rsh), and increased space-charge 

recombination. At the same time, voltage-dependent collection does not appear to increase significantly with stress for 

CdTe devices using either substrate type. Increased recombination is likely due to the increased deep state density during 

stress testing. The latter manifests as an increase in the capacitance hysteresis observed during stress. It is interesting to 

note that the increased concentration of deep states does not appear to significantly increase voltage-dependent 

collection.

(a) (b)

(a) (b)
9 

Substrate Stress Time Jp J(o1) J(o2) Rs Rsh Rb Jb

CTO/ZTO 0 0.024502 3.00E-16 8.00E-10 4.3 200K 0.5 1.00E-01

CTO/ZTO 115 0.025289 3.00E-16 5.70E-09 4.6 595 6.7 2.70E-02

iSnO2/SnO2 0 0.02273 2.50E-16 6.00E-10 2.4 200K 1.3 8.50E-02

iSnO2/SnO2 115 0.023104 2.50E-16 2.90E-09 2.6 200K 4.6 4.80E-02

Table 1. PSpice Fit parameters of initial and degraded J-V performance for CdTe devices deposited on both CTO/ZTO 

and iSnO2/SnO2 substrates

4. CONCLUSIONS

The transient behavior observed in C-V measurements obtained on CdTe devices deposited on either SnO2 or 

CTO/ZTO based substrates is likely due to the presence of deep states in the space-charge region. The increase in C-V 

hysteresis with stress testing of these cells is likely due to an increase in deep state density. This increases space-charge 

recombination. Higher levels of hysteresis are correlated with higher levels of degradation in cells. The latter is 

correlated with higher levels of recombination. Increased recombination does not appear to increase voltage-dependent 

collection. TID measurements performed as part of our C-V measurement technique do not support the motion of ions 

for explaining hysteresis. Again, the latter is more reflective of an increase in the density of deep states.

5. ACKNOWLEDGEMENTS 

This work was supported by the U.S. Department of Energy under Contract No. DOE-AC36-08G028308 with 

the National Renewable Energy Laboratory (NREL). The authors thank Dr. Jian Li, and Clay Dehart for modifying the 

Labview code used for the capacitance and J-V measurements respectively.

6. REFERENCES 

[1] del Cueto, J.A and von Roedern, B., “Long-term Transient and Metastable Effects in Cadmium Telluride Photovoltaic Modules,” 

Prog. Photovolt: Res. Appl. 14, 615-628 (2006).

[2] del Cueto, J.A., Deline, C.A., Albin, D.S., Rummel, S.R., and Anderberg, A., “Striving for a standard protocol for 

preconditioning or stabilization of polycrystalline thin film photovoltaic modules,” Proceedings of SPIE Vol. 7412, 741204 

(2009). 

[3] Albin, D.S., Dhere, R.G., Glynn, S.C., del Cueto, J.A., and Metzger, W.K., “Degradation and Capacitance-Voltage Hysteresis in 

CdTe Devices,” Proceedings of SPIE Vol. 7412, 741201 (2009).

[4] Enzenroth, R.A., Barth, K.L., and Sampath, W.S., “Transient Ion Drift Measurements of Polycrystalline CdTe PV Devices,” 4th

IEEE – World Conference Photovoltaic Energy Conversion (WCPEC), Hawaii, 449-452 (2006).

[5] Loef, R., Schoonman, J., Goossens, A., “Investigation of capacitance transients in CuInS2 due to ionic migration,” Solar Energy 

Materials & Solar Cells 92, 1579-1585 (2008). 

[6] Heiser, T., and Mesli, A., “Determination of the Copper Diffusion Coefficient in Silicon from Transient Ion-Drift,” Appl. Phys. 

A 57, 325-328 (1993).

[7] Lyubomirsky, I., Rabinal, J.K., and Cahen, D., “Room-temperature detection of mobile impurities in compound semiconductors 

by transient ion drift,” J. Appl. Phys. 81(10), 6684-6691 (1997).

[8] Levi, D., Albin, D., and King, D., “Influence of Surface Composition on Back-contact Performance in CdTe/CdS PV Devices,” 

Prog. Photovolt: Res. Appl. 8, 591-602 (2000). 

[9] Demtsu, S., Sites, J., “Effect of back-contact barrier on thin-film CdTe solar cells,” Thin Solid Films 510, 320-324 (2006).

[10] Luque, A., Hegedus, S., eds., Handbook of Photovoltaic Science and Engineering, John Wiley & Sons, in particular, Chapter 3 

by Gray, J., “The Physics of the Solar Cell” (2003).

[11] Albin, D.S., del Cueto, J.A., Demtsu, S.H., and Bansal, S., “The use of 2nd and 3rd level correlation analysis for studying 

degradation in polycrystalline thin-film solar cells”, 35th IEEE Photovoltaic Specialists Conference, in press (2010).

[12] Hegedus, S., Desai, D., and Thompson, C., “Voltage Dependent Photocurrent Collection in CdTe/CdS Solar Cells,” Prog. 

Photovolt: Res. Appl. 15, 587-602 (2007).
F1147-E(10/2008) 

REPORT DOCUMENTATION PAGE Form Approved

OMB No. 0704-0188

The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, 

gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this 

collection of information, including suggestions for reducing the burden, to Department of Defense, Executive Services and Communications Directorate (0704-0188). Respondents 

should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a 

currently valid OMB control number.

PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ORGANIZATION.

1. REPORT DATE (DD-MM-YYYY)

March 2011

2. REPORT TYPE

Conference Paper

3. DATES COVERED (From - To)

 

4. TITLE AND SUBTITLE

Effect of Hysteresis on Measurements of Thin-Film Cell 

Performance

5a. CONTRACT NUMBER

DE-AC36-08GO28308

5b. GRANT NUMBER

5c. PROGRAM ELEMENT NUMBER

6. AUTHOR(S)

D. Albin and J. del Cueto

5d. PROJECT NUMBER

NREL/CP-5200-48996

5e. TASK NUMBER

PVA9.2450

5f. WORK UNIT NUMBER

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)

National Renewable Energy Laboratory

1617 Cole Blvd.

Golden, CO 80401-3393

8. PERFORMING ORGANIZATION

REPORT NUMBER

NREL/CP-5200-48996

9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)

NREL

11. SPONSORING/MONITORING

AGENCY REPORT NUMBER

12. DISTRIBUTION AVAILABILITY STATEMENT

National Technical Information Service

U.S. Department of Commerce

5285 Port Royal Road

Springfield, VA 22161

13. SUPPLEMENTARY NOTES

14. ABSTRACT (Maximum 200 Words)

Transient or hysteresis effects in polycrystalline thin film CdS/CdTe cells are a function of pre-measurement voltage 

bias and whether Cu is introduced as an intentional dopant during back contact fabrication. When Cu is added, the 

current-density (J) vs. voltage (V) measurements performed in a reverse-to-forward voltage direction will yield higher 

open-circuit voltage (Voc), up to 10 mV, and smaller short-circuit current density (Jsc), by up to 2 mA/cm2, relative to 

scanning voltage in a forward-to-reverse direction. The variation at the maximum power point, Pmax, is however 

small. The resulting variation in FF can be as large as 3%. When Cu is not added, hysteresis in both Voc and Jsc is 

negligible however Pmax hysteresis is considerably greater. This behavior corroborates observed changes in 

depletion width, Wd, derived from capacitance (C) vs voltage (V) scans. Measured values of Wd are always smaller 

in reverse-to-forward voltage scans, and conversely, larger in the forward-to-reverse voltage direction. Transient ion 

drift (TID) measurements performed on Cu-containing cells do not show ionic behavior suggesting that capacitance 

transients are more likely due to electronic capture-emission processes. J-V curve simulation using Pspice shows 

that increased transient capacitance during light-soak stress at 100 oC correlates with increased space-charge 

recombination. Voltage-dependent collection however was not observed to increase with stress in these cells.

15. SUBJECT TERMS

CdTe solar cell; transient capacitance; DLTS; transient ion drift; reliability; degradation; voltage-dependent collection

16. SECURITY CLASSIFICATION OF: 17. LIMITATION 

OF ABSTRACT

UL

18. NUMBER 

OF PAGES

19a. NAME OF RESPONSIBLE PERSON

a. REPORT

Unclassified

b. ABSTRACT

Unclassified

c. THIS PAGE

Unclassified 19b. TELEPHONE NUMBER (Include area code)

Standard Form 298 (Rev. 8/98)

Prescribed by ANSI Std. Z39.18