# Patent

## Title
System and method for offset voltage calibration

## Abstract

An embodiment method includes measuring, by a calibration device, a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting and measuring, by a calibration device, a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting. The method further includes calculating, by the calibration device, an offset voltage of a signal path including the VGA using the first output voltage and the second output voltage and calculating, by the calibration device, an internal offset voltage of the VGA using the first output voltage and the second output voltage.

## Background
TECHNICAL FIELD
The present invention relates generally to integrated circuits, and, in particular embodiments, to a system and method for DC Offset voltage Correction for Variable Gain Amplifiers.
BACKGROUND
Generally, in a network device, various circuit elements are interconnected in order to filter, mix, amplify, and convert signals. There may be multiple stages of filtering and amplification in a signal's path, and each stage may contribute some offset voltage (e.g., error) to the signal as it is modified along the circuit. A variable gain amplifier (VGA) may be used in a signal's path (e.g., at a last stage of the path). The VGA may take a differential input signal (e.g., as modified by previous circuit elements in the path) and output an amplified differential signal or an amplified single ended signal
However, the differential input signal may include an offset voltage of the signal path (e.g., error generated along the signal path). The VGA may also contribute an internal offset voltage to the signal. These offset voltages, if uncorrected, may be amplified by the VGA and reduce the usable amplitude range of the VGA output. Thus, calibration of the signal is desirable to counteract both the offset voltage of the input signal as well as the offset voltage internal to the VGA.
Calibration may include determining the offset voltage of the signal path and the offset voltage of the VGA. For example, the output of the VGA may be swept over its entire range while applying an offset correction voltage to the VGA until the output crosses zero. Alternatively, a binary or intelligent search may be conducted to arrive at these offset voltages. However, these methods require taking a large range of measurements, which may be time intensive and costly.
SUMMARY
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention which includes a system and method for offset voltage calibration.
In accordance with an embodiment, a method includes measuring, by a calibration device, a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting and measuring, by a calibration device, a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting. The method further includes calculating, by the calibration device, an offset voltage of a signal path including the VGA using the first output voltage and the second output voltage and calculating, by the calibration device, an internal offset voltage of the VGA using the first output voltage and the second output voltage.
In accordance with another embodiment, a method for calibrating a circuit includes activating a circuit path with no input signal, wherein the circuit path includes a variable gain amplifier (VGA), setting, by a calibration device, the VGA to a first gain step, measuring, by the calibration device, a first output voltage of the VGA when the VGA is set to the first gain step, setting, by the calibration device, the VGA to a second gain step, and measuring, by the calibration device, a second output voltage of the VGA when the VGA is set to the second gain step. The first gain step and the second gain step are different. The method further includes calculating, by the calibration device, a first offset voltage and a second offset voltage in accordance with the first output voltage, the second output voltage, the first gain step, and the second gain step. The first offset voltage is an offset voltage caused by circuit elements in the circuit path prior to the VGA, and the second offset voltage is an internal offset voltage of the VGA. The method further includes calculating, by the calibration device, offset correction voltages for different gain steps of the VGA in accordance with the first offset voltage and the second offset voltage and configuring, by the calibration device, a DC offset correction (DCOC) digital to analog convertor (DAC) with the offset correction voltages for the different gain steps of the VGA.
In accordance with yet another embodiment, a calibration system includes a signal circuit having a variable gain amplifier (VGA); and a dc offset correction (DCOC) digital to analog convertor (DAC) applying an offset correction voltage to the VGA. The calibration system further includes a calibration circuit electrically connected to the signal circuit. The calibration circuit is configured to measure a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting; measure a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting; and calculate an offset voltage of the signal circuit and an internal offset voltage of the VGA using the first output voltage and the second output voltage. The calibration system is further configured to calculate offset correction voltages corresponding to different gain settings of the VGA in accordance with the offset voltage of the signal circuit and the internal offset voltage of the VGA.



BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGS. 1 and 2 are block diagrams of circuit paths in accordance with some embodiments;
FIG. 3 is a diagram of an integrated circuit in accordance with some embodiments; and
FIG. 4 is a process flow for performing calibration in accordance with some embodiments.



DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Various embodiments are described within a specific context, namely DC offset voltage correction for a receiver (RX) circuit path in a transceiver device. However, various embodiment devices may be used in any integrated circuit where calibration is desired.
Various embodiments include a calibration system for DC offset voltage correction in a RX circuit path of a transceiver. The DC offset voltage correction may occur at a last stage of the RX path (e.g., at a variable gain amplifier (VGA)). During calibration, the VGA is set to two different gain settings (also referred to as gain steps), and the output of each setting is measured using an analog to digital convertor (ADC), for example. The offset voltage of the signal path (e.g., offset voltage to the signal caused by various elements along the RX path) as well as the internal offset voltage of the VGA is calculated in accordance with the two output measurements of the two gain settings. Knowing these offset voltages, a suitable offset correction voltage may be calculated for each gain step of the VGA. As the VGA gain is changed during operation of the transceiver, a suitable offset correction voltage can be applied by a DC offset voltage correction (DCOC) digital to analog convertor (DAC), which feeds into the VGA. Thus, the DC offset voltage calculation may be achieved by taking as few as two measurements, which allows for fast and accurate calibration of a circuit path.
FIG. 1 illustrates an example RX path lineup 100, which may be used in a transceiver to amplify, mix, and/or filter a received signal, for example. The various elements of RX path 100 are for illustration sake only, and various embodiments may include any combination of the illustrated elements as well as additional elements depending on device design. RX path 100 may take an input signal 102, which may be a differential signal. Signal 102 may be amplified by low noise amplified (LNA) 104 to achieve an amplified signal 102A. Amplified signal 102A may be mixed with other signals by a mixer 106 to achieve a mixed signal 102B. For example, the signal 102 may be a high frequency radio signal and the mixer acts as a downconverter to convert the desired portion of the radio spectrum to a lower frequency for further processing. Mixed signal 102B may further be amplified by a trans-impedance amplifier (TIA) 108 to achieve an amplified signal 102C. Amplified signal 102C may then be filtered by a low pass filter (LPF) 110 in order to remove or at least reduce high frequency noise and signals, for example, to generate a filtered signal 102D. Filtered signal 102D applies an input voltage Vin to VGA 112, which amplifies Vin and generates an output signal 120 having an output voltage Vout. In an embodiment, VGA 112 is an inverting amplifier. In another embodiment, VGA 112 may be a non-inverting amplifier. Output signal 120 may then be measured by ADC 118. Output signal 120 may be a differential signal or a single ended signal.
The input to VGA 112 (e.g., filtered signal 102D) is a differential signal that may include an offset voltage VOS1 generated at least in part by various elements in the RX lineup prior to VGA 112 (e.g., LNA 104, mixer 106, TIA 108, and LPF 110). Furthermore, VGA 112 may also contribute an internal offset voltage VOS2 to output voltage Vout, which further increases the error of output signal 120. In order to counteract this error, an offset correction voltage may be applied in calibration portion 116 of RX path 100. In various embodiments, a DCOC DAC 114 applies an offset correction voltage VDCOC to a summing node of VGA 112. During operation of RX path 100, offset correction voltage VDCOC is selected in accordance with a selected gain setting of VGA 112, offset voltage VOS1 of the signal path, and internal offset voltage VOS2 of VGA 112.
In some embodiments, the output voltage Vout of VGA 112 operating with DCOC DAC 114 can be modeled in accordance with Equation (1), below:




  
    
      
        
          V
          out
        
        =
        
          
            GV
            in
          
          +
          
            
              V
              OSAMP
            
            f
          
          +
          
            
              I
              DCOC
            
            ⁢
            RG
          
        
      
    
    
      
        (
        1
        )
      
    
  




where G is the gain of VGA 112, Vin is a function of offset voltage VOS1, VOSAMP is the input offset voltage internal to VGA 112, f is the feedback factor of passive components around VGA 112, and IDCOCR is the offset correction voltage VDCOC.

In an embodiment, feedback factor f is substantially constant over the different gain steps of VGA 112. In such embodiments, the internal offset voltage VOS2 of VGA 112 is constant and equals




  
    V
    OSAMP
  
  f




for all gain steps of VGA 112. Thus, when feedback factor f is substantially constant, Equation (1) can also be expressed as:

Vout=GVin+VOS2+IDCOCRG  (2)

In such embodiments, feedback factor f may be approximated as substantially constant for all gain steps of VGA 112 In other embodiments, feedback factor f varies but is predictable for different gain steps of VGA 112 as will be described in greater detail below.

In the above embodiment, DCOC DAC 114 generates a current IDCOC, and R is the resistance by which current IDCOC creates voltage VDCOC (e.g., VDCOC=IDCOCR). In various embodiments, R may be configured to remain constant through all gain steps of VGA 112. Furthermore, VDCOC may adjust Vout linearly over the current range of DCOC DAC 114, but VDCOC corrects Vout in accordance with changes in the gain setting (e.g., gain G) of VGA 112. Thus, once offset voltages VO1 and VO2 from RX path 100 and VGA 112 are calibrated out of the output signal, changing the gain setting of VGA 112 will not require new calibration.
FIG. 2 illustrates a block diagram of RX path 100 during calibration. Calibration of RX path 100 may occur at any time, such as, during manufacture, during field operations, combinations thereof, and the like. In some embodiments, an automated calibration device, such as, a baseband chip 200 (also referred, may perform calibration of RX path 100 although other devices (e.g., other calibration circuits) or manual calibration may be used in other embodiments. In some embodiments, baseband chip 200 controls signal reception and transmission in the transceiver device, and baseband chip 200 includes circuitry (e.g., a processor) capable of measuring output voltages, calculating offset voltages, calculating offset correction voltages, and programming DCOC DAC 114 with suitable offset correction voltages for different gain settings of VGA 112.
To initiate calibration, RX path 100 is activated with no input signal. Circuit block 202 represents elements of RX path 100 (e.g., LNA 104, mixer 106, TIA 108, and LPF 110) prior to VGA 112. Because no input signal is activated, the output of circuit block 202 is equivalent to offset voltage VOS1 of the signal path (e.g., caused by elements in circuit block 202). Thus, during calibration, as illustrated by FIG. 2, the input voltage Vin of VGA 112 is equivalent to VOS1. Assuming feedback factor f is constant, output voltage Vout of VGA 112 during calibration can be expressed as:

Vout=GVOS1+VOS2+IDCOC,RG  (3)

During calibration, a constant calibration offset correction voltage VDCOC′ may also be applied by DCOC DAC 114, and the calibration offset correction voltage VDCOC′ is known by the calibration mechanism (e.g., baseband chip 200). For example, DCOC DAC 114 may be configured to generate a known, calibration offset correction current IDCOC′. In an embodiment, calibration offset correction current IDCOC′ may be set to center code, and an approximation for calibration current IDCOC′ would be 0 Amperes (A). However, in such embodiments, the center code may contribute half a least significant bit (LSB) of calibration offset current to the output voltage. In an embodiment, the calibration offset current can also be added to the below offset voltage calculations (e.g., as a constant) for improved accuracy. In other embodiments, the calibration offset correction may be omitted from the below calculations.
After activating the circuit (e.g., RX path 100), baseband chip 200 (or another calibration mechanism) measures the output voltage Vout of VGA 112 at two different gain steps (e.g., two different values of gain G). For example, the output voltage Vout may be measured using ADC 118 for each gain step. Baseband chip 200 may then calculate VOS1 and VOS2 in accordance with the two output voltage Vout measurements. In an embodiment, the calculation may be in accordance with:

Vout1=G1VOS1+VOS2+IDCOC′RG1  (4)

Vout2=G2VOS1+VOS2+IDCOC′RG2  (5)

where G1 is a first selected gain step of VGA 112, and Vout1 is the measured output voltage of VGA 112 when G1 is selected. G2 is a second selected gain step for VGA 112, and Vout2 is the measured output voltage of VGA 112 when G2 is selected. Gains G1 and G2 may be selected using any suitable criteria. In an embodiment, gain G1 is selected to be about half way above a center gain setting of VGA 112 while gain G2 is selected to be about half way below the center gain setting of VGA 112. In such embodiments, gain settings at edges (e.g., minimum and maximum) of VGA 112's ranges are avoided during calibration for improved output voltage measurement accuracy. In another embodiment, gain G1 is selected to be a maximum gain setting of VGA 112 while gain G2 is selected to be a minimum gain setting of VGA 112. In such embodiments, the variance between gain settings of VGA 112 is maximized during calibration for improved tracking of offset voltages. Any other gain step within VGA 112's range may also be selected. Furthermore, as described above, IDCOC′ R for both equations is a known constant. Thus, offset voltages VOS1 and VOS2 can be calculated in accordance with Equations (4) and (5), above. The resulting equations for offset voltages VOS1 and VOS2 are:





  
    
      
        
          
            V
            
              OS
              ⁢
              
                
              
              ⁢
              1
            
          
          =
          
            
              
                
                  V
                  
                    out
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                -
                
                  V
                  
                    out
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              
                (
                
                  
                    G
                    2
                  
                  -
                  
                    G
                    1
                  
                
                )
              
            
            -
            
              I
              DCOC
            
          
        
        ,
        R
      
    
    
      
        (
        6
        )
      
    
  
  
    
      
        
          V
          
            OS
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            
              
                G
                2
              
              ⁢
              
                V
                
                  out
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            -
            
              
                G
                1
              
              ⁢
              
                V
                
                  out
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
          
            
              G
              2
            
            -
            
              G
              1
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




After baseband chip 200 (or other calibration mechanism) calculates offset voltages VOS1 and VOS2, offset correction current IDCOC for any gain setting of VGA 112 can be calculated according to Equation (8), below:




  
    
      
        
          I
          DCOC
        
        =
        
          
            
              
                -
                G
              
              ⁢
              
                
              
              ⁢
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            -
            
              V
              
                OS
                ⁢
                
                  
                
                ⁢
                2
              
            
          
          
            R
            ⁢
            
              
            
            ⁢
            G
          
        
      
    
    
      
        (
        8
        )
      
    
  




Baseband chip 200 may then program DCOC DAC 114 with a corresponding offset correction voltage VDCOC or offset correction current IDCOC for each gain setting of VGA 112 based on the above Equation (8). During operation of the circuit, DCOC DAC 114 applies an appropriate offset correction current IDCOC based on the programming and the selected gain setting of VGA 112. By applying the appropriate offset correction current IDCOC, a suitable offset correction voltage VDCOC may be applied to VGA 112, which cancels or at least reduces the effect of offset voltages VOS1 (e.g., offset voltage of the signal path) and VOS2 (e.g., internal offset of VGA 112) on the output signal. Thus, as described above, baseband chip 200 (or other calibration mechanism) may calibrate an amplifier circuit (e.g., RX path 100) using two output voltage measurements, which allows for fast calibration of the circuit.
The above calculations are based on an assumption that feedback factor f for VGA 112 is constant. In another embodiment, feedback factor f may vary as the gain G of VGA 112 changes. In such embodiments, feedback factor f may be predictable and known for different gain steps. Calibration of the circuit may be similar to the steps described above. For example, the output voltages Vout1 and Vout2 can be measured for two different gain settings, G1 and G2, respectively. Feedback factors for the two different gains may be f1 for gain G1 and f2 for gain G2, where f1 and f2 are known but different. Calculations for offset voltages VOS1 and VOS2 may be in accordance with the following modified equations:




  
    
      
        
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              1
            
          
          =
          
            
              
                G
                1
              
              ⁢
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            +
            
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              
                f
                1
              
            
            +
            
              I
              DCOC
            
          
        
        ,
        
          RG
          1
        
      
    
    
      
        (
        9
        )
      
    
  








  
    
      
        
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              2
            
          
          =
          
            
              
                G
                2
              
              ⁢
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            +
            
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              
                f
                2
              
            
            +
            
              I
              DCOC
            
          
        
        ,
        
          RG
          2
        
      
    
    
      
        (
        10
        )
      
    
  




In such embodiments, offset voltages VOS1 and VOS2 can be calculated by the calibration mechanism (e.g., baseband chip 200) in accordance with Equations (11) and (12) below:




  
    
      
        
          
            V
            
              OS
              ⁢
              
                
              
              ⁢
              1
            
          
          =
          
            
              
                
                  
                    V
                    
                      out
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  ⁢
                  
                    f
                    2
                  
                
                -
                
                  
                    V
                    
                      out
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  ⁢
                  
                    f
                    1
                  
                
              
              
                
                  
                    G
                    2
                  
                  ⁢
                  
                    f
                    2
                  
                
                -
                
                  
                    G
                    1
                  
                  ⁢
                  
                    f
                    1
                  
                
              
            
            -
            
              I
              DCOC
            
          
        
        ,
        R
      
    
    
      
        (
        11
        )
      
    
  
  
    
      
        
          V
          
            OS
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            
              
                G
                2
              
              ⁢
              
                V
                
                  out
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            -
            
              
                G
                1
              
              ⁢
              
                V
                
                  out
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
          
            
              
                G
                2
              
              
                f
                1
              
            
            -
            
              
                G
                1
              
              
                f
                2
              
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




Once offset voltages VOS1 and VOS2 are calculated, offset correction current IDCOC for any gain setting of VGA 112 can be calculated according to:




  
    
      
        
          I
          DCOC
        
        =
        
          
            
              -
              
                GV
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            -
            
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              f
            
          
          RG
        
      
    
    
      
        (
        13
        )
      
    
  




DCOC DAC 114 may then be programmed with an offset correction current IDCOC for all gain settings of VGA 112 as described above.

The above calculations are based on an assumption that the value of the correction voltage applied by DCOC DAC 114 is constant during calibration. In another embodiment, the correction voltage may vary between the two calibration measurements. In such embodiments, the value IDCOC RG will be predictable and known for different gain steps. Calibration of the circuit may be similar to the steps described above. For example, the output voltages Vout1 and Vout2 can be measured for two different gain settings, G1 and G2, respectively. Correction values applied by DCOC DAC 114 for the two different gains may be IDCOC1 for the first gain G1 and IDCOC2 for the second gain G2, where the offset calibration currents IDCOC1 and IDCOC2 are known but different. In the below equations, the feedback factor f1 (corresponding to gain G1) and f2 (corresponding to gain G2) may be different or the same for the two different gain settings. Calculations for offset voltages VOS1 and VOS2 may be in accordance with the following modified equations:




  
    
      
        
          V
          
            out
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            
              G
              1
            
            ⁢
            
              V
              
                OS
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          +
          
            
              V
              
                OS
                ⁢
                
                  
                
                ⁢
                2
              
            
            
              f
              1
            
          
          +
          
            
              I
              
                DCOC
                ⁢
                
                  
                
                ⁢
                1
              
            
            ⁢
            
              RG
              1
            
          
        
      
    
    
      
        (
        14
        )
      
    
  
  
    
      
        
          V
          
            out
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            
              G
              2
            
            ⁢
            
              V
              
                OS
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          +
          
            
              V
              
                OS
                ⁢
                
                  
                
                ⁢
                2
              
            
            
              f
              2
            
          
          +
          
            
              I
              
                DCOC
                ⁢
                
                  
                
                ⁢
                2
              
            
            ⁢
            
              RG
              2
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




In such embodiments, offset voltages VOS1 and VOS2 can be calculated by the calibration mechanism (e.g., baseband chip 200) in accordance with Equations (16) and (17) below:




  
    
      
        
          V
          
            OS
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            
              
                
                  V
                  
                    out
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                ⁢
                
                  f
                  2
                
              
              -
              
                
                  V
                  
                    out
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  f
                  1
                
              
            
            
              
                
                  G
                  2
                
                ⁢
                
                  f
                  2
                
              
              -
              
                
                  G
                  1
                
                ⁢
                
                  f
                  1
                
              
            
          
          +
          
            (
            
              
                
                  
                    I
                    
                      DCOC
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  ⁢
                  
                    RG
                    1
                  
                
                -
                
                  
                    I
                    
                      DCOC
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  ⁢
                  
                    RG
                    2
                  
                
              
              
                
                  
                    G
                    2
                  
                  ⁢
                  
                    f
                    2
                  
                
                -
                
                  
                    G
                    1
                  
                  ⁢
                  
                    f
                    1
                  
                
              
            
            )
          
        
      
    
    
      
        (
        16
        )
      
    
  
  
    
      
        
          V
          
            OS
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            
              
                
                  G
                  2
                
                ⁢
                
                  V
                  
                    out
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              -
              
                
                  G
                  1
                
                ⁢
                
                  V
                  
                    out
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            
              
                
                  G
                  2
                
                
                  f
                  1
                
              
              -
              
                
                  G
                  1
                
                
                  f
                  2
                
              
            
          
          +
          
            (
            
              
                
                  
                    I
                    
                      DCOC
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  ⁢
                  
                    RG
                    1
                  
                  ⁢
                  
                    G
                    2
                  
                
                -
                
                  
                    I
                    
                      DCOC
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  ⁢
                  
                    RG
                    1
                  
                  ⁢
                  
                    G
                    2
                  
                
              
              
                
                  
                    G
                    2
                  
                  
                    f
                    1
                  
                
                -
                
                  
                    G
                    1
                  
                  
                    f
                    2
                  
                
              
            
            )
          
        
      
    
    
      
        (
        17
        )
      
    
  




Once offset voltages VOS1 and VOS2 are calculated, offset correction current IDCOC for any gain setting of VGA 112 can be calculated according to:




  
    
      
        
          I
          DCOC
        
        =
        
          
            
              
                -
                G
              
              ⁢
              
                
              
              ⁢
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            -
            
              
                V
                
                  OS
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              f
            
          
          
            R
            ⁢
            
              
            
            ⁢
            G
          
        
      
    
    
      
        (
        18
        )
      
    
  




DCOC DAC 114 may then be programmed with an offset correction current IDCOC for all gain settings of VGA 112 as described above.
FIG. 3 illustrates a circuit 300 for implementing a VGA and DCOC DAC (e.g., VGA 112 and DCOC DAC 114) during normal operations and calibration in accordance with some embodiments. Circuit 300 provides only one example implementation of a VGA and DCOC DAC. Other suitable implementations, for example, having different circuit elements and/or different configurations may be used in other embodiments.
As illustrated by FIG. 3, a pair of differential input voltages Vinp and Vinn is applied to the input of a VGA, and a pair of differential output voltages Voutp and Voutm is generated by the circuit. During a normal operation mode of circuit 300 (e.g., outside of calibration mode), differential input voltages Vinp and Vinn represent an input signal as modified by various circuit elements in the circuit path prior to the VGA (e.g., block 202 in FIG. 2). For example, differential input voltages Vinp and Vinn may include offset voltage VOS1 of the signal path. During a calibration mode of circuit 300, differential input voltages Vinp and Vinn represents the output of circuit elements in the RX path prior to the VGA (e.g., block 202 in FIG. 2) with no input signal activated. Thus, during calibration mode, differential input voltages Vinp and Vinn may be offset by offset voltage VOS1 as described above.
In circuit 300, the VGA comprises an operational amplifier (op amp) 302 and resistors R1, R2, R3, and R4. Resistors R1 and R2 may include one or more resistors, which includes at least one variable resistor that can be controlled to alter a gain setting (e.g., G) of the VGA. Resistors R3, and R4 may also be included in circuit 300 to help set the gain setting of the VGA. In some embodiments, gain G of the VGA in circuit 300 can be generally expressed as:




  
    
      
        G
        =
        
          
            R
            4
          
          
            
              R
              1
            
            ⁢
            
              
                R
                3
              
              ⁡
              
                (
                
                  
                    1
                    
                      R
                      1
                    
                  
                  +
                  
                    1
                    
                      R
                      2
                    
                  
                  +
                  
                    1
                    
                      R
                      3
                    
                  
                
                )
              
            
          
        
      
    
    
      
        (
        19
        )
      
    
  




Capacitor C may also be optionally included in the VGA, for example, to create a feedforward zero in circuits with low-bandwidth op-amps. In other embodiments, capacitor C may be omitted. In some embodiments, a variable resistor Rb in circuit 300 may also be included in order to maintain the feedback factor f of circuit 300 constant over different gain settings of the VGA. In other embodiments (e.g., when feedback factor f is variable), resistor Rb may be omitted. Furthermore, in circuit 300, resistor R6 may be optionally included to provide a path for the biasing current of the DCOC DAC 304.
Furthermore, during normal operation mode, a DCOC DAC supplies an offset correction current IDCOC to a resistor Rshunt, which applies a DC offset correction voltage VDCOC (e.g., IDCOCR) to inputs of op amp 302. During calibration mode, a DCOC DAC supplies a constant calibration offset correction current IDCOC′ to a resistor. In various embodiments, two current sources 304 configured in opposing directions are included in circuit 300 to provide a differential offset current IDCOC to the circuit. For example, when the differential offset current IDCOC is set to middle code (e.g., during calibration), both current sources 304 source the same amount of current into circuit 300, and the net differential offset current IDCOC equals 0 A. In another example, when the differential offset current IDCOC is set away from middle code, one current source 304 may source some current, and the other current source 304 may sink some current to result in a net non-zero differential offset current IDCOC being supplied to circuit 300. In circuit 300, resistors R5 may be included to help offset correction current IDCOC injected at the inputs of op amp 302 track with the gain setting of the VGA. In some embodiments resistors R5 may be about 40 kΩalthough other values for resistors R5 may be used in other embodiments. The various values of resistors in an embodiment circuit may be modified and selected based on device design as understood by one skilled in the art.
Resistor Rshunt may be a variable resistor that is varied by DCOC DAC in accordance with the gain G of the VGA. For example, as described above, the resistance R (see equation 1) of the offset correction current IDCOC is modeled as constant across all gain settings of the VGA. In circuit 300, Rshunt may be varied to provide an overall constant resistance for offset correction current IDCOC based on the gain G of the VGA. For example, the output voltage of circuit 300 is:




  
    
      
        
          V
          out
        
        =
        
          
            
              -
              
                V
                in
              
            
            ⁢
            
              
                R
                4
              
              
                
                  R
                  1
                
                ⁢
                
                  
                    R
                    3
                  
                  ⁡
                  
                    (
                    
                      
                        1
                        
                          R
                          1
                        
                      
                      +
                      
                        1
                        
                          R
                          2
                        
                      
                      +
                      
                        1
                        
                          R
                          3
                        
                      
                    
                    )
                  
                
              
            
          
          +
          
            
              R
              4
            
            ⁢
            
              
                
                  I
                  DCOC
                
                ⁢
                
                  R
                  shunt
                
              
              
                
                  R
                  5
                
                +
                
                  R
                  shunt
                
              
            
          
          +
          
            
              V
              OSAMP
            
            f
          
        
      
    
    
      
        (
        20
        )
      
    
  




Comparing Equations (1), (14), and (20) above, resistor Rshunt may be varied in accordance with a selected gain G of the VGA in order to apply a constant overall resistance R (see Equation (1)) to IDCOC across all gain settings of the VGA. In various embodiments, the DCOC DAC may control both the offset correction current IDCOC and Rshunt in circuit 300 in order to provide a suitable offset correction voltage VDCOC to the VGA.

FIG. 4 illustrates a process flow 400 for calibrating a circuit according to various embodiments. In step 402 a circuit path (e.g., RX path 100) is activated with no input signal. The circuit path may include a VGA (e.g., VGA 112) at an end of the path. In step 404, the VGA is set to a first gain setting, and an output voltage of the VGA is measured. In step 406, the VGA is set to a second gain setting, which may be different than the first gain setting. The output of the VGA from the second gain setting is measured. During steps 404 and 406, a DCOC DAC (e.g., DCOC DAC 114) may apply a same calibration offset correction voltage or a different but known calibration offset correction voltage (e.g., IDCOC′ R) to a summing node of the VGA. In step 408, an offset voltage of the signal path (e.g., VOS1) and an internal offset voltage of the VGA (e.g., VOS2) are calculated using the two output voltage measurements from steps 404 and 406. In embodiments where the feedback factor of the VGA is constant across different gain settings, the offset voltages may be calculated using Equations (6) and (7) above. In another embodiment where the feedback factor of the VGA varies across different gain settings, the offset voltages may be calculated using Equations (11) and (12) above.
After the offset voltages are determined, offset correction voltages (e.g., IDCOCR) for different gain settings of the VGA may be calculated in step 410. For example, the offset correction voltages may be calculated based in Equation (8) when the feedback factor is constant or based on equation (13) when the feedback factor varies. In step 412, a DCOC DAC is configured (e.g., programmed) in accordance with the different offset correction voltages determined in step 410. During normal operations of the device, the DCOC DAC may apply a suitable offset correction voltage based on this programming and a selected gain of the VGA.
Thus, as described above, various embodiments include a calibration system for offset voltage correction in a RX circuit path of a transceiver. The DC offset voltage correction may occur at a last stage of the RX path. For example, a DCOC DAC may apply a suitable offset correction voltage to a summing node of a VGA at the end of the RX path. During calibration, the VGA is set to two different gain settings (also referred to as gain steps) with no input signal being applied to the circuit path. The output voltage of each gain setting is measured. Based on the output voltages, an offset voltage of the signal path (e.g., offset voltage to the signal caused by various elements along the RX path) as well as the internal offset voltage of the VGA is calculated. Knowing these offset voltages, a suitable offset correction voltage may be calculated for each gain step of the VGA. As the VGA gain is changed during operation of the transceiver, a suitable offset correction voltage can be applied by a DC offset voltage correction (DCOC) digital to analog convertor (DAC), which feeds into the VGA. Thus, DC offset voltage calculation may be achieved by taking as few as two measurements, which allows for fast calibration of a circuit path.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

## Claims

1. A method comprising:
measuring, by a calibration device, a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting;
measuring, by the calibration device, a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting;
calculating, by the calibration device, an offset voltage of a signal path comprising the VGA using the first output voltage and the second output voltage; and
calculating, by the calibration device, an internal offset voltage of the VGA using the first output voltage and the second output voltage.

2. The method of claim 1 further comprising calculating an offset correction voltage for each gain setting of the VGA using the offset voltage of the signal path and the internal offset voltage of the VGA.

3. The method of claim 2, further comprising programming, by the calibration device, a DC offset correction (DCOC) digital to analog convertor (DAC) with the offset correction voltage for different gain settings of the VGA.

4. The method of claim 3 further comprising applying, by the DCOC DAC, a same offset correction voltage to the VGA while measuring the first output voltage and measuring the second output voltage.

5. The method of claim 3 further comprising:
applying, by the DCOC DAC, a first offset correction voltage to the VGA while measuring the first output voltage; and
applying, by the DCOC DAC, a second offset correction voltage to the VGA while measuring the second output voltage, wherein the first offset correction voltage and the second offset correction voltage are different, and wherein calculating the offset voltage of the signal path and the internal offset voltage of the VGA are in accordance with the first offset correction voltage and the second offset correction voltage.

6. The method of claim 1, wherein measuring the first output voltage and measuring the second output voltage comprises measuring the first output voltage and measuring the second output voltage while the signal path is activated with no input signal.

7. The method of claim 1, wherein a feedback factor of the VGA varies across different gain settings of the VGA, and wherein calculating the offset voltage of the signal path and calculating the internal offset voltage of the VGA is in accordance with a first feedback factor corresponding to the first gain setting and a second feedback factor corresponding to the second gain setting.

8. The method of claim 1, wherein a feedback factor of the VGA is approximately constant across different gain settings of the VGA.

9. A method for calibrating a circuit comprising:
activating a circuit path with no input signal, wherein the circuit path comprises a variable gain amplifier (VGA);
setting, by a calibration device, the VGA to a first gain step;
measuring, by the calibration device, a first output voltage of the VGA when the VGA is set to the first gain step;
setting, by the calibration device, the VGA to a second gain step, wherein the first gain step and the second gain step are different;
measuring, by the calibration device, a second output voltage of the VGA when the VGA is set to the second gain step;
calculating, by the calibration device, a first offset voltage and a second offset voltage in accordance with the first output voltage, the second output voltage, the first gain step, and the second gain step, wherein the first offset voltage is an offset voltage caused by circuit elements in the circuit path prior to the VGA, and wherein the second offset voltage is an internal offset voltage of the VGA;
calculating, by the calibration device, offset correction voltages for different gain steps of the VGA in accordance with the first offset voltage and the second offset voltage; and
configuring, by the calibration device, a DC offset correction (DCOC) digital to analog convertor (DAC) with the offset correction voltages for the different gain steps of the VGA.

10. The method of claim 9, wherein a feedback factor of the VGA is approximately constant across the different gain steps of the VGA, and wherein the method further comprises calculating the first offset voltage and calculating the second offset voltage in accordance with




  
    
      V
      
        OS
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      
        
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              2
            
          
          -
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              1
            
          
        
        
          (
          
            
              G
              2
            
            -
            
              G
              1
            
          
          )
        
      
      -
      
        I
        DCOC
      
    
  
  ,
  R




and




  
    
      V
      
        OS
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          
            G
            2
          
          ⁢
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              1
            
          
        
        -
        
          
            G
            1
          
          ⁢
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              2
            
          
        
      
      
        
          G
          2
        
        -
        
          G
          1
        
      
    
  
  ,




wherein VOS1 is the first offset voltage, wherein VOS2 is the second offset voltage, wherein Vout1 is the first output voltage, wherein Vout2 is the second output voltage, wherein G1 is the first gain step, wherein G2 is the second gain step, and wherein IDCOC′ R is a calibration offset correction voltage applied, by the DCOC DAC, to the VGA while measuring the first output voltage and the second output voltage.

11. The method of claim 10 further comprising calculating the offset correction voltages for different gain steps of the VGA comprises calculating an offset correction voltage for a gain step in accordance with




  
    
      
        I
        DCOC
      
      ⁢
      R
    
    =
    
      
        
          -
          
            GV
            
              OS
              ⁢
              
                
              
              ⁢
              1
            
          
        
        -
        
          V
          
            OS
            ⁢
            
              
            
            ⁢
            2
          
        
      
      G
    
  
  ,




wherein IDCOCR is the offset correction voltage, and wherein G is the gain step.

12. The method of claim 9, wherein a feedback factor of the VGA varies across the different gain steps of the VGA, and wherein the method further comprises calculating the first offset voltage and calculating the second offset voltage in accordance with




  
    
      V
      
        OS
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      
        
          
            
              V
              
                out
                ⁢
                
                  
                
                ⁢
                2
              
            
            ⁢
            
              f
              2
            
          
          -
          
            
              V
              
                out
                ⁢
                
                  
                
                ⁢
                1
              
            
            ⁢
            
              f
              1
            
          
        
        
          
            
              G
              2
            
            ⁢
            
              f
              2
            
          
          -
          
            
              G
              1
            
            ⁢
            
              f
              1
            
          
        
      
      -
      
        I
        DCOC
      
    
  
  ,
  R




and




  
    
      V
      
        OS
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          
            G
            2
          
          ⁢
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              1
            
          
        
        -
        
          
            G
            1
          
          ⁢
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              2
            
          
        
      
      
        
          
            G
            2
          
          
            f
            1
          
        
        -
        
          
            G
            1
          
          
            f
            2
          
        
      
    
  
  ,




wherein VOS1 is the first offset voltage, wherein VOS2 is the second offset voltage, wherein Vout1 is the first output voltage, wherein Vout2 is the second output voltage, wherein G1 is the first gain step, wherein G2 is the second gain step, wherein IDCOC′ R is a calibration offset correction voltage applied, by the DCOC DAC, to the VGA while measuring the first output voltage and the second output voltage, wherein f1 is a first feedback factor of the VGA corresponding to the first gain step, and wherein f2 is a second feedback factor of the VGA corresponding to the second gain step.

13. The method of claim 12 further comprising calculating the offset correction voltages for different gain steps of the VGA comprises calculating an offset correction voltage for a gain step in accordance with




  
    
      
        I
        DCOC
      
      ⁢
      R
    
    =
    
      
        
          -
          
            GV
            
              OS
              ⁢
              
                
              
              ⁢
              1
            
          
        
        -
        
          
            V
            
              OS
              ⁢
              
                
              
              ⁢
              2
            
          
          f
        
      
      G
    
  
  ,




wherein IDCOCR is the offset correction voltage, wherein G is the gain step, and wherein f is a feedback factor of the VGA corresponding to the gain step.

14. The method of claim 9, wherein the DCOC DAC applies a first calibration offset correction voltage while measuring the first output voltage and applies a second calibration offset correction voltage while measuring the second output voltage, wherein the first calibration offset correction voltage and the second calibration offset correction voltage are different, and wherein the method further comprises calculating the first offset voltage and calculating the second offset voltage in accordance with




  
    V
    
      OS
      ⁢
      
        
      
      ⁢
      1
    
  
  =
  
    
      
        
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              2
            
          
          ⁢
          
            f
            2
          
        
        -
        
          
            V
            
              out
              ⁢
              
                
              
              ⁢
              1
            
          
          ⁢
          
            f
            1
          
        
      
      
        
          
            G
            2
          
          ⁢
          
            f
            2
          
        
        -
        
          
            G
            1
          
          ⁢
          
            f
            1
          
        
      
    
    +
    
      (
      
        
          
            
              I
              
                DCOC
                ⁢
                
                  
                
                ⁢
                1
              
            
            ⁢
            
              RG
              1
            
          
          -
          
            
              I
              
                DCOC
                ⁢
                
                  
                
                ⁢
                2
              
            
            ⁢
            
              RG
              2
            
          
        
        
          
            
              G
              2
            
            ⁢
            
              f
              2
            
          
          -
          
            
              G
              1
            
            ⁢
            
              f
              1
            
          
        
      
      )
    
  




and




  
    
      V
      
        OS
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          
            
              G
              2
            
            ⁢
            
              V
              
                out
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          -
          
            
              G
              1
            
            ⁢
            
              V
              
                out
                ⁢
                
                  
                
                ⁢
                2
              
            
          
        
        
          
            
              G
              2
            
            
              f
              1
            
          
          -
          
            
              G
              1
            
            
              f
              2
            
          
        
      
      -
      
        (
        
          
            
              
                I
                
                  DCOC
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              ⁢
              
                RG
                1
              
              ⁢
              
                G
                2
              
            
            -
            
              
                I
                
                  DCOC
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ⁢
              
                RG
                1
              
              ⁢
              
                G
                2
              
            
          
          
            
              
                G
                2
              
              
                f
                1
              
            
            -
            
              
                G
                1
              
              
                f
                2
              
            
          
        
        )
      
    
  
  ,




wherein VOS1 is the first offset voltage, wherein VOS2 is the second offset voltage, wherein Vout1 is the first output voltage, wherein Vout2 is the second output voltage, wherein G1 is the first gain step, wherein G2 is the second gain step, wherein IDCOC1R is the first calibration offset correction voltage, wherein IDCOC2R is the second calibration offset correction voltage, wherein f1 is a first feedback factor of the VGA corresponding to the first gain step, and wherein f2 is a second feedback factor of the VGA corresponding to the second gain step.

15. The method of claim 9 further comprising taking no more than two output voltage measurements for each calibration process.

16. A calibration system comprising:
a signal circuit comprising:
a variable gain amplifier (VGA); and
a DC offset correction (DCOC) digital to analog convertor (DAC) applying an offset correction voltage to the VGA; and

a calibration circuit electrically connected to the signal circuit, wherein the calibration circuit:
measures a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting;
measures a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting;
calculates an offset voltage of the signal circuit and an internal offset voltage of the VGA using the first output voltage and the second output voltage; and
calculates offset correction voltages corresponding to different gain settings of the VGA in accordance with the offset voltage of the signal circuit and the internal offset voltage of the VGA.

17. The calibration system of claim 16, wherein the calibration circuit is further configured to program the DCOC DAC with the offset correction voltages corresponding to the different gain settings of the VGA.

18. The calibration system of claim 16, wherein the calibration circuit comprises a baseband chip.

19. The calibration system of claim 16, wherein the signal circuit comprises a low noise amplifier, a mixer, a trans-impedance amplifier, a low pass filter, or a combination thereof.

20. The calibration system of claim 16, wherein the signal circuit comprises an analog to digital convertor (ADC) connected to an output of the VGA, wherein the first output voltage and the second output voltage are measured using the ADC.