# Patent

## Title
Group III arsenide material smoothing and chemical mechanical planarization processes

## Abstract

A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.

## Background
CROSS REFERENCE TO RELATED APPLICATION
The present application claims the benefit of U.S. Provisional Patent Application No. 62/241,425, filed Oct. 14, 2015, the entire content and disclosure of which is incorporated herein by reference.


BACKGROUND
The present application relates to a semiconductor structure and a method for fabricating the same. More particularly, the present application relates to slurry compositions and a method for planarizing a Group III arsenide material, which can be used, for instance, in fabrication of semiconductor structures, such as, n-type MOSFETs (NFET) devices.
As the density of semiconductor integrated circuits increases and the corresponding size of circuit elements decreases, one of the key strategies to increase performance at lower operating voltages is to increase carrier mobility in the channel region. By way of an example, the carrier mobility in the channel region may be enhanced, for instance, by employing a non-silicon, high mobility charge carrier material such as, for example, germanium or a III-V compound semiconductor material, in the fabrication of the channel region. For instance, high electron mobility materials, such as, for example, III-V semiconductor materials are utilized for fabricating n-type MOSFET (PFET) devices. These III-V semiconductor materials which may be, or include, materials such as, indium phosphide (InP), gallium arsenide (GaAs), InGaAs, InAs, GaSb, and InSb exhibit outstanding electron transport properties with bulk mobility of 104 cm2 V−1 s−1 or higher.
The fabrication of semiconductor material, for example, a Group III arsenide material, on a semiconductor substrate, such as, a silicon wafer, disadvantageously, leads to several issues such as, for instance, defect densities, owing to a high lattice mismatch of the Group III arsenide material and the silicon wafer. For instance, the differences in lattice constants of the III-V compound semiconductor material (e.g., gallium arsenide) and the silicon wafer (which, in one example, may have (100) crystallographic orientation) results in a lattice mismatch of 4% for the gallium arsenide material on the silicon wafer. Disadvantageously, such lattice mismatch could result in threading dislocations during the epitaxial growth of the gallium arsenide material over the silicon wafer. In one example, the typical defect densities for the gallium arsenide material grown on the silicon wafer are of the order of 108/cm2. The extremely high number of defect densities could degrade the electron mobility and may enhance junction leakage resulting in poor transistor performance. Aspect ratio trapping is one way to overcome the lattice mismatch which, for instance, includes trapping threading dislocations of the gallium arsenide material along the sidewalls of the dielectric layer disposed over the semiconductor substrate, such as, for instance, a silicon substrate. This results in a portion of the gallium arsenide material that extends above the dielectric layer, and is subsequently planarized using a chemical mechanical planarization (CMP) processes.
Enhancements in CMP processing techniques and slurry compositions employed therein continue to be desired for enhanced performance, while minimizing surface and sub-surface damage.
BRIEF SUMMARY
A method for chemical mechanical planarization of a Group III arsenide material is disclosed. By “Group III arsenide” it is meant that a material that includes at least one element from Group III of the Periodic Table of Elements and arsenide. In one embodiment a method for chemical mechanical planarization is disclosed in which a Group III arsenide material that extends above a topmost surface of a dielectric layer present on a substrate, is planarized to form coplanar surfaces of the Group III arsenide material and the dielectric layer. The Group III arsenide material has a first lattice constant, and the substrate includes a semiconductor material having a second lattice constant that is less than the first lattice constant of the Group III arsenide material. The method includes epitaxial growth of a Group III arsenide material within one or more openings, i.e., trenches, of the dielectric layer. The epitaxially grown Group III arsenide material has a lower region having a first defect density within the openings, an upper region having a second defect density that is less than the first defect density, and an overburden portion that extends above the topmost surface of the dielectric layer. The overburden portion of the Group III arsenide material that extends above the topmost surface of the dielectric layer is planarized using at least one slurry composition. In the present application, each slurry composition of the at least one slurry composition has a different removal rate selectivity towards the Group III arsenide material and the dielectric layer. In one aspect, the slurry composition of the at least one slurry composition may include an abrasive, at least one pH modulator, and an oxidizer. In the slurry composition, the at least one pH modulator may include an acidic pH modulator, and it may lack a basic pH modulator. Further, the oxidizer present in the slurry composition suppresses generation of arsine gas, and may also enhance a rate of removal of the Group III arsenide material, relative to a rate of removal of the dielectric layer. In another embodiment, an additional slurry composition of the at least one slurry composition may include an abrasive, at least one pH modulator, and an oxidizer, where the oxidizer suppresses generation of arsine gas. In this aspect, the at least one pH modulator includes at least one of an acidic pH modulator and a basic pH modulator. In such an example, the additional slurry composition has an enhanced Group III arsenide removal rate, and thus may reduce overburden and planarizes an initial topography of the Group III arsenide material, prior to the planarization of the Group III arsenide material with the slurry composition. This planarization process with the additional slurry composition may leave a planarized Group III arsenide material extended above the topmost surface of the dielectric layer, which can be removed using the slurry composition mentioned above.
In a further embodiment, the method may further include a Group III arsenide stack, located on a substrate, with the Group III arsenide stack includes a Group III arsenide material. In such an example, the Group III arsenide material of the Group III arsenide stack is bonded to a substrate stack, subsequent to the planarizing with the additional slurry composition. A subsequent planarization process with the slurry composition may be performed to planarize the Group III arsenide stack and the substrate to expose a surface of the Group III arsenide material that is opposite to the substrate stack.
In one embodiment, a method for chemical mechanical planarization of Group III arsenide is provided in which a dielectric layer containing at least one opening is formed above a substrate. A Group III arsenide material which includes a portion that extends above a topmost surface of the dielectric layer is epitaxially grown within the at least one opening of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of a remaining portion of the Group III arsenide material and the dielectric layer. The method, for instance, may further include a slurry composition of the at least one slurry composition that polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and may include an abrasive, at least one pH modulator and an oxidizer, with the at least one pH modulator including an acidic pH modulator, but lacking a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.
In another aspect of the present application, a method for chemical mechanical planarization is provided in which a Group III arsenide stack including a Group III arsenide material, is provided, and located on a substrate. The Group III arsenide material of the Group III arsenide stack is bonded to a substrate stack. The method, for instance, may further include planarizing the substrate and at least one additional Group III arsenide material of the Group III arsenide stack with a slurry composition to expose a surface of the Group III arsenide material that is opposite to the substrate stack, where the slurry composition may include an abrasive, at least one pH modulator and an oxidizer, with the at least one pH modulator including an acidic pH modulator, but lacking a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.
In yet another aspect of the present application, a slurry composition for planarizing Group III arsenide material is provided that includes an abrasive, at least one pH modulator, and an oxidizer. In such implementation, the at least one pH modulator includes an acidic pH modulator and a basic pH modulator. The slurry composition, for instance, may further include an abrasive, at least one pH modulator, and an oxidizer. In such implementation, the at least one pH modulator includes an acidic pH modulator, but lacks a basic pH modulator. Further, the oxidizer present in the slurry composition may, in some embodiments, suppress generation of an arsine gas.



BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
FIG. 1 is a cross-sectional view of one embodiment of a structure that includes a dielectric layer disposed over a substrate, in accordance with one or more aspects of the present application.
FIG. 2 depicts the structure of FIG. 1 after forming one or more openings within the dielectric layer, in accordance with one or more aspects of the present application.
FIG. 3 depicts the structure of FIG. 2 after epitaxially growing a Group III arsenide material in each of the opening(s) which extends above a topmost surface of the dielectric layer, in accordance with one or more aspects of the present application.
FIG. 4 depicts the structure of FIG. 3 with a planarized Group III arsenide material having been formed above the topmost surface of the dielectric layer, in accordance with one or more aspects of the present application.
FIG. 5 depicts the structure of FIG. 4 after further planarizing the planarized Group III arsenide material to form coplanar topmost surfaces of a remaining portion of the Group III arsenide material and the dielectric layer, in accordance with one or more aspects of the present application.
FIG. 6 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates the rate of removal of the Group III arsenide material as a function of concentration of the oxidizer, in accordance with one or more aspects of the present application.
FIG. 7 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates a comparison between the rate of removal of the Group III arsenide material and the abrasive particle utilized in the slurry compositions, in accordance with one or more aspects of the present application.
FIG. 8 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates the rate of removal of the dielectric material at various locations across a diameter of the wafer at various applied pressure, in accordance with one or more aspects of the present application.
FIG. 9 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates the rate of removal of the Group III arsenide material and uniformity of the Group III arsenide material across the wafer, in accordance with one or more aspects of the present application.
FIG. 10 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates the RMS roughness of the Group III arsenide material prior to, and subsequent to the planarization processes mentioned herein, in accordance with one or more aspects of the present application.
FIG. 11 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates the thickness of the dielectric layer prior to, and subsequent to the planarization processes mentioned herein, in accordance with one or more aspects of the present application.
FIG. 12 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates that polystyrene sulfonate reduces the rate of removal of the dielectric material, in accordance with one or more aspects of the present application.
FIG. 13 depicts a representative example of the first and the second slurry compositions utilized in the forming of the coplanar surfaces of the Group III arsenide material and the dielectric layer, and illustrates that poly(acrylic acid) reduces the rate of removal of the dielectric material, in accordance with one or more aspects of the present application.
FIG. 14 depicts an alternative embodiment of the structure of FIG. 5 with the Group III arsenide material having been partially etched to forming one or more trenches, in accordance with one or more aspects of the present application.
FIG. 15 depicts the structure of FIG. 14 after epitaxially growing an additional semiconductor material within the one or more trenches which, for instance, extends above the topmost surface of the dielectric layer, in accordance with one or more aspects of the present application.
FIG. 16 depicts the structure of FIG. 15 with a planarized additional semiconductor material having been formed above the topmost surface of the dielectric layer, in accordance with one or more aspects of the present application.
FIG. 17 depicts the structure of FIG. 16 after planarizing the additional semiconductor material to form coplanar topmost surfaces of the additional semiconductor material and the dielectric layer, in accordance with one or more aspects of the present application.
FIG. 18 is a cross-sectional view of a process of a structure that includes a Group III arsenide stack bonded to a substrate stack and planarizing the Group III arsenide stack to expose a surface of the Group III arsenide material that is opposite to the substrate stack, in accordance with one or more aspects of the present application.
FIG. 19 depicts an alternative embodiment of the structure of FIG. 5, and includes coplanar surfaces of the Group III arsenide material and a dielectric stack structure disposed over the substrate, in accordance with one or more aspects of the present application.
FIG. 20 depicts an alternative embodiment of the structure of FIG. 19, and includes coplanar surfaces of additional semiconductor material and a dielectric stack structure disposed over the substrate, in accordance with one or more aspects of the present application.
FIG. 21 depicts an alternative embodiment of the structure of FIG. 20, and includes coplanar surfaces of the Group III arsenide material and a dielectric stack structure having one or more sacrificial semiconductor layer(s) disposed over the substrate, in accordance with one or more aspects of the present application.
FIG. 22 depicts an alternative embodiment of the structure of FIG. 5, and includes coplanar surfaces of the Group III arsenide material disposed over a buried template layer, and the dielectric layer, in accordance with one or more aspects of the present application.



DETAILED DESCRIPTION
Aspects of the present application and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the application in details. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Furthermore, reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
Integration of different semiconductor materials having different lattice constants is one challenging aspect of forming high performance devices of future technology nodes. Aspect ratio trapping (ART) is one way to overcome the lattice mismatch which, for instance, includes trapping threading dislocations of a semiconductor material such as, for example, a Group III arsenide material, along the sidewalls of a dielectric layer disposed over a semiconductor substrate. In conventional ART processing, the aspect ratio trapping typically includes forming one or more openings, i.e., trenches, having an aspect ratio (opening depth to opening width) of 1:2 within the dielectric layer. A semiconductor material having a different lattice constant than the underlying semiconductor substrate is epitaxially grown from an exposed surface of the semiconductor substrate within the openings of the dielectric layer, and along the sidewalls of the dielectric layer. This, for instance, results in varying defect density regions of the semiconductor material being located within the openings. For example, a lower portion of the semiconductor material within the opening may have a first defect density, while an upper portion of the semiconductor material may have a second defect density that is less than the first defect density. The upper portion of the semiconductor material may extend above a topmost surface of the dielectric layer. The present application provides an enhanced method for CMP processing of the semiconductor material that is formed above the topmost surface of the dielectric layer.
In one embodiment of the present application, a process for facilitating chemical mechanical planarization of a Group III arsenide material is provided. The process includes first providing a dielectric layer having one or more openings formed therein and located on a substrate. Next, a Group III arsenide material is epitaxially grown within the one or more openings of the dielectric layer disposed over a substrate. The Group III arsenide material includes a portion that extends above the dielectric layer; the portion of the Group III arsenide material that extends above the dielectric layer can be referred to herein as an overburden portion. Planarization of the Group III arsenide material is then performed using a slurry composition that includes an abrasive, at least one pH modulator having an acidic pH modulator, but lacking a basic pH modulator, and an oxidizer. The planarization process results in forming a remaining portion of the Group III arsenide material that has a topmost surface that is coplanar with a topmost surface of the dielectric layer. The planarization process of the present application further includes planarizing the Group III arsenide material, prior to the planarizing with the slurry composition, with an additional slurry composition leaving a planarized Group III arsenide material extended above the dielectric layer. In some embodiments, a final surface cleaning may be employed to remove remaining first and the second slurry particles and rinse off other chemicals.
By way of example, FIGS. 1-5 depict one embodiment of a method and one or more slurry composition(s) to planarize the Group III arsenide material that extends above the topmost surface of the dielectric layer, and to form a remaining Group III arsenide material in which the topmost surface thereof is coplanar surface with a topmost surface of the dielectric layer, in accordance with one or more aspects of the present application.
Referring first to FIG. 1, there is illustrated a structure 200 that includes a dielectric layer 204 disposed over a substrate 202. The structure 200 may include a dielectric layer 204 disposed over, and located on, a substrate. As depicted, substrate 202 may be (in one example) a bulk semiconductor material such as, a bulk silicon wafer, having a first lattice constant. By way of example, the substrate may include a single crystalline silicon material with any suitable crystallographic orientation. For instance, the crystallographic orientation of the silicon substrate may be {100}, {110} or {111} orientations. In another example, the substrate 202 may be any silicon-containing substrate including, but not limited to, silicon (Si), polycrystalline Si, amorphous Si or the like. Although not depicted in the figures, substrate 202 may further include a layered semiconductor structure such as, for example, silicon-on-nothing (SON), silicon-on-insulator (SOI), silicon germanium-on-insulator (SiGeOI), Group III arsenide-on-insulator (GOI), silicon-on replacement insulator (SRI) or the like. Substrate 202 may in addition or instead include various isolation structures or regions, nanowire structures, dopant regions and/or device features.
The dielectric layer 204, which has been disposed over the substrate 202, may be, or include, a dielectric material such as, an oxide material, (e.g., silicon dioxide, tetraethyl orthosilicate (TEOS), a high density plasma (HDP) oxide, a low temperature oxide, a high aspect ratio process (HARP) oxide or the like), a nitride material (e.g., silicon nitride (SiN)) or oxynitride material (e.g., silicon oxynitride (SiOxNy)). The dielectric layer 204 may be deposited using conventional deposition processes such as, for instance, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD) or rapid thermal chemical vapor deposition (RTCVD). In one example, the dielectric layer 204 may have thickness within a range from 100 nm to 500 nm. Other thickness that are lesser than, or greater than, the aforementioned thickness range may also be employed in the present application as the thickness of the dielectric layer 204.
One or more patterning processes may be performed to form one or more openings 206 within the dielectric layer 204, as depicted in FIG. 2. As illustrated, the openings 206 extend down from a topmost surface of the dielectric layer 204 exposing a portion of the underlying substrate 202. Although not depicted in the drawings for ease of understanding, in one embodiment, the openings 206 may extend below a surface of the substrate 202 creating a trench within the substrate 202.
In one embodiment, the patterning process used to define each opening 206 may include lithography and etching. Lithography includes forming a photoresist material (not shown) atop a material or material stack to be patterned. The photoresist material may include a positive-tone photoresist composition, a negative-tone photoresist composition or a hybrid-tone photoresist composition. The photoresist material may be formed by a deposition process such as, for example, spin-on coating. After forming the photoresist material, the deposited photoresist material is subjected to a pattern of irradiation. Next, the exposed photoresist material is developed utilizing a conventional resist developer. This provides a patterned photoresist atop a portion of the material or material stack to be patterned. The pattern provided by the patterned photoresist material is thereafter transferred into the underlying material layer or material layers utilizing at least one pattern transfer etching process. Typically, the at least one pattern transfer etching process is an anisotropic etch. In one embodiment, a dry etching process such as, for example, reactive ion etching can be used. In another embodiment, a chemical etchant can be used. In still a further embodiment, a combination of dry etching and wet etching can be used. After etching, the patterned photoresist can be removed utilizing any photoresist stripping process such as, for example, ashing.
In another embodiment, the patterning process used to define each opening 206 may include a sidewall image transfer (SIT) process. In yet another embodiment, the patterning process used to define each opening 206 may include a direct self-assembly (DSA) patterning process.
In an alternative embodiment of the present application, the exemplary semiconductor structure shown in FIG. 2 can be formed by first providing a plurality of semiconductor fins (not shown) extending upwards from a semiconductor substrate utilizing one of the above mentioned patterning processes. Next, a dielectric material that provides the dielectric layer 204 is formed between each semiconductor fin and thereafter a planarization process such as, for example, chemical mechanical polishing (CMP) may be employed. Each semiconductor fin is then removed utilizing an etch to form the openings 204. The etch may include hydrochloric (HCl) gas. As trench, as mentioned above may be formed within the substrate 202 utilizing an etch.
Referring now to FIG. 3, there is illustrated the structure of FIG. 2 after epitaxially growing a Group III arsenide material 208 in each of the opening(s) 206 of the dielectric layer 204. In one embodiment, the Group III arsenide material 208 can be epitaxially grown from an exposed portion of substrate 202 within the opening(s) 206 using any suitable epitaxial deposition process such as, for instance, atmospheric pressure CVD (APCVD), low-(or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHCVD), by molecular beam epitaxy (MBE), metal-organic CVD (MOCVD) or by atomic layer deposition (ALD). For instance, the Group III arsenide material 208 may be epitaxially grown using metalorganic CVD (MOCVD) process, for instance, by introducing an gallium-containing precursor, such as, for instance, an organogallium compound (e.g., trimethyl gallium, triethyl gallium and/or tributyl gallium), and an arsenide precursor such as, for instance, arsine (AsH3), into a reaction chamber of an MOCVD apparatus. The epitaxial growth process of the Group III arsenide material 208 proceeds upwards from the exposed surface of substrate 202 and extends above the topmost surface of the dielectric layer 204. As used herein, “epitaxially growing/growth” refers to the orderly growth of the Group III arsenide material over the exposed portion of the substrate 202, where the grown material arranges itself in the same crystal orientation as the underlying semiconductor material. The Group III arsenide material 208 that is formed has a lattice constant that is greater than the lattice constant of the substrate 202. The Group III arsenide material 208 that is formed thus has a varying defect density within the openings 206. For instance, the epitaxial growth process provides an Group III arsenide material 208 that contains a lower portion 208a having a first defect density, and an upper portion 208b having a second defect density, wherein the second defect density is less than the first defect density. In some embodiments of the present application, threading dislocations within the lower portion 208a of the Group III arsenide material 208 are trapped along the sidewalls of the dielectric layer 204 in a lower portion of the openings 206. The epitaxial growth process further proceeds to form an overburden portion 208c that extends above the topmost surface of the dielectric layer 204. The defect density within the overburden 208c can be the same as, or less than, the second defect density. The thickness of the overburden region 208c may be sufficient to allow subsequent planarization of the structure and, in one example, may be within a range from 100 nm to 5 μm.
One or more chemical mechanical planarization processes may be employed to planarize the overburden portion 208c of the Group III arsenide material 208 that extends above the topmost surface of the dielectric layer 204. By way of example, the CMP processing may be performed using, for instance, one or more slurry compositions, each slurry composition having a different removal rate selectivity towards the Group III arsenide material 208 and the dielectric layer 204. As used herein, the first slurry composition refers to the additional slurry composition, and the second slurry composition refers to the slurry composition mentioned herein. In some embodiments, the CMP processing of the present application facilitates selectively planarizing the overburden portion 208c of the Group III arsenide material 208, without affecting the remaining upper and lower portions of the Group III arsenide material 208 located within the openings 206. Further, the overburden portion 208c of the Group III arsenide material 208 may have an extremely rough surface, necessitating the first slurry composition to have an enhanced Group III arsenide removal rate so as to reduce the overburden of the Group III arsenide material 208 and planarize the initial topography, leaving, at least in part, a planarized Group III arsenide material 208′ extending above the topmost surface of the dielectric layer 204, as depicted in FIG. 4. In one embodiment, the enhanced Group III arsenide removal rate of the first slurry composition may be within a range of 3000 Å/min to 5000 Å/min. In one embodiment, and since the first slurry composition only reduces the overburden and planarizes the initial topography, without exposing the underlying dielectric layer 204, a removal rate selectivity of the slurry composition towards the Group III arsenide material 208 and the dielectric layer 204 may not be critical. In one example, a first slurry composition may be employed that is composed of, or includes, an abrasive material, one or more pH modulators, and an oxidizer. Such a first slurry composition, can be employed, in some embodiments, to form a planarized Group III arsenide material 208′ having a thickness from about 1000 Å to 2500 Å. In one embodiment, the oxidizer utilized in the first slurry composition may facilitate suppressing the generation of arsine gas during the planarization processes described herein, thereby enhancing the rate of removal of Group III arsenide extended above the dielectric layer 204. For instance, the oxidizers described herein react with the toxic arsine gas to form soluble salts. The oxidizer may also increase the rate of removal of the Group III arsenide material.
By way of example, the abrasive particles of the first slurry composition may include one or more inorganic particles and/or organic particles. In one embodiment, each abrasive particle may have an average particle diameter of from 5 nm to 500 nm, while in another embodiment, each abrasive particle may have an average particle diameter of from 10 nm to 200 nm, and the average particle diameter is determined by conventional laser light scattering techniques. The abrasive particles, in one embodiment, may be present in the first slurry composition in an amount in the range of 0.5 to 30 percent by weight. In another embodiment, the abrasive particles may be present in the first slurry composition in an amount from 0.1 to 10 percent by weight. In one embodiment, the inorganic particles may include, for instance, silica, alumina, titania, zirconia, ceria, and the like. Examples of the silica include, but are not limited to, fumed silica, silica synthesized by a sol-gel method, colloidal silica, or the like. In one example, the fumed silica may be obtained by reacting silicon chloride or the like, with oxygen and water in an aqueous phase. In another example, the silica synthesized by a sol-gel method may be obtained by hydrolysis and/or condensation of an alkoxysilicon compound which may be used as a raw material. In yet another example, the colloidal silica may be obtained utilizing a conventional inorganic colloid method. In another embodiment, the organic particles may include, but are not limited to, polyvinyl chloride, a styrene (co)polymer, polyacetal, polyester, polyamide, polycarbonate, an olefin (co)polymer, a phenoxy resin, an acrylic (co)polymer, or the like. In one example, the olefin (co)polymer may include, for instance, polyethylene, polypropylene, poly-1-butene, poly-4-methyl-1-pentene, and the like. Examples of the acrylic (co)polymer include polymethyl methacrylate or the like. By way of example, the abrasive particles used in the first slurry composition can be selected, but are not limited to, the examples of abrasive particles provided in Table 1:










TABLE 1










Particle size (DLS diameter)












Silica


Association



Abrasive *
Primary
Secondary
Number







SCM-030B
46.3 nm
74.7 nm
1.61



532-X02
31.5 nm
57.0 nm
1.81



SCM-020B
15.4 nm
42.1 nm
2.73



SCM-070B
46.3 nm
74.7 nm
1.61



532-X04
46.4 nm
54.5 nm
1.17



532-X05
31.6 nm
37.7 nm
1.19



S32-X08
31.1 nm
109.9 nm 
3.53



S32-X09
30.5 nm
64.0 nm
2.10



S32-X10
37.4 nm
82.1 nm
2.20



S32-X11
90.0 nm
218.0 nm 
2.42



S32-X12
13.3 nm
54.5 nm
4.10



S32-X13
14.0 nm
17.7 nm
1.26



S32-X16
N/A
N/A
N/A



S32-X17
57.5 nm
63.3 nm
1.10



S32-X18
N/A
  80 nm
N/A



S32-X19
N/A
N/A
N/A



S32-X20
N/A
N/A
N/A



S32-X103
  12 nm
  20 nm
1.66



S32-X104
  22 nm
  35 nm
1.59



S32-X105
  45 nm
  80 nm
1.78



S32-X106
13.3 nm
54.5 nm
4.10







*All the abrasive particles listed in Table 1 are supplied by JSR Corporation.






Continuing further with FIG. 4, the first slurry composition may include, in one embodiment, one or more acidic pH modulators, and one or more basic pH modulators, which may modulate the pH of the first slurry composition to be in a range from 1 to 13, or in a range from 3 to 11. In these embodiments, the acidic pH modulators of the first slurry composition may include an inorganic acid, while the basic pH modulators of the first slurry composition may include at least one of an organic base and an inorganic base. In one example, the organic base may include, but is not limited to, tetramethylammonium hydroxide, triethylamine, N-methylethanolamine, methylamine, triethanolamine or the like. In another example, the inorganic base may include, but is not limited to, ammonium hydroxide, potassium hydroxide, sodium hydroxide, or the like. In one embodiment of the present application, the inorganic base present in the first slurry composition is within a range of 0.0001 to 0.1 percent by weight. In yet another example, the inorganic acid may include, but is not limited to, nitric acid, sulfuric acid, phosphoric acid or the like. In one embodiment of the present application, the inorganic acid present in the first slurry composition is within a range of 0.0001 to 0.1 percent by weight.
The oxidizer that is present in the first slurry composition may, in some embodiments, facilitate the suppression of the generation of arsine gas during the planarization processes described herein. Additionally, the oxidizer may enhance the rate of removal of Group III arsenide extended above the dielectric layer 204, i.e., the overburden portion 208c. For instance, the oxidizers described herein react with the toxic arsine gas to form soluble salts which may help the suppression of the arsine gas. In one example, the oxidizer includes, but is not limited to, ceric ammonium nitrate, ferric nitrate, sodium persulfate, potassium persulfate, hydrogen peroxide, and potassium permanganate or the like. By way of an example, the oxidizer present in the first slurry composition may be within the range of 0.5 to 200 mL/L, or within a range of 1 to 100 mL/L.
Still further, the first slurry composition may include one or more of the following optional components: surfactants, additives, dispersants, polyelectrolytes, soluble polymers and molecules that adsorb on to the surface of the dielectric layers and reduce the removal rate. In addition, they may adsorb onto the colloidal abrasive surface and may improve colloidal stability and may enhance shelf life of the first slurry composition. Additionally, the surfactants may also facilitate removal of the abrasive particles from the wafer surface during the CMP processing. In one example, the surfactant is an anionic surfactant which may include, but is not limited to, a surfactant containing at least one functional group selected from a carboxyl group (—COOX), a sulfonic acid group (—SO3X), and a phosphate group (—HPO4X) (wherein X represents hydrogen, ammonium, or a metal). In another example, the anionic surfactant may include, but is not limited to, aliphatic and aromatic sulfates and sulfonates, and a phosphate salt, or the like. Still further, the anionic surfactants may also include compounds such as, for instance, potassium dodecylbenzenesulfonate, ammonium dodecylbenzenesulfonate, sodium alkylnaphthalenesulphonate, alkyl sulfosuccinate, potassium alkenylsuccinate, or the like, as well as aliphatic soaps like potassium oleate or the like. These anionic surfactants may be used either individually or in combination. In another aspect, the surfactant is a nonionic surfactant which may include, but is limited to, a polyoxyethylene alkyl ether, an ethylene oxide-propylene oxide block copolymer, acetylene glycol, an ethylene oxide addition product of acetylene glycol, an acetylene alcohol, or the like. In another example, a nonionic polymer compound such as polyvinyl alcohol, cyclodextrin, polyvinyl methyl ether, or hydroxyethylcellulose may also be used as the nonionic surfactant. In another embodiment, the surfactant is a cationic surfactant which may include, but is not limited to, an aliphatic amine salts, aliphatic ammonium salts, or the like. In addition, polyelectrolytes, such as, for instance, poly (acrylic acid) and their salts such as sodium, potassium and ammonium, polystyrene sulfonate, carboxymethyl cellulose, polyvinyl pyrrolidone and polyacrylamides can also be added during the polishing to control the selectivity. Other additives such as nitrogen compounds including triazoles, imines, amides and imides can also be used. In a specific example, the additives may include, but are not limited to, benzotriazole, aminotriazole, guanidine hydrochloride, urea derivatives and thioureas.
By way of example, a general formulation of the first slurry composition having a pH within a range of 1 to 12, or within a range of 2 to 6, may include:

    
    
        a) Abrasive particle, such as, silica in the range of 0.5 to 30 percent by weight, or within a range of 1 to 10 percent by weight;
        b) An acidic pH modulator within the range of 0.0001 to 0.1 percent by weight;
        c) A basic pH modulator within the range of 0.0001 to 0.1 percent by weight;
        d) An oxidizer, such as, 30% solution of hydrogen peroxide within the range of 0.5 to 200 mL/L, or within the range of 1 to 100 mL/L.
    
    


The following examples of the first slurry composition are provided to, and should not be construed as in any way limiting the scope of the application. The first slurry composition may be prepared by admixing various components, for example, abrasive particle, pH modulators, oxidizers, surfactants, additives, etc.
Example 1
The first slurry composition having a pH within a range of 2 to 6 was prepared and included:

    
    
        a) abrasive particle such as, 5% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator containing an inorganic acid, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight;
        c) a basic pH modulator containing an inorganic base, such as, for instance, potassium hydroxide within a range of 0.0005 to 0.002% by weight; and
        d) an oxidizer, such as, for instance, 30% solution of hydrogen peroxide of 10 to 100 mL/L, and more preferably, 10 mL/L.
    
    


Example 2
The first slurry composition having a pH within a range of 2 to 6 was prepared and included:

    
    
        a) abrasive particle such as, 1% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator containing an inorganic acid, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight;
        c) a basic pH modulator containing an inorganic base, such as, for instance, potassium hydroxide within a range of 0.0005 to 0.002% by weight; and
        d) an oxidizer, such as, for instance, 30% solution of hydrogen of 1 mL/L.
    
    


Example 3
The first slurry composition having a pH within a range of 2 to 6 was prepared and included:

    
    
        a) abrasive particle such as, 5% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator containing an inorganic acid, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight;
        c) a basic pH modulator containing an inorganic base, such as, for instance, potassium hydroxide within a range of 0.0005 to 0.002% by weight; and
        d) an oxidizer, such as, for instance, 30% solution of hydrogen peroxide within a range of 10 to 100 mL/L, and more preferably, 5 mL/L.
    
    


Example 4
The first slurry composition having a pH within a range of 3 to 11 was prepared and included:

    
    
        a) abrasive particle such as, 5% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator containing an inorganic acid, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight;
        c) a basic pH modulator containing an inorganic base, such as, for instance, potassium hydroxide within a range of 0.0005 to 0.002% by weight; and
        d) an oxidizer, such as, for instance, 30% solution of hydrogen peroxide within a range of 10 to 100 mL/L, and more preferably, from 1 to 10 mL/L.
    
    


One or more chemical planarization steps may be extended using a second slurry composition to polish the remaining planarized Group III arsenide material 208′ that extends above the topmost surface of the dielectric layer 204, using (in one embodiment) the topmost surface of dielectric layer 204, as a polish stop. The result is that topmost surface 212 of a remaining portion of the Group III arsenide material 208 is coplanar with the topmost surface 214 of the dielectric layer 204, although height differences may exist locally, as depicted in FIG. 5. The second slurry composition may include an abrasive particle, one or more pH modulators lacking a basic pH modulator, and an oxidizer. In one embodiment, the second slurry composition has a high Group III arsenide removal rate and a low dielectric material removal rate which may facilitate planarizing and/or polishing the planarized Group III arsenide material 208′ selective to the dielectric layer 204. In one example, the second slurry composition may have a Group III arsenide removal rate of 500 Å/min to 1000 Å/min and a dielectric material removal rate of 10 Å/min to 50 Å/min. In some embodiments, this may prevent any significant erosion of the dielectric layer 204 and may enable complete removal of any residual Group III arsenide extended above the topmost surface 214 of the dielectric layer 204. The first and the second slurry compositions are employed sequentially to form the coplanar surfaces of the dielectric layer 204 and the remaining portion of the Group III arsenide material 208. The second slurry composition has a rate of removal of the dielectric materials (for instance, that provide the dielectric layer 204) lower than the rate of removal of the Group III arsenide material. In one embodiment, the second slurry composition may be polish-resistant to at least one dielectric material that provides the dielectric layer. As used herein, “polish-resistant” refers to the one or more dielectric materials, such as, oxide and/or nitride materials, that provide the dielectric layer being resistant to polishing and/or planarization processes described herein using the second slurry composition. In some embodiments, and when an initial topography of the overburden portion 208c of the Group III arsenide material is relatively small (for instance, within a range of about 1000 Å-1500 Å), the CMP processing may be accomplished using only the second slurry composition, thereby eliminating an additional CMP processing step using the first slurry composition. As depicted, the root mean square (RMS) roughness of the remaining Group III arsenide material 208, having a coplanar topmost surface with the dielectric layer 204, upon CMP processing may be, in one embodiment, less than 0.5 nm. The remaining portion of the Group III arsenide material 208 has the upper portion of the second defect density and the lower portion of the first defect density; the overburden portion 208c has been removed. At this stage of the present application, and in some embodiments, the dielectric layer 204 may be partially recessed to expose an upper portion of the Group III arsenide material and a semiconductor device, such as, a field effect transistor can be formed on the exposed upper portion of the Group III arsenide material 208. In some embodiments, a semiconductor device may be formed directly upon the topmost surface of the remaining portion of the Group III arsenide material as shown in FIG. 5.
In one embodiment, the CMP processing described herein with the first slurry composition and the second slurry composition may be accomplished using the same polishing pad. The first slurry composition and the second slurry composition can be sequentially utilized to form coplanar surfaces of the Group III arsenide material and the dielectric layer, and can be applied between the polishing pad and the structure. Still further, although not depicted in the drawings, a final surface cleaning process is performed to remove any of the remaining first and the second slurry compositions and rinse off other chemicals, resulting in the resultant semiconductor structure.
By way of example, the abrasive particles of the second slurry composition may include, for instance, one or more inorganic particles and/or organic particles which, for instance, may have a particle diameter that is equal to the particle diameter of the abrasive particle used in the first slurry composition, and may be selected from any of the abrasive particles employed in the first slurry composition, described above in connection with FIG. 4. In one embodiment, the abrasive particles of the second slurry composition may be different from the abrasive particle of the first slurry composition, while the chemistry of the first slurry composition and the second slurry composition may remain the same. In another embodiment, the abrasive particles of the second slurry composition may be the same as the abrasive particles of the first slurry composition, but the concentration of the abrasive particle of the second slurry composition may be different from the concentration of the abrasive particles of the first slurry composition. In yet another embodiment, the abrasive particles and the chemistry of the first slurry composition and the second slurry composition may be entirely different.
In one implementation, the pH modulator of the second slurry composition which, for instance, includes an acidic pH modulator, but lacks a basic pH modulator, may modulate the pH of the second slurry composition to be 3 to 11. In one example, the pH modulator of the second slurry composition may be selected from any of the inorganic acids utilized for the first slurry composition, as described above in connection with FIG. 4. For instance, the inorganic acid may include, but is not limited to, nitric acid, sulfuric acid, phosphoric acid or the like. In one embodiment, the inorganic acid present in the second slurry composition is within a range of 0.0001 to 0.1 percent by weight. In another implementation, the oxidizer of the second slurry composition may be selected from any of the oxidizer materials of the first slurry composition, described above in connection with FIG. 4. As described above, the oxidizer present in the second slurry composition may facilitate the suppression of the generation of arsine gas during the planarization processes described herein. It may also enhance the rate of removal of Group III arsenide extended above the dielectric layer 204. For instance, the oxidizers described herein react with the toxic arsine gas to form soluble salts. Additionally, the second slurry composition may also include surfactants, additives, dispersants, polyelectrolytes, soluble polymers and molecules that adsorb on to the surface of the dielectric layers and reduce the removal rates. In addition they may improve colloidal stability and may enhance the shelf life of the second slurry composition as well. These materials of the second slurry composition may be similar or same as the materials utilized for first slurry composition, described above in connection with FIG. 4.
By way of example, a general formulation of the second slurry composition having a pH within a range of 3 to 11, may, in one embodiment, include:

    
    
        a) Abrasive particle, such as, silica in the range of 0.5 to 30 percent by weight, or within a range of 0.5 to 10 percent by weight;
        b) An acidic pH modulator within the range of 0.0001 to 0.1 percent by weight;
        c) An oxidizer, such as, 30% solution of hydrogen peroxide within the range of 0.5 to 200 mL/L, or within the range of 1 to 100 mL/L.
    
    


The following examples of the second slurry composition are provided to further describe the invention, and should not be construed as in any way limiting the scope of the invention. The second slurry composition may be prepared by admixing various components, for example, abrasive particles, pH modulators, oxidizers, surfactants, additives, etc.
Example 1
The second slurry composition having a pH within a range of 3 to 5 was prepared and included:

    
    
        a) abrasive particle such as, 2% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight; and
        c) an oxidizer, such as, for instance, 30% solution of hydrogen peroxide from 10 to 100 mL, and more preferably, 2 mL/L.
    
    


Example 2
The second slurry composition having a pH within a range of 3 to 5 was prepared and included:

    
    
        a) abrasive particle such as, 5% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight; and
        c) an oxidizer, such as, for instance, 30% solution of hydrogen peroxide of 5 mL/L.
    
    


Example 3
The second slurry composition having a pH within a range of 3 to 5 was prepared and included:

    
    
        a) abrasive particle such as, 1% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight; and
        c) an oxidizer, such as, for instance, 30% solution of hydrogen peroxide within a range of 10 to 100 mL/L, and more preferably, 1 mL/L; and
        d) a polyelectrolyte, such as, for instance, polystyrene sulfonate (having a molecular weight of 10,000 to 400,000) within a range of 0.01 to 0.1 percent by weight, and more preferably, 0.002 to 0.003 percent by weight.
    
    


Example 4
The second slurry composition having a pH within a range of 3 to 5 was prepared and included:

    
    
        a) abrasive particle such as, 1% by weight of colloidal silica abrasive dispersed in water;
        b) an acidic pH modulator, such as, for instance, phosphoric acid within a range of 0.0004 to 0.0006% by weight;
        c) an oxidizer, such as, for instance, 30% solution of hydrogen peroxide within a range of 10 to 100 mL/L, and more preferably, 50 mL/L; and
        d) a polyelectrolyte, such as, for instance, poly(acrylic acid) (having a molecular weight of 400,000) within a range of 0.01 to 0.1 percent by weight.
    
    


By way of further clarification, FIGS. 6-13 illustrate representative examples of experimental data of the first and the second slurry compositions described herein to form coplanar surfaces of the Group III arsenide material and the dielectric layer, in accordance with one or more aspects of the present application. The following representative examples of the experimental data of the first and the second slurry compositions should not be construed as in any way limiting the scope of the present application.
Notably, FIG. 6 depicts a representative example of the rate of removal of the Group III arsenide material as a function of concentration of the oxidizer, in accordance with one or more aspects of the present application. As evident from FIG. 6, the rate of removal of Group III arsenide increases with an increase in the concentration of the oxidizer, such as, hydrogen peroxide, and in the depicted example, the enhanced rate of removal of Group III arsenide material are achieved by an abrasive particle, such as, S32-X08 (as supplied by JSR Corporation) at pH 4. In one implementation, FIG. 7 illustrates a comparison between the rate of removal of Group III arsenide material and the abrasive particle utilized in the first and the second slurry compositions described herein. As depicted, the enhanced rate of removal of Group III arsenide material is achieved by abrasive particle, such as, SCM-70B, relative to abrasive particle, for example, S32-X08 (as supplied by JSR Corporation) at pH 8.5.
By way of further explanation, FIG. 8 illustrates the rate of removal of dielectric material, such as, for instance, oxide material and uniformity of the dielectric layer across the wafer (for example, having a diameter of 200 mm) at various applied pressure, and as depicted, the rate of removal of the dielectric material is uniformly low resulting in coplanar surfaces of the dielectric layer and the Group III arsenide material. FIG. 9 illustrates the rate of removal of the Group III arsenide material and uniformity of the Group III arsenide material across the wafer (for example, having a diameter of 200 mm), and as depicted, the rate of removal of the Group III arsenide material is uniformly high resulting in coplanar surfaces of the dielectric layer and the Group III arsenide material. Still further, FIG. 10 depicts comparative examples of RMS roughness of the Group III arsenide material prior to, and subsequent to, the planarization processes mentioned herein at pH values of 4 and 7, respectively, and as depicted, the root mean square (RMS) roughness of the remaining Group III arsenide material, upon CMP processing, is 0.24 nm and 0.22 nm, respectively. In another example, FIG. 11 illustrates the thickness of the dielectric layer prior to and subsequent to the chemical mechanical planarization processes described herein, and as depicted, no loss of the dielectric material, such as, for instance, oxide material is observed. Still further, FIGS. 12 and 13 illustrate comparative examples of a relation between the rate of removal of the dielectric material and the concentration of water soluble polymers, such as, polyelectrolytes (for instance, polystyrene sulfonate (see FIG. 12), and poly(acrylic acid) (see FIG. 13)), and as evident, illustrates that the polystyrene sulfonate and poly(acrylic acid) reduces the rate of removal of the dielectric layer having, for instance, nitride material and, for instance, may serve to act as stop layers.
Referring now to FIG. 14, there is illustrated an alternative embodiment of the structure of FIG. 6 with the Group III arsenide material 208 having been partially etched to form one or more trenches 216 within the dielectric layer 204, in accordance with one or more aspects of the present application. The Group III arsenide material may be partially etched using any conventional anisotropic dry etching process, such as, a reactive ion etch, or conventional isotropic etching process, such as, a wet etch. In one example, the Group III arsenide material 208 may be recessed to a depth of 100 nm to 200 nm. As depicted, the Group III arsenide material being etched includes the upper portion 208b of the second defect density disposed above the lower portion 208a of the first defect density, without affecting the underlying the lower portion 208a. 
Referring now to FIG. 15, there is illustrated the structure of FIG. 14 after epitaxially growing an additional semiconductor material 218 within the one or more trenches 216 which extends above the topmost surface of the dielectric layer 204. The additional semiconductor material 218 may include, or be fabricated of, a semiconductor material, such as, silicon germanium material, or a III-V compound semiconductor material other than Group III arsenide material, such as, InSb, GaP, GaN, GaSb, etc., having a lattice constant that is substantially similar to the lattice constant of the lower portion 208b of the Group III arsenide material. The additional semiconductor material 218 may be formed by an epitaxial growth process such as described herein in the forming of the Group III arsenide material 208. In one example, the additional semiconductor material, such as, silicon germanium material, may be epitaxially grown using a silicon source gas, such as, for instance, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexmethyldisilane, and combinations thereof, and the germanium source gas, such as, for instance, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. As described above, the additional semiconductor material 218 may have substantially similar crystalline characteristics as the Group III arsenide material 208 disposed within the openings 206. In one embodiment, the thickness of the additional semiconductor material 218 extended above the topmost surface of the dielectric layer 204 may be sufficient to allow subsequent planarization of the structure. The additional semiconductor material 218 may be used to form the channel regions of III-V compound semiconductor material transistor devices such as, planar CMOS Field Effect Transistor (FETs) or non-planar FinFET devices to be formed, during subsequent fabrication processing.
One or more chemical mechanical planarization steps may be employed to planarize the additional semiconductor material 218 extended above the topmost surface of the dielectric layer 204, while the Group III arsenide material 208 disposed within the openings 206 remains unaffected. The CMP processing may be performed using, for instance, the first and the second slurry compositions described above in connection with FIGS. 4 and 5. For instance, the additional semiconductor material 218 that extends above the topmost surface of the dielectric layer 204, owing to the epitaxial growth process, may have an extremely rough surface which may be planarized using the first slurry composition so as to reduce the overburden and to planarize the initial topography, leaving a planarized additional semiconductor material 218′ extended above the topmost surface of the dielectric layer 204, as depicted in FIG. 16. Further, since the first slurry composition only reduces the overburden and planarizes the initial topography, without exposing the underlying dielectric layer, removal rate selectivity of the slurry composition towards the additional semiconductor material and the dielectric layer may not be critical. As described in previous embodiment, the first slurry composition may include, for instance, an abrasive material, one or more pH modulators having an acidic pH modulator and a basic pH modulator, and an oxidizer.
The abrasive particles of the first slurry composition may include, for instance, one or more inorganic particles and/or organic particles which may have a particle diameter that is equal to the particle diameter of the abrasive particles used in the first slurry composition, and may be selected from any of the abrasive particles employed in the first slurry composition, described above in connection with FIG. 4. In one implementation, the pH modulator of the first slurry composition which, for instance, includes an acidic pH modulator and a basic pH modulator, may modulate the pH of the first slurry composition to be 3 to 11. In one example, the pH modulators of the first slurry composition may be selected from any of the pH modulators utilized for the first slurry composition, as described above in connection with FIG. 4. In one embodiment, the acidic pH modulator and the basic pH modulator present in the first slurry composition may be within a range of 0.0001 to 0.1 percent by weight. In one implementation of the present invention, the oxidizer of the first slurry composition may be selected from any of the oxidizer materials of the first slurry composition, described above in connection with FIG. 4. In one example, the oxidizer present in the first slurry composition may be within the range of 0.5 to 200 mL/L, or within a range of about 10 to 100 mL/L. Additionally, the first slurry composition may also include surfactants, additives, dispersants, polyelectrolytes, soluble polymers and molecules that adsorb on to the surface of the dielectric layers and reduce the removal rates. In addition these molecules may also improve colloidal stability and may enhance the shelf life of the first slurry composition. These materials of the first slurry composition may be similar or same as the materials utilized for first slurry composition, described above in connection with FIG. 4.
One or more chemical mechanical planarization processing may be extended using the second slurry composition of the one or more slurry compositions to polish the remaining planarized additional semiconductor material 218′ extended above the dielectric layer, using the topmost surface of the dielectric layer 204, as a polish stop. The result is that topmost surface 220 of the additional semiconductor material 218 is substantially coplanar with the topmost surface 222 of the dielectric layer 204, as depicted in FIG. 17. As described in the previous embodiment, the second slurry composition may include an abrasive particle, one or more pH modulators lacking a basic pH modulator, and an oxidizer, along with the surfactants, additives, dispersants, polyelectrolytes described herein in the second slurry composition utilized in the planarization of the Group III arsenide material, and the various materials of the second slurry composition may be substantially similar or the same materials of the second slurry composition described above in connection with FIG. 5. Further, as described above in the previous embodiment, the second slurry composition can have a high additional semiconductor material removal rate and a low dielectric removal rate which may facilitate planarizing and/or polishing the planarized additional semiconductor material, selective to the dielectric layer. This may prevent any significant erosion of the dielectric layer and enables complete removal of any residual additional semiconductor material 218 extended above the topmost surface 222 of the dielectric layer 204. Further, although not depicted in the drawings, a final surface cleaning process is performed to remove any of the remaining first and the second slurry compositions and rinse off other chemicals, resulting in the resultant semiconductor structure.
Referring now to FIG. 18, there is illustrated another embodiment of a process that includes a Group III arsenide stack 207 disposed over, and located on a substrate 202. As described in previous embodiments, although not depicted in the drawings, a dielectric layer containing one or more openings within which the Group III arsenide stack 207 is disposed, may also be present above the substrate 202. As illustrated in FIG. 18, the substrate 202 may include, or be fabricated of, one or more intermediate layers, such as, for instance, silicon-containing layer 202a, germanium-containing layer 202b disposed over the silicon-containing layer 202a, a sacrificial Group III-V compound semiconductor layer 202c disposed over the germanium-containing layer 202b, a sacrificial bonding stack 202d disposed over the sacrificial Group III-V compound semiconductor layer 202c, and/or a metamorphic buffer layer 202e disposed over the sacrificial bonding stack 202e. In one embodiment, these layers may be formed using a variety of different materials and techniques, such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD) or the like. The thickness of the layers may also vary, depending upon the particular application. As depicted, a layer of Group III arsenide material 205, (for example, indium aluminum arsenide material), may be epitaxially grown over the substrate 202, and a layer of another Group III arsenide material 208 (for example, indium gallium arsenide (InGaAs)) may be epitaxially grown over the Group III arsenide material 205. The one or more Group III arsenide material layers 205 and 208 define one example of Group III arsenide stack 207. As described in previous embodiments, the portion of the Group III arsenide material 208 that extends above the dielectric layer (if present) can be referred to herein as an overburden portion. The overburden portion of the Group III arsenide material 208, in one embodiment, may be subsequently planarized using the first slurry composition leaving a planarized Group III arsenide material 208, as described above in connection with FIG. 4. For instance, as described in the previous embodiments, the oxidizer present in the first slurry composition described herein may facilitate the suppression of the generation of the toxic arsine gas during the planarization processes described herein. It may also enhance the rate of removal of the Group III arsenide material 205.
Continuing with FIG. 18, the planarized Group III arsenide material 208 may subsequently be bonded to a substrate stack 225 using one or more conventional direct wafer bonding (DWB) processes. In direct wafer bonding, two or more wafers can be fused together via mass transport at the bonding interface, and can be performed between any combination of semiconductor, oxide, and dielectric material. For instance, the planarized Group III arsenide material 208 may be bonded to an insulator layer 224, which, in one example, may be or include, a dielectric material (e.g., an oxide material (SiO2)) by annealing at a high temperature (>400° C.) and under uniaxial pressure. A semiconductor material 226, such as, a silicon-containing substrate material may subsequently be fused to the insulator layer 224, resulting in substrate stack 225. Planarization of the Group III arsenide material is then performed using the second slurry composition mentioned herein, which, in one example, may facilitate polishing the substrate 202, and any undesirable Group III arsenide material 205 of the Group III arsenide stack 207, resulting in exposing a surface 227 that is opposite to the substrate stack 225. As described in the previous embodiments, the oxidizer present in the second slurry composition described herein may facilitate the suppression of the generation of the toxic arsine gas during the planarization processes described herein. It may also enhance the rate of removal of the additional Group III arsenide material 205. The result is that the planarization processes described herein may be utilized to achieve the smooth, low defect density device quality layers of III-V heteroepitaxial semiconductor devices, such as, indium gallium arsenide (InGaAs)-on-insulator substrates. Thus, in some embodiments, the direct wafer bonding described herein may facilitate combining the possibility to co-integrate n-type field effect transistors (NFETs) and p-type field-effect transistors (PFETs) at fin pitch of 50 nm and beyond, and with a minimum height difference between the III-V compound semiconductor materials, and the silicon germanium and/or silicon material using the III-V on insulator approach.
Referring now to FIG. 19, there is illustrated an alternative embodiment of the structure of FIG. 5, and includes coplanar surfaces of Group III arsenide material 208 and a dielectric stack structure 228 disposed over the substrate 202. As illustrated in FIG. 19, the dielectric layer 204 may, in an additional or an alternative embodiment, be disposed with one or more additional dielectric layer(s) 230. In such embodiments, the dielectric layer 204 and the additional dielectric layer(s) 230 together define one example of a dielectric stack structure 228. The additional dielectric layer(s) 230 may be, or include, a dielectric material, such as, for instance, an oxide material (e.g., silicon dioxide, tetraethyl orthosilicate (TEOS), a high density plasma (HDP) oxide, a low temperature oxide, a high aspect ratio process (HARP) oxide or the like), a nitride material (e.g., silicon nitride (SiN)) or oxynitride material (e.g., silicon oxynitride (SiOxNy)) or the like, and may be deposited using any of the conventional deposition techniques described above in connection with the formation of the dielectric layer 204. The materials of the dielectric layer 204 and the additional dielectric layer 230 may be different. For instance, in one embodiment, when the dielectric layer 204 is an oxide material, the additional dielectric layer 230 can be a nitride material or vice versa, which, for instance, results in the additional dielectric layer 230 serving as a polish stop layer, during the subsequent CMP processes. As described in the previous embodiments, the Group III arsenide material 208 may be subsequently planarized using the first and/or the second slurry compositions as described in previous embodiments. As depicted further in FIG. 19, this results in the topmost surface 232 of the Group III arsenide material 208 being substantially coplanar the topmost surface 234 of the additional dielectric layer 230 of the dielectric stack structure 228.
Further, as illustrated in FIG. 20, a portion of the Group III arsenide material 208 may be partially etched to form one or more trenches, as described above in connection with FIG. 14. An additional semiconductor material 218 which, in one example, may include, or be fabricated of a semiconductor material, such as, silicon germanium or a III-V compound semiconductor material, may be epitaxially grown within the trenches, as described above in connection with FIG. 15. As described in previous embodiments of the present application, the additional semiconductor material 218 that extends above the topmost surface of the dielectric stack structure 228, in one embodiment, is subsequently planarized using the first and the second slurry compositions described herein in the present application. The result is that the topmost surface 236 of the additional semiconductor material 218 is coplanar with the topmost surface 238 of the additional dielectric layer 230 of the dielectric stack structure 228.
Further, in an additional or an alternative embodiment, the dielectric stack structure 228 may also include one or more sacrificial semiconductor layer(s) 240, as depicted in FIG. 21. By way of example, the sacrificial semiconductor layer 240 may be, or include a silicon germanium material with multiple layers of varying concentrations. In such an embodiment, the additional dielectric layer 226 may serve as a protective layer so as to protect the various underlying layers of the dielectric stack structure 228. The sacrificial semiconductor layer 240 (if present), and the additional dielectric layer 226 over the sacrificial semiconductor layer 240 may be formed over the dielectric layer 204, resulting in the dielectric stack structure 228. The dielectric stack structure 228 may subsequently be patterned and etched to form one or more opening(s) (not shown) using any conventional lithographic patterning processes, as described above in connection with the formation of the opening(s) 206 in FIG. 2. The Group III arsenide material 208 may be subsequently deposited within the openings, as described in previous embodiments, and planarized using the first and/or the second slurry compositions as described in previous embodiments. As depicted further in FIG. 21, this results in the topmost surface 242 of the Group III arsenide material 208 being substantially coplanar the topmost surface 244 of the additional dielectric layer 226 of the dielectric stack structure 228. As described in the previous embodiments, the one or more slurry compositions, in particular, the second slurry composition described herein has a rate of removal of the additional dielectric material (e.g., oxide and/or nitride materials) that is lower than the rate of removal of the germanium material. In one embodiment, the second slurry composition may be polish-resistant to any of the materials of the additional dielectric layer 226.
Referring now to FIG. 22, there is illustrated an alternative embodiment of the structure of FIG. 5, and includes coplanar surfaces of Group III arsenide material 208 disposed over a buried template layer 246, and the dielectric layer 204, in accordance with one or more aspects of the present application. By way of example, the buried template layer 246, which may be, or include, any suitable III-V template layer, may be epitaxially grown within the openings 206 of the dielectric layer, prior to the epitaxial growth of the Group III arsenide layer 208. The buried template layer 246 may serve to act as a buffer layer and enable a defect-free epitaxial growth of the Group III arsenide material over the exposed portions of the substrate 202. As described above in previous embodiments, the Group III arsenide material 208 extends above the topmost surface of the dielectric layer which, for instance, is subsequently planarized using the first and the second slurry compositions described in the previous embodiments. The result is that the topmost surface 212 of the Group III arsenide material 208 is coplanar with the topmost surface 214 of the dielectric layer 204.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including’), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the present invention for various embodiments with various modifications as are suited to the particular use contemplated.

## Claims

1. A method for chemical mechanical planarization, the method comprising:
forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate;
epitaxially growing a Group III arsenide material within the at least one opening, the Group III arsenide material extended above a topmost surface of the dielectric layer; and
planarizing the Group III arsenide material using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, wherein a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and comprises an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator comprising an acidic pH modulator, but lacks a basic pH modulator, and wherein the oxidizer suppresses generation of an arsine gas.

2. The method of claim 1, wherein the at least one slurry composition comprises an additional slurry composition, and the planarizing comprises planarizing the Group III arsenide material using the additional slurry composition, prior to the planarizing with the slurry composition.

3. The method of claim 2, wherein the additional slurry composition planarizes an initial topography of the Group III arsenide material.

4. The method of claim 2, wherein the additional slurry composition comprises an abrasive, at least one pH modulator and the oxidizer, wherein the at least one pH modulator comprises at least one of an acidic pH modulator and a basic pH modulator.

5. The method of claim 2, wherein the oxidizer of the additional slurry composition suppresses generation of the arsine gas.

6. The method of claim 2, wherein the oxidizer of the additional slurry composition enhances a rate of removal of the Group III arsenide material.

7. The method of claim 2, wherein the Group III arsenide material includes a lower portion having a first defect density, an upper portion having a second defect density that is less than the first defect density and an overburden portion having a defect density that is the same as or less than the second defect density, and wherein the additional slurry composition planarizes the overburden portion selectively without affecting the upper and lower portions of the Group III arsenide material.

8. The method of claim 1, wherein the slurry composition has a rate of removal of the Group III arsenide material greater than a rate of removal of the dielectric layer.

9. The method of claim 1, wherein a root mean square (RMS) roughness of the Group III arsenide material, subsequent to the planarization using the at least one slurry composition, is less than 0.5 nm.

10. The method of claim 1, further comprising etching the Group III arsenide material, subsequent to forming coplanar surfaces of the Group III arsenide material and the dielectric layer, to form a trench within the at least one opening, and epitaxially growing an additional semiconductor material within the cavity, the additional semiconductor material extending above the dielectric layer.

11. The method of claim 10, wherein the additional semiconductor material comprises a semiconductor material having a Group III-V semiconductor material, the additional semiconductor material being different from the Group III arsenide material.

12. The method of claim 10, wherein the planarizing of the additional semiconductor material using the at least one slurry composition forms the coplanar surfaces of the additional semiconductor material and the dielectric layer.

13. The method of claim 1, further comprising a dielectric stack structure disposed over the substrate, the dielectric stack structure comprising the dielectric layer, and at least one layer disposed over the dielectric layer, wherein the at least one layer comprises at least one of an additional dielectric layer and a sacrificial semiconductor material.

14. A method for chemical mechanical planarization, the method comprising:
providing a Group III arsenide stack comprising a Group III arsenide material, located on a substrate;
bonding the Group III arsenide material of the Group III arsenide stack to a substrate stack; and
planarizing the substrate and at least one additional Group III arsenide material of the Group III arsenide stack with a slurry composition to expose a surface of the Group III arsenide material that is opposite to the substrate stack, wherein the slurry composition comprises at least one pH modulator and an oxidizer, with the at least one pH modulator including an acidic pH modulator, but lacking a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.

15. The method of claim 14, wherein the planarizing comprises planarizing the Group III arsenide material of the Group III arsenide material with an additional slurry composition, prior to the bonding to the substrate stack.

16. The method of claim 15, wherein the additional slurry composition has a chemical composition that is different from a chemical composition of the slurry composition.

17. The method of claim 15, wherein the additional slurry composition comprises an abrasive, at least one pH modulator and an oxidizer, wherein the at least one pH modulator comprises at least one of an acidic pH modulator and a basic pH modulator, and wherein the oxidizer of the additional slurry composition suppresses generation of the arsine gas.

18. The method of claim 14, wherein the oxidizer of the slurry composition enhances a rate of removal of the at least one additional Group III arsenide material.

19. A slurry composition for planarizing a Group III arsenide material, the slurry composition comprising:
an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator comprising at least one of an acidic pH modulator and a basic pH modulator; or
an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator comprising an acidic pH modulator, but lacks a basic pH modulator, wherein the oxidizer of the slurry composition suppresses generation of an arsine gas.

20. The slurry composition of claim 19, wherein the oxidizer enhances a rate of removal of the Group III arsenide material.