# Patent

## Title
Low-noise low-distortion signal acquisition circuit and method with reduced area utilization

## Abstract

A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

## Background
CROSS REFERENCE TO RELATED APPLICATION
The present application is a continuation of and claims priority of U.S. non-provisional patent application Ser. No. 14/260,885, filed on Apr. 24, 2014 and U.S. provisional patent application Ser. No. 61/929,867, filed on Jan. 21, 2014. The disclosure of the foregoing United States Patent Application is specifically incorporated herein by this reference.


FIELD OF THE INVENTION
The present invention is related to sample and hold circuits and sampling systems including a plurality of sampling channels, each channel including a sample and hold circuit.
BACKGROUND OF THE INVENTION
Virtually all digitization systems interacting with the analog world are faced with the challenge of acquiring an external input signal with a circuit that minimizes noise and distortion. In fact, once the signal under observation in the external world has been corrupted by either adding noise onto it or generating spurious harmonics, its quality cannot be recovered afterwards, unless other parametric information about the input were already known; and the signal recovery method will add its own non-idealities and design burden on the whole data acquisition (DAQ) chain. This is true, for example, in the case of sampling circuits, which survey the input at discrete times (usually dictated by synchronous clock circuitry) and retain the values as observed in between adjacent samples. In this case, if the sampling apparatus is implemented, e.g., by way of a switched-capacitor circuit, the noise added by the sampler itself assumes the well-known form of kT/C wideband RMS noise; while the resistive and capacitive non-linearities of the switch introduce harmonic distortion, usually as 2nd and 3rd harmonic tones, to the input signal. Obviously one technique to reduce both kT/C and distortion is to increase the size of the capacitor used in the sampling process, since that automatically reduces the bandwidth of the noise and diminishes the impact of any charge injection term generated by the switch. However, this simple design choice often conflicts with the speed and especially with the area requirements of an integrated solution, in particular when the sampling circuit is employed at the front-end of a multi-channel system such as the ones found in imaging and/or bio-medical machines, which can range from 2 to 256 or more channels, activated simultaneously or in a time-staggered fashion.
FIG. 1 represents prior art of a sampling channel 100 for the acquisition of the charge signal provided by a photo-diode, which is in turn proportional to the intensity of the light (visible, or UV, or infra-red, or of another region of the electromagnetic spectrum such as X-ray radiation) sensed on a target such as a scintillator or a Photo-Multiplying Tube (PMT). The charge from the photodiode 102 is sampled by a switched-capacitor Sample/Hold (S/H) circuit including switches 104 and 106, capacitor Cs, and operational amplifier 108 configured as a buffer amplifier. The photodiode 102 may have some levels of multiplexing between the sensor and the reading electronics. Besides the issue of area, the aforementioned prior art suffers from a different potential problem: the capacitance non-linearity vs. voltage, often quantified by voltage coefficients VC1 [ppm/V] and VC2 [ppm/V2], respectively for linear and quadratic dependence of the capacitance Cs on the input signal (charge q(t)). Notice that, while the coefficients have been minimized by many silicon foundries for certain types of capacitors, and they approach a few 10 ppm/V or 10 ppm/V2 for low-density capacitor implementations, they can easily exceed 1000's of ppm/V or ppm/V2 for the capacitor structures offering the highest densities, such as M-O-S varactor implementations. The low-noise requirement is therefore at odds with the low-distortion performance, and a low-area solution using a dense capacitor (>5 fF/μm2) would provide low kT/C noise at the expense of significant distortion, as compared to the best dielectric solutions that use capacitor densities around 1 fF/μm2 with the current state of the art. It would therefore be desirable to design a circuit able to minimize all three figures of merit for a S/H apparatus: noise, distortion, and area.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a Sample and Hold (S/H) amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal. The sample and hold amplifier can include a third switch in series connection with the linear capacitor, wherein the third switch is configured to switch according to the second phase signal. The input current signal can be provided by a photodiode.
According to another embodiment of the present invention a Sample and Hold circuit includes a plurality of sampling channels, each sampling channel including a sample and hold amplifier having a switched non-linear capacitor and a linear feedback capacitor. The sample and hold may further include a plurality of analog to digital converters respectively coupled to an output of each sampling channel, and a FIFO coupled to an output of each of the analog to digital converters. The FIFO may be coupled to the analog to digital converters through a multi-bit parallel bus and include a multi-bit parallel bus output. The sample and hold circuit may otherwise include a multiplexer having multiple inputs respectively coupled to an output of each sampling channel and an analog to digital converter having an input coupled to an output of the multiplexer. The analog to digital converter may further include a multi-bit parallel bus output.
According to another embodiment of the present invention a sample and hold amplifier includes an operational amplifier having a negative input, a positive input coupled to ground, and an output, a non-linear capacitor having a first terminal, and a second terminal coupled to the negative input of the operational amplifier, a linear capacitor having a first terminal, and a second terminal coupled to the negative input of the operational amplifier, a first switch coupled between the first terminal of the non-linear capacitor and the output of the operational amplifier, a second switch coupled between the first terminal of the non-linear capacitor and ground, a third switch coupled between an input node and the negative input of the operational amplifier, a fourth switch coupled between a first terminal of the linear capacitor and ground, and a fifth switch coupled between a first terminal of the linear capacitor and the output of the operational amplifier. The first, third, and fourth switches are configured to switch according to a first phase signal. The second and fifth switches are configured to switch according to a second phase signal. The input node constitutes a virtual ground useful for the biasing of, and receives an input current signal provided by, a photodiode. The sample and hold amplifier further includes a reset switch coupled between the negative input of the operational amplifier and the output of the operational amplifier, wherein the reset switch is configured for receiving a reset signal. The sample and hold amplifier may further include a linear load capacitor coupled to the output of the operational amplifier through a switch configured to switch according to the second phase signal.
The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of an embodiment of the invention as illustrated in the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a sample and hold amplifier according to the prior art;
FIG. 2 is a schematic diagram of a first sample and hold amplifier embodiment according to the present invention;
FIG. 3 is a schematic diagram of an additional circuit detail which may be embedded or used as an alternative to the feedback path configuration in the sample and hold amplifier of FIG. 2;
FIG. 4A is a schematic diagram of a first sample and hold circuit including a plurality of sampling channels according to the present invention;
FIG. 4B is a timing diagram associated with the sample and hold circuit of FIG. 4A;
FIG. 5A is a schematic diagram of a second sample and hold circuit including a plurality of sampling channels according to the present invention;
FIG. 5B is a timing diagram associated with the sample and hold circuit of FIG. 5A; and
FIG. 6 is a schematic diagram of an additional sample and hold amplifier embodiment according to the present invention.



DETAILED DESCRIPTION
Referring now to FIG. 2, a sample and hold amplifier 200 according to the present invention includes a sampling capacitor circuit including a non-linear capacitor Cs, a first switch 204 and a second switch 206. The first switch is switched with a first phase signal, and the second switch is switched with a second phase signal. The sampling capacitor circuit is coupled to the negative input of an operational amplifier 208. The positive input of operational amplifier 208 is coupled to ground. The output of operational amplifier 208 provides the voltage output signal VSHA. The input current is provided by a photodiode 202, although the input current can also obviously be provided by other sources if desired.
As in the prior art, the signal current i(t) is integrated on a capacitor CS which can be made large to minimize silicon area and kT/CS noise. In a practical implementation as an I.C. (integrated circuit), CS will necessarily be non-linear (as indicated in figure by its symbol) and the voltage VIN=qIN(t)/CS(V) will be input-charge dependent; however the charge qIN(t) stored on the capacitor will be unaffected by the voltage characteristics of the device, provided the time allowed for the capacitor to get fully charged is sufficient. One aspect of the invention therefore takes advantage of this fact, as the circuit in a hold phase φ2 extracts all the charge qIN(t) from CS and transfers it over a lower-density, linear capacitor CH. In the figure the capacitor is indicated as linear by way of its symbol, and it is closed in the feedback loop of the operational amplifier 208; notice that “stray capacitor”, parasitics-insensitive topologies can be alternatively adopted and are presented e.g. on the classic book by Gregorian and Temes “Analog CMOS Integrated Circuits for Signal Processing”. Since the charge qIN(t) is now transferred on a smaller but linear capacitor CH, the voltage VSHA at the output of the circuit will not suffer from harmonic distortion; and the area of CH will be a fraction, CS/CH, of the area that a direct sampling of the photocurrent i(t) onto a CS built with the same elements as CH would have required. Naturally, if the charge transfer process onto CH were as broad-band as the sampling over CS, to the minimized √kT/CS noise RMS term we would be adding a √kT/CH RMS term that would exceed √kT/CS, since CS>CH; and in the limit case of CS=CH, increase the RMS noise by √2. However, the noise power contributed by CH is not kT/CH in the arrangement of FIG. 2.
Referring now to FIG. 3 for sake of clarity, another practical implementation of the sample and hold amplifier of FIG. 2 requires at least one switch 310 in series with capacitor CH in the feedback loop of the operational amplifier 308, in lieu e.g. of switch 206 in FIG. 2. Even though such practical implementation requires at least one switch to enclose CH into the loop, the equivalent noise bandwidth of the topology is not 1/(4·Rsw·CH), since the dominant role of the loop is not simply 1/(2π·Rsw·CH) but is proportionally lowered by the narrower bandwidth of the operational amplifier. In the limit case of no parasitic input capacitance, the operational amplifier is closed in unity-gain loop and thus its bandwidth in closed-loop equals the GBWP (Gain-BandWidth Product) of the operational amplifier itself:




  
    
      
        
          
            n
            2
          
          _
        
        =
        
          
            
              ∫
              0
              
                +
                ∞
              
            
            ⁢
            
              4
              ⁢
              
                kT
                ·
                
                  R
                  sw
                
                ·
                
                  BW
                  
                    closed
                    ⁢
                    
                      
                    
                    ⁢
                    loop
                  
                
                ·
                
                  
                
                ⁢
                
                  d
                  f
                
              
              ⁢
              
                
              
              ⁢
              
                <<
              
              ⁢
              
                
              
              ⁢
              
                
                  ∫
                  0
                  
                    +
                    ∞
                  
                
                ⁢
                
                  
                    
                      4
                      ⁢
                      
                        kT
                        ·
                        
                          R
                          sw
                        
                      
                    
                    
                      1
                      +
                      
                        
                          (
                          
                            2
                            ⁢
                            π
                            ⁢
                            
                              
                            
                            ⁢
                            
                              R
                              sw
                            
                            ⁢
                            
                              
                                C
                                H
                              
                              ·
                              f
                            
                          
                          )
                        
                        2
                      
                    
                  
                  ·
                  
                    
                  
                  ⁢
                  
                    d
                    f
                  
                
              
            
          
          =
          
            
              
                4
                ⁢
                
                  kT
                  ·
                  
                    R
                    sw
                  
                
              
              
                4
                ⁢
                
                  R
                  sw
                
                ⁢
                
                  C
                  H
                
              
            
            =
            
              kT
              
                C
                H
              
            
          
        
      
    
    
      
        (
        0
        )
      
    
  




Since the lower the bandwidth of the closed loop, i.e. the slower the amplifier, the lower the integrated noise and consequently the lower the RMS noise, the amplifier will be designed to settle in a relatively long time; this prevents the trivial application of the virtual ground technique feeding CH, directly to the photodiode. In fact, the current output response of the diode will follow immediately the exposure of the illuminated target to the imager's array of photodiodes, which may be very quick to either save energy for the illumination mechanism (say, a “flash” lamp) or to avoid medical consequences of a prolonged exposure (say, during an X-ray or tomography scanning of a patient). The fast acquisition, i.e. large bandwidth, of the sampler's front-end including CS allows for capturing the incoming signal; and once the charge is stored, it can be post-processed at slower speed to preserve noise and linearity, within a small-area circuit, thanks to the de-coupling of these requirements as devised by the present invention. In the interest of preserving the throughput of the acquisition system, a staggered parallel operation of the channels can be envisioned, whereby the target of the imager is illuminated for a whole Sample+Hold period, and the image's “pixels” (picture elements) are scanned one by one by a sequential activation of the photodiodes' biases. This of course entails a predefined level of stability of the target image.

Referring now to FIG. 4A, a sample and hold circuit 400 according to the present invention is shown including an image source 402 including a plurality of photodiodes 404 for providing a plurality of input currents. Each photodiode 404 is coupled to a plurality of sample and hold channels 406, each including a sample and hold amplifier as described above according to the present invention. The analog output of each sample and hold channel in 406 is coupled to a multiplexer 408, which is in turn coupled to an ADC 410 having a multi-bit parallel (or serialized) output bus. The channel data outputs can be digitized by a fast ADC sequentially, on the fly. As shown in the timing diagram of FIG. 4B, one new data element is output every TS seconds, avoiding some channels having to sample and hold/process signals faster than others if ADC, DSP or FPGA post-processors treat them sequentially rather than in parallel.
At the expense of some latency, a simultaneous Sample/Hold phase arrangement can be handled by a FIFO queue (First-In, First-Out) digital synchronization once the signal has been acquired, if every channel is digitized by a local A-to-D converter rather than multiplexed and digitized by a single ADC, as is shown in FIG. 5A. Referring now to FIG. 5A, a sample and hold circuit 500 according to the present invention is shown including an image source 502 including a plurality of photodiodes 504 for providing a plurality of input currents. Each photodiode 504 is coupled to a plurality of sample and hold channels 506, each including a sample and hold amplifier as described above according to the present invention. The output of each sample and hold channel in 506 is respectively coupled to a plurality of ADCs 508. Each ADC 508 includes a multi-bit parallel output bus, all of which are coupled to a FIFO 510. The FIFO 510 also includes a multi-bit parallel output bus. The corresponding timing diagram associated with the sample and hold circuit 500 is shown in FIG. 5B.
In conclusion, especially in a large array's paradigm, techniques exist which are fully compatible with the long hold phase that permits to abate the noise during the “re-sampling” phase of the signal onto a smaller, linear capacitor. The fast, broad-band noise acquisition of the fast input signal is instead effected on a large, non-linear capacitor. Notice that the CS/CH signal gain inherent in the charge re-sampling is usually a desirable feature to incorporate in the acquisition system, since a gain in the front-end stage fixes the SNR (Signal-to-Noise Ratio) for the rest of the system. This entails a noise gain 1+CS/CH for the input-referred En2 noise of the operational amplifier, which however, since it can be relatively slow, can be designed as a low-noise/low-bandwidth block. Prior art work to L. Williams III discusses a voltage sampling circuit that acquires two stages with complementary characteristics; does not mention area constraints between the two types of capacitors; and especially poses no limitations nor requirements on the noise transfer function of the front-end, with regards to the noise bandwidth limitations of the operational amplifier with element CH in feedback, which in this disclosure we have instead shown to be greatly advantageous. Notice that the arrangement in FIG. 2 causes the node VIN to move during the i(t) current readout, which one would avoid (if needed) by interposing a pre-amplifier with virtual ground to the invention. Since the pre-amp output voltage, and not charge, would drive the invention however, a capacitor of the same technological kind as CS would be used in feedback, as shown in FIG. 1 to Williams, whereby all the noise requirements of this invention would apply to such pre-amplifier stage as well, whose feedback capacitor would also have to be sized reasonably large for this purpose.
Finally, while the embodiment of FIG. 2 is only representative of the operation principle of the invention and is e.g. subject to stray parasitics capacitors, other implementations exist that are insensitive to such non-idealities. The fundamental requirements of capacitor type, size, operational amplifier bandwidth (or loop bandwidth at large) and sampling sequence in the case of a multi-channel implementation as stated in this invention do hold, in order for all the advantages in performance to apply as claimed.
Another embodiment of the invention that maintains constant voltage during the sampling phase is illustrated in FIG. 6. Sample and Hold amplifier 600 includes a first switch SWS1, a second switch SWS2, a third switch SWI1, a fourth switch SWH1, and a fifth switch SWH2. The first, third, and fourth switches are configured to switch using the first phase signal, φ1 and the second and fifth switches are configured to switch using the second phase signal, φ2, as shown. The input current is provided by photodiode 602. A non-linear capacitor CS is coupled between the first and second switches and the negative input of an operational amplifier 604. The third switch is coupled between the photodiode 602 and the negative input of the operational amplifier 604. A linear capacitor CH is coupled between the fourth and fifth switches and the negative input of operational amplifier 604. The positive input of the operational amplifier 604 is coupled to ground. The output node (OUT) of the operational amplifier is coupled to a linear or non-linear load capacitor CL through switch SWL2 which receives the φ2 signal as shown. An optional reset switch SWR is coupled between the negative input and the output of operational amplifier 604.
Two non-overlapping clock phases are denoted by φ1 and φ2, as noted above. The switch SWR is activated by the RESET signal to establish a proper DC operating point, by configuring the Operational Transconductance Amplifier (OTA) in FIG. 6 in unity gain mode. This RESET phase can be activated at the very initial phase of the operation prior to the sample and hold phases described below. The RESET phase may also be activated after the sample/hold dual-phase operation has started at an appropriate time in order to re-establish the initial DC operating point, if necessary.
During φ1 (sample phase), the photodiode D is connected to the negative input of A1 (operational amplifier) via switch SWI1, injecting the signal current i(t) into node SJ. Capacitor CS is connected between SJ at its top plate and the output of A1 at its bottom plate through switch SWS1 and integrates i(t) during the φ1 phase of the non-overlapping clock. During the φ1 phase, capacitor CH is connected between node SJ at its top plate and ground at its bottom plate. Since A1 keeps the voltage at SJ equal to its offset voltage VOS, CH samples the input offset voltage of A1 during the φ1 phase. The anode terminal of the photodiode D is continuously connected to a negative reference voltage −VREF. Since its cathode terminal is held at VOS, the voltage bias across the photodiode is kept at a constant voltage −VREF-VOS during the sample phase, eliminating the dependence of its signal current i(t) on the bias voltage across anode and cathode. Prior to the beginning of the sample phase at the end of the previous hold phase (φ2), CS had been charged to VOS via switch SWS2. Therefore, the charge accumulated on the top plate (which is connected to SJ) during the present sample phase (whose duration is T1) is given by:

QS(φ1)=CS·VOS+∫t=0T1i(t)·dt  (1)

The charge on the top plate of CH at node SJ during φ1 is:

QH(φ1)=CH·VOS  (2)

The OTA A1 is designed such that during φ1, the closed loop bandwidth at −3 dB of A1 is given by:





  
    
      
        
          Fu
          ⁡
          
            (
            Ø1
            )
          
        
        =
        
          
            gm
            
              2
              ⁢
              
                π
                ·
                
                  C
                  S
                
              
            
          
          ·
          
            
              C
              S
            
            
              
                C
                S
              
              +
              
                C
                H
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




In Eq. (3), gm is the transconductance of the input devices of the differential pair inside A1. The voltage noise spectral density of the predominant noise source A1 is given by 4 kT·4/(3·gm), where T is the absolute temperature, and k is Boltzmann's constant. Therefore, the noise voltage across CS in phase φ1 is given by:





  
    
      
        
          
            Vn
            2
          
          ⁡
          
            (
            Ø1
            )
          
        
        =
        
          
            4
            ⁢
            kT
            ⁢
            
              4
              
                3
                ⁢
                gm
              
            
            ⁢
            
              
                gm
                
                  2
                  ⁢
                  
                    π
                    ·
                    
                      C
                      S
                    
                  
                
              
              ·
              
                π
                2
              
              ·
              
                
                  C
                  S
                
                
                  
                    C
                    S
                  
                  +
                  
                    C
                    H
                  
                
              
              ·
              
                
                  (
                  
                    
                      
                        C
                        S
                      
                      +
                      
                        C
                        H
                      
                    
                    
                      C
                      S
                    
                  
                  )
                
                2
              
            
          
          =
          
            
              
                4
                ⁢
                kT
              
              3
            
            ·
            
              
                
                  C
                  S
                
                +
                
                  C
                  H
                
              
              
                C
                S
                2
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Notice this noise voltage is slightly more than √{square root over (kT/Cs)} because it multiplies √{square root over (kT/Cs)} noise by √{square root over ((4/3)·[(Cs+Ch)/Cs])}.
In the hold phase when φ2 is active, the bottom plate of capacitor CS is driven to ground through SWS2 while its top plate is held at VOS. The top plate of CH is at VOS, and its bottom plate is driven by the output node OUT of A1. The charge accumulated in CS during the sample phase will all be transferred to CH with the exception of CS·VOS which remain across CS. The charges on top plates of CS and CH in φ2 phase are given respectively by:

QS(φ2)=CS·VOS  (5)

QH(φ2)=CH·(VOS−VOUT)  (6)

Here, VOUT is the voltage at the output of A1. The total charge held at node SJ remains constant through the two phases of the operation, namely the sample and hold phases. Therefore, QS(φ1)+QH(φ1)=QS(φ2)+QH(φ2). From this equation, we obtain:





  
    
      
        VOUT
        =
        
          
            -
            
              1
              
                C
                H
              
            
          
          ⁢
          
            
              ∫
              
                t
                =
                1
              
              
                T
                ⁢
                
                  
                
                ⁢
                1
              
            
            ⁢
            
              
                i
                ⁡
                
                  (
                  t
                  )
                
              
              ·
              
                
              
              ⁢
              
                d
                t
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




The output of A1 at the end of hold phase is proportional to the time integral of the input current from the photodiode given by Eq. (7). Notice that in this circuit configuration the input offset voltage VOS does not affect VOUT. As previously described, the closed loop bandwidth of A1 during the hold phase (φ2) can be purposely designed to be low. By connecting the load capacitance CL during this phase, one can set the bandwidth to be reduced to:





  
    
      
        
          Fu
          ⁡
          
            (
            Ø2
            )
          
        
        =
        
          
            gm
            
              2
              ⁢
              
                π
                ·
                CL
              
            
          
          ·
          
            
              C
              H
            
            
              
                C
                H
              
              +
              
                C
                S
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




The noise at VOUT is therefore:





  
    
      
        
          
            Vn
            2
          
          ⁡
          
            (
            Ø2
            )
          
        
        =
        
          
            4
            ⁢
            kT
            ⁢
            
              4
              
                3
                ⁢
                gm
              
            
            ⁢
            
              
                gm
                
                  2
                  ⁢
                  
                    π
                    ·
                    CL
                  
                
              
              ·
              
                π
                2
              
              ·
              
                
                  C
                  H
                
                
                  
                    C
                    S
                  
                  +
                  
                    C
                    H
                  
                
              
              ·
              
                
                  (
                  
                    
                      
                        C
                        S
                      
                      +
                      
                        C
                        H
                      
                    
                    
                      C
                      H
                    
                  
                  )
                
                2
              
            
          
          =
          
            
              
                4
                ⁢
                kT
              
              3
            
            ·
            
              
                
                  C
                  S
                
                +
                
                  C
                  H
                
              
              
                C
                H
              
            
            ·
            
              1
              CL
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




Note that the voltage gain seen from capacitor CS around A1 in the hold phase is CS/CH. The equivalent noise in the hold phase to the same noise given by Eq. (4) is calculated as:





  
    
      
        
          
            Vn
            2
          
          ⁡
          
            (
            
              Ø2
              ,
              Ø1
            
            )
          
        
        =
        
          
            
              
                Vn
                2
              
              ⁡
              
                (
                Ø2
                )
              
            
            ·
            
              
                (
                
                  
                    C
                    H
                  
                  ⁢
                  
                    /
                  
                  ⁢
                  
                    C
                    S
                  
                
                )
              
              2
            
          
          =
          
            
              
                
                  4
                  ⁢
                  kT
                
                3
              
              ·
              
                
                  
                    C
                    H
                  
                  +
                  
                    C
                    S
                  
                
                
                  C
                  S
                  2
                
              
              ·
              
                
                  C
                  H
                
                CL
              
            
            =
            
              
                
                  Vn
                  2
                
                ⁡
                
                  (
                  Ø1
                  )
                
              
              ·
              
                
                  C
                  H
                
                CL
              
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




One can set CL to be significantly larger than CH, making the voltage noise at VOUT referred to the input in the hold phase much smaller than the voltage noise sensed during the sample phase.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention. It should be understood that this description has been made by way of example, and that the invention is defined by the scope of the following claims.

## Claims

1. A sample and hold amplifier comprising:
an input node for receiving an input current signal;
a non-linear sampling capacitor circuit having an input coupled to the input node comprising a non-linear capacitor coupled between an intermediate node and ground;
an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal; and
a linear capacitor circuit coupled between the negative input and the output of the operational amplifier.

2. The sample and hold amplifier according to claim 1 wherein the non-linear sampling capacitor circuit further comprises:
a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal; and
a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal, and
wherein the linear capacitor circuit comprises a linear capacitor coupled directly between the negative input and the output of the operational amplifier.

3. The sample and hold amplifier according to claim 1 wherein the non-linear sampling capacitor circuit further comprises:
a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and
wherein the linear capacitor circuit comprises:
a linear capacitor coupled between a second intermediate node and the negative input of the operational amplifier; and
a second switch coupled between the output of the operational amplifier and the second intermediate node, in series connection with the linear capacitor.

4. The sample and hold amplifier according to claim 3 wherein the second switch is configured to switch according to the second phase signal.

5. The sample and hold amplifier according to claim 1 wherein the input current signal is provided by a photodiode.

6. A sample and hold circuit comprising a plurality of parallel sampling channels operatively coupled together, each sampling channel including a sample and hold amplifier having a switched non-linear capacitor circuit operatively coupled to a linear feedback capacitor circuit, the non-linear capacitor circuit comprising a non-linear capacitor coupled between an intermediate node and ground.

7. The sample and hold circuit of claim 6 further comprising a plurality of analog to digital converters respectively coupled to an output of each sampling channel.

8. The sample and hold circuit of claim 7 further comprising a First-In First-Out digital queue circuit (FIFO) coupled to a digital output of the analog to digital converter in each sampling channel.

9. The sample and hold circuit of claim 8 wherein the FIFO is coupled to the analog to digital converters through a multi-bit parallel bus.

10. The sample and hold circuit of claim 8 wherein the FIFO comprises a multi-bit parallel bus output.

11. The sample and hold circuit of claim 6 further comprising a multiplexer having multiple inputs respectively coupled to an analog output of each sampling channel.

12. The sample and hold circuit of claim 11 further comprising an analog to digital converter having an input coupled to an output of the multiplexer.

13. The sample and hold circuit of claim 12 wherein the analog to digital converter comprises a multi-bit parallel bus output.

14. A sample and hold circuit comprising a plurality of parallel sampling channels operatively coupled together, each sampling channel comprising:
an input node for receiving an input current signal;
a non-linear sampling capacitor circuit having an input coupled to the input node comprising a non-linear capacitor coupled between an intermediate node and ground;
an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal; and
a linear capacitor circuit coupled between the negative input and the output of the operational amplifier.

15. The sample and hold circuit according to claim 14 wherein the non-linear sampling capacitor circuit further comprises:
a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal; and
a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal, and
wherein the linear capacitor circuit comprises a linear capacitor coupled directly between the negative input and the output of the operational amplifier.

16. The sample and hold circuit according to claim 14 wherein the non-linear sampling capacitor circuit further comprises:
a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal; and
wherein the linear capacitor circuit comprises:
a linear capacitor coupled between a second intermediate node and the negative input of the operational amplifier;
a second switch coupled between the output of the operational amplifier and the second intermediate node, in series connection with the linear capacitor.

17. The sample and hold circuit according to claim 16 wherein the second switch is configured to switch according to the second phase signal.

18. The sample and hold circuit according to claim 14 wherein the input current signal is provided by a photodiode.