# Patent

## Title
Low power circuit for amplifying a voltage without using resistors

## Abstract

A resistor-less amplifying circuit includes a plurality of resistor-less cells. Each cell includes a plurality of MOS transistors. Each cell generates a differential output equal to ΔVGS of two MOS transistors with a magnitude of the differential output controlled by a control voltage generated by a differential amplifier coupled to a feedback loop around a cell. In one embodiment, the resistor-less amplifying circuit is a part of a bandgap voltage reference circuit. In another embodiment, the resistor-less amplifying circuit is part of a temperature sensor circuit.

## Background
BACKGROUND
Field
This invention relates generally to electronic circuits, and more specifically to amplification of signals in low power consumption circuits.
Related Art
Low power consumption circuits (circuits consuming less than 5 μW) that amplify a small magnitude voltage typically use resistors that have very high ohmic values to maintain low currents. Examples of such low power consumption circuits are low-power voltage reference circuits and low-power temperature sensor circuits. A bandgap voltage reference circuit is a temperature-independent voltage reference circuit that outputs a fixed DC voltage at or near a bandgap voltage of a semiconductor substrate on which the voltage reference circuit resides. The extrapolated bandgap voltage of silicon at zero kelvin is 1.22V.
With most low-power bandgap voltage reference circuits, there is a need to amplify a small signal of a few to tens of millivolts into a larger signal of several hundreds of millivolts. In some known low-power bandgap voltage reference circuits, the small signal that is amplified is a proportional-to-absolute-temperature (PTAT) voltage. If resistors are used in such known circuits, a drop of several hundreds of millivolts across the resistors is needed, which requires resistors having values in the range of tens of megaohms so that the current is limited to nanoamps. Such high ohmic value resistors occupy very large areas, which result in high area cost and/or impose a minimum power constraint. This unfavorable power/area trade-off usually determines a minimum power that can be obtained at an acceptable area cost.
Several low-power bandgap voltage reference circuits that do not use resistors, and instead use metal-oxide-semiconductor (MOS) transistors, are known. However such known circuits do not provide sufficient linearity because of the presence of various error sources such as second-order effects. Furthermore, such known circuits are subject to fabrication process and spread. Also, such known circuits require extensive trimming. Consequently, such known circuits are much less accurate than conventional bandgap voltage reference circuits that employ resistors.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
FIG. 1 is a schematic of a first type of cell comprising MOS transistors, in accordance with one embodiment of the present invention.
FIG. 2 is a schematic of a second type of cell comprising MOS transistors, in accordance with one embodiment of the present invention.
FIG. 3 is a graph of a family of differential outputs of a cell, such as the cell of FIG. 1 or FIG. 2.
FIG. 4 is a schematic of a low power consumption bandgap voltage reference circuit in accordance with one embodiment of the present invention.
FIG. 5 is a schematic of a low power consumption bandgap voltage reference circuit in accordance with another embodiment of the present invention.
FIG. 6 is a schematic of a low power consumption bandgap voltage reference circuit in accordance with yet another embodiment of the present invention.
FIG. 7 is a schematic of a low power consumption temperature sensor circuit in accordance with one embodiment of the present invention.



DETAILED DESCRIPTION
Circuits in accordance with embodiments of the present invention employ compact structures, or cells, comprising metal-oxide-semiconductor (MOS) transistors instead of resistors to amplify a small magnitude signal. Embodiments may amplify a small magnitude PTAT voltage. However, circuits in accordance with the present invention do not use MOS transistors to produce a PTAT voltage. Instead, embodiments of the present invention use two bipolar junction transistors (BJTs) to produce the PTAT voltage, as done with high-precision bandgap voltage reference circuits. Circuits in accordance with the present invention use stacked cells of MOS transistors that are actively controlled (using a closed-loop structure) to accurately replicate the small magnitude signal.
A circuit in accordance with the present invention adjusts, through feedback, a difference between gate-to-source voltages of two MOS transistors. A feedback loop around one cell forces a difference between gate-to-source voltages of two MOS transistors in the cell to become equal to a small magnitude voltage that is inputted into the cell. A control voltage produced by the feedback loop is applied to all other cells in the circuit. Each cell then produces a copy of the small magnitude voltage input signal. The individual cells are cascaded in order to build an amplified copy of the small magnitude voltage.
FIG. 1 is a schematic of a first type of cell 102 comprising MOS transistors. The cell 102 comprises MOS transistor M1 111 configured as a diode, MOS transistor M2 112, and MOS transistor M3 113. A drain terminal of MOS transistor M2 112 is coupled to VDD and a source terminal of MOS transistor M2 is coupled to a current source 115. A voltage Vm is present at the gate of MOS transistor M2 112. A source terminal of MOS transistor M3 113 is coupled to VDD and a drain terminal of MOS transistor M3 is coupled to drain and gate terminals of MOS transistor M1 111. A control voltage VC is inputted to the gate of MOS transistor M3 113. A source terminal of MOS transistor M1 111 is coupled to the current source 115. A voltage Vp is present at the gate of MOS transistor M1 111. A voltage defined as a difference between Vp and Vm may be considered to be the output of the cell 102. The following relationship exists in cell 102: Vp−Vm=VGS1−VGS2=ΔVGS. The cell 102 does not include any BJTs. Advantageously, the cell 102 does not include any resistors. When used alone, the cell 102 receives, as an input, the control voltage VC, and then the cell produces, as an output, the voltage (Vp−Vm). Because the gates of M1 111 and M2 112 are floating with respect to VDD and ground, a plurality of the cells 102 can be cascaded, or stacked, as shown in FIGS. 4-7.
FIG. 2 is a schematic of a second type of cell 202 comprising MOS transistors. The cell 202 comprises MOS transistor M1 221, MOS transistor M2 222 configured as a diode, MOS transistor M3 223, and MOS transistor M4 224. A source terminal of MOS transistor M3 223 is coupled to a current source 225. A drain terminal of MOS transistor M3 223 is coupled to a node 220. The control voltage VC is inputted at the gate of MOS transistor M3 223. A source terminal of MOS transistor M4 224 is coupled to the current source 225. A drain terminal of MOS transistor M4 224 is coupled to gate and drain terminals of a MOS transistor M2 222 and to a gate of a MOS transistor M1 221. A bias voltage VB is inputted at the gate of MOS transistor M4 224. A source terminal of MOS transistor M2 222 is coupled to the node 220. A drain terminal of MOS transistor M1 221 is also coupled to the node 220. A voltage Vp is present at the node 220. A voltage Vm is present at a source terminal of MOS transistor M1 221. A voltage defined as a difference between Vp and Vm may be considered to be the output of the cell 202. The following relationship exists in cell 202: Vp−Vm=VGS1−VGS2=ΔVGS. The cell 202 does not include any BJTs. Advantageously, the cell 202 does not include any resistors. Because the gates of M1 221 and M2 222 are floating with respect to VDD and ground, a plurality of the cells 202 can be cascaded, or stacked. When the cell 202 is used as part of a larger circuit, as described hereinafter, the source terminal of MOS transistor M1 221 is also coupled to other circuitry including to ground potential. When used alone, the cell 202 receives, as an input, the control voltage VC, and then the cell 202 produces, as an output, the voltage (Vp−Vm).
In the illustrated embodiments, MOS transistors M1 and M2 are of a same size, and a gate-to-source (VGS) voltage difference between MOS transistors M1 and M2 is adjusted by controlling a relationship between their drain currents, to obtain the desired ΔVGS=ΔVBE. In the illustrated embodiments, the drain current of M1 is larger than the drain current of M2 in order to produce VGS1−VGS2=ΔVBE (VGS1 is greater than VGS2). In another embodiment, MOS transistors M1 and M2 have same drain currents and have different W/L ratios to obtain the desired ΔVGS=ΔVBE. In yet another embodiment, MOS transistors M1 and M2 have different drain currents and different W/L ratios to obtain the desired ΔVGS=ΔVBE.
FIG. 3 is a graph of a family of differential outputs of a cell, such as cell 102 or cell 202. In the graph of FIG. 3, the vertical, or y-axis, represents voltage and the horizontal, or x-axis, represents temperature. FIG. 3 shows how a voltage (Vp−Vm) changes with respect to temperature for eight (8) different values of Id1/Id2. Other values of Id1/Id2 are possible, but only eight (8) representative values of values of Id1/Id2 are shown in FIG. 3, for simplicity of illustration. FIG. 3 shows that, for each representative value of Id1/Id2, (Vp−Vm) increases with temperature. Because the graph of each voltage versus temperature appears in FIG. 3 as almost a straight line, it can be concluded that the voltage (Vp−Vm) has nearly PTAT behavior for a given Id1/Id2. The graph of FIG. 3 shows a range 308 of values of Id1/Id2 over which ΔVGS may be adjusted using the control voltage V. In one embodiment, the range 308 is 600 mV.
By controlling VC, the ratio Id1/Id2 can be controlled. The ratio Id1/Id2, in turn, adjusts ΔVGS. There is a range 308 over which ΔVGS may be successfully adjusted through VC. For proper operation, (Vp−Vm) must fall within the range 308 over which ΔVGS may be successfully adjusted. ΔVGS can be adjusted to any value within the range 308 by controlling Id1/Id2. A top limit of the range 308 corresponds to a ΔVGS produced with a maximum Id1/Id2 that is practical to implement. The behavior shown on the graph of FIG. 3 is basically the same for all cases of I (for the various MOS operation region cases) with some change only in the y-axis values. Nevertheless, for any given case, provided that (Vp−Vm) falls within the range 308, ΔVGS can be made equal to (Vp−Vm) by feedback, as explained hereinbelow with regard to FIGS. 4-7.
The graph of FIG. 3 shows that Vp−Vm is nearly PTAT and that (Vp−Vm) increases almost linearly with temperature for a given Id1/Id2. Provided that (Vp−Vm) falls within the range 308, the graph of FIG. 3 can be obtained even if one of M1 and M2 is operated in strong inversion and the other of M1 and M2 is operated in weak or moderate inversion.
When used in a resistor-less amplifying circuit, the cells 102 and 202 are particularly suitable to track a nearly-PTAT small magnitude input signal because a nearly-PTAT signal requires smaller variations of Id1/Id2 over temperature compared to when a signal is not nearly-PTAT. The circuits in accordance with the embodiment are particularly suitable to track a nearly-PTAT small magnitude input signal also because the ΔVGS output of each cell 102 and 202 is, by its design, nearly-PTAT when a constant ratio between the MOS transistor currents (a mid-point in the control range) is maintained.
FIG. 4 is a schematic of a low power consumption bandgap voltage reference circuit 402 in accordance with one embodiment of the present invention. In one embodiment, the bandgap voltage reference circuit 402 is implemented as an integrated circuit 404 disposed on a silicon substrate 406. The bandgap voltage reference circuit 402 includes BJT Q1 421 and BJT Q2 422. The bandgap voltage reference circuit 402 also includes a resistor-less amplifying circuit coupled to the aforesaid BJTs. In the illustrated embodiment, the BJTs provide a small magnitude signal to the resistor-less amplifying circuit. The resistor-less amplifying circuit amplifies the small magnitude signal. The resistor-less amplifying circuit comprises a plurality of the first type of cell 102. The resistor-less amplifying circuit also comprises a closed-loop structure, or feedback loop 420, as described hereinbelow. In the illustrated embodiment of the bandgap voltage reference circuit 402, three cells are shown: a first cell 411, a second cell 412 and an nth cell 413. Each cell 411, 412 and 413 has an identical structure and is identically biased. The cells of the bandgap voltage reference circuit 402 are stacked, or cascaded together, such that a differential voltage that occurs at each cell can be added together. A sum of the differential voltage that occurs at each cell contributes to an output signal, VREF, of the bandgap voltage reference circuit 402.
An emitter terminal of BJT Q1 421 is coupled to a current source I1. Base and collect terminals of BJT Q1 421 are coupled to ground. An emitter terminal of BJT Q2 422 is coupled to a current source I2. Base and collect terminals of BJT Q2 422 are coupled to ground. The base-to-emitter voltage of BJT Q1 421 (VBE1) depends upon a value of I1 and a size of Q1. The base-to-emitter voltage of BJT Q2 422 (VBE2) depends upon a value of I2 and a size of Q2. ΔVBE=VBE1−VBE2. In the bandgap voltage reference circuit 402, ΔVBE has PTAT behavior. To generate a ΔVBE that has PTAT behavior, it is necessary that Q1 and Q2 be of different sizes and/or that I1 and I2 have different values. In one embodiment, Q2 is larger than Q1, and I1=I2. In one such embodiment, Q2 is 8 to 25 times larger than Q1.
In the bandgap voltage reference circuit 402, the feedback loop 420 goes around the first cell 411. The feedback loop 420 includes a differential amplifier 423. An inverting input terminal of the differential amplifier 423 is coupled to an emitter terminal of BJT Q1 421 at which the voltage VBE1 is obtained. A non-inverting input terminal of the differential amplifier 423 is coupled to a gate of MOS transistor M11. An output terminal of the differential amplifier 423 is coupled to a gate of MOS transistor M31. The output terminal of the differential amplifier 423 is also coupled to a gate of a MOS transistor in each of the other cells that corresponds to MOS transistor M31 in the first cell 411. Control voltage VC is outputted by the differential amplifier 423. The gain of the feedback loop 420 is selected to be high enough so that a systematic offset can be neglected. A voltage difference between the non-inverting and the inverting input terminals of the amplifier 421 represents the systematic offset.
A small magnitude differential voltage is applied to the first cell 411 of the resistor-less amplifying circuit as an input signal thereto. More specifically, one end of the small magnitude differential voltage is applied at the inverting input terminal of the differential amplifier 423 and the other end of the small magnitude differential voltage is applied at the gate of MOS transistor M21. When an input signal is applied to the first cell 411, the bandgap voltage reference circuit 402 produces a value of VC as a result of the feedback loop 420. In the illustrated embodiment, BJT Q1 421 and BJT Q2 422 produce the small magnitude differential signal.
The small magnitude differential signal that BJT Q1 421 and BJT Q2 422 produce is ΔVBE. For purposes of analysis, it should be noted that the first cell 411 of the bandgap voltage reference circuit 402 has a differential voltage that consists of a difference between a gate-to-source voltage of MOS transistor M11 and a gate-to-source voltage of MOS transistor M12, i.e., ΔVGS. A magnitude of ΔVGS is modifiable by a value of VC, which is coupled to the gate of M31 of the first cell 411. By feedback, the differential voltage ΔVGS at the first cell 411 is adjusted to become equal to ΔVBE. In other words, the feedback loop 420 determines a particular value of VC that causes ΔVGS to equal ΔVBE at the first cell 411.
VBE2, which has complementary-to-absolute-temperature (CTAT) behavior, is applied to the gate of MOS transistor M21. The feedback loop 420 causes VBE1 to occur at the gate of MOS transistor M11. If VBE1 is higher than the gate voltage of M11, then VC will decrease, which means that VGS of M31 will increase, so that the current through M31 will increase. As the current through M31 increases, M11 drains more current and produces a higher VGS for M11. Therefore, the gate of M11 increases until the gate voltage of M11 equals VBE1.
By adjusting a gate voltage of M31, the feedback loop 420 forces ΔVGS between M11 and M21 to equal the difference between the base-to-emitter voltages of the BJTs, Q1 421 and Q2 422. In other words, the feedback loop 420 forces ΔVGS to become equal ΔVBE for the first cell 411. Therefore, as a result of feedback, a voltage at the gate of M11 with respect to ground is VBE2 ΔVBE.
The particular value of VC that forced ΔVGS to become equal to ΔVBE in the first cell 411 is then applied to each of the other cells, including cell 412 and cell 413, in a similar manner, and each of the other cells will create its own ΔVGS ΔVBE. By applying the particular value of VC to a gate of a MOS transistor in each cell that corresponds to M31, ΔVGS in all the other cells in the bandgap voltage reference circuit 402 also become equal to ΔVBE. The gate of MOS transistor M11 of cell 411 is coupled to the gate of MOS transistor M22 of cell 412, thereby allowing the differential voltage that occurs across cell 411 to be added to the differential voltage that occurs across cell 412. As a result, a voltage at the gate of M12 with respect to ground is VBE2+2·ΔVBE. Consequently, a voltage produced across the entire stack of cells becomes an amplified version of ΔVBE. The other cells are coupled together in an analogous manner, thereby allowing the N stacked cells of the resistor-less amplifying circuit to produce a voltage equal to N·ΔVBE. The voltage N·ΔVBE is part of the voltage outputted by the bandgap voltage reference circuit 402. The other part of the voltage outputted by the bandgap voltage reference circuit 402 is VBE2. When N cells are stacked, as in the bandgap voltage reference circuit 402, the output voltage VREF of the bandgap voltage reference circuit with respect to ground becomes VBE2 plus the sum of N voltages, each voltage being ΔVBE. In other words, VREF=VBE2+N·ΔVBE. Consequently, the output voltage VREF can be looked upon as VBE2 plus the product of ΔVBE multiplied by an integer.
Typical N=8 for low-power designs of the bandgap voltage reference circuit 402. Because N is integer, changing only N results in a gross adjustment to the value of VREF and to the behavior of VREF with respect to temperature. After choosing an appropriate N, fine tuning of VREF is done by adjusting collector currents of BJT Q1 421 and BJT Q2 422 to set appropriate thermal coefficients for VBE2 and ΔVBE. ΔVBE is very linear over temperature. ΔVBE can be written as a function of the absolute temperature T as ΔVBE=C*T. VBE can also be written as a function of the absolute temperature T as VBE=A−B*T. The parameter A is a constant, i.e., it does not depend on biasing currents. The parameters B and C depend on biasing currents, and these parameters are first-order thermal coefficients. Reasonable values of biasing currents would typically make B about 2 mV/K and C about 0.2 mV/K. In other words, by adjusting the biasing currents B and C can be adjusted to any real value near the aforesaid reasonable values. Considering VBE2=A−B*T and ΔVBE=C*T as written above, and given VREF=VBE2+N*ΔVBE, then it follows that VREF=A+(N*C−B)*T. To have no variation over temperature, values are chosen such that N*C=B. When N*C=B is substituted into the preceding equation, the results is VREF=A (bandgap reference). Because N is an integer, B needs to be a multiple of C in order to make N*C=B. The parameter B is made a multiple of C by adjusting the biasing currents, i.e., adjusting B and C values.
When implementing bandgap voltage reference circuit 402, I1 and I2 are varied so that N×ΔVBE rises with temperature (PTAT behavior) at a same rate that VBE2 decays with temperature (CTAT behavior). First, it is determined which current density values to apply to BJT Q1 421 and BJT Q2 422 based on technology curves, power constraints, and other factors. Then, the values of B and C are obtained from the current densities. Next, the current density values are adjusted to make B a multiple of C, i.e., B/C=N. The value of N determines the number of cells needed to produce VREF.
For minimum power consumption, BJT Q1 421 and BJT Q2 422 are selected to be of minimum sizes (and equal areas), and I1 is selected to be greater than I2 (e.g., I1=24×I2). However, for a simple implementation I1=I2, and emitter area of Q2>>emitter area of Q1.
FIG. 5 is a schematic of a low power consumption bandgap voltage reference circuit 502 in accordance with another embodiment of the present invention. In most respects, the bandgap voltage reference circuit 502 is similar to the bandgap voltage reference circuit 402; therefore, only the differences will be emphasized hereinafter.
In the bandgap voltage reference circuit 402 (see FIG. 4), scaling of ΔVBE was by an integer factor. However, in the bandgap voltage reference circuit 502 (see FIG. 5), scaling is done by a non-integer factor notwithstanding N being an integer. To accomplish scaling by a non-integer factor, a single feedback loop 520 is closed around K number of cells in order to generate input signal copies scaled by (1/K), where K is an integer greater than 1 and less than N, and where N is a total number of cells in the bandgap voltage reference circuit 502. In the bandgap voltage reference circuit 502, the feedback loop 520 is around two cells. Therefore, for the bandgap voltage reference circuit 502, K=2.
In the illustrated embodiment of the bandgap voltage reference circuit 502, three cells are shown: a first cell 411, a second cell 412 and an nth cell 413. The bandgap voltage reference circuit 502 includes the feedback loop 520 around both the first cell 411 and the second cell 412. The feedback loop 520 includes a differential amplifier 523. An inverting input terminal of the differential amplifier 523 is coupled to an emitter terminal of BJT Q1 421 at which the voltage VBE1 is obtained. A non-inverting input terminal of the differential amplifier 523 is coupled to a gate of MOS transistor M12 of cell 412. The output terminal of the differential amplifier 523 is coupled to a gate of MOS transistor M31, M32, . . . , M3N in each cell. Control voltage VC is outputted by the differential amplifier 523. The gain of the feedback loop 520 is selected to be high enough so that the systematic offset can be neglected.
A feedback loop around K cells creates a 1/K fraction of ΔVBE. The feedback loop 520 forces ΔVGS+ΔVGS=ΔVBE. As a result, each cell 411 and 412 copies 1/2 ΔVBE. Therefore, if the total number of cells in the bandgap voltage reference circuit 502 was three, i.e., N=3, then the output VREF would be VBE2 plus 3/2 ΔVBE. Consequently, if the bandgap voltage reference circuit 502 had three (3) cells, the signal ΔVBE would be multiplied by a non-integer.
If instead, the total number of cells in the bandgap voltage reference circuit 502 was four, i.e., N=4, the output VREF would be VBE2 plus 4/2 ΔVBE. Consequently, if the bandgap voltage reference circuit 502 had four (4) cells, the signal ΔVBE would be multiplied by an integer.
If instead, the total number of cells in the bandgap voltage reference circuit 502 was five, i.e., N=5, the output VREF would be VBE2 plus 5/2 ΔVBE. Consequently, if the bandgap voltage reference circuit 502 had five cells, the signal ΔVBE would be multiplied by a non-integer.
If the total number of cells in another bandgap voltage reference circuit (not shown) was five, i.e., N=5, and if such other circuit had a similar feedback loop closed around three cells (instead of two cells) but was otherwise similar to FIG. 5, the feedback loop would force ΔVGS+ΔVGS+ΔVGS=ΔVBE. Each cell in such other circuit would copy 1/3 ΔVBE. Therefore, the output VREF of such other circuit would be VBE2 plus 5/3 ΔVBE.
An advantage, under certain circumstances, of closing the feedback loop 520 around more than one cell is the feedback having a more accurate effect compared to when a feedback loop is closed around only one cell.
FIGS. 4 and 5 show that VREF is taken at the output of the rightmost cell. However, taking VREF from one of the nodes between the cells can be a way of implementing coarse trimming of VREF.
FIG. 6 is a schematic of a low power consumption bandgap voltage reference circuit 602 in accordance with yet another embodiment of the present invention. The bandgap voltage reference circuit 602 comprises a plurality of the second type of cell 202 each of which is described in detail hereinabove with respect to FIG. 2. Each cell 631, 632, 633, 634 and 635 of the bandgap voltage reference circuit 602 has an identical structure (except for MOS transistors M11, M12, M13, . . . , M1N) and is identically biased. In the bandgap voltage reference circuit 602, MOS transistors M11, M12, M13, . . . , M1N conduct currents I, 2I, 3I, . . . , NI. Hence, parallel transistors are added (1×, 2×, 3×, . . . , N×) to maintain current I through the unitary MOS transistors of each cell.
In the illustrated embodiment of the bandgap voltage reference circuit 602, five cells are shown, which are, from right to left in FIG. 6: cell 631, cell 632, cell 633, an nth cell 634 and an initial cell 635. The bandgap voltage reference circuit 602 includes a feedback loop 620 around the initial cell 635. The feedback loop 620 includes a differential amplifier 623. A non-inverting input terminal of the differential amplifier 623 is coupled to a drain terminal of MOS transistor M1. An inverting input terminal of the differential amplifier 623 is coupled to an emitter terminal of BJT Q1 641 at which VBE1 is present. An output terminal of the differential amplifier 623 is coupled to a gate of MOS transistor M3. The differential amplifier 623 outputs control voltage VC. For purposes of analysis, it can be considered that an input signal is applied between source and drain terminals MOS transistor M1 of the initial cell 635. The control voltage VC is applied to a gate of M3. Because of feedback, the closed-loop structure of the bandgap voltage reference circuit 602 produces a VC that has a particular value. As a result of the particular value of VC controlling a gate voltage of MOS transistor M3, the feedback loop forces ΔVGS between MOS transistors M1 and M2 to equal the difference between the base-to-emitter voltages of the BJTs, Q1 641 and Q2 642. In other words, the feedback loop 620 forces ΔVGS to equal ΔVBE for the initial cell 635. Because the particular value of VC that forced ΔVGS=ΔVBE in the initial cell 635 is also applied to each of the other cells in a similar manner, then each of the other cells creates a ΔVGS=ΔVBE of their own.
The (N−1) stacked cells (for example, cell 631, cell 632 and cell 633) of FIG. 6 produce a voltage of (N−1)·ΔVBE. Therefore, VREF=VBE1+N·ΔVBE=VBE2+(N+1)·ΔVBE.
All the current consumed by the bandgap voltage reference circuit 602 goes eventually to the BJTs Q1 641 and Q2 642. In other words, no current goes to ground without first going through the BJTs 641 and 642. This means that the bandgap voltage reference circuit 602 consumes the lowest possible current. When designing the bandgap voltage reference circuit 602, a first step is to determine which value of current is needed to bias Q1 and Q2. Then, the biasing of the MOS transistors is determined.
For very low power designs, it is advantageous that the BJTs 641 and 642 do not have their own, additional, current sources that consume power. Compared to embodiment shown in FIGS. 4 and 5, the embodiment shown in FIG. 6 enables lower power consumption for the same BJT bias conditions. However, if the MOS transistors are operated in strong inversion, then the bandgap voltage reference circuits 402 and 502 may be advantageous over the bandgap voltage reference circuit 602.
Corner and mismatch simulations of the bandgap voltage reference circuit 602 shows that VREF is 1.20V+10 mV after trimming for temperatures between −40° C. and 150° C., and that the maximum current consumption is 502 nA at 150° C. and 5.5V supply. Typical-case simulation of the bandgap voltage reference circuit 602 shows that VREF is 1.201V+1.1 mV for temperatures between −40° C. and 150° C., and that the current consumption is 250 nA at 25° C. and 5V supply. The simulations reveal that VREF outputted by the bandgap voltage reference circuit 602 is almost equal to the bandgap voltage of silicon and is nearly temperature independent.
On a given technology, the bandgap voltage reference circuits 402, 502 and 602 can be made as accurate as a conventional bandgap voltage reference circuit that employs resistors. The accuracy of the bandgap voltage reference circuits 402, 502 and 602 is dependent upon matching of corresponding MOS transistors in each cell are matched.
FIG. 7 is a schematic of a low power consumption temperature sensor circuit 702 in accordance with one embodiment of the present invention. The temperature sensor circuit 702 uses BJTs to produce highly accurate temperature-related signals and uses cells of matched MOS transistors to amplify those signals. The temperature sensor circuit 702 comprises a plurality of the second type of cell 202. In the illustrated embodiment of the temperature sensor circuit 702, five cells are shown, which are, from right to left in FIG. 7: cell 731, cell 732, cell 733, an nth cell 734 and an initial cell 735. Each cell 731, 732, 733, 734 and 735 of the temperature sensor circuit 702 has an identical structure (except for MOS transistors M11, M12, M13, . . . , M1N) and is identically biased. In the temperature sensor circuit 702, MOS transistors M11, M12, M13, . . . , M1N conduct currents I, 2I, 3I, . . . , NI. Hence, parallel transistors are added (indicated by 1×, 2×, 3×, . . . , N× in FIG. 7) to MOS transistors M11, M12, M13, . . . , M1N to maintain a same current I through the unitary MOS transistors of each cell.
The temperature sensor circuit 702 includes a feedback loop 720 around the initial cell 735. The temperature sensor circuit 702 uses the feedback loop 720 for precise replication of a voltage created by BJT Q1 741 and BJT Q 742. The feedback loop 720 includes a differential amplifier 723. A non-inverting input terminal of the differential amplifier 723 is coupled to a drain terminal of MOS transistor M1. An inverting input terminal of the differential amplifier 723 is coupled to an emitter terminal of BJT Q1 741 at which VBE1 is present. An output terminal of the differential amplifier 723 is coupled to a gate of MOS transistor M3. The differential amplifier 723 outputs control voltage VC. The gain of the feedback loop 720 is selected to be high enough so that the systematic offset can be neglected. In most respects, the temperature sensor circuit 702 is similar to the bandgap voltage reference circuit 602; therefore, only the differences will be emphasized hereinafter.
In the temperature sensor circuit 702, MOS transistor M1N is stacked on top of ground potential rather than stacked on top of a BJT (as in the bandgap voltage reference circuit 602). In the temperature sensor circuit 702, the stack of cascaded cells is referenced to ground to create a PTAT output. As a result, the output, VPTAT, is a voltage that is proportional to temperature. In the temperature sensor circuit 702, VPTAT=N·ΔVBE because the N stacked cells start at ground potential, i.e., the source terminal of MOS transistor M1N is at ground potential.
With the temperature sensor circuit 702, a threshold is detectable at a crossing between VBE and N·ΔVBE signals.
In one embodiment, VPTAT is coupled to a non-inverting input terminal of a comparator 750. Another voltage VCTAT, such as VBE of BJT Q2 742, is coupled to an inverting input terminal of the comparator 750. The comparator 750 toggles an over-temperature flag OTFLAG when VPTAT and VCTAT have a same value.
In another embodiment (not shown), a temperature sensor circuit, which is otherwise similar to the temperature sensor circuit 702, is built using the first type of cell 102 instead of the second type of cell 202; however, in such other embodiment, the MOS transistors are re-oriented and there is polarity changed in a manner known by a person skilled in the art.
To be technically accurate, VGS, used hereinabove, should be interpreted to mean |VGS|, and VBE, used hereinabove, should be interpreted to mean |VBE|. This is because, for PMOS transistors and PNP BJTs, VSG (VSG=VS−VG) instead of VGS, and VEB (VEB=VE−VB) instead of VBE, respectively, should be used to represent positive voltages.
Each of the circuits in accordance with the present invention is implemented, in one embodiment, as an integrated circuit disposed on a silicon substrate.
In another embodiment (not shown), the circuits in accordance with the present invention can be used to amplify any differential voltage signal including those that are not related to BJTs, provided that such differential voltage signal falls within the range 308 shown in FIG. 3.
In another embodiment (not shown), the circuits in accordance with the present invention can be used to amplify a single-ended signal because a single-ended signal can be viewed as a differential voltage with respect to ground potential or VDD.
Advantageously, the behavior of the output of the circuits in accordance with the present invention is not significantly dependent on MOS transistor operation region or process corners provided that a magnitude of ΔVBE is within a range over which ΔVGS may adjusted through control voltage VC.
Advantageously, the circuits in accordance with the present invention are not sensitive to MOS transistor parameters other than matching of MOS transistors, and, therefore, are not subject to some of the sources of distortion that adversely affect known circuits.
Advantageously, the circuits in accordance with the present invention compensate for systematic offsets (process deviations, model inaccuracies, etc.).
Compared to known circuits that employ resistors, the circuits in accordance with the present invention improve a power/area trade-off for low-power circuits. This results in lower cost (lower area usage for given power) or better performance (lower power for a given area). For example, when fabricated using 180 nm process, a circuit in accordance with the present invention encompasses an area one-eight the size of a similar circuit that employs resistors. Compared with known resistor-less circuits, the circuits in accordance with the present invention enable higher accuracy figures because such circuits are insensitive to process and other systematic sources of error.
Cascodes and/or other similar techniques may be added to the circuits in accordance with the invention, if needed, to reduce systematic offset.
To further improve accuracy, trimming structures may be added to the circuits in accordance with the present invention.
The term “coupled”, as used herein, is defined as “connected”, and encompasses the coupling of devices that may be physically, electrically or communicatively connected, although the coupling may not necessarily be directly, and not necessarily be mechanically. The term “configured to” describes hardware, software or a combination of hardware and software that is adapted to, set up, arranged, built, composed, constructed, designed or that has any combination of these characteristics to carry out a given function. The term “adapted to” describes hardware, software or a combination of hardware and software that is capable of, able to accommodate, to make, or that is suitable to carry out a given function.
The terms “a” or “an”, as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an”. The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The term “coupled”, as used herein, is not intended to be limited to a direct coupling or a mechanical coupling, and that one or more additional elements may be interposed between two elements that are coupled. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
The Detailed Description section, and not the Abstract section, is intended to be used to interpret the claims. The Abstract section may set forth one or more but not all embodiments of the invention, and the Abstract section is not intended to limit the invention or the claims in any way.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

## Claims

1. A resistor-less amplifying circuit configured to receive an input voltage, comprising:
a plurality of resistor-less cells comprising MOS transistors; and
a closed loop around at least one cell, wherein
a value of a control voltage is adjusted, by feedback through the closed loop,
each cell generates an output signal of the cell equal to a difference between gate-to-source voltages (ΔVGS) of two MOS transistors,
a magnitude of ΔVGS is controlled by the control voltage, and
the magnitude of ΔVGS is made equal to the input voltage.

2. The resistor-less amplifying circuit of claim 1, in which an output signal of the resistor-less amplifying circuit consists of a sum of the output signals generated by each cell.

3. The resistor-less amplifying circuit of claim 2, in which the resistor-less amplifying circuit has N cells, and including a closed loop around K cells, where K is less than N.

4. The resistor-less amplifying circuit of claim 3, including a closed loop around one cell.

5. The resistor-less amplifying circuit of claim 4, in which the output signal of the resistor-less amplifying circuit is equal to the input voltage multiplied by an integer.

6. The resistor-less amplifying circuit of claim 3, including a closed loop around two cells.

7. The resistor-less amplifying circuit of claim 6, in which the output signal of the resistor-less amplifying circuit is equal to the input voltage multiplied by a non-integer.

8. The resistor-less amplifying circuit of claim 1, wherein each cell is identical in structure and is biased identically.

9. The resistor-less amplifying circuit of claim 1, in which the input voltage is a differential input voltage, and in which each cell includes:
a first MOS transistor,
a second MOS transistor, and
a third MOS transistor,
wherein the first and second MOS transistors of each cell generate ΔVGS.

10. The resistor-less amplifying circuit of claim 9, in which the input voltage is a differential input voltage, and in which a first cell includes:
a first MOS transistor,
a second MOS transistor having a gate for receiving one end of the differential input voltage, and
a third MOS transistor,
and in which the closed loop includes a differential amplifier having an inverting input terminal for receiving another end of the differential input voltage, a non-inverting input terminal coupled to a gate of the first MOS transistor, and an output terminal coupled to a gate of the third MOS transistor.

11. The resistor-less amplifying circuit of claim 10, in which the first MOS transistor has a gate coupled to the non-inverting input terminal of the differential amplifier, and a source terminal coupled to a current source, and is configured as a diode,
the second MOS transistor has a drain terminal coupled to VDD and a source terminal coupled to the current source, and
the third MOS transistor has a gate coupled to the output terminal of the differential amplifier, a source terminal coupled to VDD and a drain terminal coupled to drain and gate terminals of the first MOS transistor.

12. The resistor-less amplifying circuit of claim 1, in which the input voltage has proportional-to-absolute-temperature (PTAT) behavior and in which each cell has PTAT behavior.

13. An integrated circuit, comprising:
a substrate having a bandgap voltage; and
a bandgap voltage reference circuit disposed on the substrate, the bandgap voltage reference circuit including:
a plurality of resistor-less cells, each cell including MOS transistors, wherein each cell generates a proportional-to-absolute-temperature (PTAT) voltage and wherein the plurality of cells generates a sum of the PTAT voltages generated by each cell,
a device, coupled to the plurality of cells, the device having a complementary-to-absolute-temperature (CTAT) voltage associated therewith,
connections for adding the CTAT voltage and the sum of the PTAT voltages generated by each cell, and
an output terminal for providing a temperature-independent voltage reference at the bandgap voltage.

14. The integrated circuit of claim 13, in which each cell is identical in structure and is biased identically.

15. The integrated circuit of claim 14, in which each cell includes:
a first MOS transistor,
a second MOS transistor having a gate for receiving the CTAT voltage, and
a third MOS transistor, and
wherein the PTAT voltage is a difference between a gate-to-source voltage of the first MOS transistor a gate-to-source voltage of the second MOS transistor (ΔVGS).

16. The integrated circuit of claim 15, including a closed loop around at least one cell, wherein a magnitude of ΔVGS is controlled by feedback through the closed loop.

17. The integrated circuit of claim 16, in which the closed loop includes a differential amplifier having
an inverting input terminal for receiving another CTAT voltage,
a non-inverting input terminal coupled to a gate of the first MOS transistor, and
an output terminal coupled to a gate of the third MOS transistor.

18. A bandgap voltage reference circuit for providing a temperature-independent voltage reference (VREF), comprising:
a first bipolar junction transistor (BJT) having a first base-to-emitter voltage VBE1, and a second BJT having a second base-to-emitter voltage VBE2, wherein the first and second bipolar transistors operate at different emitter current densities and generate a ΔVBE=|VBE1−VBE2|;
at least one resistor-less cell including:
a first MOS transistor,
a second MOS transistor having a gate for receiving VBE2, and
a third MOS transistor; and

a feedback loop including a differential amplifier having an inverting input terminal for receiving VBE1, a non-inverting input terminal coupled to a gate of the first MOS transistor, and an output terminal coupled to a gate of the third MOS transistor,
wherein each cell generates a difference between a gate-to-source voltage of the first MOS transistor and a gate-to-source voltage of the second MOS transistor (ΔVGS), and wherein a value of a control voltage outputted by the differential amplifier causes ΔVGS of each cell to equal ΔVBE.

19. The bandgap voltage reference circuit of claim 18, in which each cell is identical in structure and is biased identically.

20. The bandgap voltage reference circuit of claim 18, in which VREF consists of VBE2 plus a sum of each ΔVBE generated by each cell.