Rainee N. Simons

QSS Group, Inc., Cleveland, Ohio

Kavita Goverdhanam

Bell Laboratories, Murray Hill, New Jersey

Linda P.B. Katehi

University of Michigan, Ann Arbor, Michigan

Novel Low Loss Wide-Band Multi-Port

Integrated Circuit Technology for

RF/Microwave Applications

NASA/CR—2001-209679

June 2001
The NASA STI Program Office . . . in Profile

Since its founding, NASA has been dedicated to

the advancement of aeronautics and space

science. The NASA Scientific and Technical

Information (STI) Program Office plays a key part

in helping NASA maintain this important role.

The NASA STI Program Office is operated by

Langley Research Center, the Lead Center for

NASA’s scientific and technical information. The

NASA STI Program Office provides access to the

NASA STI Database, the largest collection of

aeronautical and space science STI in the world.

The Program Office is also NASA’s institutional

mechanism for disseminating the results of its

research and development activities. These results

are published by NASA in the NASA STI Report

Series, which includes the following report types:

• TECHNICAL PUBLICATION. Reports of

completed research or a major significant

phase of research that present the results of

NASA programs and include extensive data

or theoretical analysis. Includes compilations

of significant scientific and technical data and

information deemed to be of continuing

reference value. NASA’s counterpart of peerreviewed formal professional papers but

has less stringent limitations on manuscript

length and extent of graphic presentations.

• TECHNICAL MEMORANDUM. Scientific

and technical findings that are preliminary or

of specialized interest, e.g., quick release

reports, working papers, and bibliographies

that contain minimal annotation. Does not

contain extensive analysis.

• CONTRACTOR REPORT. Scientific and

technical findings by NASA-sponsored

contractors and grantees.

• CONFERENCE PUBLICATION. Collected

papers from scientific and technical

conferences, symposia, seminars, or other

meetings sponsored or cosponsored by

NASA.

• SPECIAL PUBLICATION. Scientific,

technical, or historical information from

NASA programs, projects, and missions,

often concerned with subjects having

substantial public interest.

• TECHNICAL TRANSLATION. Englishlanguage translations of foreign scientific

and technical material pertinent to NASA’s

mission.

Specialized services that complement the STI

Program Office’s diverse offerings include

creating custom thesauri, building customized

data bases, organizing and publishing research

results . . . even providing videos.

For more information about the NASA STI

Program Office, see the following:

• Access the NASA STI Program Home Page

at http://www.sti.nasa.gov

• E-mail your question via the Internet to

help@sti.nasa.gov

• Fax your question to the NASA Access

Help Desk at 301–621–0134

• Telephone the NASA Access Help Desk at

301–621–0390

• Write to:

 NASA Access Help Desk

 NASA Center for AeroSpace Information

 7121 Standard Drive

 Hanover, MD 21076
June 2001

National Aeronautics and

Space Administration

Glenn Research Center

Prepared under Contract NAS3–00145

Prepared for the

2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

cosponsored by the IEEE MTT-S, ARO, NASA GRC, and NSF

Ann Arbor, Michigan, September 12–14, 2001

Novel Low Loss Wide-Band Multi-Port

Integrated Circuit Technology for

RF/Microwave Applications

NASA/CR—2001-209679

Rainee N. Simons

QSS Group, Inc., Cleveland, Ohio

Kavita Goverdhanam

Bell Laboratories, Murray Hill, New Jersey

Linda P.B. Katehi

University of Michigan, Ann Arbor, Michigan
Acknowledgments

The authors are grateful to ONR (N00014–95–1–0546) for their support.

Available from

NASA Center for Aerospace Information

7121 Standard Drive

Hanover, MD 21076

National Technical Information Service

5285 Port Royal Road

Springfield, VA 22100

Available electronically at http://gltrs.grc.nasa.gov/GLTRS

This report contains preliminary

findings, subject to revision as

analysis proceeds.

Trade names or manufacturers’ names are used in this report for

identification only. This usage does not constitute an official

endorsement, either expressed or implied, by the National

Aeronautics and Space Administration.
NASA/CR—2001-209679 1

Abstract – In this paper, novel low loss, wide-band coplanar

stripline technology for RF/microwave integrated circuits is

demonstrated on high resistivity silicon wafer. In particular,

the fabrication process for the deposition of spin-on-glass

(SOG) as a dielectric layer, the etching of microvias for the

vertical interconnects, the design methodology for the

multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits

with very low loss, large bandwidth and compact size are

feasible using this technology. This multilayer planar

technology has potential to significantly enhance

RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems

(MEMS).

I. INTRODUCTION

Recently, silicon/silicon germanium (Si/SiGe) based

technology has emerged as a viable approach for integrating

analog, RF and digital functions on a single integrated

circuit (IC) needed for advanced wireless communications

systems [1]. The Si/SiGe technology also has the advantage

of low cost since the devices and circuits are fabricated

using established silicon CMOS processes. The above ICs

are now being introduced in products with more functions

in a small volume, involving greater circuit/function

integration. To accomplish this goal, multiport threedimensional interconnects are needed.

In this paper, we present several new design concepts for

low loss, wide bandwidth multiport integrated circuits on a

high resistivity (HR) silicon wafer. The multiport circuits

are made of small sections of coplanar stripline (CPS) or a

junction formed by the intersection of several CPS

interconnects printed at two levels separated by a thin layer

of spin-on-glass (SOG) and connected by metallized vias.

The CPS has the advantage of eliminating backside

processing due to its uniplanar nature and allows simplified

vertical integration by the use of metallized vias.

In addition, CPS allows easy integration of other

transmission media, such as, slotline, finite width coplanar

waveguide (FW-CPW) and micro-CPS [2] for greater

design flexibility. The SOG has the advantage of low

dielectric constant [3] and hence low parasitic coupling

capacitance. In addition, the SOG planarizes the circuit,

facilitating vertical integration [4]. The HR silicon wafer

 

1

NASA Glenn Research Center, QSS, Inc., Cleveland, Ohio 44135

2

Bell Laboratories, Lucent Technologies, Murray Hill, New Jersey 07974.

3

University of Michigan, Radiation Laboratory, EECS Department,

 Ann Arbor, Michigan 48109–2122.

(r > 3000 W cm) has the advantage of lowering signal

attenuation in addition to improving isolation between

adjacent circuits. In the following sections, first, the

fabrication process is briefly explained. Next, design

considerations, measured insertion loss, return loss and

isolation are presented for: (a) a two-port CPS overpass

with vertical interconnect, (b) a three-port CPS T-junction

with vertical interconnect and (c) a four-port CPS

crossover. The results are discussed extensively. The

numerical simulations are carried out using the CST

Microwave StudioTM*

. In the simulations, the CPS

conductors are assumed to be perfectly conducting. In

addition, the silicon substrate as well as the SOG layer are

considered as perfect dielectrics.

II. INTERCONNECT FABRICATION

The first step is the fabrication of the buried strip

conductors using titanium/gold on the HR silicon wafer.

These conductors are fabricated using a lift-off process. The

thickness of the metal is about 0.8 mm. Next, a thin insulating spacer layer to support the elevated strip conductors is

built-up to the required thickness by multiple spin-coats.

Accuglass® 512 SOG of thickness h1 about 2.0 mm is used

as the dielectric spacer layer. Third, the vias for the vertical

interconnect is patterned using photoresist and dry etched in

a fluorocarbon-based plasma. As a last step, the elevated

strip conductors are fabricated using titanium/gold by a

second lift-off process. This step also metallizes the via

holes to ensure electrical continuity between the buried and

elevated strip conductors. The thickness of the elevated

strip conductor is about 2.0 mm. The cross-section of the

CPS is shown in Fig. 1.

 

*

Registered Trademark of CST of America, Inc., Wellesley, MA.

NOVEL LOW LOSS WIDE-BAND

MULTI-PORT INTEGRATED CIRCUIT

TECHNOLOGY FOR RF/MICROWAVE

APPLICATIONS

Rainee N. Simons,1 Kavita Goverdhanam,2 and Linda P.B. Katehi3

Figure 1.—Coplanar stripline (CPS) on a HR-silicon 

 wafer with a SOG layer on top, h = 400 m, 

 r = 11.7, h1 = 2 m, r1 = 3.1.

SOG layer

HR-silicon 

wafer h1

h

W W

0

0

0r1

S

0r
NASA/CR—2001-209679 2

III. DESIGN, RESULTS AND DISCUSSIONS

The design considerations for the via hole and probe pads

for each of the aforementioned interconnects are as follows:

each via is symmetrically located on the strip conductor and

has a diameter (d) which is a function of the strip width

(W). A via pair is designed as a small section of a vertical

balanced transmission line with characteristic impedance

Z0(via) = 50 W. The Z0(via) is related to the diameter (d),

separation between vias (S1) and the dielectric constant of

the medium surrounding the via (er1) through the

expression:

Z0(via) = (60/sqrt(er1))cosh–1(N)

where N = 0.5[(2S1/d)2

-2].

The probe pads are about 100¥100 mm in size for

compatibility with the signal-ground RF probes for onwafer characterization. In all of the measurements the

parasitics associated with the probe pads and the 700 mm

long lines between the pads and the circuits are

de-embedded using on-wafer CPS Thru-Reflect-Line (TRL)

calibration standards. The coplanar stripline circuits

investigated here are uniplanar in construction and hence do

not have a ground plane on the opposite side of the wafer.

Therefore, the wafer is supported on a StyrofoamTM block,

instead of the regular metal vacuum chuck, in the RF probe

station while measuring the S-parameters.

A. Two-port CPS overpass with vertical interconnect:

This circuit is shown in Fig. 2. The characteristic

impedance Z0(CPS) is 50 W. The length of the overpass is

>(2W+S) to ensure a clear passage below for a 50 W line.

The measured (de-embedded) and simulated insertion loss

(S21) and return loss (S11) are shown in Fig. 3. The S21 and

S11 are better than –0.5 and –22.0 dB, respectively. The S21

includes losses due to the 216 mm long CPS overpass and

the vias at either ends. The loss in the 216 mm line is

0.08 dB at the center frequency of 10.0 GHz [4]. Hence the

loss per via pair is about 0.21 dB. The numerical

simulations of this circuit show that the insertion loss is

negligibly small and the return loss is better than –35 dB

across the 3 to 18 GHz frequency range.

B. Three-port CPS T-junction with vertical interconnect:

A schematic and a microphotograph of the circuit are

shown in Figs. 4(a) and 4(b), respectively. From the

microphotograph it is seen that the width of the elevated

strip conductor is reduced by symmetrically notching out a

rectangular portion of the strip at the location of the overlap

with the buried strip conductor. The notch compensates for

the parasitic parallel plate capacitance at the overlap region.

The characteristic impedance Z0(CPS) of each arm is = 50 W.

No attempt was made to match the junction in the initial

investigation. Contrary to a conventional slotline

T-junction, the new circuit can provide equal phase at both

output ports.

The measured (de-embedded) and simulated insertion loss

(S21 and S31) at the two output ports and the input return loss

(S11) are shown in Fig. 5. It is observed that the power

output from ports 2 and 3 are unequal but it is within

–3.0±0.5 dB over the frequency range of 8.5 to 9.5 GHz.

The phase of S21 and S31 differ by 20∞ at the center

frequency f0 = 9.0 GHz. The above insertion loss includes

the losses associated with the right angle bend integrated at

the output ports of the circuit to facilitate in-line

characterization using straight CPS TRL calibration

standards and RF probes. The numerical simulations show

that the power output from ports 2 and 3 (S21 and S31) are

about –3.5 dB and the return loss (S11) is about –9.5 dB

across the frequency range of 1 to 18 GHz.

Figure 2.—CPS overpass with vertical interconnects, 

 W = 54 m, S = 4 m, d = 45 m and L = 216 m.

SOG

HR-silicon wafer

S

W

Over pass

Ground signal

probe pads

Port #1

Port #2 d

Metalized VIA

L

S1

Figure 3.—Measured (de-embedded) and 

 simulated insertion loss (S21) and return 

 loss (S11) of CPS overpass.

0 3 18 6 9 12 15 –50

0

–40

–30

–20

Return loss (dB) –10

–10

–6

–8

–4

–2

Insertion loss (dB)

0

Frequency (GHz)

S21

S

Simulated

Simulated

11
NASA/CR—2001-209679 3

C. Four-port CPS crossover with vertical interconnect:

A schematic and a microphotograph of the circuit are

shown in Figs. 6(a) and 6(b), respectively. The simulated

characteristics using FDTD technique are presented in [4].

In this paper, the experimentally characterized results are

reported. The measured (de-embedded) and simulated

insertion loss (S21) and return loss (S11) of the in-line ports

are better than –0.5 and –30.0 dB, respectively (Fig. 7). The

measured (de-embedded) and simulated isolation (S31)

between the orthogonal ports is better than –45.0 dB up to

8.0 GHz and is –22.0 dB at 18.0 GHz (Fig. 8). The

numerical simulations show that insertion loss (S21)

negligibly small and the return loss (S11) is better than

–45 dB across the 1 to 18 GHz frequency range. The

isolation (S31) is also better than –45 dB across the same

frequency range. Since this interconnect has low loss and

excellent isolation, it has potential applications in the

construction of multilayer CPS circuits [5] and MEMSbased actuators for reconfigurable antennas [6].

Figure 4(a).—CPS T-junction with vertical interconnects, 

 W = 40 m, S = 3 m, d = 45 m and L = 243 m.

SOG

HR-silicon wafer

S

W

Port #1

Port #2

Port #3 d

Metal Strip

L

Figure 4(b).—Microphotograph of CPS T-junction.

Figure 6(a).—CPS Vertically interconnected overpass, 

 with crossover W = 40 m, S = 3 m, d = 33 m and

 L = 243 m.

S

SOG

HR-silicon wafer

W

Over pass

Port #1

Port #4 Port #2

Port #3

d

L

Figure 6(b).—Microphotograph of CPS overpass with

 crossover.

0 3 18 6 9 12 15

Frequency (GHz)

Figure 5.—Measured (de-embedded) and simulated

 insertion loss (S21 and S31) and input return loss

 (S11) of CPS T-junction.

–25

0

–15

–5

–30

Return loss (dB)

–20

–10

S21

S31

S11

–18

–9

–15

–6

–3

Insertion loss (dB)

0

–12

Simulated
NASA/CR—2001-209679 4

IV. CONCLUSIONS

A novel low loss wide bandwidth multiport integrated

circuit technology suitable for applications at RF/

microwaves has been proposed. These CPS multiport

circuits have small dimensions compared to the wavelength

of operation, resulting in low parasitics. Consequently these

circuits have an almost ideal performance with low loss,

good impedance match, good isolation and large bandwidth. As examples, a two-port CPS overpass with vertical

interconnect, a three-port CPS T-junction with vertical

interconnect and a four-port CPS crossover with vertical

interconnect have been presented. The results presented

demonstrate the potential of the proposed approach in

enhancing Si/SiGe RF/microwave IC performance.

V. REFERENCES

[1] J. Browne, “SiGe Technology Makes Practical Advances,”

(Special Report), Microwaves & RF, vol. 38, no. 10, pp. 121–126,

Oct. 1999.

[2] K. Goverdhanam, R.N. Simons, and L.P.B. Katehi, “MicroCoplanar Striplines-New Transmission Media for Microwave

Applications,” 1998 IEEE MTT-S Inter. Microwave Symp., Dig.,

vol. 2, Baltimore, Maryland, pp. 1035–1038, 1998.

[3] Accuglass“ 512 Spin-on-Glass (SOG), Product Bulletin, AlliedSignal Inc., Planarization and diffusion products, 1090 S. Milpitas

Blvd., Milpitas, California 95035.

[4] K. Goverdhanam, R.N. Simons, and L.P.B. Katehi, “Novel ThreeDimensional Vertical Interconnect Technology for Microwave and

RF Applications,” 1999 IEEE MTT-S Inter. Microwave Symp., Dig.,

vol. 2, Anaheim, California, pp. 641–644, 1999.

[5] L.P.B. Katehi, J.F. Harvey, and K.J. Herrick, “3-D Integration of

RF Circuits Using Si Micromachining,” IEEE Microwave Magazine,

vol. 2, no. 1, pp. 30–39, March 2001.

[6] R.N. Simons, D. Chun and L.P.B. Katehi, “Microelectromechanical Systems (MEMS) Actuators for Antenna Reconfigurability,” 2001 IEEE MTT-S Inter. Microwave Symp., Dig.,

vol.1, Phoenix, Arizona, pp. 215–218, 2001.

Figure 7.—Measured (de-embedded) and simulated

 insertion loss (S21) and return loss (S11) of CPS 

 overpass with crossover.

0 3 18 6 9 12 15 –80

0

–60

–40

–20

Return loss (dB)

Frequency (GHz)

S21

S11

Simulated

Simulated

–10

–6

–8

–4

–2

Insertion loss (dB)

0

Figure 8.—Measured (de-embedded) and simulated

 coupling (S31) of CPS overpass with crossover.

0 3 18 6 9 12 15 –80

0

–60

–40

–20

Coupling (dB)

Frequency (GHz)

S31

Simulated
This publication is available from the NASA Center for AeroSpace Information, 301–621–0390.

REPORT DOCUMENTATION PAGE

2. REPORT DATE

19. SECURITY CLASSIFICATION

 OF ABSTRACT

18. SECURITY CLASSIFICATION

 OF THIS PAGE

Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources,

gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this

collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson

Davis Highway, Suite 1204, Arlington, VA 22202-4302, and to the Office of Management and Budget, Paperwork Reduction Project (0704-0188), Washington, DC 20503.

NSN 7540-01-280-5500 Standard Form 298 (Rev. 2-89)

Prescribed by ANSI Std. Z39-18

298-102

Form Approved

OMB No. 0704-0188

12b. DISTRIBUTION CODE

8. PERFORMING ORGANIZATION

 REPORT NUMBER

5. FUNDING NUMBERS

3. REPORT TYPE AND DATES COVERED

4. TITLE AND SUBTITLE

6. AUTHOR(S)

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)

11. SUPPLEMENTARY NOTES

12a. DISTRIBUTION/AVAILABILITY STATEMENT

13. ABSTRACT (Maximum 200 words)

14. SUBJECT TERMS

17. SECURITY CLASSIFICATION

 OF REPORT

16. PRICE CODE

15. NUMBER OF PAGES

20. LIMITATION OF ABSTRACT

Unclassified Unclassified

Final Contractor Report

Unclassified

1. AGENCY USE ONLY (Leave blank)

10. SPONSORING/MONITORING

 AGENCY REPORT NUMBER

9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES)

National Aeronautics and Space Administration

Washington, DC 20546–0001

Available electronically at http://gltrs.grc.nasa.gov/GLTRS

June 2001

NASA CR—2001-209679

E–12024–2

WU–755–08–0B–00

NAS3–00145

Coplanar waveguide; Stripline circuits; High resistivity silicon; Spin-on-glass; 10

Monolithic microwave integrated circuits

Unclassified -Unlimited

Subject Category: 33 Distribution: Nonstandard

QSS Group, Inc.

2000 Aerospace Parkway

Brookpark, Ohio 44142

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as

a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits

and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss,

large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to

significantly enhance RF/microwave IC performance when combined with semi-conductor devices and

microelectromechanical systems (MEMS).

Rainee N. Simons, Kavita Goverdhanam, and Linda P.B. Katehi

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology

for RF/Microwave Applications

Prepared for the 2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems cosponsored by IEE MTT-S, ARO,

NASA GRC, and NSF, Ann Arbor, Michigan, September 12–14, 2001. Rainee N. Simons, QSS Group, Inc., 2000 Aerospace Parkway,

Brookpark, Ohio 44142; Kavita Goverdhanam, Bell Laboratories, Lucent Technologies, Murray Hill, New Jersey 07974; and Linda P.B.

Katehi, University of Michigan, Radiation Laboratory, EECS Department, Ann Arbor, Michigan 48109–2122. Project Manager, Thomas

P. Burke, Systems Engineering Division, NASA Glenn Research Center, organization code 7800, 216–433–5172.