# Patent

## Title
Method and apparatus for distorting duty cycle of a clock

## Abstract

An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described.

## Background
BACKGROUND
An embodiment of the invention is directed at the control of one or more clocks under which electronic circuits operate. These clocks provide a way for events affecting (or caused by) the circuit to be sequenced reliably. For example, digital circuits such as microprocessors, digital signal processors and memories rely on clocks to synchronize and drive their operations.
One long-standing trend in the development of electronic circuits is the increase in clock speeds; another is the increase in the size of electronic circuits relative to the size of the components that make up the circuit. Both of these trends increase the difficulty of providing stable, useful clock signals to all parts of the circuit (or system) that need them. Transmitting the multi-gigahertz clock signals used in modern circuits from one place in the system to another often results in degradation of the signals, so that (for example) a circuit designed to work with a 50% duty cycle clock might receive a 20% or 70% duty cycle clock. The degraded clock may cause deleterious effects ranging from increased power usage to unstable or incorrect circuit operation.
A number of techniques have been developed to stabilize or correct clock signal waveforms. For example, duty cycle correctors are described in A portable digital DLL for high-speed CMOS interface circuits by Garlepp et al. (IEEE Journal of Solid State Circuits, vol. 34, no. 5 (May 1999)) and A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM by T. H. Lee et al. (IEEE Journal of Solid State Circuits, vol. 29, no. 12 (December 1994)).



BRIEF DESCRIPTION OF DRAWINGS
Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”
FIG. 1 shows a clock generator and duty cycle distorter connected in a feedback lop, according to an embodiment of the invention.
FIG. 2 shows a current comparator that can be used to adjust the duty cycle of an input clock.
FIG. 3 shows a charge-pump circuit for detecting asymmetrical clock duty cycles.
FIGS. 4 and 5 show examples of the time-correlation of several signals in the circuit of FIG. 3.
FIG. 6 shows a clock generator and duty cycle corrector connected in a feedback loop.
FIG. 7 shows a charge-pump circuit extended with an embodiment of the invention.
FIGS. 8 and 9 shows systems that can make use of a duty cycle distorter to adjust their clocks.
FIG. 10 shows the results of simulations of an embodiment of the invention.



DETAILED DESCRIPTION OF DRAWINGS
FIG. 1 shows a clock generator and duty cycle distorter according to an embodiment of the invention. The elements shown produce, monitor, and adjust a differential clock (signals CLK_A 140 and CLK_B 150). The clock may also be used by circuits not shown in the figure (as suggested by the notation “clock-consuming circuits”). The clock generator and duty cycle distorter include oscillator 110, clock adjuster 200, and charge pump 700 connected in a feedback loop so that oscillator signals φA 120 and φB 130 can be adjusted to produce signals CLK_A 140 and CLK_B 150 under the control of feedback signals VDCC—SIGa 770 and VDCC—SIGb 780. Oscillator 110 and clock adjuster 200 together form clock generator 100, which produces a differential clock with its duty cycle regulated according to analog feedback signals VDCC—SIGa and VDCC—SIGb. The differential clock may be transmitted to clock-consuming circuits as shown, e.g., as part of a clock distribution tree.
Charge pump 700 produces feedback signals VDCC—SIGa and VDCC—SIGb based upon the duty cycle of CLK_A 140 and CLK_B 150 and variable currents IX 162 and IY 164 from n-bit digital-to-analog converter (“DAC”) current source 160. The details of the operation of charge pump 700 and the effect of variable currents IX 162 and IY 164 on its outputs are discussed in greater detail below using an example.
The functions of clock adjuster 200, depicted in FIG. 1, can be performed by a circuit such as the one shown in FIG. 2. The circuit is a current comparator that can use control signals VCTLa 270 and VCTLb 280 to adjust the duty cycle of a raw differential clock such as φA 120 and φB 130 from an oscillator circuit (not shown). VCTLa 270 and VCTLb 280 adjust the trip point of the current comparator so that φA 120 and φB 130 become CLK_A 140 and CLK_B 150, a differential clock which has a duty cycle controlled by the control signals. Other circuits could also perform the clock adjustment of FIG. 1's element 200.
Charge pump 700 shown in FIG. 1 may be based upon the circuit shown in FIG. 3. This circuit can be used to detect asymmetrical clock duty cycles. Current sources I1 through I4 (301, 302, 303 and 304) supply or remove charge from capacitors Ca (320) and Cb (321) through switches 310 and 311, which are controlled by a differential clock (CLK_A 140 and CLK_B 150). In one phase of the clock, Ca 320 charges from I1, while Cb 321 discharges to I4. In another phase, Ca 320 discharges to I3, while Cb 321 charges from I2. The charge pump produces signals VCa 370 and VCb 380 as the voltages across Ca 320 and Cb 321, respectively.
When the basic charge pump circuit of FIG. 3 is provided with a 50% duty cycle differential clock, its outputs VCa and VCb will produce signals similar to those shown in FIG. 4. There, example waveforms showing the relationship between the phases of differential clocks CLK_A 140 and CLK_B 150, the instantaneous voltages across each capacitor (VCa 370 and VCb 380), and the average voltages across each capacitor ( VCa and VCb 480) are plotted. If all the current sources are the same and the capacitors are equal, then the difference between average voltages at VCa and VCb will remain constant when the clock duty cycle is 50%. If the clock becomes distorted so that one phase is longer than the other, the difference between average voltages VCa and VCb will change, as shown in FIG. 5. In that figure, CLK_A 140 has a shortened duty cycle, while CLK_B 150 has a lengthened duty cycle. (The frequency, however, has not changed.) Because of the altered duty cycle, Ca spends more time discharging than charging (see the instantaneous voltage VCa 370), and the average value VCa, 570, tends to decrease. In a complementary fashion, Cb spends more time charging than discharging (instantaneous VCb 380); and the average value VCb, 580, tends to rise. The difference between VCa and VCb is proportional to the duty cycle distortion. Thus, the basic charge pump circuit of FIG. 3 analyzes the duty cycles of CLK_A and CLK_B and produces a signal that indicates how far the duty cycles are from a target value.
Note that the amplitudes of the sawtooth waveforms for VCa and VCb are greatly exaggerated for clarity in FIGS. 4 and 5. In a practical circuit, Ca and Cb should be large enough in relation to the current sources so that per-clock-cycle fluctuations in VCa and VCb do not cause instability in a current comparator circuit. In effect, the capacitors operate as a low-pass filter, so that the feedback signals are proportional to VCa and VCb, and not to the rapidly-fluctuating VCa and VCb. In other words, the low-pass filter reduces signal components at or above the frequency of the clock.
At equilibrium, a system such as that depicted in FIG. 6 where oscillator 110 produces signals φA 120 and φB 130; clock adjuster 200 produces adjusted signals CLK_A 140 and CLK_B 150; and charge pump 300 compares CLK_A 140 with CLK_B 150 and provides feedback signals VCa 370 and VCb 380; could be described by these equations:

ΔVCa∝I1×ta−I3×tb  Eq. 1

ΔVCb∝I2×tb−I4×ta  Eq. 2

where ΔVCa and ΔVCb are the change in voltage across Ca and Cb, respectively, in one cycle; ta is the duration of the “A” phase of the clock and tb is the duration of the “B” phase of the clock (in this example, a two-phase clock). The current sources I1-I4 in the charge pump should be fabricated near to each other on the same semiconductor chip, and may be designed to mirror a single reference current I0 (or a constant multiple of I0). This provides a great degree of temperature, voltage, and frequency independence for the charge pump distortion detector. If all current sources are identical (e.g. I1=I2=I3=I4=K×I0) and the feedback circuit operates to ensure that ΔVCa=ΔVCb, then ta=tb (in other words, CLK_A and CLK_B will operate at a 50% duty cycle).

If a fixed, non-symmetrical clock is desired, the values of the current sources can be made unequal so that the feedback signal causes the current comparator to produce the desired asymmetrical clock. For example, if I1=I4=2×K×I0 and I2=I3=K×I0, then the feedback circuit will ensure that ta=0.5 tb (33% duty cycle for CLK_A).
The clock duty cycle corrector described above with reference to FIG. 6 works well, but only clock distortions that can be detected by the charge pump can be corrected by the feedback loop. If another portion of the clock distribution tree on the same chip as the duty cycle corrector, or an off-chip component of the system, is adversely affected by clock distortion that is not detected, there is no way to incorporate an error signal proportional to that distortion into the feedback loop of FIG. 6. Embodiments of the present invention may be useful in addressing this shortcoming by incorporating a duty cycle distorter at the charge pump, as introduced in FIG. 1.
FIG. 7 shows the charge pump distortion detector of FIG. 3, augmented by variable current sources IX 162 and IY, 164, to form a duty cycle distorter according to an embodiment of this invention. IX and IY should operate under the control of a DAC (see FIG. 1). An n-bit parameter applied to the DAC causes IX and IY to transfer additional charge from Ca 320 and Cb 321 during one phase of the clock. Specifically, in the circuit depicted and for a two-phase clock, IX removes additional charge from Ca during one phase, and IY removes additional charge from Cb during the other phase. Alternate embodiments are possible wherein the controllable current sources deliver additional charge (e.g., IX and IY are placed in parallel with I1 301 and I2 302 instead of I3 303 and I4 304); or where additional charge can be transferred (delivered and removed) from only one of the capacitors. A less-favorable embodiment would deliver only one variable current to only one of the charge collectors. The currents transferred by IX and IY may be smaller than those transferred by I1 through I4. The clock phases can be distorted over a useful range when IX and IY can alter the current drawn from Ca and Cb over a range from about 50% of I1 to 150% of I1. Other ranges of operation are also possible.
When IX and IY are not active (i.e. they are set to transfer zero charge), the circuit of FIG. 7 operates identically to that of FIG. 3, and the clock duty cycle is corrected as detected by and according to the feedback loop. For a differential clock, the currents drawn (or delivered) by IX and IY should preferably be related as:

IX=+ΔI  Eq. 3

IY=−ΔI  Eq. 4

where |ΔI|<0.5×In, n ε {1,2,3,4}. Then, the equilibrium equations described above become:

ΔVCa∝I1×ta−(I3+ΔI)×tb  Eq. 5

ΔVCb∝I2×tb−(I4−ΔI)×ta  Eq. 6

and the feedback circuit operating to keep ΔVCa=ΔVCb will cause

ta×(I1+I4−ΔI)=tb×(I2−I3+ΔI)  Eq. 7

Assume a reference current I0=I1=I2=I3=I4, then from Eq. 7,




  
    
      
        
          Duty
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                t
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                I
              
              
                I
                0
              
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        8
      
    
  




Current sources IX and IY permit the equilibrium established by the feedback loop to be perturbed in a desired direction, resulting in a feedback signal that causes the clock adjuster to produce a distorted clock. For example, if IX and IY are set to transfer more charge from Ca than from Cb, then the charge pump feedback circuit will produce a signal identical to that produced if CLK_B's duty cycle had increased, and the feedback loop would operate to reduce CLK_B's duty cycle. However, since the detected increase in CLK_B's duty cycle was only apparent, and not a real increase, CLK_B's actual duty cycle would be reduced below that targeted by the unperturbed feedback circuit. Programmable current sources IX and IY cause the charge pump to detect a phantom duty cycle distortion and produce a signal that causes the real duty cycle to be distorted in an opposite amount. IX and IY permit the clock duty cycle to be adjusted under the control of a discrete integer-valued parameter applied to the DAC.
Furthermore, Equation 8 implies that control of clock duty cycle is linearly dependent on




  
    
      Δ
      ⁢
      
        
      
      ⁢
      I
    
    
      I
      0
    
  
  .




If a DAC is configured so that the n-bit control word affects IX and IY linearly, then the duty cycle of the clock can be adjusted linearly from one extreme to another according to that n-bit value. It is clear from Equation 8 that the duty cycle depends only on the ratio of currents ΔI and I0, which can easily be set to a precise constant independent of the process, voltage, and temperature variations.

Instead of producing a charge pump with four fixed current sources and two variable, DAC-controlled current sources (which, furthermore, should ideally be capable of providing both positive and negative currents), a more practical circuit would contain two fixed, mirrored current sources and two DAC-controlled current sources that can be varied over a range from about 0.5×K×Iref to about 1.5×K×Iref. In this practical circuit, setting the DAC to the middle of its range would cause the variable current sources to match the fixed current sources, while DAC settings above and below the midpoint would effectively permit positive and negative ΔI currents to be applied.
This precise numerical control over clock duty cycle may be useful in a system such as the one depicted in FIG. 8. There, processor 810, which may be a general purpose microprocessor such as the Tukwila microprocessor by Intel Corporation of Santa Clara, Calif., contains a clock generator circuit 812 and a clock distorter circuit 814 according to an embodiment of this invention, connected in a feedback loop 825. The distorter circuit monitors and controls the clock signals near the point where those signals are exported from the chip for use by other components in the system. The signals are transmitted over interconnect wires 820 to integrated circuit 830, which may be a system component such as an Advanced Memory Buffer (“AMB”). The AMB provides an interface between processor 810 and banks of random access memory (“RAM”) 840 and/or other AMBs 850.
If the clock received at an AMB is distorted for any reason (e.g. sub-optimal circuit layout or manufacturing tolerance effects) so that the AMB fails to operate reliably, the clock cycle distorter 814 can be configured by programming a value into a current DAC in the charge pump circuit to pre-distort the clock to compensate for the distortion introduced elsewhere in the system. The amount and direction of pre-distortion is selected to counteract the external distortion, so that the clock arriving at the AMB 830 is within acceptable parameters. In other words, the pre-distortion is set to be the inverse or complement of the external distortion. This clock tuning capability can improve system operational margins or even restore failed systems to functionality.
FIG. 9 shows another embodiment of the invention. Here, a first integrated circuit chip 910 contains a clock generator 812, and provides clock signals to other components 920, 930 in the system. A second integrated circuit chip 940 contains a clock distorter circuit 814. The second chip receives the clock signal and provides a feedback signal. 825 to the clock generator on the first chip, aiding the generator to produce a clock that has an acceptable duty cycle at points within the system where the clock is used. This example shows that the clock generator and clock distorter circuits need not be integrated together in the same semiconductor die (although that arrangement is possible). In fact, the generator and distorter need not even be placed on the same circuit board.
In FIG. 10 the results of a simulated clock generator and distortion introducing feedback circuit according to an embodiment of the invention are presented. In the simulated circuit, a five-bit DAC was used to control current sources IX and IY (thus, thirty two distinct values could be programmed into the DAC). The effect of the DAC control word on the dock duty cycle was plotted for simulation runs under nominal, realistic fast corner and realistic slow corner conditions. (Realistic fast and slow conditions were selected as ±3 standard deviations (±3σ) from nominal device characteristics.) The graph shows that the duty cycle can be varied with almost perfect linearity under many realistic conditions; the duty cycle was dependent only on the control word input to the DAC and was thus largely independent of process, temperature, and supply voltage.
A duty cycle distorter according to an embodiment of the invention is not merely useful in testing applications. The duty cycle distorters can be fabricated on production integrated circuits and can improve circuit and system production yields by more easily compensating for board- and system-level distortion effects. Because the adjustment is digital (e.g. an n-bit binary value) and the induced distortions are largely fabrication process independent, it is easier and less expensive to correct for unanticipated clock degradation than, for example, by reworking parts or trimming analog adjusters in every individual production IC die. Rather, once a few, or even a single, example system has been tuned by adjusting the n-bit DAC control word, the same control word can be programmed into the other instances of the system to obtain the same properly-adjusted clock signals.
The embodiments of the invention have been described largely by reference to specific examples and in terms of particular allocations of functionality to certain hardware implementations. However, those of skill in the art will recognize that clock duty cycle distortion can also be accomplished by alternate electronic circuits that achieve the objectives of the invention in other ways. For example, the techniques described above can also be applied to distort a single-ended clock. Such alternative circuits are understood to be apprehended according to the following claims.
In the following claims, the phrases “delivering current” and “transferring charge” are explicitly defined to have the following meanings, without regard to a direction indicated by a preposition such as “to” or “from” that may follow them:
“Delivering current” refers to providing a path from one node in a circuit to another node in the circuit through which current may flow.
“Transferring charge” refers to increasing or decreasing the potential of a node in a circuit by delivering current to or from the node.

## Claims

1. An apparatus comprising:
a first charge collector and a second charge collector;
a first current source, a second current source and a third current source; and
a digitally-controlled adjustable current source; wherein
the first current source is to deliver current to the first charge collector and the second current source is to deliver current from the second charge collector on a first phase of a clock signal;
the third current source is to deliver current to the second charge collector and the digitally-controlled adjustable current source is to deliver current from the first charge collector on a second phase of the clock signal; and wherein
a difference between a voltage across the first charge collector and a voltage across the second charge collector is used to alter a duty cycle of the clock signal, the duty cycle of the clock signal having a substantially linear relationship to a control word of the digitally-controlled adjustable current source.

2. The apparatus of claim 1 wherein there is a linear relationship between an adjustment of the digitally-controlled adjustable current source and the duty cycle of the clock signal.

3. The apparatus of claim 1 wherein the duty cycle of the clock is independent of an operating temperature and an operating voltage of the apparatus.

4. The apparatus of claim 1 wherein the first charge collector and the second charge collector operate as low-pass filters to attenuate signals at or above a frequency of the clock signal.

5. The apparatus of claim 1 wherein the first, second and third current sources mirror a constant multiple of a reference current.

6. The apparatus of claim 1 wherein the apparatus is integrated on a first substrate and a circuit to generate the clock signal is integrated on a second, separate substrate.

7. The apparatus of claim 1 wherein the duty cycle of the clock signal is independent of a process variation affecting the apparatus.

8. The apparatus of claim 1 wherein the apparatus is integrated on a first substrate and a circuit to generate the clock signal is integrated on the first substrate.