NASA/CR—2001-209680

June 2001

Kavita Goverdhanam

Bell Laboratories, Murray Hill, New Jersey

Rainee N. Simons

QSS Group, Inc., Cleveland, Ohio

Linda P.B. Katehi

University of Michigan, Ann Arbor, Michigan

Novel Vertical Interconnects With 180 Degree

Phase Shift for Amplifiers, Filters, and

Integrated Antennas
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Prepared under Contract NAS3–00145

Prepared for the

2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

cosponsored by the IEEE MTT-S, ARO, NASA GRC, and NSF

Ann Arbor, Michigan, September 12–14, 2001

Novel Vertical Interconnects With 180 Degree

Phase Shift for Amplifiers, Filters, and

Integrated Antennas

NASA/CR—2001-209680

Kavita Goverdhanam

Bell Laboratories, Murray Hill, New Jersey

Rainee N. Simons

QSS Group, Inc., Cleveland, Ohio

Linda P.B. Katehi

University of Michigan, Ann Arbor, Michigan
Acknowledgments

The authors are grateful to ONR (N00014–95–1–0546) for their support.

Available from

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Available electronically at http://gltrs.grc.nasa.gov/GLTRS

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NASA/CR—2001-209680 1

Abs tr act – I nt h i sp ap e r, n ovel low los s , w id e b an d w i d t h , c om p act 

cop lan ar s t rip l in e/cop lan ar w avegu id e vert ical in t e rcon n e ct sw i t h 

180°p h as e s h if tan dvert ic ally i n t ercon n ect e db alu n sf or 

R F / m icrow ave in t egrat edcir cu it sare d e m on s t r at ed . Th e

in t ercon n ect san db al u n sar e f ab r icat ed onh i ghres is t ivi t y s il icon 

w af er w it ha t h inlayer ofs p in - on - glas sasanin s u lat or b et w ee n 

t h e b u rie dan dt h e el evat ed s t rip con d u ct orsw h ichare

in t ercon n ect edb y m ic rovias . Th e m eas u r edan d s im u l at ed 

ch aract er is t ics oft h es e in t ercon n ect sare p r es en t e dan dt h ey s h ow 

t h atvery com p act , lowlos s an dw id e b an d w id t hcirc u it sare

f eas ib le w it ht h ist e ch n ology. Th ist ec h n ology h ast h e p ot en t ial t o

s ign if ican t ly e n h an ce t h e p erf orm an ce ofam p l if iers , f ilt ers , an d 

in t egrat e dan t e n n asi nS i/S iG e b as edR F /m icrow ave I C s .

I. INTRODUCTION

Silicon/silicon germanium (Si/SiGe) based RF/ microwave

integrated circuits (ICs) [1] for wireless communications/

sensors require linear amplifiers for low distortion and

filters for interference suppression. In some situations they

may also require an integrated planar antenna for

transmission/reception, in applications such as automobile

collision avoidance. The amplifiers may require a balun to

realize a push-pull circuit to suppress the second-order

intermodulation products and thus enhance the spurious

free dynamic range. The filters may require a phase inverter

for impedance transformation. The antenna such as, logperiodic dipole array may require a fixed 180° phase shift

for generating an endfire beam.

In this paper, we present several new integrated circuit

design concepts for: (a) wide bandwidth vertical

interconnects with 180o phase shift and (b) vertically

interconnected baluns. These interconnects and baluns are

fabricated on a high resistivity (HR) silicon wafer. The

vertical interconnects discussed here constitute a small

section of coplanar stripline (CPS) and coplanar waveguide

(CPW) at two levels separated by a thin layer of spin-onglass (SOG). The interconnections between the two levels

are realized by metallized vias. The CPS and CPW have the

advantages of eliminating backside processing due to

uniplanar construction, thus simplifying vertical integration

by the use of metallized vias. In addition, CPS and CPW

allow easy integration of other transmission media, such as,

slotline, and micro-CPS [2] for greater design flexibility.

The SOG has the advantage of low dielectric constant [3]

and hence low parasitic coupling capacitance. In addition,

 

1

Bell Laboratories, Lucent Technologies, Murray Hill, New Jersey 07974

2

NASA Glenn Research Center, QSS, Inc., Cleveland, Ohio 44135

3

University of Michigan, Radiation Laboratory, EECS Department,

 Ann Arbor, Michigan 48109–2122

the SOG planarizes the circuit and this facilitates vertical

integration [4]. The HR silicon wafer (r > 3000 W cm) has

the advantage of lowering the signal attenuation in addition

to improving the isolation between adjacent circuits.

In the following sections, first, the fabrication process is

briefly explained. This is followed by a discussion of the

design considerations, measured insertion loss and return

loss of the CPS vertical interconnects with 180o phase shift.

The interconnects considered are: (a) CPS vertical

interconnect with 180° phase shift, (b) CPW vertically

interconnected by CPS overpass and with 180° phase shift,

(c) CPW vertical interconnect with 180° phase shift and

(d) CPS-to-elevated CPW balun. The numerical simulations

of the circuits are carried out using the CST microwave

studioTM*

. In the simulations, the CPS and CPW conductors

are assumed to be perfectly conducting. In addition, the

silicon substrate as well as the SOG layer are considered as

perfect dielectrics. 

II. INTERCONNECT FABRICATION

As a first step in fabricating the aforementioned

interconnects, the buried strip conductors are fabricated on

the HR silicon wafer. The strip conductors are fabricated

using a lift-off process. The thickness of the titanium/gold

metal is about 0.8 mm. Next, a thin insulating spacer layer

to support the elevated strip conductors is built-up to the

required thickness using multiple spin-coats of Accuglass®

512. The thickness h1 of the SOG used here is about

2.0 mm. Following this, the vias for the vertical interconnect

are patterned using photoresist and dry etched in a

fluorocarbon-based plasma. Finally, the elevated strip

conductors are fabricated with titanium/gold by a second

lift-off process. During this step the via holes are metallized

to ensure electrical continuity between the buried and the

elevated strip conductors. The thickness of the elevated

strip conductor is about 2.0 mm. The cross-sections of the

CPS and CPW with a SOG overlay are shown in Fig. 1. 

III. DESIGN, RESULTS AND DISCUSSIONS

The design considerations for the via hole and probe pads

required for each of the aforementioned interconnects are as

follows: each via has a diameter d which is about 0.75 times

the strip width S and is symmetrically located on the strip

conductor. The probe pads in the case of CPS circuits for

on-wafer characterization using signal-ground RF probes

are about 100¥100 mm in size. In the case of CPW circuits,

 

*

Registered Trademark of CST of America, Inc., Wellesley, MA.

NOVEL VERTICAL INTERCONNECTS

WITH 180 DEGREE PHASE SHIFT

FOR AMPLIFIERS, FILTERS, AND

INTEGRATED ANTENNAS

Kavita Goverdhanam,1 Rainee N. Simons,2 and Linda P.B. Katehi3
NASA/CR—2001-209680 2

the center strip conductor as well as the ground planes are

extended to form the probe pads. These CPW interconnects

are characterized using ground-signal-ground RF probes.

The length of the CPS and the CPW between the

input/output ports of the circuit and the probe pads is

700 mm for all the circuits investigated here. The losses

associated these connecting lines and the probe pads are deembedded using on-wafer CPS and CPW Thru-Reflect-Line

(TRL) calibration standards. The coplanar stripline and

coplanar waveguide circuits investigated here are uniplanar

in construction and hence do not have a ground plane on the

opposite side of the wafer. Therefore, the wafer is

supported on a StyrofoamTM block, instead of the regular

metal vacuum chuck, in the RF probe station while

measuring the S-parameters.

A. CPS vertical interconnect with 180o phase shift:

A schematic and microphotograph of the circuit are shown

in Figs. 2(a) and 2(b), respectively. In this circuit, the strip

conductors are transposed to provide the 180°° phase shift.

This type of inter-connect is ideally suited for adding a

180° phase shift to the terminals of each element in a

log-periodic array as explained in [5]. The characteristic

impedance Z0(CPS) is 50 W.

The measured (de-embedded) and simulated insertion loss

(S21) and return loss (S11) are better than –0.5 dB and

–20.0 dB respectively over the frequency range of 3 to

18 GHz (Fig. 3). The numerical simulations of this circuit

show that the insertion loss is negligibly small and the

return loss is better than –18.0 dB across the 3 to 18 GHz

frequency range. The measured phase difference between

the CPS vertical interconnect with 180° phase shift and a

CPS through line of equivalent length is shown in Fig. 4.

The phase difference is 180° at the center frequency of

10.5 GHz and deviates from 180° by 8° at the two band

edges which are at 3 and 18 GHz respectively. The phase is

Figure 1.—Coplanar stripline (CPS) and Coplanar

 waveguide (CPW) on a HR-silicon wafer with a

 SOG overlay, h = 400 m, r = 11.7, h1 = 2 m,

 r1 = 3.1.

SOG

layer

HR-silicon

h1

h

W1 W1

0r1

0

S1

0r

0

h1

G G WSW

SOG layer

0r1

h 0r

0 HR-silicon

Simulated

Figure 3.—Measured (De-embedded) and simulated

 insertion loss (S21) and return loss (S11) of CPS 

 vertical interconnect with 180 phase shift.

0 3 18 15 –10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1296 –80

0

–60

–40

–20

Return loss (dB)

Insertion loss (dB)

Frequency (GHz)

S21

S11

Simulated

Figure 2.—(a) CPS vertical interconnect with 180 phase

 shift W1 = 65 m, S1 = 5 m, d = 40 m, L = 265 m,

 L1 = 282.1 m. (b) Microphotograph of CPS vertical

 interconnect with 180° phase shift.

h

h1

L1

Metallized

via

Twisted 

overpass

Step

compensation

SOG

CPS 

probe 

pads

d

S1

W1

W1

W1

(a) W1

L

0r1

0r

HRsilicon

(b)

°

°
NASA/CR—2001-209680 3

within ±3° from 180° over 3 GHz band centered at

10.5 GHz which results in a bandwidth of 28.5 percent.

B. CPW vertically interconnected by CPS overpass with

180o phase shift:

A s ch em a ti c a nd m ic r op ho t og r a ph of t h e ci r c u it a r e s h ow n i n

F ig s . 5 ( a) a n d 5( b) , r es p ec ti ve l y. T he c ha r ac te r is ti c

i m p ed an c e Z 0( C P S ) an d Z 0( C P W ) ar e 50 W. T he m ea s ur ed ( d ee m b ed de d ) an d s im ul a te d i ns er ti o n lo s s( S 21) a nd t h e r e t ur n

l os s( S 11) a r e s h ow n i n F i g. 6. T h e in s e r ti on lo s s a n d th e 

r et ur n l os sa r e b et t er t h an – 1.0 d B a nd – 17 .5 dB r e s p ec t iv el y 

u p to 6 .0 G H z w hi c h in c lu de st he I S M ba nd s . T h e m ax im u m 

i ns er ti o n lo s s o f th e c ir cu i t is – 1 .7 5 d B. T he m e as u r e d r e t ur n

l os s is be tt e r th an –1 3 d B ac r o s s th e e nt ir e f r e q ue nc y r an ge of 

3 t o 18 .0 G H z . T h e d is cr e pa nc ie s i n t he m ea s ur ed an d

m od el ed S - pa r am et er s a r e at tr ib u te d t o th e s im pl i f i ca ti o ns i n 

t he s im u la te d g eo m e t r y . S pe ci f i c al ly , t he c o m p en s at in g

n ot ch es in t h e el ev a te d l in es w e r e n o t in cl u de d.

C. CPW vertical interconnect with 180o phase shift:

A schematic and microphotograph of the circuit are shown

in Figs. 7(a) and 7(b), respectively. The line has a

characteristic impedance Z0(CPW) = 50 W . The measured

(de-embedded) and simulated insertion loss (S21) and the

return loss (S11) are better than –1.0 dB and –15.5 dB

respectively up to 6.5 GHz. The measured return loss is

better than –11 dB across the entire frequency range of 3 to

18.0 GHz. These characteristics are shown in Fig. 8. As in

case B, the discrepancies between measured and simulated

S-parameters are attributed to the absence of compensating

notches in the simulations.

D. CPS-to-elevated CPW balun with vertical

interconnects:

In this circuit shown in Fig. 9, the CPS and the elevated

CPW are fabricated on the HR silicon wafer and on the

SOG layer respectively. One of the strip conductors of the

CPS is extended below the SOG layer to form the buried

center strip conductor of the CPW, while the other CPS

strip conductor is terminated in a via. This via provides a

vertical interconnection to the elevated finite width ground

planes of the CPW. The elevation or the height provides an

Figure 6.—Measured (De-embedded) and simulated

 insertion loss (S21) and input return loss (S11) for 

 CPW vertically interconnected by CPS overpass 

 and with 180 phase shift.

0 3 18 151296 –50

0

–40

–30

–20

Return loss (dB) –10

Frequency (GHz)

S21

S11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

Insertion loss (dB)

Simulated

Simulated

Figure 4.—Measured phase difference between an

 equivalent CPS through line and the CPS vertical

 interconnect with 180 phase shift.

0 3 18 96 1512

Frequency (GHz)

160

170

180

190

200

Phase difference (deg)

Figure 5.—(a) CPW vertically interconnected by CPS

 overpass with 180 phase shift. W = 34 m,

 G = 239 m, S = 54 m, S1 = 4 m, d = 40 m,

 W1 = 54 m, L = 300 m. (b) Microphotograph of

 CPW vertical interconnectd by CPS overpass.

d

L

h1 h

S1

0r

0r1

W1

HR-silicon

CPW probe

pads

(a)

G

G

S

W

(b)

°

°

°
NASA/CR—2001-209680 4

Figure 9.—CPS to CPW balun with burried center strip

 conductor and vertical interconnects W = 34 m,

 G = 239 m, S = 54 m, S1 = 4 m, W1 = 54 m,

 d = 40 m.

S1

W

S G

G

W1

CPS 

probe 

pads

h1

0r

0r1

Metallized via

CPW burried strip

SOG

d

h

CPW elevated

ground plane

HR-silicon

additional design parameter which can be used first, to

obtain a target Z0, and second, to lower the attenuation as

explained in [6]. The characteristic impedance Z0(CPS) and

Z0(CPW) are both 50 W. The results for this structure will be

presented at the conference.

II. CONCLUSIONS

Novel vertical interconnects with 180° phase shift and

vertically interconnected balun for integrated circuit

applications at RF/microwaves frequencies have been

demonstrated. The vertical interconnects have small

dimensions compared to the wavelength of operation,

resulting in low parasitics. The CPS vertical interconnect

with 180° phase shift has almost ideal performance with

low loss, good impedance match, and very wide bandwidth

extending from 3 to 18 GHz. The CPW vertical

interconnects have low loss and good impedance match up

to 6.5 GHz which includes the ISM bands. The results

presented demonstrate the potential of the vertical

interconnects with 180° phase shift/baluns for amplifiers,

filters and integrated antennas in Si/SiGe based

RF/microwave ICs.

III. REFERENCES

[1] J. Browne, “SiGe Technology Makes Practical Advances,” (Special

Report), Microwaves & RF, vol. 38, no. 10, pp. 121–126, Oct. 1999.

[2] K. Goverdhanam, R.N. Simons, and L.P.B. Katehi, “Micro-Coplanar

Striplines—New Transmission Media for Microwave Applications,”

1998 IEEE MTT-S Inter. Microwave Symp., Dig., vol. 2, Baltimore,

Maryland, pp. 1035–1038, 1998.

[3] Accuglass“ 512 Spin-on-Glass (SOG), Product Bulletin, AlliedSignal Inc., Planarization and diffusion products, 1090 S. Milpitas

Blvd., Milpitas, California 95035.

[4] K. Goverdhanam, R.N. Simons, and L.P.B. Katehi, “Novel ThreeDimensional Vertical Interconnect Technology for Microwave and

RF Applications,” 1999 IEEE MTT-S Inter. Microwave Symp., Dig.,

vol. 2, Anaheim, California, pp. 641–644, 1999.

[5] C.A. Balanis, Antenna Theory Analysis and Design, Second Edition,

John Wiley & Sons, Inc., New York, 1997, Section 11.4.2, p. 555.

[6] H. Kamitsuna, “A Very Small, Low-Loss MMIC Rat-Race Hybrid

Using Elevated Coplanar Waveguides,” IEEE Microwave & Guided

Wave Lett., vol. 2 , no. 8, pp. 337–339, Aug. 1992.

Figure 7.—(a) CPW vertical interconnect with 180 phase

 shift S = 54 m, W = 34 m, G = 239 m, d = 54 m,

 L = 298 m, L1 = 230 m. (b) Microphotograph of CPW

 vertical interconnect with 180 phase shift.

d

h

h1

U-shaped

overpass

Step

compensation

SOG

CPW 

probe 

pads

0r

0r1

S

G W

G

HR-silicon

(a)

S

Metallized

via

L L 1

(b)

Figure 8.—Measured (De-embedded) and simulated

 insertion loss (S21) and input return loss (S11) for CPW 

 vertical interconnect with 180 phase shift.

0 3 18 15 –10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1296 –50

0

–40

–30

–20

Return loss (dB)

Insertion loss (dB)

–10

Frequency (GHz)

S21

Simuated

Simuated

S11

°

°

°
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Available electronically at http://gltrs.grc.nasa.gov/GLTRS

June 2001

NASA CR—2001-209680

E–12025–2

WU–755–08–0B–00

NAS3–00145

Coplanar waveguide; Stripline circuits; High resistivity silicon; Spin-on-glass; 10

Monolithic microwave integrated circuits

Unclassified -Unlimited

Subject Category: 33 Distribution: Nonstandard

QSS Group, Inc.

2000 Aerospace Parkway

Brookpark, Ohio 44142

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as

a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits

and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss,

large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to

significantly enhance RF/microwave IC performance when combined with semi-conductor devices and

microelectromechanical systems (MEMS).

Kavita Goverdhanam, Rainee N. Simons, and Linda P.B. Katehi

Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifers,

Filters, and Integrated Antennas

Prepared for the 2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems cosponsored by IEE MTT-S, ARO,

NASA GRC, and NSF, Ann Arbor, Michigan, September 12–14, 2001. Kavita Goverdhanam, Bell Laboratories, Lucent Technologies,

Murray Hill, New Jersey 07974; Rainee N. Simons, QSS Group, Inc. 2000 Aerospace Parkway, Brookpark, Ohio 44142; and

Linda P.B. Katehi, University of Michigan, Radiation Laboratory, EECS Department, Ann Arbor, Michigan 48109–2122. Project

Manager, Thomas P. Burke, Systems Engineering Division, NASA Glenn Research Center, organization code 7800, 216–433–5172.