# Patent

## Title
Multilayer pillar for reduced stress interconnect and method of making same

## Abstract

A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

## Background
FIELD OF THE INVENTION
The present invention relates generally to a multi-layer pillar and method of fabricating the same and, more particularly, to a multi-layer pillar interconnect and method of fabricating the same.
BACKGROUND OF THE INVENTION
Traditionally, high temperature C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a substrate. Conventionally, the C4 bumps are made from leaded solder, as it has superior properties. For example, the lead is known to mitigate thermal coefficient (TCE) mismatch between the package and the substrate. Accordingly, stresses imposed during the cooling cycle are mitigated by the C4 bumps, thus preventing delaminations or other damage from occurring to the chip or the substrate.
However, lead-free requirements imposed by the European Union onto electronic components are forcing manufacturers to implement new ways to produce chip-to-substrate-joints. For example, manufactures have used solder interconnects consisting of copper as a replacement for leaded solder interconnents. More specifically, another type of lead free chip-to-substrate-connection is copper pillar technology. In such joints, a solder C4 bump is replaced with a copper pillar or copper pillars plated onto a chip's Under Bump Metallization (UBM). Such connection allows plating of long (80-100 μm), small diameter (30-60 μm) copper pillars. Also, such chip to package connections are favorable since they offer higher connection density, superior electrical conductivity and allows more uniform current distribution and heat dissipating performance, and hence potentially increased reliability.
However, copper has a high Young's modulus and a high thermal expansion. This being the case, copper is not an ideal candidate for mitigating thermal coefficient (TCE) mismatch between the chip and the substrate. Accordingly, stresses imposed during the cooling cycle cannot be effectively mitigated by the copper pillars, thus resulting in fractures or delaminations or other damage to the package.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
SUMMARY OF THE INVENTION
In a first aspect of the invention a structure comprises a modulated copper pillar having at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
In another aspect of the invention, an interconnect pillar comprises an intermediate layer interposed between two copper layers. The intermediate layer has a lower modulus of elasticity than that of the two copper layers and thereby is configured to absorb stress imposed during a cooling cycle of an interconnect process which would otherwise be imparted onto a chip.
In another aspect of the invention, a method of forming a structure comprises forming a first copper layer; interrupting the forming of the first copper layer to form an intermediate layer; and forming a second copper layer on the intermediate layer. The intermediate layer has a modulus of elasticity lower than the first copper layer and the second copper layer.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention, in which:
FIG. 1 shows a first implementation of a multi-layer copper pillar in accordance with the invention;
FIG. 2 shows a second implementation of a multi-layer copper pillar in accordance with the invention;
FIG. 3 shows a third implementation of a multi-layer copper pillar in accordance with the invention;
FIG. 4 shows a fourth implementation of a multi-layer copper pillar in accordance with the invention; and
FIG. 5 shows a structure implementing the multi-layer copper pillar in accordance with the invention.



DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
The present invention relates generally to a multi-layer pillar interconnect and method of fabricating the multi-layer pillar interconnect and, more particularly, to a multi-layer pillar configured and structured to reduce stress at the joint between the pillar and a chip. In embodiments, copper pillar technology is improved by the addition of one or more layers of high ductility and low strength metal as intermediate layers. The metals, in embodiments, have a higher ductility and lower Young's modulus than copper. The addition of one or more layers of metal creates low strength, high ductility “deformation” or stress relieving regions which absorb tensile stresses generated during chip assembly (reflow) processes, e.g., during the cooling cycle of the chip-substrate joining process.
In one mechanism, the intermediate metal layers allow the pillar to tilt and/or slide to compensate for Thermal Coefficient of Expansion (TCE) mismatch between the chip and the substrate (e.g., organic laminate). This may be due to the melting of the material during the heating processes (e.g., peak temperature being about 240° C. to 270° C.). In another mechanism, the intermediate metal layers, being more ductile than copper, can absorb stresses created during the cooling cycle (which would otherwise be imparted onto the chip or copper metallurgy, itself). Thus, by implementing the structures of the invention, stresses normally transmitted to the chip will be absorbed by the intermediate metal layers in the structures of the invention, preventing chip damage and increasing module yield.
First Embodiment of the Invention
In the embodiment of FIG. 1, a multi-layer pillar in accordance with the invention is generally depicted as reference numeral 10. In embodiments, the multi-layer pillar 10 is typically between 60 to 80 microns in thickness; although any thickness for a particular application is contemplated by the invention. Accordingly, the invention should not be limited to the exemplary illustration of between 60 to 80 microns in thickness, in any of the embodiments.
The multi-layer pillar 10 includes a barrier and adhesion layer 12. In one embodiment, the barrier and adhesion layer 12 may be Titanium Tungsten (TiW); although, other barrier and adhesion materials are also contemplated by the invention. For example, as should be understood by those of skill in the art, the barrier and adhesion layer 12 can be any material which prevents diffusion of materials between a chip (shown in FIG. 5) and materials of the multi-layer pillar 10 or substrate (shown in FIG. 5).
Still referring to FIG. 1, a seed layer 14 is formed on the barrier and adhesion layer 12. In embodiments, the seed layer 14 is Chromium Copper (Cr/Cu). Alternatively, the seed layer 14 is Copper (Cu). The seed layer 14 may be formed by any conventional chemical or physical vapor deposition process (CVD or PVD). As should be understood by those of skill in the art, the seed layer 14 is used for the formation of the copper layer of the pillar, in subsequent processing steps.
A copper layer 16a is formed on the seed layer 14 to a certain height, depending on the particular application. In embodiments, the copper 16a is formed in a high-deposition-rate electroplating bath. At a predetermined time and/or height of the copper column the electroplating of copper is interrupted in order to form a low strength, high ductile layer 18a (e.g., solder-type disc layer) on the copper layer 16a. In embodiments, the formation of the copper column can be interrupted when the copper column is about 5 to 30 μm. The low strength, high ductile layer 18a is an intermediate layer of about 5 to 20 microns and more preferably 5 to 10 microns, formed by a deposition process. The deposition process may be provided by an electrolytic bath, in embodiments.
In embodiments, the low strength, high ductile layer 18a is, for example, Tin (Sn), Bismuth (Bi) or Indium (In), depending on the particular application. The Young's modulus (modulus of elasticity) of Sn is 50, the Young's modulus of Bi is 32 and the Young's modulus of In is 11; whereas, the Young's modulus of Cu is 130. Moreover, the rigidity modulus (i.e., the change of shape produced by a tangential stress) of Sn is 18, the rigidity modulus of Bi 12 and the rigidity modulus of In is 12; whereas the rigidity modulus of Cu is 48.
According to the principles of the invention, as the materials of layer 18a are less rigid (of lower strength) than copper, once formed, the entire pillar is capable of sliding or tilting to compensate for Thermal Coefficient of Expansion (TCE) mismatch between the chip and the substrate (e.g., organic laminate) during heating processes. This may be due to the melting of the material during the chip-joining processes (e.g., peak temperature being about 240° C. to 270° C.). In another mechanism, as the materials used for the layer 18a are more ductile than copper, such materials can absorb stresses created during the cooling cycle. That is, the low strength, high ductile layer 18a forms a low strength, high ductile region which absorbs forces imposed during the chip assembly and thermal excursions of the interconnect process thereby absorbing stresses that would otherwise have been transmitted to the chip or copper metallurgy. Thus, by implementing the structures of the invention, stresses normally imposed on the chip or copper metallurgy will be absorbed by layer 18a in the structures of the invention, preventing chip damage, delamination of UBM structure and increasing module yield.
In embodiments, an optional nickel barrier layer 20 (at the interface between the low strength, high ductile layer 18a and the copper layer(s)) can be used to minimize the interaction between high ductile layer 18a and the copper layer(s). In the case that the layer 18a is Sn, the reaction product between copper and tin, a material of higher electrical resistivity, is relatively thicker. In the presence of the optional nickel layer, this reaction product, a material of higher electrical resistivity, between layer 18a and the nickel layer is relatively thinner. In embodiments, the optional nickel barrier layer 20 is approximately 1.0 to 2.0 μm in thickness. In further embodiments, the optional nickel barrier layer 20 can be formed on both sides of the low strength, high ductile layer 18a to prevent a reaction between the layer 18a (e.g., solder-type disc layer) and the copper.
A copper layer 16b is formed on the low strength, high ductile layer 18a (or nickel layer 20) to form the remaining portions of the multi-layer pillar 10. Much like the copper layer 16a, a high-rate electroplating bath forms the copper layer 16b. In further embodiments, the tip of the multi-layer pillar 10 can be plated with an optional solder disc 22 to provide a connection to a substrate (FIG. 5) during a reflow process.
Second Embodiment of the Invention
In the embodiment of FIG. 2, the multi-layer pillar is generally depicted as reference numeral 10. As in the embodiment of FIG. 1, the multi-layer pillar 10 is typically between 60 to 80 microns in thickness; although any thickness for a particular application is contemplated by the invention. As discussed below, the embodiment of FIG. 2 includes two or more intermediate layers.
The multi-layer pillar 10 includes a barrier and adhesion layer 12. In one embodiment, the barrier and adhesion layer 12 may be Titanium Tungsten (TiW); although, other barrier and adhesion materials are also contemplated by the invention. Again, the barrier and adhesion layer 12 can be any material which prevents diffusion of materials between a chip (shown in FIG. 5) and materials of the pillar 10 or substrate (shown in FIG. 5).
Still referring to FIG. 2, a seed layer 14 is formed on the barrier and adhesion layer 12. In embodiments, the seed layer 14 is Chromium Copper (Cr/Cu) or Copper (Cu). The seed layer 14 may be formed by any conventional chemical or physical vapor deposition process (CVD or PVD). A copper layer 16a is formed on the seed layer 14 to a certain height, depending on the particular application. In embodiments, the copper layer 16a is formed in a high-rate electroplating bath. In embodiments, the formation of the copper layer 16a can be interrupted when the copper column is about 5 to 30 μm.
As discussed above, prior to the formation of the entire pillar 10, the electroplating of copper is interrupted in order to form a low strength, high ductile layer 18a (e.g., solder-type disc layer) on the copper layer 16a. In embodiments, the high ductile metal 18a is an intermediate layer of about 5 to 20 microns and more preferably 5 to 10 microns, formed by a deposition process. The deposition process may be provided by an electrolytic bath, in embodiments. In embodiments, the high ductile metal layer 18a is, for example, Tin (Sn), Bismuth (Bi) or Indium (In), depending on the particular application.
In embodiments, an optional nickel barrier layer 20 (represented as the interface between the low strength, high ductile layer 18a and the copper layer(s)) can be used to prevent the interaction between high ductile layer 18a and the copper layer(s). In the case that layer 18a is Sn, the reaction product between copper and tin, a material of higher electrical resistivity, is relatively thicker. In presence of the optional nickel layer, this reaction product, a material of higher electrical resistivity, between layer 18a and the nickel layer is relatively thinner minimize the interaction between high ductile layer 18a and the copper layer(s). In embodiments, the optional nickel barrier layer is approximately 1.0 to 2.0 μm in thickness. In further embodiments, the optional nickel barrier layer 20 can be formed on both sides of the intermediate layer or layers to prevent a reaction between the intermediate layers (e.g., solder-type disc layer) and the copper.
A second copper layer 16b is formed on the low strength, high ductile layer 18a (or nickel layer) to form an additional portion of the multi-layer pillar 10. As with the copper layer 16a, the copper layer 16b can be formed in a high-rate electroplating bath. The electroplating of copper is interrupted again to form a second low strength, high ductile layer 18b (e.g., solder-type disc layer) on the copper layer 16b. In embodiments, the formation of the copper layer 16b can be interrupted when the copper column is about 10 to 30 μm.
In embodiments, the low strength, high ductile layer 18b is an intermediate layer of about 5 to 20 microns and more preferably 5 to 10 microns, formed by a deposition process. The deposition process may be provided by an electrolytic bath, in embodiments. In embodiments, the low strength, high ductile layer 18b is, for example, Tin (Sn), Bismuth (Bi) or Indium (In), depending on the particular application.
Again, according to the principles of the invention, as the materials of layers 18a, 18b are less rigid (of lower strength) than copper, once formed, the entire pillar is capable of sliding or tilting to compensate for Thermal Coefficient of Expansion (during heating processes) mismatch between the chip and the substrate (e.g., organic laminate). In another mechanism, as the materials used for the layers 18a, 18b are more ductile than copper, such materials can absorb stresses created during the cooling cycle. That is, the layers 18a, 18b form a low strength, high ductile region which absorb forces imposed during the chip assembly and thermal excursions thereby absorbing stresses that would otherwise have been transmitted to the chip or copper metallurgy. Thus, by implementing the structures of the invention, stresses normally transmitted to the chip or copper metallurgy will be absorbed by the layers 18a, 18b in the structures of the invention, thereby preventing delamination of the UBM layers.
A copper layer 16c is formed on the low strength, high ductile layer 18b (or nickel layer) to form the remaining portion of the multi-layer pillar 10. As with the copper layers 16a and 16b, the copper layer 16c can be formed in a high-rate electroplating bath. In embodiments, the formation of the copper layer 16c can be interrupted when the copper column is about 20 to 30 μm. Additionally, an optional nickel layer 20 may be formed at the interfaces between the low strength, high ductile layer 18b and the copper layers 16b, 16c to prevent a reaction between the intermediate layer 18b (e.g., solder-type disc layer) and the copper layers 16b, 16c. In an optional embodiment, the tip of the multi-layer pillar 10 can be plated with an optional solder disc 22 to provide a connection to a substrate (FIG. 5) during a reflow process.
In the embodiments of FIGS. 1 and 2, the number, position and thickness of the low strength, high ductile layers can vary according to technology application and space (e.g. chip size, number of C4 type connections, position of C4 connections on the chip, etc.). Additionally, the above materials for the low strength, high ductile layers can vary depending on the technology, noting that the modulus of elasticity should be lower than that of copper. Also, the number of modulated pillars in accordance with the invention deposited onto a single Under Bump Metallization (UBM) may vary depending on the particular application.
Third Embodiment of the Invention
FIG. 3 shows a third embodiment in accordance with the invention. In this embodiment, the multi-layer pillar 10 includes high melting point materials as discussed below. In embodiments, the multi-layer pillar 10 is typically between 60 to 80 microns in thickness; although any thickness for a particular application is contemplated by the invention.
The multi-layer pillar 10 includes a barrier and adhesion layer 12. In one embodiment, the barrier and adhesion layer 12 may be Titanium Tungsten (TiW); although, other barrier and adhesion materials are contemplated by the invention. A seed layer 14 is formed on the barrier and adhesion layer 12. In embodiments, the seed layer 14 is Chromium Copper (Cr/Cu) or Copper (Cu). The seed layer 14 may be formed by any conventional chemical deposition or physical deposition (CVD or PVD) method.
A copper layer 16a is formed on the seed layer 14 to a certain height, depending on the particular application. In embodiments, the formation of the copper layer 16a can be interrupted when the copper column is about 5 to 30 μm. In embodiments, the copper layer 16a is formed in a high-rate electroplating bath. The electroplating of copper is interrupted to form a low strength, high ductile layer 18a on the copper layer 16a. In embodiments, the low strength, high ductile layer 18a is an intermediate layer of about 0.2 to 2.0 micron, formed by a deposition process. The deposition process may be provided by an electrolytic bath, in embodiments.
In embodiments, the low strength, high ductile layer 18a is, for example, Gold (Au), Silver (Ag) or Aluminum (Al), depending on the particular application. The Young's modulus (modulus of elasticity) of Au is 78, the Young's modulus of Ag is 83 and the Young's modulus of Al is 76; whereas, the Young's modulus of Cu is 130. Moreover, the rigidity modulus (i.e., the change of shape produced by a tangential stress) of Au is 27, the rigidity modulus of Ag 30 and the rigidity modulus of Al is 26; whereas the rigidity modulus of Cu is 48.
In the embodiment of FIG. 3, the low strength, high ductile layer 18a has a higher melting temperature than lead-free solder and, as such, it does not melt during the assembly processing. And, again, according to the principles of the invention, the materials of low strength, high ductile layer 18a are configured such that the entire pillar is capable of sliding or tilting to compensate for Thermal Coefficient of Expansion (TCE) mismatch between the chip and the substrate (e.g., organic laminate) during the cooling part of the chip joining processes. In another mechanism, the materials used for the low strength, high ductile layer 18a are more ductile than copper and, as such, are capable of absorbing stresses created during the cooling cycle. That is, the low strength, high ductile layer 18a can deform during the cooling cycle thereby absorbing stresses that would otherwise have been imposed on the UBM metallurgy. Thus, by implementing the structures of the invention, stresses normally transmitted to the chip or copper metallurgy will be absorbed by the low strength, high ductile layer in the structures of the invention, preventing delamination of UBM layers, chip damage and increasing module yield.
In embodiments, an optional nickel barrier layer 20 can be formed on both sides of the low strength, high ductile layer 18a to have a reduced reaction product between layer 18a and prevent a reaction between the layer 18a and the copper. A copper layer 16b is formed on the low strength, high ductile layer 18a (or nickel layer 20) to form the remaining portion of the multi-layer pillar 10. Much like the copper layer 16a, a high-rate electroplating process forms the copper layer 16b. In further embodiments, the tip of the multi-layer pillar 10 can be plated with an optional solder disc 22 to provide a connection to a substrate (FIG. 5) during a reflow process.
Fourth Embodiment of the Invention
In the embodiment of FIG. 4, the multi-layer pillar 10 includes two (or more) intermediate layers, as discussed below. As in the embodiment of FIGS. 1-3, the multi-layer pillar 10 is typically between 60 to 80 microns in thickness; although any thickness for a particular application is contemplated by the invention.
The multi-layer pillar 10 includes a barrier and adhesion layer 12. In one embodiment, the barrier and adhesion layer 12 may be Titanium Tungsten (TiW); although, other barrier and adhesion materials are also contemplated by the invention. Again, the barrier and adhesion layer 12 can be any material which prevents diffusion of materials between a chip (shown in FIG. 5) and materials of the pillar 10 or substrate (shown in FIG. 5).
Still referring to FIG. 4, a seed layer 14 is formed on the barrier and adhesion layer 12. In embodiments, the seed layer 14 is Chromium Copper (Cr/Cu) or Copper (Cu). The seed layer 14 may be formed by any conventional chemical or physical process (CVD or PVD). A copper layer 16a is formed on the seed layer 14 to a certain height, depending on the particular application. In embodiments, the copper 16a is formed in a high-rate electroplating bath.
Again, prior to the formation of the entire multi-layer pillar 10, the electroplating of copper is interrupted in order to form a low strength, high ductile layer 18a on the copper layer 16a. In embodiments, the formation of the copper layer 16a can be interrupted when the copper column is about 5 to 30 μm. In embodiments, the low strength, high ductile layer 18a is, for example, Gold (Au), Silver (Ag) or aluminum (Al), depending on the particular application. In embodiments, the low strength, high ductile layer 18a is an intermediate layer of about 0.2 to 2.0 micron, formed by a deposition process. The deposition process may be provided in an electrolytic bath, in embodiments.
In embodiments, an optional nickel barrier layer 20 (at the interface between the intermediate layer 18a and the copper layer(s)) can be formed on both sides of the intermediate layer or layers to prevent a reaction between the intermediate layers and the copper. A second copper layer 16b is formed on the low strength, high ductile layer 18a (or nickel layer) to form an additional portion of the multi-layer pillar 10. As with the layer 16a, the copper layer 16b can be formed in a high-rate electroplating bath. In embodiments, the formation of the copper layer 16b can be interrupted when the copper column is about 10 to 30 μm.
In embodiments, the electroplating of copper is interrupted to form a second low strength, high ductile layer 18b on the copper layer 16b. In embodiments, the second high ductile metal layer 18b is, for example, Gold (Au), Silver (Ag) or aluminum (Al), depending on the particular application. In embodiments, the second high ductile metal layer 18b is an intermediate layer of about 0.2 to 2.0 micron, formed by a deposition process. The deposition process may be provided in an electrolytic bath, in embodiments.
A copper layer 16c is formed on the second high ductile metal layer 18b (or nickel layer) to form the remaining portion of the multi-layer pillar 10. As with the layers 16a and 16b, the copper layer 16c can be formed in a high-rate-electroplating bath. Additionally, an optional nickel layer may be formed at the interfaces between the intermediate layer 18b and the copper layers 16b, 16c to prevent a reaction between the intermediate layer 18b and the copper layers 16b, 16c. In an optional embodiment, the tip of the multi-layer pillar 10 can be plated with an optional solder disc to provide a connection to a substrate (FIG. 5) during a reflow process.
In the embodiment of FIG. 4, the layers 18a, 18b have a higher melting temperature than lead-free solder, and, as such do not melt during assembly processing. Additionally, according to the principles of the invention, the materials of layers 18a, 18b permit the entire pillar to slide or tilt to compensate for Thermal Coefficient of Expansion (TCE) mismatch between the chip and the substrate (e.g., organic laminate) during the heating processes. In another mechanism, the layers 18a, 18b are more ductile than copper and, as such, are capable of absorbing stresses created during the cooling cycle. That is, the layers 18a, 18b can deform during the cooling cycle thereby absorbing stresses that would otherwise have been imposed on the UBM metallurgy. Thus, by implementing the structures of the invention, stresses normally transmitted to the chip or copper metallurgy will be absorbed by layers 18a, 18b in the structures of the invention, thereby preventing UBM fatigue and increasing module yield.
In the embodiments of FIGS. 3 and 4, the number, position and thickness of the intermediate layers can vary according to technology application and space (e.g. chip size, number of C4 type connections, position of C4 connections on the chip, etc.). Additionally, the above materials for the intermediate layers can vary depending on the technology, noting that the modulus of elasticity should be lower than that of copper. Also, the number of modulated pillars in accordance with the invention the deposited onto a single UBM may vary depending on the particular application.
Structure of the Invention
FIG. 5 shows a packaged structure in accordance with the invention. In particular, FIG. 5 shows the utilization of the multi-layer pillar 10 of FIG. 1 bonded to a substrate 50 and a chip 60. It should be recognized that any of the structures discussed above can be implemented with the substrate 50 and chip 60 shown in FIG. 5.
In the structure of FIG. 5, a via 70 is provided in the substrate. The via 70 includes Cu and materials such as, for example, SnCu solder or SnCuAg solder or NiP and Au or Ag, to name a few materials, which can be used to assist in the bonding of the substrate 50 to the multi-layer pillar 10 during the heating process. That is, the material on the via 70 will flow during the heating process, bonding the substrate 50 to the multi-layer pillar 10 or the solder on the copper pillar (disc 22 in FIG. 5) will flow and provide the bonding.
As should be understood by those of skill in the art, the chip 60 has a lower CTE than that of the organic substrate 50. Thus, during the cooling cycle, the substrate 50 will shrink faster than the chip 50. Compared to a conventional structure, as the multi-layer pillar 10 of the invention includes a deformation zone, the stresses created by the substrate 50 (shrinking faster than chip 60) will be absorbed by the multi-layer pillar 10. This will protect the chip from fracture of layers under the UBM during the connection process and thermal excursions thus increasing overall module yield and reliability.
The methods and structures as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with the structures of the invention) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.

## Claims

1. A structure comprising a modulated copper pillar including:
a barrier and adhesion layer that connects the modulated copper pillar to a chip;
a seed layer contacting the barrier and adhesion layer;
a first copper layer contacting the seed layer;
a second copper layer contacting a solder material; and
at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions, wherein the at least one low strength, high ductility deformation region is between the first copper layer and the second copper layer and has a modulus of elasticity less than copper.

2. The structure of claim 1, wherein the barrier and adhesion layer prevents diffusion of materials between the chip and materials of the modulated copper pillar.

3. The structure of claim 1, wherein the solder material contacts a via in a substrate.

4. The structure of claim 1, further comprising:
a first nickel layer between and contacting the first copper layer and the at least one low strength, high ductility deformation region; and
a second nickel layer between and contacting the second copper layer and the at least one low strength, high ductility deformation region.

5. The structure of claim 1, wherein a vertical sidewall of the first copper layer is aligned with both a vertical sidewall of the intermediate layer and a vertical sidewall of the second copper layer.

6. The structure of claim 1, wherein the at least one low strength, high ductility deformation region comprises two separate low strength, high ductility deformation regions between the first copper layer and the second copper layer.

7. The structure of claim 6, further comprising a third copper layer between the two separate low strength, high ductility deformation regions.

8. The structure of claim 1, wherein the at least one low strength, high ductility deformation region includes one of gold, aluminum and silver.

9. The structure of claim 8, wherein the at least one low strength, high ductility deformation region is about 0.2 to 1 microns in thickness.

10. The structure of claim 1, further comprising:
a first protective layer interposed at an interface between the uppermost surface of the at least one low strength, high ductility deformation region and the first upper copper layer; and
a second protective layer interposed at an interface between the lowermost surface of the second copper layer and the at least one low strength, high ductility deformation region and the lower copper layer.

11. The structure of claim 10, wherein:
the first protective layer is a layer of nickel covering the entire uppermost surface of the at least one low strength, high ductility deformation region; and
the second protective layer is another layer of nickel covering the entire lowermost most surface of the at least one low strength, high ductility deformation region.

12. An interconnect pillar between a chip and a substrate, the interconnect pillar comprising:
a first copper layer connected to the chip by a barrier and adhesion layer;
a second copper layer connected to a via in the substrate by a solder layer;
an intermediate layer interposed between the first copper layer and the second copper layer, the intermediate layer having a lower modulus of elasticity than that of the first copper layer and the second copper layer, the intermediate layer being structured to absorb stress imposed during a cooling cycle of an interconnect process which would otherwise be imparted to a chip.

13. The interconnect pillar of claim 12, wherein the intermediate layer is one of Aluminum, Gold and Silver.

14. The interconnect pillar of claim 12, wherein the intermediate layer is configured to slide or tilt during a heating cycle of the interconnect process.

15. The interconnect pillar of claim 12, further comprising a second intermediate layer between the second copper layer and a third copper layer.

16. The interconnect pillar of claim 12, wherein the intermediate layer is configured to slide or tilt during a heating cycle of the interconnect process with the chip.

17. The interconnect pillar of claim 12, wherein the first copper layer is on and contacting a seed layer that is on and contacting the barrier and adhesion layer.

18. The interconnect pillar of claim 12, wherein a sidewall of the first copper layer is aligned with a sidewall of the intermediate layer.

19. The interconnect pillar of claim 18, wherein the sidewall of the intermediate layer is aligned with a sidewall of the second copper layer.