# Patent

## Title
Dual residue pipelined analog-to-digital converter

## Abstract

Consistent with an example embodiment, there is dual residue pipelined AD converter comprising a cascade of, preferably balanced, switched capacitor dual residue converter stages for producing from first and second residue input signals one or more digital bits and first and second residue output signals for application to the next stage in the cascade. Preferably the first and second residue input signals charge input capacitors whose charge is subsequently transferred to output capacitors by means of operational amplifiers. The switched capacitor architecture allows compensating for DC-offset voltages of the operational amplifiers. The switched capacitor architecture also allows the implementation of 1.5 bit converter stages.

## Background
This application is a 371 of PCT/IB04/52129, which has an international filing date of Oct. 18, 2004, designating the United States of America, and claims the benefit of European patent application 03103935.7 filed Oct. 23, 2003.
The invention relates to a dual residue pipelined AD-converter for converting an analog input signal to a digital output signal, said converter comprising a cascade of dual residue converter stages, the first of said stages comprising means to receive the analog input signal, means to derive one or more digital bits from said analog input signal and means to generate first and second residue signals representing the quantization error left after the AD-conversion of said first stage, each of the following stages in the cascade of dual residue converter stages comprising means to receive the first and second residue signals generated by the previous stage in the cascade, means to derive one or more further digital bits from said received first and second residue signals and each of said following stages except the last one in the cascade comprising means to generate first and second residue signals representing the quantization error left after the AD-conversion of the stage. Such dual residue pipelined AD converter is known from the paper “A Two Residue Architecture for Multistage ADC's” by Mangelsdorf et al, 1993 IEEE International Solid State Circuits Conference, Feb. 24, 1993.
A single residue pipelined AD converter comprises a plurality of cascaded stages of which each stage calculates only a part (k) of the bits of the desired total digital word. To this end the stage contains a k-bit AD converter that compares the analog input with at least one reference voltage and that outputs a k-bit digital signal resulting from this comparison. Subsequently a residue signal is derived. This derivation may be considered as applying the k-bit digital output of the AD converter to a DAC that delivers the analog representation of this k-bit signal and generating the difference between the analog input and the analog representation of the k-bit signal. This difference is the quantization error or residue that is applied to the next stage of the cascade for deriving the next bit(s) of the digital word. A major drawback of such single residue pipelined AD converter is that the residue signal, prior to being applied to the next stage of the cascade, has to be amplified with a factor that is very closely equal to 2k. This not only in order to optimally use the dynamic range of the next stage but, more importantly, to be able to use the derived reference voltage(s) for the digitization of the residue signal in all the stages of the cascade.
This problem can be solved when not only the residue is amplified but with the same amplification factor also the reference level(s), see e.g. U.S. Pat. No. 5,739,781. The result is that the value of the gain factor is not anymore critical, because now the only task of the interstage amplification is to accommodate the residue signal to the dynamic range of the next stage in the pipeline. Equivalent to amplifying the reference level(s) simultaneously with the residue signal is to process and amplify two residue signals. One of these residue signals represents the distance between the analog input signal and the nearest reference level below the input signal and the other residue signal represents the distance between the analog input signal and the nearest reference level above the input signal. Such AD-converter is known as “dual-residue pipelined AD converter”.
The prior art dual residue pipelined AD converters normally operate with resistive dividers. The present invention provides a dual residue pipelined AD converter that has the advantages of the prior art converters and that operates at reduced power and the dual residue pipelined AD converter according to the present invention is therefore characterized in that each of the stages of the dual residue pipelined AD-converter, except the last one, comprises switched capacitor means for the generation of the first and second residue signals.
It may be observed that the use of switched capacitors in single residue pipelined AD converters is per se well known in the art. In these prior art converters the interstage gain should ideally be exactly equal to 2 in order to have no linearity problems. In these converters the interstage gain is determined by capacitor ratios of different capacitors and therefore dependent on the parasitic capacitances of the operational amplifiers that are used as amplifying elements in the stages. In practice the problem of the insufficiently accurate interstage amplification factor is attacked in various ways. One way is to calibrate the errors and to use the result of the calibration to correct the effect of the errors. E.g. in “IEEE Journal of Solid State Circuits, Vol. 33, No 12, December 1998, pp. 1898-1903” it is proposed to calibrate capacitor mismatches and errors due to finite opamp-gain by calibration during an initial power up cycle and then the correction is done in a dual digital pipeline that works synchronously with the analog pipeline. In “IEEE Journal of Solid State Circuits, Vol. 33, No 12, December 1998, pp. 1920-1931” the pipeline stages are successively replaced by a pre-corrected extra stage, then corrected and then replaced to their original position. In “2001 International Solid State Circuits Conference/Session 8, Digest of Technical Papers, pp. 136-137, 439-440” the capacitors of the stages are shuffled to minimize the errors by averaging. In “IEEE Journal of Solid State Circuits, Vol. 36, No 12, December 2001, pp. 1931-1936” it is proposed to use more sophisticated technology, such as double poly, to increase the accurateness of the components. Obviously this latter solution makes the converter more expensive and is especially not appropriate when the converter should be part of a large-scale integrated circuit that is usually implemented with standard process technology.
In a pipelined AD converter according to the invention the linearity of the converter is no longer determined by the ratio between input and output capacitors, i.e. the ratio of dissimilar capacitors, but solely by the matching of the gain factors within one stage i.e. by the matching of similar capacitors within the stage. This requirement is usually reasonably easy to meet in monolithic integrated circuit technology, without the need of calibration or the use of a more expensive IC-process technology.
In switched capacitor architectures one or more capacitors may be connected to an input terminal during a first clock phase and subsequently these capacitors may be switched to an output terminal during a second clock phase. In a dual residue generator according to the invention it is not anymore critical for the gain of the residue signals to be exactly equal to 2 but it is of importance that the gain of the two residue signals is mutually equal. In order to facilitate this mutual gain equality the AD converter according to the invention is further characterized in that each of said following stages except the last one comprise input capacitors for receiving during a sampling phase the first and second residue signals generated by the previous stage, switching means to transfer during a tracking phase the charge of said input capacitors to first and second output capacitors, and means to generate first and second residue signals from said first and second output capacitors respectively.
The pipelined AD-converter of the present invention may be still further characterized in that said switching means are arranged to transfer charge from said first received residue signal to said first output capacitor with a gain factor of approximately 2 and charge from both said first and second received residue signals to said second output capacitor each with a gain factor of approximately 1 in a first sub-range mode and to transfer charge from said second received residue signal to said second output capacitor with a gain factor of approximately 2 and charge from both said first and second received residue signals to said first output capacitor each with a gain factor of approximately 1 in a second sub-range mode. With this arrangement a simple and reliable circuit is provided for assembling each of the two output residue signals from both the two input residue signals.
As mentioned earlier, each of the stages in the cascade comprises comparator means to derive one or more bits that serve to construct the digital output word of the AD-converter. The decision point of the comparator is very critical especially in the earlier stages of the cascade and/or when the AD-converter has to generate a high precision digital output signal of e.g. 12 bit or more. Such decision point may easily be corrupted by imperfections such as offsets in the comparator. In order to prevent such corruption of the comparator output it has already been proposed to use so-called 1.5 bit converter stages, in which the critical decision point is effectively replaced by a third sub-range between and partly overlapping the original sub-ranges. It is another object of the present invention to provide a switched capacitor implementation of such 1.5 bit converter stage and the AD converter according to the invention may therefore be further characterized in that said switching means are additionally arranged to transfer charge from both said first and second received residue signals to said first output capacitor with a gain factor of approximately 3/2 and 1/2 respectively and charge from both said first and second received residue signals to said second output capacitor with a gain factor of approximately 1/2 and 3/2 respectively in a third sub-range mode which lies symmetrically between said first and second sub-range modes.
It is a further aspect of the invention that for the generation of each residue signal an operational amplifier is provided and that each output capacitor is connected during the tracking phase between an output terminal and the inverting input terminal of said operational amplifier. With such arrangement a high speed AD converter can be made because simultaneously with the tracking phase of all even stages the sampling stage of all odd stages can take place. The operational amplifier supplies the energy not only for transferring the charge from the input capacitors to the output capacitors of one stage but also to simultaneously charge the input capacitor(s) of the next stage. Normally a drawback of using operational amplifiers in pipelined AD-converters is that it asks a relatively long period of time for the operational amplifier to fully settle and complete the charge transfer from the input capacitor(s) to the output capacitor. This limits the conversion speed of the converter. However, in dual residue switched capacitor converters according to the present invention it is not necessary for the converter stages to reach their full gain and therefore it is not necessary for the output capacitors to become fully charged, provided that the incomplete charge is similar for the output capacitors of both residue signals. This gives the possibility to increase the conversion speed without risking substantial loss of conversion-linearity.
A drawback of using operational amplifiers for the transfer of charge between input and output capacitors is the DC-offset that often occurs in the operational amplifiers, especially because in practice it is impossible to make the DC-offsets for the various opamp inputs equal to each other. It is a further object of the invention to compensate the offset-voltages of the operational amplifiers and the AD-converter in accordance with the invention may therefore be characterized in that one side of each input capacitor is connected to said inverting input terminal both during the sampling phase and during the tracking phase and that each output capacitor is charged during the sampling phase by the offset voltage at the inverting input of the operational amplifier.
The dual residue pipelined AD-converter according to the invention may also be characterized in that the switched capacitor means are arranged to receive balanced first and second residue signals and to generate there from balanced first and second residue signals for application to the next stage in the cascade. A balanced dual residue converter stage requires balanced operational amplifiers and twice as much capacitors and switches as the unbalanced version. But it allows a twice as large input signal swing and its operation is affected to a lesser extend by substrate-disturbances and even harmonic distortion.



The invention will be described with reference to the accompanying figures. Herein shows:
FIG. 1 a block diagram of an unbalanced dual residue pipeline converter,
FIG. 2 a schematic diagram of an embodiment of a dual residue generator for use in the first stage of a converter as shown in FIG. 1,
FIG. 3 a schematic diagram of an embodiment of a dual residue generator for use in an intermediary stage of a converter as shown in FIG. 1,
FIG. 4 arrow-graphs for explaining the operation of the unbalanced AD converter of FIG. 1 and the balanced AD converter of FIG. 5,
FIG. 5 a block diagram of a balanced dual residue pipeline converter,
FIG. 6 a schematic diagram of an embodiment of a balanced dual residue generator for use in the first stage of a converter as shown in FIG. 5,
FIG. 7 a schematic diagram of a first embodiment of a balanced dual residue generator for use in an intermediary stage of a converter as shown in FIG. 5,
FIG. 8 a schematic diagram of a second embodiment of a balanced dual residue generator for use in an intermediary stage of a converter as shown in FIG. 5,
FIG. 9 a schematic diagram of part of a third embodiment of a balanced dual residue generator for use in an intermediary stage of a converter as shown in FIG. 5 and
FIG. 10 arrow graphs for explaining the operation of the residue generator of FIG. 9.



The pipelined AD converter of FIG. 1 comprises a cascade of converter stages S1 . . . SN each of which delivers one bit (k=1) of the digital output word. The first stage S1 delivers the most significant bit D1, the second stage S2 delivers the second most significant bit D2 etcetera, while the last stage SN delivers the least significant bit DN.
The stage S1 receives the analog input signal I as well as the voltages R1 and R2, which represent the extreme values between which the input signal may vary. A voltage divider of equal resistors V1 and W1 derives the mean voltage Z of these extreme values (Z=(R1+R2)/2) and this voltage Z is also transferred as a reference voltage to the next stages. The stage S1 further comprises a comparator G1 in which the input signal I is compared with the reference voltage Z and which delivers the bit D1. This bit is 1 when the input signal I is above Z i.e. in the upper half of the voltage range between R1 and R2 and the bit D1 is 0 when the input signal is below Z i.e. in the lower half of this voltage range. Finally the stage S1 contains a residue generator H1, which receives the input signal I, the bit D1 and the reference voltages R1, R2, Z and which produces two residue signals A1 and B1. The construction and the operation of this residue generator will be explained hereafter with reference to FIG. 2.
The two residue signals A1 and B1 are applied to the second stage S2. A voltage divider of equal resistors V2 and W2 derives the mean value (A1+B1)/2 of the two residue signals and this mean value is compared with the reference voltage Z in a comparator G2. This comparator produces the second bit D2 which is 0 when the mean value (A1+B1)/2 of the residue signal is below the reference Z and which is 1 when this mean value is above the reference voltage Z. A residue generator H2 receives the two residue signals A1 and B1 and the Z reference and it produces the next residue signals A2 and B2. The construction and operation of the residue generator H2 will be explained with reference to FIG. 3.
The further stages S3 . . . SN−1, except the last one, are identical in construction and operation with the stage S2 and each of said further stages produces a further bit of the digital output word and the residue signals for the next stage.
The dual residue generator of FIG. 2 comprises an operational amplifier J1 with an output capacitor C′1 in feedback arrangement between the output and the inverting input of the operational amplifier and the reference voltage Z connected to the non-inverting input thereof. An input capacitor C1 receives through switches the input voltage I and the reference voltages R1 and Z. The switches do not bear reference numerals but are indicated by their switch-phases. The switches indicated by φ are closed during a sampling phase of a clock cycle and open during a tracking phase of the clock cycle. The switches indicated by φ are closed during the tracking phase and open during the sampling phase. The switches indicated by φD1 are closed during the tracking phase but only when the bit D1 is “zero” and the switches indicated by φD1 are closed during the tracking phase but only when the bit D1 is “one”. Thus it may be seen from FIG. 1 that during the sampling phase φ the input capacitor C1 is loaded to the voltage I−Z and that the output capacitor C′1 is emptied during this phase. During the tracking phase φ and if the bit D1 is “zero”, the left hand plate of the input capacitor is connected to the voltage R1 while the right hand plate of this capacitor is connected to the inverting input of the operational amplifier J1. This inverting input is kept at the voltage Z by the feedback operation of this amplifier. Consequently, the charge of the input capacitor, which was (I−Z).C at the end of the sampling phase, becomes (R1−Z)C during the tracking phase. The difference (I−R1).C is transferred to the output capacitance, so that the voltage across this capacitor becomes (I−R1).C/C′ and the voltage at the A1-output of the operational amplifier J1 becomes A1=Z+(I−R1).C/C′. Herein C is the capacitance of the input capacitor C1 and of the other input capacitors. C′ is the capacitance of the output capacitor C′1 and of the other output capacitors. If the bit D1 is “one”, a similar operation applies except in that during the tracking phase, instead of the voltage R1, the voltage Z is applied to the left plate of the input capacitor C1. The result is that the residue signal A1 now becomes: A1=Z+(I−Z).C/C′.
The dual residue generator H1 further comprises a second branch with a second operational amplifier J2, a second output capacitor C′2 and a second input capacitor C2 for the generation of the residue signal B1. This second branch is identical to the first branch except in that, instead of the voltages R1 and Z, now the voltages Z and R2 are applied to the input capacitor C2 during the tracking phase and when the bit D1 is “zero” and “one” respectively. The result is that for the second residue signal B1 the following expressions hold:

B1=Z+(I−Z).C/C′ if D1=0

B1=Z+(I−R2).C/C′ if D1=1

With the four above given equations the input signal I and the two residue signals A1 and B1 are depicted in the arrow-graphs of FIGS. 4a and 4b. These figures show that the two residue signals are identical for input signal values in the lower half of its range R1<I<Z and for input signal values in the upper half of its range Z<I<R2. This is essential for a pipelined converter stage.
The residue generator H2 in the second stage S2 of the pipelined converter of FIG. 1 has to calculate the two residue signals A2 and B2 from the signals A1 and B1 delivered by the first stage. This generator, illustrated in FIG. 3, has two branches, each with an operational amplifier J3, J4, an output capacitor C′3, C′4 in feedback arrangement, input capacitors C3-C4, C5-C6 and accompanying switches. Unlike the branches of FIG. 2, the two branches of FIG. 3 have each two input capacitors. The branch for the generation of the first residue signal A2 has the two input capacitors C3 and C4 and the branch for the generation of the residue signal B2 has the input capacitors C5 and C6. The input capacitor C3 receives the residue signal A1 of the first stage during the sampling phase. The input capacitor C4 receives the residue signal A1 during the sampling phase if the bit D2 is “zero” and receives the second residue signal B1 during the sampling phase if the bit D2 is “one”. During the tracking phase and when the bit D2 is “zero” each of the two input capacitors C3 and C4 transfers the charge (A1−Z).C to the output capacitor C′3 with the result that the output residue A2=Z+2.(A1−Z).C/C′. On the other hand, when the bit D2 is “one”, the input capacitor C3 transfers during the tracking phase the charge (A1−Z).C to the output capacitor C′3 and the input capacitor C4 transfers the charge (B1−Z).C to this output capacitor C3 with the result that the output residue A2=Z+(A1−Z).C/C′+(B1−Z).C/C′.
The second branch of the dual residue generator of FIG. 3 serves for the generation of the residue B2. This branch contains an operational amplifier J4 with output capacitor C′4 in feedback arrangement, input capacitors C5 and C6 and accompanying switches. The branch is identical with the A2-branch except in that now the input capacitor C5 receives during the sampling mode the residue signal B1 instead of the residue signal A1. The result is that when the bit D2 is “zero” the output residue B2=Z+(A1−Z).C/C′+(B1−Z).C/C′ and when bit D2 is “one” this output residue B2=Z+2.(B1−Z).C/C′.
With the four equations for the residues A2 and B2 the arrows of these residues with increasing input signal can be drawn. This is shown in FIG. 4c. Again it may be seen that each of the two generated residue signals A2 and B2 for the upper part of the input residues A1 and B1 when D2=1 is identical with the same signal for the lower part of the input residues when D2=0.
The dual residue generators H3 . . . HN−1 of the converter stages S3 . . . SN−1 are all identical with the dual residue generator H2 explained above. Of course only the input residue references and the output residue references have to be increased accordingly.
From the graphs of FIGS. 4b and 4c it is apparent that the dual residue signals A2 and B2 are amplified by a factor 2 with respect to the dual residue signals A1 and B1. This is done to make optimum use of the dynamic range of the converter stages. The amplification is achieved by the fact that in the dual residue generator of FIG. 3 the charge of two input capacitors is transferred to one single output capacitor. It is hereby assumed that the capacitance value C′ of each output capacitor is approximately equal to the value C of each input capacitor. It is noted that the gain of the dual residue generator of the first stage S1 is (approximately) 1, because here the dynamic range of the single input signal has to be used by two output residues.
In practice it is not possible to make the capacitance values of the input and output capacitors accurately equal to each other. This is because the parasitic capacitances of the operational amplifier and of the switches have different influence on the input capacitance C and on the output capacitance C′. Therefore the “amplification factor” C/C′ that appear in the above given equations, will in practice not have the exact desired value. In contrast to the single residue converter, the dual residue converter is insensitive to these inaccuracies of the amplification factor, because the decisions made by the comparators G1 . . . GN are not influenced by the inaccurate amplification factor C/C′. This may be exemplified by the arrow-diagram of FIG. 4b. The decision criterion for the generation of the second bit D2 lies at (A1+B1)/2=Z. With other words: at one side of this point the bit D2=0 and at the other side this bit D2=1. When the ratio C/C′ increases or decreases then the slope of the arrows A1 and B1 in FIG. 4b increases or decreases. Also the slope of the dashed arrow (A1+B1)/2 just between the arrows A1 and B1 increases or decreases but the intersection of this arrow with the level Z remains unchanged, and consequently the decision made by the comparator G2 remains correct. The value of the ratio C/C′ of a converter stage may be inaccurate and even the ratio C/C′ of one stage may be different from the ratio C/C′ of the other stages in the cascade. What remains of importance is that the values C of the input capacitances in one stage are sufficiently equal to each other and also that the values C′ of the output capacitances in one stage are sufficiently equal to each other. This is not a big problem in monolithic integration processes, because in integrated circuit technology elements with corresponding functions may easily be given a corresponding structure with substantially equal values.
The balanced dual residue pipelined AD converter of FIG. 5 comprises N cascaded stages T1 . . . TN of which the first one receives a balanced input signal I+, I− and which contains a dual residue signal generator M1 for generating two balanced residue signals A1+, A1− and B1+, B1−. These two balanced residue signals are applied to the second stage T2 which comprises a dual residue signal generator M2 for generating two balanced residue signals A2+, A2− and B2+, B2− and so on. Each of the stages T1 . . . TN has a comparator K1 . . . KN for deriving one digital bit D1 . . . DN. In the balanced converter the bits can be simply obtained by comparing received signals with each other, so that the voltage dividers V2, W2 . . . VN, WN of FIG. 1 can be dispensed with. The comparator K1 compares the input signals I+ and I− with each other and produces a first bit D1 which is “zero” when I+<I− and which is “one” when I+>1−. The comparator K2 compares the residue signals A1+ and B1− with each other and produces a second bit D2 which is “zero” when A1+<B1− and which is “one” when A1+>B1− and so on. Only the first stage T1 contains a voltage divider of equal resistors L1 and L2 for deriving a reference level Z, which is used in all stages T1 . . . TN−1. When in the converter stage S2 the residue signals A1+, A1− and B1+, B1− have different common mode offsets ΔA≠ΔB, the decision point of the bit D2 is at A1++ΔA=B1−+ΔB i.e. at A1+−B1−=ΔB−ΔA≠0. This error may be avoided by applying the four residue signals A1+, A1−, B1+ and B1− to the comparator K2 and to have the decision point of the bit D2 at A1+−A1−=B1−−B1+. Then the common mode offsets in A1+ and A1− cancel against each other and also the offsets in B1+ and B1−. Of course a corresponding measure can be taken in any of the other comparators K3 . . . KN.
FIG. 6 shows the contents of the first balanced residue generator M1 of the AD converter of FIG. 5. The generator contains two branches, one for the generation of the balanced residue signals A1+, A1− and one for the generation of the balanced residue signals B1+, B1−. The first branch comprises a balanced operational amplifier J5 with one output for the A1+ residue signal, one output for the A1− residue signal and two inputs. Two output capacitors C′5 and C′6 are connected in feedback arrangement between each output and the respective inverting input of the operational amplifier. Input capacitors C7 and C8 are arranged for being coupled to the said inputs of the operational amplifier during the tracking phase φ. Switches are present to charge during the sampling phase φ of the clock pulse cycle the input capacitors C7 and C8 from applied input signals I+ and I− respectively and to transfer the charge during the tracking phase φ to the output capacitors C′5 and C′6 respectively. In FIG. 6 the switches bear no reference numerals but they are provided with indications about their opening and closing phases, just the same as has been done in the FIGS. 2 and 3.
The second branch of the generator of FIG. 6, with a balanced operational amplifier J6, output capacitors C′7 and C′8, input capacitors C9 and C10 and associated switches, is equal in construction to the first branch but operates with different input voltages. The balanced dual residue generator of FIG. 6 generates the two balanced residue signals A1+, A1− and B1+, B1− according to the following equations:











If D1 = 0 (I+ < I−)
If D1 = 1 (I+ > I−)







AI+ = Z + (I+ − R1) · C/C′′
AI+ = Z + (I+ − Z) · C/C′′


AI− = Z + (I− − R2) · C/C′′
AI− = Z + (I− − Z) · C/C′′


BI+ = Z + (I+ − Z) · C/C′′
BI+ = Z + (I+ − R2) · C/C′


BI− = Z + (I− − Z) · C/C′′
BI− = Z + (I− − R1) · C/C′′









FIG. 7 shows an exemplary schematic diagram of the balanced dual residue generator M2 of the converter of FIG. 5. Two balanced operational amplifiers J7 and J8 and four output capacitors C′9, C′10, C′11 and C′12 connected thereto in feedback arrangement have an operation similar to those described with reference to FIG. 6. The arrangement comprises eight input capacitors 2C11, C12, 2C13, C14, 2C15, C16, 2C17 and C18. The capacitors C12, C14, C16 and C18 ideally have equal values C and the capacitors 2C11, 2C13, 2C15 and 2C17 ideally have the double value 2C. The charging of the input capacitors during the sampling phase of the clock cycle and the charge transfer from the input capacitors to the output capacitors during the tracking phase of the clock cycle is performed through switches of which the opening and closing phases are indicated in the same way as in the FIGS. 2, 3 and 6.
In operation: during the sampling phase the output capacitor C′9 is emptied and the input capacitor 2C11 is loaded with a charge (A1+−Z).2C. During the tracking phase and when the bit D2=0 this charge is transferred to the output capacitor C′9 so that the voltage across this capacitor will be equal to (A1+−Z).2C/C′ and the output signal A2+ will be equal to A2+=Z+(A1+−Z).2C/C′. When D2=1 the charge of the input capacitor 2C11 remains unused. During the sampling phase is the input capacitor C12 charged with (A1+−Z).C. During the tracking phase and when D2=0 this charge is transferred to the output capacitor C′11 through the connection indicated by the arrows I, and when D2=1 this charge is transferred to the output capacitor C′9. Simultaneously, when D2=1, the output capacitor C′9 receives, through the connection indicated by the arrows 3, a charge (B1+−Z).C from input capacitor C16. The result is that, when D2=1, the output residue A2+=Z+(A1+−Z).C/C′+(B1+−Z).C/C′.The other elements of the residue generator of FIG. 7 operate in a similar manner, so that the total result of this generator may be expressed by the following equations:



  
    
      
        
          
            
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                  C
                  ′
                
              
            
          
        
      
    
    
      
        
          
            B
            
              2
              +
            
          
          =
          
            Z
            +
            
              
                (
                
                  
                    B
                    
                      1
                      +
                    
                  
                  -
                  Z
                
                )
              
              ⁢
              
                
                  2
                  ⁢
                  C
                
                
                  C
                  ′
                
              
            
          
        
      
    
    
      
        
          
            B
            
              2
              -
            
          
          =
          
            Z
            +
            
              
                (
                
                  
                    B
                    
                      1
                      -
                    
                  
                  -
                  Z
                
                )
              
              ⁢
              
                
                  2
                  ⁢
                  C
                
                
                  C
                  ′
                
              
            
          
        
      
    
  



These relations between the input residue signals and the output residue signals of the second stage are illustrated with the arrow-graphs of FIGS. 4e and 4f. It is seen that the generated residue signals for D2=1 are identical to the generated residue signals for D2=0. This characteristic repeats itself in the further converter stages. It is further noted that the crossing of the A2+ arrow and the B2− arrow, which determines the signal level where the bit D3 will change its value, lies exactly in the middle of the ranges D2=0 and D2=1 and that this crossing remains in place when the slope of the residue signals A2+ and B2− alters. This means that the bit-generation is independent on the gain of the stage i.e. on the ratio of the input capacitances and the output capacitances of the stage. On the other hand the slopes of the two arrows have to be as much as possible equal to each other, which means that the input capacitances of the stage have to be as equal as possible to each other and the same holds for the output capacitances of the stage.
In the residue generator of FIG. 3 the bit D2 controls switches (φD2, φD2) that are closed in the sampling phase. This implies that the decision of the comparator G2 has to be made prior to the sampling phase of the stage G2 i.e. the stage has to have three clock phases: a comparison phase, a sampling phase and a tracking phase. In contradistinction the arrangement of FIG. 7 has, at the cost of more input capacitance, only D2-controlled switches (φD2, φD2) that are closed during the tracking phase. This means that the comparator-decision can be made in the sampling phase and the result is an AD-converter with a higher conversion rate.
The arrangement of FIG. 8 comprises balanced operational amplifiers J9 and J10 for the generation of the first and second residue output signals A2+, A2− and B2+, B2− respectively. Four output capacitors C′13, C′14, C′15 and C′16 are provided, each of which is connected through a switch that is closed during the tracking phase φ in feedback arrangement between an amplifier output terminal and the corresponding inverting amplifier input. Further switches are provided that directly connect each amplifier output to the corresponding inverting amplifier input and that discharges the output capacitor to the reference voltage Z during the sampling phase φ.
Each of the input terminals of the operational amplifiers J9 and J10 is connected to one side of three input capacitors whose other sides receive input residue signals during the sampling phase φ. For example, the upper input terminal of the amplifier J9 is connected to a first input capacitor 2C19 that receives the input residue signal A1+ during the sampling phase, to a second input capacitor C20 that also receives the input residue signal A1+ during this phase and to a third input capacitor C21 that receives the input residue signal B1+ during this phase. Said other sides of the input capacitors receive the reference voltage Z during the tracking phase φ, the capacitor 2C19 when the bit D2=0 and the capacitors C20 and C21 when D2=1. In similar way three input capacitors 2C22, C23 and C24 are arranged to feed the lower input terminal of J9, three input capacitors 2C25, C26 and C27 feed the upper terminal of amplifier J10 and three input capacitors 2C28, C29 and C30 feed the lower input terminal of J10. The reference of the capacitors 2C19, 2C22, 2C25 and 2C28 indicate that these capacitors have double capacitance value 2C with respect to the other input capacitors that have the value C.
In FIG. 8 the DC-offset appearing at the upper input terminal of the amplifier J9 is indicated by an offset source with value ΔV. Although this offset is shown outside the opamp, it will be apparent that the offset is intrinsic to the opamp and that therefore the left hand terminal of the offset voltage source is the actual input terminal of the amplifier.
When comparing the arrangement of FIG. 8 with that of FIG. 7, it may be seen that during the sampling phase the right hand side of the input capacitors is not connected to the reference voltage Z, as is the case in FIG. 7, but to the virtual reference of the input terminal of the opamp. Because of the offset ΔV at this terminal this virtual reference has the value Z+ΔV. Moreover, the output capacitor C′13, in stead of being completely discharged during the sampling phase, is now connected between the virtual reference voltage Z+ΔΔV at one side and the reference voltage at the other side, so that the output capacitor is “loaded” by the offset voltage −ΔV.
In operation, during the sampling phase φ the input capacitor 2C19 is connected between the input residue signal A1+ and the virtual reference Z+ΔV, so that the charge of this capacitor is {A1+−(Z+ΔV)}.2C. During the tracking phase and when D2=0, this capacitor is connected between Z and Z+ΔV so that its charge is {Z−(Z+ΔV)}.2C. The difference there between, i.e. the charge (A1+−Z).2C is transferred to the output capacitor C′13 during the tracking phase. This output capacitor, which is loaded during the sampling phase with the charge −ΔV.C′, receives the charge (A1+−Z).2C from the input capacitor so that the resulting charge is (A1+−Z).2C−ΔV.C′. This charge results in a voltage (A1+−Z).2C/C′−ΔV across the output capacitor C′ and because the left hand side of C′13 remains connected to the virtual reference Z+ΔV, the output voltage A2+ at the right hand side of this capacitor is equal to A2+=Z+(A1+−Z).2C/C′. The offset voltage ΔV is completely cancelled in the output signal and the expression for this output residue is the same as in the arrangement of FIG. 7. This result is achieved because, in the arrangement of FIG. 8, the input capacitance is connected to the offset disturbed input of the operational amplifier both during the sampling phase and during the tracking phase, so that the charge transferred from the input capacitor to the output capacitor is free of offset. Moreover, during the sampling phase the output capacitor is charged by the offset voltage so that the offset applied to the output terminal through the output capacitor is cancelled by the offset across this capacitor.
It may be noted that in FIG. 8 only the offset voltage of the upper input terminal of the opamp J9 is shown. Also the other opamp input-terminals have offsets, which usually are different in value from each other. Each of these offsets is cancelled in a similar arrangement of switched input and output capacitors as described above with reference to the capacitors 2C19 and C′13. It is further observed that in the arrangement of FIG. 7 each of the input capacitors C12, C14, C16 and C18 serves the generation of two residue output signals. E.g. the input capacitor C12 serves the generation of the output residues A2+ and B2+. In the arrangement of FIG. 8 a similar dual use of input capacitors would result in that the offset of one opamp input terminal has to cancel the offset of another opamp input terminal. Because the offsets are usually unequal such dual use of input capacitors cannot be applied in the arrangement of FIG. 8.
FIG. 9 shows a balanced residue generator for use in a so-called 1.5 bit converter stage. A residue generator for a 1.5 bit pipeline architecture is per se known from the article “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter” from T. B. Cho and P. R. Gray in IEEE Journal of Solid State Circuits, Vol. 30, No 3 March 1995 pp. 166-172. The residue generator of FIG. 9 is supposed to operate with a comparator that provides two bits D and E that are 0.0 in a first input range, 1.0 in a second input range and 0.1 in a third input range lying symmetrically between the first and second input ranges. The generator of FIG. 9 comprises an output circuit for the balanced residue signal A2+, A2− with an operational amplifier J11 and two output capacitors 2C′17 and 2C′18, that is identical in operation with the output circuits of the arrangement of FIG. 7. The arrangement has three input capacitors 4C31, 3C32 and 2C33 for the storage of the input residue signal A1+, two input capacitors C34, and 2C35 for the storage of the input residue signal B1+, three input capacitors 4C36, 3C37 and 2C38 for the storage of the input residue signal A1− and two input capacitors C39 and 2C40 for the storage of the input residue signal B1−. As in FIG. 7 the leading ciphers of these references indicate the capacitance value of these capacitors. The capacitance of 4C31 and 4C36 is equal to 4C, the value of 3C32 and 3C37 is equal to 3C, the value of 2C33, 2C35, 2C38, and 2C40 is 2C and the value of C34 and C39 is equal to C. Switches indicated with φ that are closed during the sampling mode and open during the tracking mode, serve for the charge of the input capacitors with the signals A1+−Z, B1+−Z, A1−−Z and B1−−Z and the discharge of the output capacitors during the sampling mode φ. Switches indicated with φ that are open during the sampling mode and may be closed during the tracking mode serve for the transfer of the charge of the input capacitors to the output capacitors during the tracking mode.
The switches φ that serve the transfer of charge from input capacitors to output capacitors, have references D, E, D and E indicating the range mode that they are closed during the tracking phase. The switches with reference φDE are closed during the tracking phase when D=0 and E=0, in which case charge transfer takes place from the input capacitors 4C31 and 4C36 to the output capacitors 2C′17 and 2C′18 respectively. Equal switches 3C32, C34, 3C37 and C39 referenced by φE are closed during the tracking phase when E=1 and the switches 2C33, 2C35, 2C38 and 2C40 referenced by φDE are closed during the tracking phase when D=1 and E=0.
The part of the residue generator for the second balanced output residue signals B2+, B2− is not shown in FIG. 9 but is identical to the part depicted in this figure with the exceptions that the indications A and B should be interchanged and that the references D and D should be interchanged. The equations resulting from the charge transfers in this arrangement are:



  
    
      for
      ⁢
      
        
      
      ⁢
      D
    
    =
    
      
        0
        ⁢
        
          
        
        ⁢
        and
        ⁢
        
          
        
        ⁢
        E
      
      =
      0
    
  




  
    
      
        
          
            A
            
              2
              +
            
          
          =
          
          ⁢
          
            Z
            +
            
              
                (
                
                  
                    A
                    
                      1
                      +
                    
                  
                  -
                  Z
                
                )
              
              ⁢
              
                
                  4
                  ⁢
                  C
                
                
                  2
                  ⁢
                  
                    C
                    ′
                  
                
              
            
          
        
      
    
    
      
        
          
            A
            
              2
              -
            
          
          =
          
          ⁢
          
            Z
            +
            
              
                (
                
                  
                    A
                    
                      1
                      -
                    
                  
                  -
                  Z
                
                )
              
              ⁢
              
                
                  4
                  ⁢
                  C
                
                
                  2
                  ⁢
                  
                    C
                    ′
                  
                
              
            
          
        
      
    
    
      
        
          
            B
            
              2
              +
            
          
          =
          
          ⁢
          
            Z
            +
            
              
                (
                
                  
                    B
                    
                      1
                      +
                    
                  
                  -
                  Z
                
                )
              
              ⁢
              
                
                  2
                  ⁢
                  C
                
                
                  2
                  ⁢
                  
                    C
                    ′
                  
                
              
            
            +
            
              
                (
                
                  
                    A
                    
                      1
                      +
                    
                  
                  -
                  Z
                
                )
              
              ⁢
              
                
                  2
                  ⁢
                  C
                
                
                  2
                  ⁢
                  
                    C
                    ′
                  
                
              
            
          
        
      
    
    
      
        
          
            
              B
              
                2
                -
              
            
            =
            
            ⁢
            
              Z
              +
              
                
                  (
                  
                    
                      B
                      
                        1
                        -
                      
                    
                    -
                    Z
                  
                  )
                
                ⁢
                
                  
                    2
                    ⁢
                    C
                  
                  
                    2
                    ⁢
                    
                      C
                      ′
                    
                  
                
              
              +
              
                
                  (
                  
                    
                      A
                      
                        1
                        -
                      
                    
                    -
                    Z
                  
                  )
                
                ⁢
                
                  
                    2
                    ⁢
                    C
                  
                  
                    2
                    ⁢
                    
                      C
                      ′
                    
                  
                
              
            
          
          ⁢
          
            

          
          ⁢
          
            
              for
              ⁢
              
                
              
              ⁢
              E
            
            =
            
              1
              ⁢
              
                
                  
                    
                      
                        A
                        
                          2
                          +
                        
                      
                      =
                      
                        Z
                        +
                        
                          
                            (
                            
                              
                                A
                                
                                  1
                                  +
                                
                              
                              -
                              Z
                            
                            )
                          
                          ⁢
                          
                            
                              3
                              ⁢
                              C
                            
                            
                              2
                              ⁢
                              
                                C
                                ′
                              
                            
                          
                        
                        +
                        
                          
                            (
                            
                              
                                B
                                
                                  1
                                  +
                                
                              
                              -
                              Z
                            
                            )
                          
                          ⁢
                          
                            C
                            
                              2
                              ⁢
                              
                                C
                                ′
                              
                            
                          
                        
                      
                    
                  
                
                
                  
                    
                      
                        A
                        
                          2
                          -
                        
                      
                      =
                      
                        Z
                        +
                        
                          
                            (
                            
                              
                                A
                                
                                  1
                                  -
                                
                              
                              -
                              Z
                            
                            )
                          
                          ⁢
                          
                            
                              3
                              ⁢
                              C
                            
                            
                              2
                              ⁢
                              
                                C
                                ′
                              
                            
                          
                        
                        +
                        
                          
                            (
                            
                              
                                B
                                
                                  1
                                  -
                                
                              
                              -
                              Z
                            
                            )
                          
                          ⁢
                          
                            C
                            
                              2
                              ⁢
                              
                                C
                                ′
                              
                            
                          
                        
                      
                    
                  
                
                
                  
                    
                      
                        B
                        
                          2
                          +
                        
                      
                      =
                      
                        Z
                        +
                        
                          
                            (
                            
                              
                                B
                                
                                  1
                                  +
                                
                              
                              -
                              Z
                            
                            )
                          
                          ⁢
                          
                            
                              3
                              ⁢
                              C
                            
                            
                              2
                              ⁢
                              
                                C
                                ′
                              
                            
                          
                        
                        +
                        
                          
                            (
                            
                              
                                A
                                
                                  1
                                  +
                                
                              
                              -
                              Z
                            
                            )
                          
                          ⁢
                          
                            C
                            
                              2
                              ⁢
                              
                                C
                                ′
                              
                            
                          
                        
                      
                    
                  
                
                
                  
                    
                      
                        
                          B
                          
                            2
                            -
                          
                        
                        =
                        
                          Z
                          +
                          
                            
                              (
                              
                                
                                  B
                                  
                                    1
                                    -
                                  
                                
                                -
                                Z
                              
                              )
                            
                            ⁢
                            
                              
                                3
                                ⁢
                                C
                              
                              
                                2
                                ⁢
                                
                                  C
                                  ′
                                
                              
                            
                          
                          +
                          
                            
                              (
                              
                                
                                  A
                                  
                                    1
                                    -
                                  
                                
                                -
                                Z
                              
                              )
                            
                            ⁢
                            
                              C
                              
                                2
                                ⁢
                                
                                  C
                                  ′
                                
                              
                            
                          
                        
                      
                      ⁢
                      
                        

                      
                      ⁢
                      
                        
                          for
                          ⁢
                          
                            
                              
                            
                            ⁢
                            
                              
                            
                          
                          ⁢
                          D
                        
                        =
                        
                          
                            1
                            ⁢
                            
                              
                            
                            ⁢
                            and
                            ⁢
                            
                              
                            
                            ⁢
                            E
                          
                          =
                          0
                        
                      
                      ⁢
                      
                        

                      
                      ⁢
                      
                        
                          
                            
                              
                                A
                                
                                  2
                                  +
                                
                              
                              =
                              
                                Z
                                +
                                
                                  
                                    (
                                    
                                      
                                        A
                                        
                                          1
                                          +
                                        
                                      
                                      -
                                      Z
                                    
                                    )
                                  
                                  ⁢
                                  
                                    
                                      2
                                      ⁢
                                      C
                                    
                                    
                                      2
                                      ⁢
                                      
                                        C
                                        ′
                                      
                                    
                                  
                                
                                +
                                
                                  
                                    (
                                    
                                      
                                        B
                                        
                                          1
                                          +
                                        
                                      
                                      -
                                      Z
                                    
                                    )
                                  
                                  ⁢
                                  
                                    
                                      2
                                      ⁢
                                      C
                                    
                                    
                                      2
                                      ⁢
                                      
                                        C
                                        ′
                                      
                                    
                                  
                                
                              
                            
                          
                        
                        
                          
                            
                              
                                A
                                
                                  2
                                  -
                                
                              
                              =
                              
                                Z
                                +
                                
                                  
                                    (
                                    
                                      
                                        A
                                        
                                          1
                                          -
                                        
                                      
                                      -
                                      Z
                                    
                                    )
                                  
                                  ⁢
                                  
                                    
                                      2
                                      ⁢
                                      C
                                    
                                    
                                      2
                                      ⁢
                                      
                                        C
                                        ′
                                      
                                    
                                  
                                
                                +
                                
                                  
                                    (
                                    
                                      
                                        B
                                        
                                          1
                                          -
                                        
                                      
                                      -
                                      Z
                                    
                                    )
                                  
                                  ⁢
                                  
                                    
                                      2
                                      ⁢
                                      C
                                    
                                    
                                      2
                                      ⁢
                                      
                                        C
                                        ′
                                      
                                    
                                  
                                
                              
                            
                          
                        
                        
                          
                            
                              
                                B
                                
                                  2
                                  +
                                
                              
                              =
                              
                                Z
                                +
                                
                                  
                                    (
                                    
                                      
                                        B
                                        
                                          1
                                          +
                                        
                                      
                                      -
                                      Z
                                    
                                    )
                                  
                                  ⁢
                                  
                                    
                                      4
                                      ⁢
                                      C
                                    
                                    
                                      2
                                      ⁢
                                      
                                        C
                                        ′
                                      
                                    
                                  
                                
                              
                            
                          
                        
                        
                          
                            
                              
                                B
                                
                                  2
                                  -
                                
                              
                              =
                              
                                Z
                                +
                                
                                  
                                    (
                                    
                                      
                                        B
                                        
                                          1
                                          -
                                        
                                      
                                      -
                                      Z
                                    
                                    )
                                  
                                  ⁢
                                  
                                    
                                      4
                                      ⁢
                                      C
                                    
                                    
                                      2
                                      ⁢
                                      
                                        C
                                        ′
                                      
                                    
                                  
                                
                              
                            
                          
                        
                      
                    
                  
                
              
            
          
        
      
    
  



The operation of the 1.5 bit architecture of FIG. 9 is illustrated in the arrow-graph of FIG. 10. The introduction of the input capacitors 3C32, C34, 3C37 and C39 has created a third range (E=1) between the original first and second ranges as shown in FIG. 7.
When the critical decision point determined in the comparator K2 of FIG. 5, i.e. the point where A1+=B1−, is corrupted, for instance by DC-offset of the comparator, then without the range E=1 not only the generated bit but also the generated residue signals for the subsequent stages in the cascade will be corrupted. The introduction of the third range (E=1) replaces the said critical decision point by two non-critical decision points namely the two borders of the third range. The arrangement described above with reference to FIG. 9 generates in this range non-corrupted balanced residue output signals. In a digital processor (not shown) the E-bit of the stage and the bits generated by the subsequent stages are used to calculate a new bit that replaces the not generated D-bit.
The converter stages described in the figures to this application are all intended to produce one bit per stage. The invention also covers stages that produce more than one bit per stage. For instance, it is quite feasible to have the first stage in the converter to produce two bits while the other stages are all single-bit. In a two-bit first stage a voltage divider for at least three reference voltages is required and the switches of the switched capacitor residue generator have to be controlled by both the generated bits. The advantage of such configuration is that more gain can be realized in the first stage, which improves the noise behavior of the converter.

## Claims

1. A dual residue pipelined AD-converter for converting an analog input signal to a digital output signal, said converter comprising
a cascade of dual residue converter stages,
at least two stages in the cascade of dual residue converter stages each including
switched capacitor means to receive two residue signals generated by a previous stage in the cascade, one of the residue signals representing quantization error relative to a first quantization level and the other one of the residue signals representing quantization error relative to a second quantization level,
means to derive one or more digital bits from said received residue signals, and
means to generate a respective first residue signal representing quantization error relative to a first quantization level and a respective second residue signal representing quantization error relative to a second quantization level, the first and second residue signals representing the quantization error resulting from an AD-conversion.

2. A dual residue pipelined AD-converter as claimed in claim 1 characterized in that the at least two stages each include input capacitors for receiving during a sampling phase the two residue signals generated by the previous stage, switching means to transfer during a tracking phase the charge of said input capacitors to first and second output capacitors, and means to generate the respective first and second residue signals from said first and second output capacitors respectively.

3. A dual residue pipelined AD-converter as claimed in claim 2 characterized in that said switching means are arranged to transfer charge from one of the received residue signals to said first output capacitor with a gain factor of approximately 2 and charge from both said received residue signals to said second output capacitor each with a gain factor of approximately 1 in a first sub-range mode and to transfer charge from the other one of the received residue signals to said second output capacitor with a gain factor of approximately 2 and charge from both said received residue signals to said first output capacitor each with a gain factor of approximately 1 in a second sub-range mode.

4. A dual residue pipelined AD-converter as claimed in claim 3 characterized in that said switching means are additionally arranged to transfer charge from both said received residue signals to said first output capacitor with a gain factor of approximately 3/2 and 1/2 respectively and charge from both said received residue signals to said second output capacitor with a gain factor of approximately 1/2 and 3/2 respectively in a third sub-range mode which lies symmetrically between said first and second sub-range modes.

5. A dual residue pipelined AD-converter as claimed in claim 2 characterized in that for the generation of each residue signal an operational amplifier is provided and that each output capacitor is connected during the tracking phase between an output terminal and the inverting input terminal of said operational amplifier.

6. A dual residue pipelined AD-converter as claimed in claim 5 characterized in that one side of each input capacitor is connected to said inverting input terminal both during the sampling phase and during the tracking phase and that each output capacitor is charged during the sampling phase by the offset voltage at the inverting input of the operational amplifier.

7. A dual residue pipelined AD-converter as claimed in claim 1, characterized in that the two residue signals are are balanced signals and the respective first and second residue signals are balanced signals.

8. A dual residue pipelined AD-converter for converting an analog input signal to a digital output signal, said converter comprising a cascade of dual residue converter stages,
the first of said stages including means to receive the analog input signal, means to derive one or more digital bits from said analog input signal and means to generate first and second residue signals representing the quantization error left after the AD-conversion of said first stage, and
each of the following stages in the cascade of dual residue converter stages including means to receive respective first and second residue signals generated by the previous stage in the cascade, means to derive one or more further digital bits from said received first and second residue signals and each of said following stages except the last one in the cascade include input capacitors for receiving during a sampling phase the first and second residue signals generated by the previous stage, switching mean to transfer during a tracking phase the charge of said input capacitors to first and second output capacitors, and means to generate first and second residue signals representing the quantization error left after the AD-conversion of the stage from said first and second output capacitors respectively,
characterized in that said switching means are arranged to transfer charge from said first received residue signal to said first output capacitor with a gain factor of approximately 2 and charge from both said first and second received residue signals to said second output capacitor each with a gain factor of approximately 1 in a first sub-range mode and to transfer charge from said second received residue signal to said second output capacitor with a gain factor of approximately 2 and charge from both said first and second received residue signals to said first output capacitor each with a gain factor of approximately 1 in a second sub-range mode.

9. A dual residue pipelined AD-converter as claimed in claim 8 characterized in that for the generation of each residue signal an operational amplifier is provided and that each output capacitor is connected during the tracking phase between an output terminal and the inverting input terminal of said operational amplifier.

10. A dual residue pipelined AD-converter as claimed in claim 9 characterized in that one side of each input capacitor is connected to said inverting input terminal both during the sampling phase and during the tracking phase and that each output capacitor is charged during the sampling phase by the offset voltage at the inverting input of the operational amplifier.

11. A dual residue pipelined AD-converter as claimed in claim 8, characterized in that each of said following stages except the last one in the cascade are arranged to receive balanced first and second residue signals from the previous stage and to generate therefrom balanced first and second residue signals for application to the next stage in the cascade.

12. A dual residue pipelined AD-converter for converting an analog input signal to a digital output signal, said converter comprising a cascade of dual residue converter stages,
the first of said stages including means to receive the analog input signal, means to derive one or more digital bits from said analog input signal and means to generate first and second residue signals representing the quantization error left after the AD-conversion of said first stage, and
each of the following stages in the cascade of dual residue converter stages including means to receive the first and second residue signals generated by the previous stage in the cascade, means to derive one or more further digital bits from said received first and second residue signals and each of said following stages except the last one in the cascade include input capacitors for receiving during a sampling phase the first and second residue signals generated by the previous stage, switching mean to transfer during a tracking phase the charge of said input capacitors to first and second output capacitors, and means to generate first and second residue signals representing the quantization error left after the AD-conversion of the stage from said first and second output capacitors respectively,
characterized in that for the generation of each residue signal an operational amplifier is provided and that one side of each input capacitor is connected to the inverting input terminal of the operational amplifier both during the sampling phase and during the tracking phase and that each output capacitor is charged during the sampling phase by the offset voltage at the inverting input of the operational amplifier.

13. A dual residue pipelined AD-converter as claimed in claim 12 characterized in that each output capacitor is connected during the tracking phase between an output terminal and the inverting input terminal of said operational amplifier.

14. A dual residue pipelined AD-converter as claimed in claim 12, characterized in that each of said following stages except the last one in the cascade are arranged to receive balanced first and second residue signals from the previous stage and to generate therefrom balanced first and second residue signals for application to the next stage in the cascade.