. (BASA-CE-178390) A FAULT IOJEC?ICIO N8 8-2 C E S5 

EYPEBIHEI'I USIYG 'JOE AIRLAE CIA.GECSTXC 

EEULATICI PACLIIXT (Research 'Iriangle 

Inst.) 130 p CSCL 09B Unclas 

G3/62 0 1345 EO 

NASA Contractor Report 178390 

A FAULT INJECTION EXPERIMENT 

USING THE AIRLAB DIAGNOSTIC 

EMULATION FACILITY 

Robert Baker, Scott Mangum, and Charlotte Scheper 

Center for Digital Systems Research 

Research Triangle Institute 

Research Triangle Park, North Carolina 27709 

Contract NAS1-17964 

Task Assignment No. 5 

March 1988 

National Aeronautics and 

Space Administration 

Langley Research Center 

Hampton. Virginia 23665 
NASA Contract Report 178390 

A lhWl,rl’ INJlCCTION EXPERIMENT 

USING rIIIJIC AIRLhF3 DIAGNOSTIC 

ICMMJ1,ATION FACILITY 

Robert Baker 

Scott Mangum 

Charlotte Scheper 

(:ontract NASl-17964 

‘I’:tsk ilssigninent No. 5 
!- 

I* 

TABLE OF CONTENTS 

I 

.. I. is1 of I'igurtxs it11d Tables ................................................................................. II 

1 . Introti~iction and Scope ..................................................................................... 1 

2 . Overview of the Data Communicator/Interstage and the 

Associated Gate Level Model ............................................................................. 4 

2.1 Functional Description ................................................................................ 4 

2.2 Circuit Description and Modeling Issues ..................................................... 7 

3 .................................................................................. . Ex p e ri men t P re p ar at io n 19 

3.1 Introduction .............................................................................................. 19 

3.2 Experiment Support Software ................................................................... 21 

3.3 Learning Use of the Diagnostic Emulator and 

Testing of Software Items .......................................................................... 25 

3.4 Development of a C/I Gate Level Model ................................................... 25 

Coni rn u ni cator/In t erst age .......................................................................... 27 

3.6 Validation of the C/I Emulation Model .................................................... 36 

3.5 Diagnostic Test Sequences for the Data 

.I . I>i agnos tic Em 11 lation Experiment Description and Results ............................ 40 

4.1 (;enrral I'lan ............................................................................................. 40 

4.2 The Expcri~nent ........................................................................................ 44 

'1.3 A~lillysis of Experiment Results ................................................................. 52 

4.4 Review of' Undetected Faults .................................................................... 70 

. 1.5 Infercnces Drawn from Experiment Results .............................................. 73 

5 . Coricl usions. 0 t)servations and Recommendations .......................................... 74 

li . Ite f'c I-(: 11 (.w ........................................................................................................ 76 

:\~)p(~n(lis .\ . I. istitlg of the Diagnostic Tests ....................................................... 77 

. \p1)(bn(lix [I . Di:l.griostic I:mulation Outputs for Non-faulted C/I ...................... 87 

i 
LIST OF FIGURES AND TABLES 

f'igure 1 . 1. Experiment Diagram .......................................................................... 3 

Figure 2.1. Fault Tolerant Processor (Quadriplex Version) ................................. 5 

Figure 2.2. C/I Exchange Network ...................................................................... 6 

Table 2.1. Data Communicator Operations ........................................................ 7 

Figure 2.3. FTP Communicator .......................................................................... 8 

Figure 2.4. Actual Circuitry for Cross Channel Links ........................................ 11 

Figure 2.5. More Accurate Model Used for Cross Channel Links ....................... 12 

Figure 2.6. Simplified Model Used for Cross Channel Links .............................. 13 

I'igiire 2.7. Programmable Logic Array .............................................................. 15 

Figure 2.8. Voter Syndrome Quaderror Function .............................................. 16 

Figure 2.10 Write XMIT State Diagram ............................................................. 18 

Figure 2.9. Communicator Control Sequencer ................................................... 17 

f7igure 3.1. System Flow Diagram ....................................................................... 20 

Figure 3.2. Network Initialization ...................................................................... 22 

Figure 3.3. Emulation Process ............................................................................ 23 

C/I Instruction Mnemonics .............................................................. 25 

Figure 3.4. Block Diagram of Test Circuit ......................................................... 26 

f4.i gure 3.5. Net work Model Preparation (Desired) ............................................. 28 

Figure 3.6. Network Model Preparation (Actual) ............................................... 29 

Figure 3.7. Cornmunicator/Interstage Exchange Network ................................. 31 

1;igure 3.8. Mask Transform/Source Locking Test ............................................. 32 

F'igiirc 3.9. Error L. ogging/Masking Network 

(One Network for Each Processor) ....................................................... 33 

1:igrire 3.10. Typical C/I Self Test Sequence for a 

Singlc Test Vector ................................................................................ 35 

It'igrire 3.1 1 . Tests 1Jsed for Experiment .............................................................. 37 

'Table 3 . L . 

Figure 3.12. Diagnostic Sequences ....................................................................... 38 

tl'igu re .I . 1 . Coiii 111 unicator/In te rstage Model ..................................................... 41 

b'igiire .I. 2. Si III 11 lation Result Space .................................................................. 42 

I~igure 4.3. Diagnostic Sequences ........................................................................ 43 

Ii'igrire .1 .. 1. Fa. tilt Sets by Functional Group ...................................................... 45 

li'igiirt> ,1.5. Coriim iinicator Fault Set Boundaries ............................................... 46 

I'igriro ,I.(;. 'I'y1)ical Good Circuit Output .......................................................... 47 

Il'igri rv 4.7. Ty pic:tl Post-P rocessing Out put ...................................................... 48 

Figiirc .I. 8. Erriiilation CPIJ Time ....................................................................... 49 

b'igiire .I.( 1. Soritc> Diagnostic Emulation Experiment Numbers .......................... 50 

b'igiiw . 1. Io . Sritnmary of Diagnostic Emulation Speed ....................................... 51 

1~'igiirt~ I . I I . I'rc~sr~rice Test ................................................................................... 53 

ii 
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3 

I'igrirc . 4.12. Currrnt Status Update Test ............................................................ 55 

ld'igiirp 4.13. Mask Transform Qiiad Test ............................................................ 56 

I'igurv '1.14. Mask Transform XAXB Test ........................................................... 57 

I:igurv dt.l(j. Diagnostic Test Performance ........................................................... 60 

I'igurc 4.18. Performance of Best Test for A 

Given Fault Set .................................................................................... 62 

Figure 4.19. Performance of Worst Test for A 

Given Fault Set .................................................................................... 63 

Figure 4.20. Performance of Best Vectors Across All Tests ................................. 64 

I4'igtire 4.21. Presence Test (Best Vectors) ........................................................... 65 

t'igurc 4.22. Current Status Update Test (Best Vectors) ................................... 66 

I'igurc 4.23. Mask Transform Quad Test (Best Vectors) ..................................... 67 

.. I4 igur c. 4.1 S . Hasic Test ........................................................................................ 58 

Vigiirv 4.17. Combined Performance of all Non-voter Tests ............................... 61 

Figure 4.24. Mask Transform XAXB Test (Best Vectors) ................................... 68 

I7igure 4.25. Basic Test (Best Vectors) ................................................................. 69 

'Table 4.1. Summary of Undetected Faults ....................................................... 72 c 

iii 
1. Introduction and Scope 

Digital flight control systems for aircraft and spacecraft perform life or mission 

critical functions. Extremely high reliability requirements must be established and 

demonstrated for these systems. To meet the reliability and performance requirements, systems become complex. Complexity and demanding requirements combine to 

render the validation of system reliability difficult. Testing, sufficient to establish the 

high reliability of these systems, is not feasible. Consequently, sophisticated reliability 

modeling tools based on analytic models are needed to predict and validate reliability 

for both the design and development phases of fault tolerant systems. Reliability 

modeling tools depend upon the accurate determination of various model parameters 

such as fault coverage and fault latency. When system testing to determine such 

parameters is precluded, computer simulations can be used in some circumstances to 

stand-in for a system. This report describes the preparation for, conduct of, and results 

of a simulation-based fault injection experiment conducted using the AIRLAB Diagnostic Emulation (DE) facilities. 

The primary objective of this experiment was to determine the effectiveness of the 

diagnostic self test sequences used to uncover latent faults in a logic network providing 

the key fault tolerance features for a flight control computer. Since this experiment 

resulted in the most extensive use of the AIRLAB Diagnostic Emulation facilities to 

date, a secondary, but essential, objective was to develop methods, tools, and techniques for conducting the experiment. 

In this experiment, more than 1600 faults were injected into a logic gate level 

model of the Data Communicator/Interstage (C/I), a key component in the Charles 

Stark Draper Laboratories (CSDL) Fault Tolerant Processor (FTP). For each fault 

injected, diagnostic self test sequences consisting of over 300 test vectors were supplied 

to the C/I model as inputs. For each test vector within a test sequence, the outputs 

from the C/I model were compared to the outputs of a fault free C/I. If the outputs 

differed, the fault was considered detectable for the given test vector. These results 

were then analyzed to determine the effectiveness of various test sequences, to identify 

latent faults, and to identify opportunities for improving the performance of the diagnostic test sequences. Figure 1.1 diagrams the essential elements of the experiment 

(1 wign. 

The Data Communicator/Interstage of the FTP was selected because of the following: 

1. the C/I network provides for the critical fault 

tolerance features of input source congruency, error 

masking, error reporting and system reconfiguration, 

i 

3. the qiiadriplex C/I network used the full capacity of 

lhe AIRLAB Diagnostic Emulator, 

3. docurrieritation for the C/I design at the logic gate level 

was available, and 

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4. the results of the experiment could provide valuable 

information about the FTP design. 

To prepare for and complete this experiment, several major issues had to be considered. Chief among these were design capture for a complex network; validation of 

the model derived from the design capture; analyses and decisions that reduced the 

required simulation time while preserving essential information; the design of test 

sequences for a complex state network; the applicability of fault models for LSI technology; the complexity management issues associated with modeling, validating, and 

simulating a large network; CAD tools and procedures to handle the complexity 

management problems; techniques to maintain data integrity for extended simulations; 

techniques for improving fault coverage and latency; and performance measures and 

techniques for analyzing the effectiveness of test vectors. Each of these issues can 

develop into significant problem areas as system complexity increases with the 

advancement of integrated circuit and computer architecture technology. Specifically, 

simulation methods, techniques, and associated tools will have to advance to meet the 

demands of computer technology. Moreover, validation research in general will be significantly impacted by some of these issues. 

Section 2 of this report provides an overview of the C/I design and discusses the 

gate model used for various parts of the C/I. Section 3 describes the various activities 

involved in the experiment preparation process. Among the activities discussed are 

design capture, test sequence design, and model validation. In section 4, the conduct 

of the experiment is reviewed and the results are presented and analyzed. Section 5 

provides a summary of experiment results, a review of lessons learned from conducting 

the experiment and a discussion of extensions to this experiment. 

. 

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2. Overview of the Data Communicator/Interstage and +.he Associated Gate 

Level Model 

2.1. Functional Description[l] [2] [3] 

The Data Communicator/Interstage (C/I), which was modeled in this experiment, 

provides the Fault Tolerant Processor (FTP) with certain key fault tolerance mechanisms. These mechanisms include circuitry to support the correct replicatim of simplex 

source data in all good FTP channels, to detect and mask errors in a single FTP channel, and to support FTP reconfiguration by blocking out faulty channels. 

I 

Figure 2.1 shows a quadriplex FTP. 

Figure 2.2 shows the data exchange network associated with a quadriplex FTP. 

Each channel, A, B, C, or D, has a transmit and receive register which can be accessed 

by the input/output processor (IOP) or computational processor (CP) via a shared 

memory bus. 

Simplex source data, that is, data available to one FTP channel may be distributed correctly to all good FTP channels by using a FROM Xexchange. Referring to 

figure 2.2, a FROM A exchange, for example, will cause the data word in the communicator transmit register of channel A to be distributed to all other data communicators 

via the cross channel links. Data transfers between communicators and interstages are 

byte serial with two bytes comprising a data word. Data distributed to each communicator are passed to associated interstages. 

Each interstage replicates the data and passes a copy to each communicator. 

Each communicator votes the data received from each interstage and writes the voted 

data into the Receive Register. The Receive Registers are then read by the associated 

channel processor. In this matter, simplex source data from channel A is replicated in 

all good processor channels. FROM B, FROM C, and FROM D exchanges occur in a 

similar manner except that the source channel is B, C, or D respectively. 

If each channel has data which requires voting for fault masking, a FROM OWN 

exchange can be executed. Each channel places its copy of the data to be voted into 

its respective Transmit Registers. Data words are transmitted to the respective interstages which in turn replicate the data and distribute the copies to each communicator. Each communicator votes all copies of the data and returns the voted result to 

tlicl Receive Register for subsequent reading by its associated computer. 

Errors detected during the voting process of an exchange are recorded in the 

Status Registers of each communicator. The Status Registers of each communicator 

rmi tw rcwl hy their associated processors. It is intended that these error reports be 

iise(1 by tlic FTP to determine and isolate faulty channels. 

A write only Mask Register allows a channel to be excluded from the voting proTlie rapability to execute exchanges which by-pass the interstage and voter is process. 

vided for network testing. 

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I 

A 

B 

C 

I> 

FAULT TOLERANT PROCESSOR 

(Quadriplex Version) 

Memory GI Central 

Processor 

1 1 

Processor Bus 

I 

I/O 

L- T I 

Figure 2.1 

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C/I EXCHANGE NETW0R.K 

COMMUNICATORS XMIT INTERSTAGE COMMUNICATORS RECEIVE 

Figure 2.2 

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Table 2.1 lists the transactions on operating that can be executed by the communic ator. 

FROM A Exchange 

FROM B Exchange 

FROM C Exchange 

FROM D Exchange 

FROM OWN Exchange 

READ Receive Register 

WRITE Receive Register 

WRITE Mask Register 

READ FROM A Status Register 

READ FROM B Status Register 

READ FROM C Status Register 

READ FROM D Status Register 

READ FROM OWN Status Register 

Table 2.1. Data Communicator Operations 

2.2. Circuit Description and Modeling Issues 

Figure 2.3 is a functional block diagram for the C/I. Each area and the associated 

gate level models will be described in the following paragraphs. 

The processor interface consists of receivers for the 20 bit processor address bus; 

16 bit bidirectional tri-state data bus driver/receivers; and receivers or drivers as 

required for processor control signals, data acknowledge, read/write, system reset, system clock and fault tolerant clock. 

For purposes of simplifying the simulation model, the processor address bits associated with the base address for the memory mapped data communicator were consolidated into a single communicator select bit. This consolidation reduced the size of the 

input files for the simulation and speeded the simulation run time. A single and gate 

(address decoder) and the several address bit receivers were modeled as a single 

receiver. No essential fault coverage information was lost by this simplification. 

The bidirectional processor data bus was modeled as separate input and output 

ports because the Diagnostic Emulator had capability for either input or output connections. No essential fault coverage information was lost due to this modeling restriction. 

-7- 
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bo 

2 

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4 

The Local Data Bus is a 16 bit tri-state bus used to communicate as follows: 

From Processor Bus to Transmit Register 

From Processor Bus to Mask Register (5 bits) 

From Processor Bus to Receive Register 

From Receive Register to Processor Bus 

From Status Register (5 bits) to Processor Bus 

From Status Register (5 bits) to Current Status Update Logic 

From Result Bus to Receive Register Most Significant Byte 

From Result Bus to Receive Register Least Significant Byte 

From Transmit Register Most Significant Byte to Transmit 

Register Least Significant Byte 

This bus was modeled by use of and gates at each data source, enabled by the 

appropriate source enable signal, and by an or gate to combine the various data 

sources to one signal line. The resulting model was functionally equivalent to a tristate bus. The or function is a phantom gate in that there is no identifiable device in 

the network to which it can be associated. Despite its phantom nature, stuck-at zero 

faults were asserted on these devices during simulation to cover certain kinds of bus 

faults. 

The Transmit Register, Mask Register and Receive Register are all implemented 

with 74LS374 octal D-type latches with tri-state outputs. The storage portion of these 

devices were modeled directly as D-type flip-flops and the tri-state output portion were 

modeled as and gates feeding an appropriate bus or gate as indicated in the previous 

p R r agrap h . 

The Source Bus communicates data bytes from the Transmit Register to cross 

rhannel links and to the interstages. Also, data bytes from cross channel links can be 

tr:insff>rrecl to the interstages. This bus was modeled with and gates and phantom or 

gxtes similar to the Local Data Bus. 

‘The cross channel links which distributes data from each communicator Source 

1311s to all other communicators’ source busses is a bidirectional tri-state bus. The circuitry is ctiagrammed in figure 2.4. ,4n adequate model for this is shown in figure 2.5. 

Since this model required a significant number of connections (384) and phantom gates 

(96) and since these particular connections had to be hand edited into the network, 

the simpler model (192 connections and 0 gates) shown in figure 2.6 was used. This 

decision was based on incomplete analysis which indicated that the model adequately 

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. captured the network behavior. While data is handled properly by this model, the 

effects of faults in the Source Select logic which supplies the enable signals for the 

cross channel links were not accurately modeled. Consequently, certain gate faults 

were not found by the C/I diagnostics. As discussed in a later chapter, these faults 

cross channel links. 

The States Register file is implemented with two 74LS189 4x16 bit RAM chips. 

Only 5 status bits, A error, B error, C error, D error and Quad error, are recorded in 

each of the 5 exchange types. Thus, only 5x5 of the potential 8x16 bits are used for 

the Status Register file. The Status Register was modeled with five, five-bit D-type 

flip-flop registers and with the address decoder and selection logic necessary to direct 

five bits of data to and from these registers. 

The Mask Transform block receives the Mask Register bits (Mask A, Mask B, 

Mask C, Mask D, and Source Lock), the two channel identification (ID) bits, and the 

three exchange type bits to determine which, if any, channel to block from the voter 

logic and to select the source of data to be routed to the Receive Register. This function is implemented with a 2048X8-bit registered programmable read only memory. 

To model this device directly required that a Diagnostic Emulator overhead feature be 

used. 

data bit connections are associated with and determined by designated nodes within 

the network being simulated. To access this memory, a change on a designated control 

line will stop normal simulation of the network and will invoke an action which uses 

the state of the designated address nodes to select a particular location in the assigned 

memory block and to impose the state of the bits in this memory location on the designated data bit nodes. 

Since this operation is generally slower than gate simulation and since validation 

of the operation of this PROM was judged to be more difficult than validating an 

simple gate network at least until the rest of the C/I network could be validated. 

The interstages consist of drivers, receivers, and D-type flip-flops. These devices 

were modeled using the Diagnostic Emulator gate and flip-flop primitives. 

The Source Select, Current Status Update, Syndrome Or, Voter, and Voter Syn- 

(trome blocks are implemented using programmable logic arrays (PLA). A diagram of a 

typical PL,I is shown in figure 2.7. The logic equations programmed for each function 

wt’r-e rriotleletl clirectly. Figure 2.8 illustrates one of these functions. The adequacy of 

stuck-at gate fault models for these devices is questionable since certain bridging faults 

h(1twwn conductors carrying the input functions and a cell with the array cannot be 

:Lcciirately represented by such a simple model. A more elaborate gate model which 

would better represent these faults was beyond the scope of this effort. 

ID bits to control the cross channel links. The Voter and Voter Syndrome block 

I would have been found had the more complex and accurate model been used for the 

i 

I 

I This feature assigns a block of memory outside normal device simulation which 

can be used to store the contents of the memory being modeled. Memory address and I 

I 

I 

I equivalent gate network for this case, a decision was made to model this block with a 

I 

I The Source Select block shown in figure 2.3 uses exchange type bits and channel 

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ENABLE 

A SOURCE I 

ENABLE 

SOURCE BUS A 

1 

81-DIRECTIONAL /I TRI-STATE DEVICE 7 

CROSS CHANNEL STRAP 

---------------------------- 

COMMUNICATOR X 

1 

OURCE BUS X 

Figure 2.4. Actual Circuitry for Cross Channel Links 

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'1 

-- 

COMMUNICATOR A 

-------------- 

I CROSS 

CHANNEL 

LINK 

nom 

ENABLE 

PHANTOH 'OR' 

COMMUNICATOR x 

Figure 2.5. More Accurate Model Used for Cross Channel Links 

-12- 
X TO A CONNECTION 

2 

ENABLE 

PHANTOU 'OR' b lt SOURCE BUS A 

ENABLE 

A SOURCE 

'1 

A TO X CONNECTION 

'i 

ENABLE 

F"" 

PHANTOM 'OR" v 4 , SOURCE BUS X ENABLE 

SOMCE~ ~ ~ 

COMMUNICATOR X 

Figure 2.6. Simplified Model Used for Cross Channel Links 

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performs the bit-for-bit voting of non-masked data copies and dytects and reports 

errors for non-consistent data copies. These voter related functions are implemented 

in four PLA’s with two data bits (dibits) processed by each PLA. The Syndrome Or 

block consolidates errors (syndromes) reported by each Voter Syndrome dibit. The 

Current Status combines these consolidated errors with the contents of the Status 

Register. 

The final major block is the Control. This block provides the timed control signals to direct the operation of the Data Communicator. It is implemented using three 

2048 X 8-bit registered programmable read only memory devices. Since these devices 

are connected so that particular processor interface control signals, processor interface 

address bits, and certain of their own output bits are used to control their address 

inputs; a classical state machine with inputs, outputs, and internal states is implemented. This state machine is depicted in figure 2.9. The circuit is modeled using D 

flip-flops for the PROM register and the external memory feature of the Diagnostic 

Emulator. However, it was found that the contents of the PROM were highly redundant and that its size could be reduced to 512 words instead of 2048 words without losing any capability. Further reductions were possible but were not carried out. Figure 

2.10 shows the state diagram for the the Write hit operation controlled by this state 

machine. Review of this design indicated that, as a result of the redundancy in the 

contents of the PROM, the state machine would require substantial additional testing 

to establish functionality. The redundancy likely resulted from the use of a high level 

design tool. This observation has implications regarding the use of high level design 

tools for fault tolerant systems. 

Except for the Control block, four complete C/I’s were modeled. Only two Control blocks were modeled. One Control block provided control signals for channels B, 

C, and D. The other provided control signals for channel A. The Channel A C/I was 

the only C/I module faulted in the experiment. In addition to the four C/I’s, support 

logic which generated fault tolerant clock and processor clock had to be modeled. 

These signals were generated by a simple ring oscillator and a divide by counter. A 

ring counter was used to create a clock whose period in gate delays or event units is 

iipproximately equal to the actual processor clock frequency. The divide by counter 

used to generate the fault tolerant clock was set at 12 processor clock pulses instead of 

.IO as used in the FTP. This change reduced the required simulation time without losing essential information. 

Every flip-flop in the C/I model has a pseudo-gate connected in line with its output so that the flip-flop output can be faulted. The addition of the pseudo-gate circrimventeci a Diagnostic Emulator constraint which does not allow flip-flop outputs to 

I)(> directly faulted. The fault gate was automatically inserted into the netlist by the 

ncbtlist translator software on each occurrence of a flip-flop. Pseudo-gates were 

inserted into the model for each external input to the C/I that went to a flip-flop. 

These inserted gates were used to satisfy a Diagnostic Emulator requirement that no 

external input be directly connected to a flip-flop. Finally, external output devices 

which ha(] no internal connections were connected to sink gates. The sink gate 

. 

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Q 

d 

B 

E 

a 

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ADR SIRORE CQNTROL 20 BITTADDRESS Bzls 

v, 

PROCESSOR 

CLWK Al4-A20 DPROCESSOR 

f. ADDmDmDE CLOcrK 'M TYPE== 

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Rm REG 

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Figure 2.9. Communicator Control Sequencer 

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synccbus, let 

dtackp,clr,votc 

dkvo t e , Id-type 

Idle 

dkrcvlsb,clkvote I 

6 enressrc, swxcn 

swxcn,ldxmit 

shifmnit 

psQ 

- enrcsult ,clkrcvmsb 

cllrvo tc , cnrcss rc , swxen 

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c 

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r 

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oestat 

westat 

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Idle 

J!scL swxcn p: 

Figure 2.10. Write XMIT State Diagram 

Esrz! 

swxen 

lscL 

swxen 

ciucssrc 

BCL 

SwXcIl 

enrcssrc 

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c 

connection satisfied the restriction that all devices must have at least one internal connection. The output of each sink gate was in turn connected to one of its own inputs 

to meet this requirement. 

3. Experiment Preparation 

3.1. Introduction[4] [5] 

Most of the effort expended in the experiment was directed toward developing 

and validating the Data Communicator/Interstage (C/I) gate level model and the associated experiment support software. This experiment preparation process can be 

divided into several general areas of activity. These areas are 

1. the development and testing of experiment support software, 

2. the activities associated with learning to use the diagnostic emulator, 

3. the development of a gate level model of the C/I, 

4. the development of C/I input sequences that would test the C/I in 

accordance with the C.S. Draper Laboratories C/I diagnostic software 

description, and 

5. the validation of the C/I model. 

A brief description of the process used to set up and use a Diagnostic Emulation 

model will be given in this paragraph. A complete description of the Diagnostic Emulation portion of this process is given in the user manual.[4] Figure 3.1 diagrams the 

process. A description of the C/I logic network was created by using FUTURENET, a 

logic schematic capture computer-aided design tool. The resulting network description 

file was translated to a format suitable for input to the NASA-LaRC Diagnostic Emulation network initializer. This file, labeled QM-1 network, combined with files 

describing initial values for network nodes sand files establishing external connections 

to the network such as network input and memory data connections, was supplied to a 

network initializer program. The resulting initialized network file, combined with an 

emulation options file and external memory initialization files, was processed by an 

emulation initialization program. The resulting emulation file, along with option files, 

l':iuIt description files, and external input data files, was used as input to the emulation. If the FORTRAN Diagnostic Emulation program was to be used, these files were 

iis~d tlirwtly. If the QM-1 emulation was to be used, these files were converted and 

then transl'erretl to the NANODATA QM-1 machine for execution. The out'put of the 

emulation process wits used to examine the behavior of the model during the debug 

and validation phase and to provide the inputs for post-processing during the experiment phase. 

The process described above is shown in more detail in figures 3.2 and 3.3. Note 

that in figure 3.2 there is a loop through the network initializer, emulation 

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SCbuMtiC 

capture via 

U 

Futurmct 

I 

TEGAS WAS to QM1 

we mnilator 

I 

Figure 3.1. Syskem Flow Diagram 

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initialization, memory map creation, external connections, and back. to the network 

initializer. This loop is necessary to establish the address references required to define 

the external connections file. This part of the process is done once, provided the network does not change. Also note that in figure 3.3 the difference between a VAX 

b'ORTRAN emulation and a NANODATA QM-1 emulation is detailed. 

3.2. Experiment Support Software 

To use the existing Diagnostic Emulator to the extent required by the experiment, 

a number of new software utilities and tools had to be developed or procured. These 

items included the following: 

1. a FUTURENET schematic capture computer-aided design tool; 

2. a translator to convert FUTURENET netlists to a format suitable 

for the Diagnostic Emulation process; 

3. an expanded set of primitive control features for the Diagnostic 

Emulator: 

4. a set of programs to facilitate the preparation of Diagnostic 

Emulation options, connection, fault lists, input, memory, and 

initialization files; 

5. a C/I mnemonic instruction translator to aid the preparation of 

C/I diagnostic test sequences; and 

6. a program to analyze the outputs of the Diagnostic Emulation. 

At the start of this project, gate level models of hardware to be emulated had to 

be created using a hardware description language. The large text file that resulted was 

then translated to a netlist suitable for Diagnostic Emulation. Creating, maintaining, 

changing, and verifying this large test file was a tedious, time-consuming, and errorprone process. The FUTURENET computer-aided schematic capture tools were purchased to facilitate the creation of the C/I emulation model or any other hardware 

models. It was felt that these tools would reduce the effort required for creating, 

rnaintaining, and verifying the C/I model. Since the schematic level is the natural 

level at which design engineers work with and document designs, it was felt that 

models created at this level would be less subject to errors. 

A software program to convert FUTURENET/TEGAS netlists to the netlist forrniit for the Diagnostic Emulator was written by RTI personnel. For the purposes of 

minimizing the resources dedicated to this conversion software, the devices used in the 

C/I schematic were restricted to those used by the Diagnostic Emulator. Adding the 

capability to accept more general devices, which in turn would be translated to Diagnostic Emulator devices, is not precluded by this restriction. 

-21- 
I 

I 

I 

I 

I 

I 

I 

I 

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I 

I 

I 

I 

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I 

I 

I 

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1 

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ZN 

ow 

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33 

-22- 
.I 

-23- 
To meet the needs of a fault insertion experiment, new control primitives were 

required for the Diagnostic Emulator. The new primitives added were as follows: 

1. the capability to assert a stuck-at logic one or zero fault 

on any device output for a defined number of emulation steps, 

2. the capability to provide external logic inputs from an 

input data file at designated emulation event numbers, 

3. the capability to direct the output of designated logic nodes 

to an output file, 

4. the capability to assert a fault on a bit in external memory 

arrays, and 

5. the capability to define the length of an emulation run and to 

recycle the emulation using the next fault defined in a fault list. 

The capability to provide each of these primitive control features had been planned 

but had not been implemented at the beginning of this effort. These capabilities were 

added to both the VAX FORTRAN emulation and the NANODATA QM-1 emulation. 

The implementation of these software features was done by NASA personnel. 

A C/I mnemonic instruction translator was written to simplify the preparation of 

twt scquences for the experiment. This translator provided the conversion of 

mnemonic representations for each C/I instruction into the proper bit pattern. In 

itddition, pseudo instructions that allowed for defining iterative loops were provided. 

This latter Capability simplified the creation of long test sequences consisting of iterat,ive data values . Table 3.1 shows the mnemonics used. 

- 24- 
NAME DEFINITION 

VECB 

WCE 

LOOP 

END 

RDRR 

WRCV 

WXMR 

WMSR 

Pseudo op to define start of a new test vector 

Pseudo op to define end of a test vector 

Pseudo op to set up a repetitive sequence of C/I operations. 

Arguments specify the level of nesting and the iteration 

increments and limits 

Pseudo op to define the end of a loop 

Read receive register 

Write receive register; arguments are data for each C/I 

Write transmit register; arguments indicate source for each 

C/I (A, B, C, D) and data for each 

Write mask register; arguments indicate mask to be written 

for each C/I 

Table 3.1. C/I Instruction Mnemonics 

Emulation outputs from the experiment were processed to determine the faults 

detected by each test vector. 

3.3. Learning Use of the Diagnostic Emulator and Testing of Software Items 

A simple logic network was used as a vehicle to learn the use of the Diagnostic 

Emulator and to test the various new software items. In addition to simplicity, the 

rietwork was designed to be similar to the C/I and to require the use of all Diagnostic 

fSmiilator primitives in the C/I model. These primitives include fault insertion, exterrial inputs, external outputs, external memory arrays, and each type of logic device. 

Siicccwful setup and emulation of this network was an essential first step in learning 

t,he usc of the Diagnostic Emulator and for validating the new software development 

itcms. 

block diagram of this network is given in figure 3.4. The network was first 

:Lrialyzetl on a simple IBM PC-based simulator, EZCAD. The EZCAD results were 

used as a basis for comparing Diagnostic Emulator results. 

3.4. Development of a C/I Gate Level Model 

Some of the circuit details of the C/I gate level model are discussed in section 2. 

The desired process for creating the model is shown in figure 3.5. In this process, a 

schematic of the entire quad C/T network would be captured using FUTURENET. 

-25- 
+ 

I I 

YOTER 1 )Wm 

1 I 

Figure 3.4. Block Diagram of Test Circuit 

-26- 

A +.- 

*I 
The resulting netlist would then be converted to a form suitaLle for the Diagnostic 

Emulator. Changes to the model would take place at the schematic entry level and 

would he followed by the translation process. 

An attempt was made to carry out this process. However, the full quad C/I network was too large for certain of the FUTURENET support tools. Consequently, 

another less desirable process had to be employed. The actual process used is shown 

in figure 3.6. In this process, the full quad C/I was broken into smaller subnets. Each 

subnet was translated and these subnets were concatenated into a larger net. The 

interconnections between subnets were handled by editing these interconnections into 

the translated net file. While the number of interconnections was small relative to the 

total network, the editing process to produce these interconnections was prone to 

error. Further, this step made it difficult to return to the schematic level for model 

checking and for any model changes. This limitation of FUTURENET and the manner 

in which the model was created made it difficult to realize the full potential of 

computer-aided design capture. Unanticipated model network configuration control 

problems had to be solved, and checking of certain parts of the model was rendered 

much more difficult since it had to be done at the netlist level. 

An indicator of the potential for difficulties is found in the network size information. The full quad C/I network consisted of more than 5000 nodes (devices) and 

15,000 connections. About 20,000 lines of text, or more than 300 pages, were required 

to list the network. 

This network is relatively small compared to most VLSI designs. The only effective way to deal with such designs is with effective CAD tools. 

3.5. Diagnostic Test Sequences for the Data Communicator/Interstage[6] [7] 

The C/I plays a critical role in FTP fault tolerance by ensuring that all good pre 

cessors receive identical data values (source congruency), by masking errors, and by 

providing for FTP reconfiguration after faults are detected. An important part of FTP 

operation is the use of diagnostic test sequences for the C/I for both pre-mission and 

in-mission testing. These test sequences are used to uncover latent faults. This experirrieiit was directed toward determining the effectiveness of proposed diagnostic test 

st1qu e 11 res. 

.4 fatilt (lctxaction, isolation, and reconfiguration (FDIR) program is used in FTP. 

I;I>IR provides for hardware implemented fault detection and error reporting, software 

impleniented I'nult isolation based on the analysis of error reports, software implemented reconfiguration by disabling failed channels, and software implemented self 

tests to uncover latent faults. The C/I is tested with self tests that operate within the 

FDIR function. FDIR tests the C/I with a frequently executed high priority limited 

scope test, called Presence, and a somewhat exhaustive low priority test sequence, 

which is executed with a much lower frequency. 

PI [91 

-27- 
!I 

t 

SCHWATIC 

CAPTURE 

VIA 

RJTUAWET 

- 

- SCHEMATIC 

DRAWINGS 

L 

: TEGAS 

TO DE 

TRANSLATOR 

Figure 3.5. Network Model Preparation 

(Desired) 

: TEGAS 

TO DE 

TRANSLATOR 

-28- 
I 

t 

I 

TE6AS 

TO OE 

TRIWSUTW 

I 

OE 

FILE 

-1 

I. 

Figure 3.8. Network Model Preparation 

(Actual) 

-29- 
The Presence test is a simple test that is executed at the beginning of a processing 

frame to determine the presence of each processing channel of the FTP. During this 

test, unique data values from each channel are exchanged via the C/I. Correct. 

exchange of a channel’s unique values establishes presence. 

The low priority C/I self tests of the FDIR assume that a certain class of C/I 

faults, such as hard errors in the data path, will be detected in the normal course of 

processing acd/or by the Presence test. Those areas of the C/I logic not stimulated in 

the normal course of operation are the focus of the self tests. These areas include error 

detection, error reporting, fault masking, and reconfiguration logic. 

The main components of the low priority C/I self tests are as follows: 

1. the Voter PAL Test, 

2. the Mask Transform Test, 

3. the Voter Syndrome Or Test, and 

4. the Current Status Update Test. 

The C/I voter is implemented using programmable logic array chips. The voting 

and error detection logic is contained in the voter PAL chips. Two bits of a data byte 

from each FTP channel are voted within a single PAL package. Four voter PAL packages are required for each communicator. The inputs to these PAL chips include 

dibits from each channel and a mask bit for each channel, as shown in figure 3.7. The 

Voter PAL Test consists of sequencing through all combinations of inputs to each 

voter PAL chip for both the least and most significant byte of a data exchange. This 

exhaustive test is used because certain failure modes of a PAL can result in any input 

to the chip coupling to any PAL output. This is true even if the gates associated with 

a given output are not programmed to accept all input signals. The total number of 

test vectors required for this test are 216. 

The Mask Transform Test targets the channel mask or blocking logic (see figure 

3.8). This logic provides the capability to exclude a channel from the voting process. 

This component of the self test requires 192 test vectors. 

The Voter Syndrome Or Test targets the two PAL chips associated with combining the error outputs of the 4 voter PAL chips. The test is intended to test only those 

gates not previously tested by the Voter PAL Test. This test was not completely 

(Icfined at the time of the fault injection experiment. 

’The Current Status Update Test is intended to uncover faults in the current 

st,atris lipdate PAL chips (see figure 3.9). In this test, all combinations of data 

exchange errors are stimulated by selection of appropriate test vectors. Stimulated 

errors are logged into the Status Registers. These test vectors are followed by test vectors that stimulate additional data exchange errors. The Status Register is then 

checked to determine if it is properly updated. 

-30- 
TRANSMIT INTERSTAGES 

8/ 

RECEIVE 

I 

- I 

XMIT .. I 

8 

Figure 3.7. Communicator/Interstage Exchange Network 

I 

-31- 

/ 

81 -1 

8, 

.. 

I Inter- I E /- * 

I stage I 
I 

' 

SOURCE 3, I 

EXCHANGE 

RCV .....L REG B( v 

SYN .. .. .. 

A 

Tests For Each PROM Input: 

I I Test Number 1 

(Nuinl)er of Mask Transfer PROM Test Vectors) = 6 - 32 = 192 

Figure 3.8. Mask Transform/Source Locking Test 

-32- 
Voter Current. 

i- Status 

Or Up d at. e 

sy I1 d I'OllleS 

> Syndrome ' 

Local Data Bus I i 

Status 

Registers 

( R Abl) 

r 

Mask 

(PROM) 

* w Transform Mask 

Registers 

A 

B 

C 

D 

- 1 

Syndromes 

- LBAD 

- RBAD 

- MBAD 

- OBAD 

- QERR 

Figure 3.8. Error Logging/Masking Network 

(One Network for each Processor) 

-33- 
Figure 3.10 illustrates a typical sequence of C/I transacti ns associat d with single test vector. Three transactions are required to exchange data, read the results, and 

retrieve the associated error report. This does not include any special setup of the 

Mask Registers and Status Registers. Once exchange results and error reports are 

obtained, it is necessary for all channels to exchange this data. This allows all good 

channels to arrive at a consensus on the results of a test vector. A total of nine 

exchange and read transactions are required for each vector. Each exchange/read 

transaction pair requires about 10 psec to complete in real time. 

Assuming that the C/I self test requires approximately 216 test vectors, and that 

the self test is constrained to use only five percent of the C/I throughput capacity, the 

C/I self test will require approximately two minutes to execute. This time sets a 

bound on the fault latency time for faults detectable via the C/I self tests. 

Estimates of the time required to conduct a fault injection experiment using the 

Diagnostic Emulator are of interest. Consider an experiment that requires the injection of 2000 faults and requires that the C/I self test sequence (about 216 test vectors) 

be executed completely for each fault. Assume that the NANODATA QM-1 is used. 

Also assume that only the self test transactions must be executed, i.e., the C/I 

throughput is 100% dedicated to self test for the experiment. The QM-1 version of the 

Diagnostic Emulator will execute approximately 50,OOO:l slower than real time for the 

C/I network. The total simulation time required would be approximately 19 years. If 

the VAX FORTRAN version was used at 106:1 slower than real time, the simulation 

would require approximately 3.8 centuries! 

The unacceptably long run times cited in the preceding paragraph provide 

motivation for restricting the extent of an experiment. If the simulation time requirements are reduced by a factor of about 1O00, 200 QM-1 hours would be required. Such 

a simulation time requirement would be well within the feasible range. 

In the planning stage of this experiment, the self test for the C/I used substantially fewer test vectors. The number of test vectors used by C.S. Draper Laboratories 

(CSDL) at that time would have resulted in reasonable simulation time requirements. 

The exhaustive test implemented by the new self tests greatly expanded the simulation 

time. 

A reduction in simulation time by a factor of 9 can be obtained by recognizing 

that the exchanges required to share opinions in an actual FTP would not be required 

in an experiment. An additional factor of about 100 was needed and was obtained by 

reducing the number of test vectors. 

Recall that the exhaustive testing addressed certain PAL failure modes. It was 

determined that these failure modes would not be reflected in a direct gate level model 

of the PAL logic. Consequently, the large set of test vectors could be reduced and not 

change the outcome of an experiment based on a gate level model. Further, it was 

decided to test the C/I voters only for the quadriplex and triplex configurations and 

only for one of the voter PAL chips. 

-34- 
From X [Test 

Read Receive Register Test, Vector 

Read Status 

Fromh [ 

Read R.eceive Register 

From A [Voted Status] 

Read Receive Register 

From B [Voted Dat~] 

Read Receive Register 

From B [Status] 

Read R.eceive Share 

From C [Voted Data] Opinions 

Read Receive 

From C [Status] 

Read Receive 

From D [Voted Data] 

Read Receive 

Froni D [ 

Read Receive 

9 Exchanges about 10 psec each 

Figure 3.10. Typical C/I Self Test Sequence for a Single Test Vector 

-35- 
The tests prepared for the experiment are summarized in figures 3.11 and 3.12. 

‘rests are characterized by the number of test vectors within a test, by the number of 

C/I transactions or instructions required for the test, and by the number of DE simulation steps required for the test. These tests include about 600 test vectors that are in 

the desired range. Appendix A gives detailed listings of these tests. 

3.6. Validation of the C/I Emulation Model 

The purpose of the validation process was to establish, to the greatest extent possible, that the C/I emulation model accurately reflected the behavior of the C/I. Most 

of the funding for this emulation experiment was directed toward this effort. In general, the validation of a complex model would be difficult. For this experiment, several 

factors further complicated the validation process. 

Ideally, the emulation model for a network would be created automatically from a 

design data base using well-established software programs, and the design verification 

data base of test vectors and results would be available for use. In this experiment, 

design information used to create the emulation model was in the form of a schematic 

drawing and a design description. Furthermore, access to the C/I designer was limited. To create the emulation model, the schematic was manually entered into a computer using a CAD schematic capture tool. The devices used in the design were 

replaced with Diagnostic Emulation gate primitives prior to schematic capture. The 

translation of the netlist for the captured schematic to a form suitable for Diagnostic 

Emulation was accomplished using a software program developed for this experiment. 

As described in section 3.5, certain of the network model interconnections had to be 

established by editing the translated netlist text files. Additional experiment software, 

described in section 3.3, was developed to support the experiment. This software 

included modifications to the Diagnostic Emulator. 

When discrepancies were found during testing/debugging of the model, errors in 

the design capture, errors in the new software, errors in the changes to the Diagnostic 

Emulator, errors in the use of the Diagnostic Emulator, and errors related to modeling 

issues were all candidates for the source of the problem. Engineering analysis based on 

liniited design documentation was required to devise tests for the model, to determine 

the correctness of the responses, and to devise additional tests for isolating the source 

of detected errors. 

The 

l,utc.d to 

1. 

2. 

3. 

additional complications of the validation process for the C/I can be attrithe following: 

the status of the Diagnostic Emulation facilities in AIRLAB 

(i.e., changes, limitations, and documentation) at the start of the 

experiment, 

the design capture process that was employed, 

the development of software to facilitate model development, and 

-36- 
0 Voter Tests 

Tested a single voter PAL chip (2 bits) 

in the qua.d and triplex configurations. 

Used both upper and lower bytes to give 

two test vectors per vote. 

0 Mask Transform Tests 

Tested mask transform logic for quad 

and duplex configurations 

0 Current Status Update Test 

Tested the current status update PAL 

0 Presence Test 

Equivalent to CSDL “Presence” 

0 Basic Test 

RTI test which tested a range of C/I 

functions beyond “Presence” 

Figure 3.11. Tests Used for Experiment 

-37- 
TEST 

NAME I ABBREV 

XBR 

VECTORS 

Presence 

Current Status 

Update 

p r esen ce 10 

cstupd 10 

Mask Transform 

Quad 

msktrnq 12 

Mask Transform 

XAXB 

msktrnxaxb 24 

NBR 

INSTRS 

s n4 

STEPS 

62 8400 

64 11900 

Basic I basic I 16 112 11900 

84 9900 

160 19200 

24 I msktrnxcxd I Mask Transform 

XCXD 

160 19200 

Voter Test vbOlquadl 772 98000 

Quad1 

Voter Test v bO 1 quad 2 

Quad2 

772 ~ 98000 

64 I vb013xa 

Voter Test 

BO1 3XA 

388 ' 48700 

64 kiii I vb013xb 

Voter Test 

BO1 3XB 

388 

64 I vb013xc 

Voter Test 

BO1 3XC 

388 1 48700 

64 I vb013xd 

Voter Test 

BO1 3XD 

388 ' 48700 

Figure 3.12. Diagnostic Sequences 

-38- 
4. the absence of a design verification data base of test vectors and 

responses. 

The effort to validate a model could have been reduced considerably by the appropriate use of well-established CAD tools that were integrated into the hardware design 

data base. The uncertainty as to the possible sources of model discrepancies encountered in this first AIRLAB Diagnostic Emulation experiment would be reduced for 

additional experiments. Integration of the design data base into the Diagnostic Emulation facilities would eliminate problems associated with design recapture. Finally, 

integration of the design data base would permit the use of the design verification test 

vectors and responses and would reduce the need for the validator/experimenter to 

fully understand the operation of the network modeled and to analyze the detailed 

responses of the network. 

The validation process for the C/I model relied to some extent on the software 

testing afforded by the emulation of the simple network described in section 3.3. The 

approach to verifying the C/I model was to verify the C/I microsequencer logic and to 

then add additional C/I functions. The C/I microsequencer model was verified using a 

simple IBM PC-based simulator, EZCAD. This simulator provided easy-to-use graphical logic analyzer-type outputs. The microsequencer was verified against its documented state transition diagram for each operation type. A microsequencer model was 

prepared for the VAX FORTRAN Diagnostic Emulator and was verified for each state 

transition and output. This provided a source of correct control signals for subsequent 

testing of the C/I model. 

The full C/I model that incorporated the verified microsequencer model was 

prepared for the VAX FORTRAN Diagnostic Emulator. This model was tested for 

each operation type with various data inputs. Numerous design recapture errors were 

found and corrected. Next, sequences of operations with various data values were 

emulated. Errors were found and corrected. Finally, all the diagnostic test sequences, 

except for the non-voter tests, were used as the emulator inputs. The emulator output 

for each test sequence was verified for correctness. 

The QM-1 version of the Diagnostic Emulation was not available when the model 

verification was complete. Consequently, the experiment was started using the VAX 

FORTRAN version. Once the QM-1 version became available, a QM-1 C/I model was 

prepared. This model was verified against extensive emulation results from the VAX 

b'ORTRAN version for both good circuit and faulted circuit conditions. Non-faulted 

(;/I outputs for each diagnostic test sequence are included in appendix B. 

Errors stemming from each of the possible sources enumerated above were found 

(1 \iring the validation process. However, most errors, including the most difficult errors 

to isolate, were traced to the manual editing of interconnections into the large netlist 

text file. 

As noted earlier, the validation part of this experiment required the most effort. 

Without appropriate CAD tools integrated into the design data base, it would be difficult to justify the cost of experiments using other designs of similar complexity. This 

-39- 
experiment involved a network of relatively modest complexity (5000 gates) relative to 

modern VLSI (50,000 to 100,000 gates). Standards for verifying the accuracy of network models are much higher for highly reliable fault tolerant systems. The only costeffective way to manage the complexity of modern VLSI designs for a highly fault 

tolerant system will be with the use of well-established validated CAD tools that are 

integrated into a common design data base. 

I 4. Diagnostic Emulation Experiment Description and Results 

4.1. General Plan 

The general plan for this experiment is to do the following: 

1. emulate at the gate level the Charles Stark Draper Laboratories 

(CSDL) Fault Tolerant Processor's Communicator/Interstage 

(C/I) hardware using the AIRLAB Diagnostic Emulator facilities, 

2. insert single faults into the gate level model, 

3. for each inserted fault, use the CSDL diagnostic self test 

sequence for the C/I as inputs for the emulation model, 

4. determine if observable errors are produced in the emulation model 

output for each fault inserted, and 

5. evaluate the results of the experiment. 

Figure 4.1 diagrams the emulation setup. Test vectors from the C/I diagnostic 

self test sequence were used as input to a gate level model of the C/I network. Faults 

that model stuck-at-one and stuck-at-zero gate output failures were inserted into the 

gate level model. Each fault was inserted for a complete pass through the diagnostic 

self test sequence, only one fault was present in the network during any pass through 

the self test sequence, and faults were only inserted into the channel A portion of the 

C/I. For each fault and test vector, outputs from the C/I model and both data and 

error reports were compared against the outputs produced by a fault-free C/I model. 

If the outputs differed, the fault was designated as detectable for the test vector in 

qiies t ion. 

Figure 4.2 diagrams the output space for this experiment. Originally, 600 test 

brrctors were planned (see section 3.5), but only 328 were used. These test vectors were 

grouped into tcsts associated with a particular purpose or functional area within the 

C/I. These tests are listed in figure 4.3 along with their associated parameters. Faults 

were grouped into sets associated with a particular functional area. Figure 4.4 lists the 

falilt groupings, and figure 4.5 diagrams the functional areas associated with these 

fault sets. Note that within Voter and Voter Syndrome fault sets, devices associated 

with 2 of the 8 bits were faulted. Excluding these faults reduced the experiment 

-40- 
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-42- 
TEST 

NAME 

presence 

cstupd 

P r esen ce 10 G2 8400 

10 G4 11900 ~ 

Current Status 

Update 

msk trnxcxd 

vbOlquad1 

Basic 

24 lG0 19200 

128 772 98000 

Mask Transform 

QUAD 

Mask Transform 

XAX-B 

Mask Transform 

XCXD 

Voter Test 

Quadl 

Voter Test 

Quad2 

Voter Test 

BO1 3XA 

Voter Test 

BO1 3XEl 

Voter Test 

1301 3xc 

Voter Test 

no 1 :3XD 

ABBREV I VECTORS NBR I INSTRS NBR I STEPS 

basic I 16 I 112 I 11900 

l2 I 84 I 9900 

msktrnq 

~~ ~ 

24 1 160 I lg2Oo 

msktrnxaxb 

vb01quad2 I 128 I 772 I 98000 

64 I 388 I 48700 

vb013xa 

64 I 388 I 48700 

vb013xb 

G4 I 388 I 48700 

vbOl3xc 

vb013xd I 64 I 388 I 48700 

Figure 4.3. Diagnostic Sequences 

-43- 
duration. Since the network topology for the remaining 6 bits was the same as for the 

2 bits where faults were injected, the results for the 2 bits could be used to determine 

the results for the remaining 6 bits. This grouping of faults and test vectors was found 

to be a useful way to interpret experiment results and to draw conclusions regarding 

the effectiveness of particular test vectors. Figure 4.6 shows a typical output from the 

emulation. The single number on a line is the simulation time step and the four 

numbers on a line are the outputs from the four channels of the C/I model. Figure 4.7 

is a typical post-processing output. For each vector in a self test sequence and for each 

fault in a fault set, the faulty circuit emulation output values are compared to good 

circuit emulation output values. If the outputs differ, the fault is considered to be 

detected by that test vector. The “1” entry in figure 4.7 indicates that the fault was 

detected. The score (the number of faults found) for each vector is given at the bottom of the fault list, and the number of vectors in the designated test detecting a particular fault is given in the right hand column. The first run and additional runs 

within the fault list are for fault-free conditions. Emulator outputs from the first run 

were used as the reference for subsequent faulted outputs. Emulation runs required 

large amounts of computer execution time and complex setup procedures. The opportunity for errors was of concern. Consequently, additional fault-free runs were 

included to help ensure consistent results. This precaution did, in fact, result in finding several problems during the experiment. 

4.2. The Experiment 

Originally, the NANODATA QM-1 version of the Diagnostic Emulator was to be 

used for this experiment and the VAX FORTRAN version was to be used for validating the model. Since the changes to the QM-1 version were not completed when the 

model validation was complete? the experiment was started using the AIRLAB VAX 

computers. After the QM-1 version became available, it was used to complete the 

experiment. Figure 4.8 summarizes the use of AIRLAB computing resources during 

the experiment. It should also be noted that more than 300K blocks of disk storage 

were in use at various points during the experiment. Figure 4.9 details some interesting experiment-related numbers. One interesting observation is that the total amount 

of real time operation of the C/I that was simulated was only two seconds. Another 

interesting number is the average stack size (12 devices) for the emulation algorithm. 

This number indicates the average number of devices whose outputs change during a 

givcn simulation step. It is indicative of the potential savings in processing time that 

roiild he realized by an event-driven simulation versus a simulation that must compute 

ill1 clrlvice oritpiits for each event time. The ratio of average stack size to total network 

si~c (I 2:5000) is substantial and represents a considerable reduction in device computat ioris. However, it is also indicative of a design that has low device activity. A ratio of 

1:20 should be more typical. From the numbers in figure 4.9, it is possible to estimate 

the average device computations per second required for an equivalent non-eventdriven sirnulation of this network. Figure 4.10 summarizes these calculations. It 

shoiild be noted that for fault simulation, a time resolution equivalent to 1/2 or 1 clock 

cycle is often sufficient. It was found that the QM-1 version operated about 6OK:l 

slower than real time for this network, and that the VAX 11/780 was about 1.2X1O6 

-44- 
Group I Number of Faults I 

Local Data Bus I 128 I 

Source Bus 370 

1 GO 

Curreii t, Status LJpdate 106 

Source Select 120 

Syndrorlle Or llG 

Voter/ANJX/Result Bus I 264 

Voter Syndrome 132 

Mask T r a.n sf o r III 62 

Microsequencer & Control 

Fan-out 

216 

I 1674 

Figure 4.4. Fault Sets by Functional Group 

-45- 
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0 

a8 

... 

2 

a 

E 

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I 

I 

I 

I 

I 

I 

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I 

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I 

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I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I I I 

Y 

CI 

a 

a 

kl 

8 

Y 

(d 

0 

E 

.-) 

3 

a a 

6 

I I I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

J 

I 

I 

I 

I 

I 

I 

I 

r----'----J 

I 

I 

I 

I 

I 

I 

I 

I 

J 

-46- 
TEST SEQUENCE - MSKTRNXAXB 

12 

0 0 

100 

0 0 

244 

0 0 

388 

0 0 

532 

0 0 

658 

0 0 

These numbers represent 766 

simulatton the step for 0 0 

whtch the followlng C/I + 1270 

GOOD CIRCUIT + FAULT CONDI1'10!% 

0 0 

0 0 

0 0 

0 0 

0 0 

0 0 

0 0 

outputs were sampled. 146063 146063 146063 146063 

1396 ' 

11 11 11 

These data are outputs / 

from the four C/I's. 

1522 

2026 

0 0 0 0 

34307 34307 

2152 

11 11 

2278 

0 0 

2782 

143470 143470 

2908 

3 3 

3034 

0 0 

3538 

31714 31714 

3664 

5 5 

3790 

0 0 

4294 

107760 107760 

4420 

3 3 

4546 

0 0 

5050 

107760 107760 

5176 

5 5 

5302 

0 0 

5410 

0 0 

5914 

34307 34307 

6040 

11 11 

6166 

34307 34307 

11 11 

0 0 

143470 143470 

3 3 

0 0 

31714 31714 

5 5 

0 0 

107760 107760 

3 3 

0 0 

107760 107760 

'5 5 

0 0 

0 0 

34307 34307 

11 11 

Figure 4.6. Typical Good Circuit Output 

-47- 
Fault file: CSrUP1FAULT.DAT 

Vector file: CSTUPD.VEC 

Data file: csTtrp1OUT.DAT 

. --I" vollulcIu..,. 

2 = no fault 

3 = stuck at "0" 

4 = stuck at "1" 

.- 

2. APAlGO1 

3; APAlGO1 

4, APAlGO2 

5. APAlco2 

6, APAlGO3 

7, APAlG03 

a, APMGO~ 

9, APAlG04 

10, ApAlGos 

11, APAlGOS 

12, APMGO6 

13, WAlGO6 

14, APAlGO7 

15. APAlG07 

16, APAlG08 

17, APAlG08 

18, APAlGO9 

19, APAlGO9 

20, APAlGlO 

21, APAlClO 

22, APAlC11 

23, APAlGl1 

24, APAlGl2 

25. APAlGl2 

26, APAlG13 

27, APAlGl3 

28, APAlG14 

29, APAlG14 

30, APAlGl5 

31, APAlGl5 

32, APAlGl6 

33, APAlG16 

34, APAlGl7 

35, APAlG17 

36, AF'AlG18 

37, APAlG18 

38. APAlG19 

39, APAlGl9 

40, APAlG20 

41, APAlG20 

42 4 

43, APAlG21 

44, APAlc21 

45. ApAlc22 

# 

0 

0 

, 

. 

8 

, 

8 

# 

, 

, 

, 

0 

, 

0 

0 

0 

0 

0 

, 

, 

, 

46; APAlG22 . 

47, AFPPMFOO , 

48, AFPPAlFOO , 

49, APAlC23 , 

50, APAlG23 , 

51, 

Y 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

4 

3 

2 

4 

3 

4 

3 

4 

3 

4 

3 

2 

'1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

i 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1' 

1 

1 

1 

7 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

1 

- 

10 

10 

6 

4 

6 

4 

6 

4 

6 

*4 

2 

1 

6 

2 

6 

2 

6 

2 

6 

2 

0 

10 

0 

0 

10 

0 

3 

10 

6 

4 

6 

0 

6 

0 

6 

0 

0 

6 

2 

6 

4 

6 

4 

,4 

6 

0 

a 

a 

a 

a 

Figure 4.7. Typical Post-Processing Output 

-40- 
Test ~~ ~ 

Presence 

Basic 

Current Status 

Update 

Mask Transfom 

XAXB 

Mask Transform 

Quad 

Voter XA 

Voter XIB 

Voter XC 

Voter XD 

~~ 

VA% 111750 

84 hrs. 

72 hrs. 

244 hrs. 

400 hrs. 

VAX 11/780 

34 hrs. 

38 hrs. 

65 hrs. 

122 hrs. 

259 hrs. 

Figure 4.8. Emulation CPU Time* 

I>ow 11 o t, i 11 c 1 11 d e post.- 1’ 1.0 c essi II g 1 

QM- 1 

6.6 hrs. 

6.6 hrs. 

13.2 hrs 

-49- 
Network size 

Si III u I at i on resol u t ion 

Gate delays per clock 

Clocks/Fault tolerant clock 

Average stack size of 

Even t-driven simulation 

Maximum stack size of 

Event- d riven simulation 

Total faults 

Tot a1 C/ I transact ions cycles/ f au 1 t 

Transaction cycles in experiment 

Si mu lat ion steps 

To tal real time 

:> 5000 (ieviccs 

> 15OOO in tercon nections 

1 gate delay - 511s 

18 - 120 ns 

12' 

12 devices 

- ,500 devices 

1670 

2034 

- 3 ?i lo6 

- 3.6 x lo8 

- 2 seconds 

*Actual fault tolerant clock has 40 processor clock periods. The simulation was scaled to 12 to reduce run time. 

Figure 4.9. Some Diagnostic Emulation Experiment Numbers 

-50- 
Processor 1 Gate Even t.s,/'Sec 

VAX' 11/750 

VAX 11/780 

QM-1 . 

1 s lo3 

2 x lo3 

37 lo3 

Real Time Ratio I 

2.4 x lo6 : 1 slow 

1.2 x lo6 : 1 slow 

60 x lo3 : 1 slow 

Est ab 1 ishi n g e qu i v a1 e: n c e to a no n- e\: en t:- d r i v en 

siniulation is difficult 

If equivalent time resolution is required for the nonevent-driven simulation, the comparable speeds are 

VAX 111750 500k Gates/Sec 

VAX 11/780 

QM- I 

1 x lo6 Gat.es/%ec 

20 s loG Gat.es/Sec 

If 1/2 clock period time resolution is required, then the 

comparable speeds are 

VAX 111750 50k C: rttles/Sec 

VAX 111780 1OOk Gatles/Sec 

QM- 1 2 x lo6 Gates/Sec 

Figure 4.10. Summary of Diagnostic Emulation Speed 

-51- 
slower than real time. 

4.3. Analysis of Experiment Results 

The experiment data presented in this section are not adjusted or modified to 

account for certain modeling problems identified after the experiment was complete. 

These problems will be discussed in a later section. Primarily, results are organized by 

diagnostic test and fault set. For each self test/fault set pair, the percentage of faults 

detected relative to the number of faults injected within the fault set are presented. 

Test vectors with the best and worst scores for each test/fault set pair are identified. 

The relative and combined performance results of the self tests are presented. Finally, 

the percentage of faults found by the best vector within a test relative to the number 

of faults detected by the test are examined. 

Before reviewing these results, it should be noted that conclusions and observations are subject to the following: 

1. There are limitations due to the adequacy of a gate 

level fault model for the C/I implementation technology; 

2. Faults were only injected in a single emulated C/I; 

3. The number of faults within a fault set varies; 

4. Self tests reflect RTI’s understanding of the CDSL 

self test description; 

5. Faults were injected in devices associated with two of the eight 

voter bits. 

The Presence (P) test results shown in figure 4.11 are of particular interest. 

CDSL executes all vectors of this test prior to every FTP processing frame (typically 10 

msec to 40 msec) under their FDIR program. Presence is a short test (small number of 

test vectors) relied on to establish the general health of the C/I channels. Note that 

the results for the Mask fault set are not shown due to loss of these computer data. As 

can be observed from figure 4.11, this test is very effective for detecting data path 

faults (Local Data Bus and Source Fault Sets). However, the performance for other 

fault sets such :E the Voter Syndrome set is about 50%. Overall, the performance of 

this test is about 62% against the injected faults. However, when adjusted for the 

clc>vic.es not faulted in the Voter and Voter Syndrome fault sets, the performance is 

rlowr to FiSu6. Kote also that both the single best and worst test vectors for the entire 

test will detect about 50% of the faults. Since this test is executed frequently, the 

itvcrage latency time for about half of all C/I faults is very short. Further, each vector 

is very efftctivc relative to overall test performance. Since this test requires a small 

riurnber of‘ test vectors, it will require only a small portion of the FTP processing 

rosoii rces. These data confirm the CSDL assumption regarding the effectiveness of 

-52- 
0 0 0 0 0 0 0 0 0 0 0 

0 a 00 h ID Ln T m cu d 

Tf 

-63- 
Presence for data path faults. 

Figure 4.12 gives the results for the Current Status Update (CSU) test. This short 

test is designed to test certain of the Status Register update logics, and of necessity 

must exercise parts of the error .reporting logic. As can be observed and as is expected, 

this test performs substantially better than the Presence test for the Status Update 

and Syndrome Or fault sets. CSU test performance is considerably less than Presence 

for the data path fault sets and is about the same for the remaining fault sets. The 

overall performance is about 50% against the injected faults. When adjusted to 

include the devices that were not faulted in the Voter and Voter Syndrome fault sets, 

the performance is about 40%. The low CSU test performance for the Source Select 

fault set should also be noted. 

The results for the two Mask Transform tests are given in figures 4.13 and 4.14. 

The Mask Transform Quad (MTQ) test has 12 test vectors and the Mask Transform 

XAXB (MTA/B) test has 24. Both tests target the C/I reconfiguration logic. Overall, 

both tests perform better than Presence. As should be expected, their performance 

against the mask fault set is somewhat better than the ubiquitous 50%. Also, their 

performance against the Voter Mux fault set is good. Their overall performances are 

near 70%. When adjusted for the additional voter bits, their performance is still 

above 65%. 

The results for the last non-voter test, Basic (B), are given in figure 4.15. This 

test is an abbreviated version of the one of the tests designed by RTI for the validation 

of the C/I model. These results are included as a point of reference. Since the test was 

not optimized against a comprehensive fault model, it is not intended as a recommended test. It does demonstrate that simulations can be used to consider alternative 

tests and demonstrates the potential for improvement in test performance. Basic 

requires 16 test vectors. The Basic test performs well on the data path faults and has 

better performance than Presence against the Status Reg, Status Update, Syndrome 

Or, arid Control fault sets. Further, its performance approaches that of MTQ and 

MTA/B for the Mask fault set. The overall performance of Basic is in excess of 70% 

agairist the injected faults and exceeds 65% when adjusted for the devices not faulted 

in the Voter and Voter Syndrome functions. 

The overall performance of each non-voter is shown in figure 4.16. The combined 

performance is close to 90% and is not significantly affected when adjusted for the 

devises riot faulted in the Voter and Voter Syndrome functions. Figure 4.17 shows the 

combined performance of all non-voter tests for each fault set. Also shown are the perf'orrriance improvements provided by the voter tests. With the voter tests included, 

overall performance is 92%. The voter tests used were XA, XB, XC, and XD and 

~~~qiiirecl a total of 256 test vectors. The non-voter tests required a combined total of 

72 test vectors. Figure 4.18 identifies and shows the performance of the best test for 

each fault set. Figure 4.19 shows the performance of the worst test for each fault set. 

The extremely poor performance of CSU against the Source Select fault set is not 

shown. Instead, the next worst test, MTA/B is indicated. Figure 4.20 shows the performanccb of the best single vector for each fault set and for the entire set of test 

-64- 
4 

a 

z 

I 

0 0 0 0 0 0 

cu -3 

0 

0 

0 0 0 0 

0 cn 00 h m Ln Kl- T.7 1 

-55- 
3 0

-50- 
I 

I 1 1 1 1 1 1 1 I 1 

1 I 

0 0 0 0 0 0 0 0 0 0 0 

0 0 a3 h Lo Ln v 0 cu d 

d 

-57- 
c I 1 1 1 1 1 1 I 1 

0 0 0 0 0 0 0 

cu d 0 0 0 0 

0 0 cn h u3 Ln v m 

rl 

-58- 
vectors. It is interesting to note that the performance of the best single vector is about 

50%. Figures 4.21 through 4.25 show for each fault set and test the percentage of 

faults found by the best vector within the test relative to the total number of faults 

found by the test. These results tend to support an assertion that for C/I network 

configuration, a high percentage of the faults that can be detected by a given test will 

be detected by a small percentage of the test vectors. Such an assertion is not true for 

all network configurations and care must be exercised in the conclusions that can be 

drawn from these data. However, the concept of identifying those test vectors that are 

more effective in terms of detecting more faults has special significance for fault 

tolerant systems. The time required to find a fault is at most T and on average is 22. 

The average time that faults remain latent within a system can be reduced by using 

the more effective test vectors more frequently than the less effective vectors. The 

potential for reduction of fault latency time is discussed in more detail in section 4.5. 

-59- 
1 1 1 I 1 I 1 1 I 1 

1 

0 0 0 0 0 0 0 0 0 0 0 cu -A 0 m 113 b co m P m 

. 

u 

u 

c 

d 

cc 

0 CI 

k 

a 

ct 

rm u 

Y 

a 

0 

c 

2 -- 

a 

-80- 

ol 

c; 

ri 

t 

0 

0 

so 

I I 

0 0 0 0 0 0 0 0 0 

m 

0 0 cu d 00 b u3 m v 

+ 

c 

U 

+ 

c 

c: 

t 

: 

c 

.C 

C 

s 

c 

C 

+ U 

+ 0 

i 

; 

c 

C 

c 

0 

b 

C 

c 

C 

a 

E 

C 

; 

a 

a 

r 

-.! 

; 

t 

.C 

k 

-62- 
3 

8 

3 

5 

l--+-+-I 1 1 1 1 1 1 

0 0 0 0 0 0 0 0 0 0 0 

0 cn ID F\ Io u-) m cu -A 

Ti 
l-t- 1 I 1 1 I I i 

0 0 0 0 0 0 0 0 0 0 0 

cn al b m 113 TJ m cu d 12 

-64- 
-t-- 

0 

17) 

-+ 

0 al 

I I I 

I I I I I 

I 1 1 

0 0 0 0 0 0 0 0 

I\ u3 LD u- m rn T( 

-05- 
10 

0 

t+ 

u 

U 

w 

tn 

3 

9 

cc 

0 

*.( 

cc 

W d 

Y 

m 

2 

al 

Y 

cd 

a 

-66- 
t 1 1 I I 1 I I I 

I 1 i 

0 0 0 0 0 0 0 0 0 0 0 

0 m a, b LD ln -T 0 cu T- I 

71 

-67- 
t 

0 

0 

0 

03 

-+-- I 1 

I 1 I 1 

0 

Lo 

1 

1 1 

m 

1 

0 0 0 

0 0 0 -3 Ln T 0 0 nl 

CD r\ 

7-i 

-88- 
-89- 
4.4. Review of Undetected Faults 

A detailed review and analysis of the device faults that were not detected in this 

experiment is presented in this section. Failure to detect certain of the faults will be 

found to be due to bus modeling problems. Other fault detection failures will be 

found to be due to deficiencies in the tests used. A few fault detections failure will be 

found to be undetectable by any test. 

The total number of faults that were not detected by any test was 141. Of these, 

47 were found to be contained in the Source Select fault set. Also, figure 4.17 shows 

that the combined performance against Source Select faults is less than for any other 

fault set. A detailed examination of the devices associated with these undetected 

One problem area was in a group of devices whose faulted condition could not be 

detected due to the bus modeling problem discussed in section 2.2. An accurate model 

of the cross channel interconnections would likely have resulted in these faults being 

detected. 

The remaining undetected faults in the Source Select fault set were associated 

with the C/I channel ID logic. The ID logic permits C/I modules ta be used for any 

C/I channel. When a module is used in a channel A processor, hardwired inputs force 

the ID logic to allow the module to function as the channel A C/I. Similarly, ID logic 

establishes the identity of modules used in other channels. If certain of the devices 

associated with channel ID are faulted in such a manner that the local channel identity 

is unchanged, these faults are indistinguishable from fault-free devices. Since there are 

no provisions for stimulating different channel ID inputs under processor control, none 

of these faults can be detected. It is not clear whether the effects of these faults are of 

significance. If the devices for a given C/I fail in the manner described, the C/I 

module will continue to operate properly so long as the module is always used for that 

channel. Non-coverage of these faults could, however, affect maintenance procedures. 

It is not uncommon for replicate modules within a system to be interchanged with a 

module that is suspected of being faulty. The potential for ambiguous results exists if 

an apparently functioning module with one of these latent faults is substituted for a 

suspected faulty module. 

The fault set with the next largest number of undetected faults is the Control set 

with 26. Examination of the associated devices indicated several problem areas. 

Again, certain of the undetected faults were traced to the cross channel bus modeling 

problem arid to the ID logic problem. Several other undetected faults were traced to 

flchviws that provide certain control signals directly to the processor interface. These 

f;~ults would be detected by the associated FTP channel processor. Either these devicw should not have been included in the fault set, or their outputs should have been 

included in the C/I model’s external outputs and subsequently checked for proper 

state in the experiment post-processing. Finally, three undetected faults were found to 

he associated with devices which propagate the system reset signal. Failure of these 

devices in a state equivalent to an inactive reset signal cannot be detected if the failure 

occurs ;&rr a valid reset has occurred. The significance of such latent faults is open to 

I 

I faults indicated that most, if not all, were associated with one of two problem areas. 

I 

~ -70- 
speculation. Failure to be able to reset could have only transient and inconsequential 

effects on a system provided that the C/I microsequence controller always returns 

itself to an idle state. However, these faults are undetectable during normal operation 

and as such represent a potential problem. 

The Voter Syndrome fault set had 19 undetected faults. After examination of the 

associated devices, it is believed that the Voter Quad test, which was not used for this 

experiment, should detect these faults. Although planned for the experiment, the use 

of the Voter Quad test could not be completed prior to the end of the experiment. 

The Status Update fault set contained 16 undetected faults and the Syndrome Or 

fault set contained 14 undetected faults. An assessment of these faults was inconclusive, but it is believed that the Voter Quad test would detect some portion of these. 

The Status Register fault set contained 15 undetected faults. An examination of 

these determined that the decode logic in the Status Register memory was associated 

with the undetected faults. They are undetected because the C/I Status Registers 

automatically reset after a Read Status Register operation and because the CSDL self 

test diagnostics, as understood by RTI, include a Read Status Register for each test 

vector. Unless a test causes different errors to be written in each Status Register prior 

to a read of any of the registers, address decode logic faults cannot be distinguished 

from fault-free behavior. A simple modification of the self tests should render these 

faults detectable. 

The four undetected faults in the Mask fault Set were associated with the ID logic 

problem described above. Fault sets, Source Bus, Voter Mux, and Local Data Bus contained no undetected faults. 

Table 4.1 summarizes the undetected faults, the causes for not being detected, 

and the estimated relevant undetectable faults. 

If the assessments of the undetected faults are correct and if the ID logic faults 

are considered inconsequential, the adjusted performance for the C/I self tests would 

exceed 98% and could approach 99.8%. If the reset faults are inconsequential, the performance approaches 100%. 

-7 1- 
Fault Set 

Source Select 

Control 

Voter Syndrome 

Status Update 

Syndrome Or 

Status Reg. 

Mask 

Local Data Bus 

Voter Mux 

Source Bus 

Com bined 

Undetected 

Faults 

47 

26 

19 

16 

14 

15 

4 

0 

0 

0 

141 

Source 

Cross channel 

model & ID logic 

ID logic & cross 

channel + product 

interface & reset 

not known 

not known 

Status Reg 

address decode 

ID logic 

Comments 

Run Voter Quad Test 

Run Voter Quad Test 

Run Voter Quad Test 

modify self test 

Estimated 

Undetectable 

0 

3 

0 

0-16 

0-14 

0 

0 

0 

0 

0 

3-33 

Table 4.1. Summary of Undetected Faults 

-72- 
I' 

I. 

4.5. Inferences Drawn from Experiment Results 

As indicated in the previous section, care must be exercised in the use of the 

experiment results. Performance numbers derived for the various tests are subject to 

the limitations of fault models, network models, and the correctness of the self tests. 

While such results cannot be considered to be precise, they can be used in some 

instances to support specific observations and conclusions. This section reviews the 

inferences drawn from the experiment data. 

The experiment results support the CSDL assumption that the Presence test will 

detect a high percentage of the C/I data path faults. In addition, Presence detects 

approximately 60% of device output faults. 

Certain faults occurring in the C/I ID logic and the system reset logic cannot be 

detected. The significance of these undetectable faults is open to speculation and an 

assessment of such is beyond the scope of this report. 

Particular faults occurring in the Status Register address decode logic cannot be 

detected by reading the Status Register after every test vector input to the C/I. If the 

CSDL self tests use this procedure, these faults will be undetectable. A simple modification of a portion of the self test would remedy this problem. 

Finally, the results suggest that certain of the test vectors detect a considerably 

larger number of faults than do other test vectors. Even though certain test vectors 

are less productive, they may be required to detect faults that are undetectable with 

the most productive test vectors. Average fault latency time could be reduced if these 

more productive test vectors are used more frequently than the less productive, but 

necessary, test vectors. 

To demonstrate the potential for reduction in average latency time for faults 

within a network, consider a test composed of Vdifferent test vectors which detects all 

network faults. Assume that each vector can be imposed on the network in time T. If 

all faults are equally likely to occur and if each vector is used once per test repetition, 

the average latency time for faults is VT/2. Suppose that 4/5 of the faults are 

detected by 1/5 of the test vectors. Define a new test composed of the same test vectors. Since the prime test vectors are four times more effective than the remaining test 

vectors, repeat the prime vectors four times more frequently than the remaining test 

vectors. The time required to complete such a test would be 8/5 VT. The average 

latency time for a fault would be 8/25 T. Thus, the new test would give. a shorter 

average latency time. This would directly reduce fault recovery times, which would 

reduce the exposure to near-coincident faults. 

Consider the average latency of the C/I FDIR self tests. From section 3.5, it is 

known that the Presence test is repeated in every processing frame and that the 

remaining C/I self tests could require approximately two minutes to complete. Assume 

that a processing frame is typically 40 msec. Experiment results indicate that the performance of the Presence test is about 60%. The remaining 40% of the faults must be 

found by the slow FDIR self tests. Average latency time for C/I faults using FDIR 

I) (: corn os 

-73- 
L = - 0.6 x 0.04 sec + 0.4 x 120 sec FZ 24 sec. 

- 2 '[ 1 

Experiment data indicates that the performance of the Presence test could be 

improved by modest increases in the number of test vectors. Both Basic and Mask 

Transform Quad have better performance than Presence and require fewer test vectors. Assume that this opportunity is not exploited. Experiment results also indicate 

that the combined performance of all non-voter tests (72 test vectors total) is on the 

order of 90%. When adjusted for model discrepancies and the ID logic, the performance is closer to 95%. Assume that a new FDIR test is designed. Assume that it 

consists of 100 test vectors that are executed with a frequency of 5 seconds and that it 

detects 35% more faults than does the Presence test. The slow FDIR is expected to 

detect the remaining 5% of the faults. The average latency for this scenario becomes: 

L = - 0.6 x 0.04 sec + 0.35 x 5 sec + 0.05 x 120 sec 4 sec. 

- 2 'i 1 

The improvement in average latency from 24 seconds to 4 seconds is substantial. 

The results of this experiment have been used to identify potential problem areas 

and to identify areas where performance can be improved by relatively modest changes 

to the self test diagnostics. 

5. Conclusions, Observations, and Recommendations 

The objective of this section is to briefly summarize the relevant conclusions and 

observations discussed in detail throughout this report. In addition, several efforts 

that are natural extensions to this experiment are discussed. 

The results of the experiment summarized in section 4.6 are as follows: 

1. Presence detects a high percentage of data path faults; 

2. Presence detects about 60% of all C/1 gate output faults; 

3. Certain faults in the C/I ID and reset devices cannot be 

detected by any test vector; 

4. Faults in the address decode logic of the Status Register 

will not, be detected by test vectors that include a Status 

Register Read after each transaction; 

5. Opportunities to reduce average fault latency and to 

improve overall performance are suggested by the results. 

x ost of the effort in this experiment was directed toward recapturing the C/I 

design and validating the C/I model derived from the recapture process. To effectively 

deal with VLSI scale designs, well-established CAD tools that are integrated into a 

design data base containing design verification test vectors will be required. 

-74 
Faster simulators will be required to support the complexity of VLSI. However, 

significant work can be accomplished with existing simulators. For studies where 

simulation results are examined in detail, faster simulators would provide results more 

rapidly than could be assimilated. 

The applicability of the gate level fault model used in this experiment is limited 

for modern devices such as gate arrays [8][9]. Since bipolar technology was employed 

for the current C/I implementation, the experiment results are more applicable than if 

FET based technology had been used. The main exception to this observation is the 

PAL devices used in the design. 

Network size relative to the tools and techniques used impacted all phases of this 

effort. The complexity management problems for this modest-sized network not only 

lead to the validation problems discussed above, but impacted areas such as experiment run times, model configuration management, and computer storage requirements. 

Dealing with more complex designs without better tools would not be cost-effective. 

The amount of computer time required to complete simulations of this scale or 

greater and the standards for the integrity of results derived for highly reliable systems 

combine to require that a methodology for using simulations include fault tolerance 

and error detection mechanisms. For example, the chances of a computer error affecting the results derived from an extremely long simulation run can become significant. 

The microsequencer for the C/1 was designed using a high-level design tool. The 

state transition table generated by this tool was highly redundant due to the manner 

in which certain address bits were allowed to reach the microsequencer register, 

PROM. While the design was functionally correct and was easy for the designer to 

create, it was much harder to test. This relatively minor example suggests that the 

new high-level design tools used to support cost-effective modern VLSI design could 

produce designs that are less testable and more expensive to validate. These tools are 

optimized for design functionality and for cost-effective designs. They are not optimized for testability. 

The experiment provided information on the performance of the Diagnostic Emulator. The VAX FORTRAN version is a factor of 1.2X106 slower than a real time C/I. 

The QM-1 version is about a factor of 60X103 slower. For the C/I with its unusually 

low activity gates, the QM-1 version of the Diagnostic Emulation should compare 

favorably with higher performance parallel non-event-driven VAX-based simulators. 

Natural extensions to the experiment described in this report are as follows: 

1. to execute the Voter self tests that were not completed; 

2. to modify diagnostic tests to confirm that Status Register 

address decoder faults can be detected: 

3. to modify cross channel link models and confirm that certain 

faults become detectable; 

-76- 
4. to modify the DE fault model to include faults on gate 

inputs and to repeat the experiment; 

5. to inject faults into other C/I.channels and observe 

test vector performance; 

6. to fault the PROM bits of the C/I microsequencer to determine performance against these faults; 

7. to build a gate level model of the PAL device that more 

accurately models the failure modes in gate arrays, to run 

self tests, and to compare results to the less sophisticated 

fault model; 

8. to inject some double faults to determine the probability 

of a double fault leading to system failure. 

These possible extensions of the original experiment would benefit from the fact 

that a C/I model has been created and validated. 

6. References 

1. 

2. 

3. 

4. 

5. 

6. 

7. 

8. 

9. 

J. Lala, Advanced Information Processing System (AIPS) System Specification, 

The Charles Stark Draper Laboratories, Cambridge, MA (May 29, 1984). 

G. Hughes, FTP Parallel Data Communicator and Interstage, The Charles Stark 

Draper Laboratories, Cam bridge, MA (November 26, 1984). 

G. Hughes, Data Communicator Schematic Number FTPO.23, FTP024, The 

Charles Stark Draper Laboratories, Cambridge, MA (May 29, 1985). 

B. Becker, Diagnostic Emulator User’s Manual, NASA-Langley Research Center 

CR178391 (December 1987). 

G. Migneault, The Diagnostic Emulation Technique in the AIRLAB, NASA TM 

4027, NASA-Langley Research Center (1 938). 

G. Troxel, Communicator Self Test Software, The Charles Stark Draper Laboratories, Cambridge, MA (September 17, 1985). 

G. Troxei, Fault Detection, Isolation and Recon figuration Software, The Charles 

Stark Draper Laboratories. Cambridge, MA (September 24, 1985). 

$J. Abraham and W. Fuchs, “Fault and Error Models for VLSI,” Proceedings of the 

fEEE 74, no. 5(May 1986). 

F. Somenzi and S. Gai, “Fault Detection in Programmable Logic Arrays,” 

Proceedings of the IEEE 74, no. 5(May 1986). 

-76- 
APPENDIXA 

Listing of the Diagnostic Tests 

-77- 
Presence Test Program 

RSTR A A A A 

RSTR B B B B 

RSTR C C C C 

RSTR D D D D 

RSTR 0 0 0 0 

WMSK M31 M31 M31 M31 

VECB WXMR A A A A A0 DO DO DO 

RDRR 

VECE RSTR A A A A 

VECB WXMR A A A A A1 D1 D1 D1 

RDRR 

VECE RSTR A A A A 

VECB WXMR B B B B D1 BO D1 D1 

RDRR 

VECE RSTR B B B B 

VECB WXMR B B B B DO B1 DO DO 

RDRR 

ECE RSTR B B B B 

VECB WXMR C C C C DO DO CO DO 

RDRR 

ECE RSTR C C C C 

VECB WXMR C C C C D1 D1 C1 D1 

RDRR 

VECE RSTR C C C C 

VECB WXMR D D D D D1 D1 D1 D2 

RDRR 

VECE RSTR D D D D 

VECB WXMR D D D D DO DO DO D3 

RDRR 

VECE RSTR D D D D 

VECB WXMR 0 0 0 0 A0 A0 A0 A0 

RDRR 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 A1 A1 A1 Al 

RDRR 

VECE RSTR 0 0 0 0 

-78- 
Current Status Update Test Program 

WMSK M15 M15 M15 M15 

RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 A0 A1 A1 A1 

WXMR 0 0 0 0 A1 A1 A1 A1 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 A1 A0 A0 A0 

WXMR 0 0 0 0 A0 A1 A1 A1 

VECE KSTR 0 0 0 0 

VECB WXMR 0 0 0 0 B1 BO B1 B1 

WXMR 0 0 0 0 B1 B1 B1 B1 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 BO B1 BO BO 

WXMR 0 0 0 0 B1 BO B1 B1 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 C1 C1 CO C1 

WXMR 0 0 0 0 c1 c1 c1 c1 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 CO CO C1 CO 

WXMR 0 0 0 0 c1 c1 co c1 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 D1 D1 D1 DO 

WXMR 0 0 0 0 D1 D1 D1 D1 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 DO DO DO D1 

WXMR 0 0 0 0 D1 Dl Dl bO 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 A1 A1 C1 C1 

WXMR 0 0 0 0 D1 D1 D1 D1 

VECE RSTR 0 0 0 0 

VECB WXMR 0 0 0 0 BO BO DO DO 

WXMR 0 0 0 0 CO CO A0 A0 

VECE RSTR 0 0 0 0 

-79- 
Basic Test Program 

RSTH A A A A 

RSTR B B B B 

RSTR C C C C 

RSTR D D D D 

RSTR 0 0 0 0 

VECB WRCV DO DO DO DO 

VECE RDRR 

VECB WRCV D2 D2 D2 D2 

VECE RDRR 

VECB WRCV D3 D3 D3 D3 

VECE RDRR 

WMSK MO MO MO MO 

VECB WXMR A A A A D2 DO DO DO 

RDE2R 

VECE RSTR A A A A 

VECB WXMR A A A A D3 DO DO DO 

RDRR 

VECE RSTR A A A A 

VECB WXMR B B B B DO D2 DO DO 

RDRR 

VECE RSTR B B B B 

VECB WXMR B B B B DO D3 DO DO 

RDRR 

VECE RSTR B B B B 

VECB WXMR C C C C DO DO D2 DO 

RDRR 

VECE RSTR C C C C 

VECB WXMR C C C C DO DO D3 DO 

RDRR 

VECE RSTR C C C C 

VECB WXMR D D D D DO DO DO D2 

RDRR 

VECE RSTR D D D D 

VECB WXMR D D D D DO DO DO D3 

RDRR 

VECE RSTR D D D D 

VECB WXMR 0 0 0 0 A0 BO CO D8 

RDRR 

RSTR 0 0 0 0 

VECE RSTR 0 0 0 0 

WMSK M1 M1 M1 Ml 

VECB WXMR 0 0 0 0 A1 B1 C1 D9 

RDRR 

VECE RSTR 0 0 0 0 

WMSK M2 M2 M2 M2 

VECB WXMR 0 0 0 0 A1 B1 C1 D9 

RDRR 

VECE RSTR 0 0 0 0 

WMSK M4 M4 M4 M4 

VECB WXMR 0 0 0 0 A1 B1 C1 D9 

RDRR 

VECE RSTR 0 0 0 0 

WMSK M8 M8 M8 M8 

VECB WXMR 0 0 0 0 A1 B1 C1 D9 

RDRR 

VECE RSTR 0 0 0 0 

-80- 
Mask Transform Quad Test Program 

RSTR A A A A 

RSTR B B B B 

RSTR C C C C I- RSTI'R D D D D I WMSK M31 M31 M31 M31 

VECB WXMR A B B A A0 BO DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO CO D8 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C A1 DO C1 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B A0 B1 DO DO 

RDRR 

VECE RSTR A B A B 

VECB WXMR B B D D DO B1 DO D9 

RDRR 

VECE RSTR B B D D 

VECB WXMR C D C D DO DO C1 D9 

RDRR 

VECE RSTR C D C D 

WMSK M15 Ml5 M15 M15 

VECB WXMR A B B A B1 C1 DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO D9 A1 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C BO DO D8 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B B1 CO DO DO 

RDRR 

VECE RSTR A B A B 

VECB WXMR B B D D DO CO DO D8 

RDRR 

VECE RSTR B B D D 

VECB WXMR C D C D DO DO D8 A1 

RDRR 

VECE RSTR C D C D 

I 

-81- 
Mask Transform XAXB Test Program 

RSTR A A A A 

RSTR B B B B 

RSTR C C C c 

RSTR D D D D 

WMSK M30 M30 M30 M30 

VECB WXMR A B B A D2 82 DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO C2 DS 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C D3 DO C3 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B D2 B3 DO DO 

RDRR 

VkE RSTR A B A B 

VECB WXMR B B D D DO B3 DO D6 

RDRR 

VECE RSTR B B D D 

VECB WXMR C D C D DO DO C3 D6 

RDRR 

VECE RSTR C D C D 

WMSK M14 M14 M14 M14 

VECB WXMR A B B A B3 C2 DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO D6 D2 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C B2 DO D5 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B B3 C2 DO DO 

RDRR 

VECE RSTR A B A B 

VECB WXMR B B D D DO-C2 DO D5 

RDRR 

ECE RSTR B B D D 

VECB WXMR C D C D DO DO D5 D3 

RDRR 

VECE RSTR C D C D 

WMSK M29 M29 M29 M29 

VECB WXMR A B B A C2 D5 DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO D2 B2 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C C3 DO D6 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B C2 B3 DO DO 

VECB WXMR B B D D DO 433 DO C3 

RDRR 

ECE RSTR B B D D 

VECB WXMR C D C D DO DO D5 C2 

RDRR 

VECE RSTR C D C D 

WMSK M13 M13 M13 M13 

VECB WXMR A B B A DO'D1 DO DO 

RDRR 

SCE RSTR A B B A 

VECB WXMR D C C D DO DO A0 B2 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C C2 DO B1 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B A1 C3 DO DO 

RDRR 

VECE RSTR A B A B 

VECB WXMR B B D D DO D5 DO B1 

RDRR 

VECE RSTR B B D D 

VECB WXMR C D C D DO DO C3 B3 

RDRR 

VECE RSTR C D C D 

RDRR 

VECE RSTR A B A B 

-82- 
Mask Transform XCXD Test Program 

. 

RSTR A A A A 

RSTR B B B B 

RSTR C C C C 

RSTR D D D D 

WMSK M27 M27 M27 M27 

VECB WXMR A B B A D2 B2 DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO C2 DS 

RDRR 

WE RSTR D C C D 

VECB WXMR A A C C D3 DO C3 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B D2 B3 DO DO 

RDRR 

VECE RSTR A B A B 

VECB WXMR B B D D DO B3 DO D6 

RDRR 

VECE RSTR B B D D 

VECB WXMR C D C D DO DO C3 D6 

RDRR 

VECE RSTR C D C D 

WMSK M11 M11 M11 Ml1 

VECB WXMR A B B A B3 C2 DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO D6 D2 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C B2 DO D5 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B B3 C2 DO DO 

RDRR 

VECE RSTR A B A B 

VECB WXMR B B D D DO C2 DO D5 

RDRR 

VECE RSTR B B D D 

VECB WXMR C D C D DO DO DS D3 

RDRR 

VECE RSTR C D C D - 

WMSK M23 M23 M23 M23 

VECB WXMR A B B A C2 D5 DO DO 

RDRR 

VECE RSTR A B B A 

VECB WXMR D C C D DO DO D2 B2 

RDRR ~. 

VECE RSTR D C C D 

VECB WXMR A A C C C3 DO D6 DO 

RDRR 

VECE RSTR A A C C 

VECB WXMR A B A B C2 B3 DO DO 

IIDRR 

VECE RSTR A B A B 

VECB WXMR B B D D DO D3 DO C3 

RDRR 

VECE RSTR B B D D 

VECB WXMR C D C D DO DO D5 C2 

RDRR 

VECE RSTR C D C D 

WK M7 M7 M7 M7 

VECB WXMR A B B A DO Dl DO DO 

RDRR 

ECE RSTR A B B A 

VECB - -~ WXMR D C C D DO DO A0 B2 

RDRR 

VECE RSTR D C C D 

VECB WXMR A A C C C2 DO B1 DO 

RDRR 

=E RSTR A A C C 

VECB WXMR A B A B A1 C3 DO DO 

RDRR 

ECE RSTR A B A B 

VECB WXMR B B D D DO DS DO B1 

RDRR 

VECE RSTR B B D D 

VECB . -_~ WXMR C D C D DO DO C3 B3 

RDRR 

VECE RSTR C D C D 

-83- 
Voter Test Quad1 Program 

WMSK M15 M15 M15 M15 

RSTR 0 0 0 0 

LOOP 0 11 0 3 10 3 10 3 1 

VECB WXMR 0 0 0 0 T4 T4 T4 T4 

RDRR 

VECE RSTR 0 0 0 0 

END 

Voter Test Quad2 Program 

WMSK 

RSTR 

LOOP 

VECB 

RDRR 

VECE 

END 

M15 M15 M15 M15 

0000 

231031031031 

WXMR 0 0 0 0 T5 TS T5 T5 

RSTR 0 0 0 0 

-84- 
Voter Test BO1 3XA Program 

- RSTR 0 0 0 0 

- VECB WXMR 0 0 0 0 DO T4 T4 T4 

WMSK M14 M14 M14 Ml4 

LOOP 0 0 0 0 11 0 3 10 3 1 

RDRR 

VECE RSTR 0 0 0 0 

END 

VECB WXMR 0 0 0 0 DO T5 T5 T5 

RDRR 

VECE RSTR 0 0 0 0 

END 

mP000231031031 

Voter Test BO1 3XB Program 

RSTR 0 0 0 0 

WMSK M13 M13 M13 M13 

VECB WXMR 0 0 0 0 T4 DO T4 T4 

RDRR 

VECE RSTR 0 0 0 0 

mP011000031031 

END 

LooP231000031031 

VECB WXMR-0-0 0 0 T5 DO T5 T5 

RDRR 

VECE RSTR 0 0 0 0 

END 

. 

-85- 
Voter Test BO1 3XC Program 

RSTR 0 0 0 0 

WMSK M11 Ml1 Mll M11 

LOOP 0 11 0 3 10 0 0 0 3 1 

VECB WXMR 0 0 0 0 T4 T4 DO T4 

RDRR 

VECE RSTR 0 0 0 0 

END 

L00P231031000031 

VECB WXMR 0 0 0 0 T5 T5 DO T5 

RDRR 

VECE RSTR 0 0 0 0 

END 

Voter Test BO1 3XD Program 

RSTR 0 0 0 0 

WMSK M7 M7 M7 M7 

LooP0110310 31000 

VECB WXMR 0 0 0 0 T4 T4 T4 DO 

RDRR 

VECE RSTR 0 0 0 0 

END 

VECB WXMR 0 0 0 0 T5 T5 T5 DO 

RDRR 

VECE RSTR 0 0 0 0 

LooP231031031000 

END 

-86- 
APPENDIX B 

Diagnostic Emulation 

Outputs for Non-faulted C/I 

-87- 
Presence Test 

PRESENCE GOOD CIRCUIT 

0 0 0 

0 0 0 

0 0 0 

0 0 0 

0 0 0 

0 0 0 

0 0 0 

0 0 0 

12 

100 

244 

388 

532 

676 

802 

910 

1414 

15744 15744 

1540 

0 0 

1666 

0 0 

2170 

162033 162033 

2296 

0 0 

2422 

0 0 

2926 

143071 143071 

3052 

0 0 

3178 

0 0 

3682 

34706 34706 

3808 

0 0 

3934 

0 0 

15744 15744 

0 0 

0 0 

162033 162033 

0 0 

0 0 

143071 143073 

0 0 

0 0 

34706 34706 

0 0 

0 0 

4438 

130516 130516 130516 130516 

4564 

4690 

0 0 0 0 

0 0 0 0 

5194 

47271 47271 47271 47271 

5320 

5116 

0 0 0 0 

0 0 0 0 

5950 

125125 125125 125125 125125 

0 0 0 0 

52652 52652 52652 52652 

0 0 0 0 

0 0 0 0 

15744 15744 15744 15744 

0 0 0 0 

0 0 0 0 

162033 162033 162033 162033 

0 0 0 0 

6706 

6832 

6958 

7462 

7588 

7714 

8218 

8344 

6076 

6202 

0 0 0 0 

-88- 
CSTUPD GOOD CIRCUIT 

12 

0 0 

82 

0 0 

208 

0 0 

334 

0 0 

838 

0 0 

1360 

1 1 

1486 

0 0 

1990 ~ 

0 0 

2512 

1 1 

2638 

0 0 

0 0 

0 0 

0 0 

0 0 

1 1 

0 0 

0 0 

1 1 

Current Status Update Test 

0 0 0 0 

0 0 0 0 

3142 

3664 

2 2 2 2 

3790 

4294 

4816 

0 0 0 0 

0 0 0 0 

2 2 

4942 

2 2 

0 0 0 0 

5446 

0 0 

4 4 

6094 

0 0 

6598 

0 0 

7120 

4 4 

7246 

0 0 

7750 

0 0 

8272 

10 10 

8398 

0 0 

8902 

0 0 

9424 

10 10 

9550 

0 0 

10054 

0 0 

10576 

37 37 

10702 

0 0 

11206 

0 0 

596a 

11728 

37 37 

0 

4 

0 

0 

4 

0 

0 

10 

0 

0 

10 

0 

0 

37 

0 

0 

37 

0 

4 

0 

0 

4 

0 

0 

10 

0 

0 

10 

0 

0 

37 

0 

0 

37 

-89- 
13m I c 

0 

0 

0 

0 

0 

0 

0 

0 

0 

OD CIRCUIT 

12 

100 

0 0 

0 0 

244 

388 

0 

0 

0 

0 

532 

676 

802 

910 

1018 

0 0 

0 0 

0 0 

0 0 

0 0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

1126 

1234 

125125 125125 125125 125125 1 0 0 0 0 

1342 

1450 

52652 52652 52652 52652 

0 0 0 0 

1558 

0 0 0 0 - 2062 

2188 

125125 125125 125125 125125 

0 0 0 0 

2314 

0 0 0 0 

2818 

2944 

52652 52652 52652 52652 

0 0 0 0 

I 3070 

0 0 0 0 

3574 

3700 

125125 125125 125125 125125 

0 0 0 0 

3826 

0 0 0 0 

I 4330 

4456 

52652 52652 52652 52652 

0 0 0 0 

4582 

0 0 0 0 

I 5086 

125125 125125 125125 125125 

5212 

0 0 0 0 

5338 

0 0 0 0 

52652 52652 52652 52652 

0 0 0 0 

0 0 0 0 

125125 125125 125125 125125 

5842 

5968 

6094 

6598 

6724 

0 0 

6850 

0 0 

7354 

52652 52652 

7480 

0 0 

7606 

0 0 

8110 

15744 143071 

8236 

16 15 

8380 

0 0 

8506 

0 0 

8614 

0 0 

9118 

162033 162033 

9244 

16 16 

9370 

0 0 

9478 

0 0 

9982. 

34706 34706 

10108 

15 15 

10234 

0 0 

10342 

0 0 

10846 

47271 47271 

10972 

13 13 

11098 

0 0 

11206 

0 0 

11710 

111554 111554 

11836 

0 0 

0 0 

52652 52652 

0 0 

0 0 

130516 66223 

13 7 

0 0 

0 0 

0 0 

162033 162033 

16 16 

0 0 

0 0 

34706 34706 

15 15 

0 0 

0 0 

47271 47271 

13 13 

0 0 

0 0 

111554 111554 

7 7 7 7 

-90- 
I 

Mask Transform Quad Test 

! 

MSKnWQ GOOD CIRCUIT 

12 

100 

244 

380 

532 

658 

766 

1270 

1396 

1522 

2026 

0 0 0 0 

0 0 0 0 

0 0 0 0 

0 0 0 0 

0 0 0 0 

0 0 0 0 

0 0 0 0 

143071 15744 15744 143071 

11 6 6 11 

0 0 0 0 

130516 66223 66223 130516 

2152 

11 6 6 11 

2278 

2782 

2908 

3034 

3538 

0 0 0 0 

47271 47271 162033 162033 

3 3 14 14 

0 0 0 0 

34706 15744 34706 15744 

3664 

5 12 

0 

111554 

3 

0 

111551 

5 

0 

0 

77777 

37 

3790 

0 

4294 

111554 

4420 

3 

4546 

0 

5050 

47271 

5176 

12 

530 2 

0 

5410 

0 

5914 

77777 

6040 

37 

6166 

5 12 

0 

34706 

14 

0 

111554 

5 

0 

0 

77777 

37 

0 

34706 

14 

0 

47271 

12 

0 

0 

77777 

37 

0 0 0 0 

173577 173577 173577 173577 

6670 

6796 

37 37 37 37 

6922 

0 0 0 0 

7426 

167273 167273 167273 167273 

7552 

37 37 

7678 

0 0 

8182 

134716 134716 

8308 

37 37 

8434 

0 0 

8938 

176737 176737 

9064 

37 37 

9190 

0 0 

9694 

166233 166233 

9820 

37 37 

37 37 

0 0 

134716 134716 

37 37 

0 0 

176737 176737 

37 37 

0 0 

166233 166233 

37 37 

-9 1- 
MSK”B 

12 

0 0 

3 00 

0 0 

244 

0 0 

388 

0 0 

532 

0 0 

658 

0 0 

766 

0 0 

1270 

Mask Transform XAXB Test 

GOOD CIRCUIT 

0 0 

0 0 

0 0 

0 0 

0 0 

0 0 

0 0 

146063 146063 14.6063 146063 

1396 

11 11 11 11 

1522 

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-124 
Report Documentation Page 

;Key Words lsuggested by Author(r)l 

Loqic Simulation 

Fault Effects 

NASA CR- 178390 

18 Distribution Statement 

Unclassified-Unlimited 

A Fdul t Injection Experiment Usina the AIRLAB 

Diagnostic Emulation Facility 

9. Security Classif (of this report) I20. Security Clamt. (of this pagel Z?. No. of pagsr 

Unclassified Uncl ass i f ied 129 

7. Authorlsl 

22. Price 

A07 

Robert Baker, Scott Mangum, and Charlotte Scheper 

.- ___- 9. Performing Organization Name and Address 

Center for Digital Zysterns Research 

Research Triangle Institute 

Research Triangle Park, NC 27709 

National Aeronautics and Space Administration 

Langley Research Center 

Hampton, VA 23665-5225 

Technical Monitor: Charles W. fleissner, Jr. 

Lan9ley Research Center 

-. 

12 Sponsoring Agency Name and Address 

KSupplernentarv Notes 

3. Aeciplenr's Catalog No. 

- 5. Report Date 

March 1988 

6. Performing Organization Code 

8. Performing Organization Report No. 

10. Work Unit No. 

505-66-21-01 

11. Contract or Grant No. 

NAS1-17964, Task 5 

13. Type of Report and Period Covered 

Contractor Report 

74. Sponsoring Agency Coda 

Sel f-Test Design 

Fault Coveracle I Subject Category 62