# Patent

## Title
Ramp signal generating circuit and signal generator, array substrate and display apparatus

## Abstract

A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first shift register (11), a second shift register (12), a voltage decreasing unit (13) and a sampling unit (14); the voltage decreasing unit (13) is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register (11) is connected to the voltage decreasing unit (13) and is configured to control the voltage decreasing unit (13) to output voltages which are decreased continuously stage by stage; the sampling unit (14) has an output terminal and is connected to the voltage decreasing unit (13); the second shift register (12) is connected to the sampling unit (14) and is configured to control the sampling unit (14) to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit (13). Such ramp signal generating circuit is capable of reducing area of the ramp signal generating circuit and improving linearity of ramp signal.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application is the National Stage of PCT/CN2014/076402 filed on Apr. 28, 2014, which claims priority under 35 U.S.C. §119 of Chinese Application No. 201310701636.4 filed on Dec. 19, 2013, the disclosure of which is incorporated by reference.
TECHNICAL FIELD OF THE DISCLOSURE
The present disclosure relates to a ramp signal generating circuit and signal generator, an array substrate and a display apparatus.
BACKGROUND
With development of electronic technology, not only rigorous demands are proposed on the appearance and the quality of electronic products, but also higher attention has been paid to price and practicability of the electronic products.
In order to meet public requirements, SOG (System on Glass) technology has been widely applied in the existing electronic products. SOG refers to integrating driving circuit and system circuit on an array substrate, and appearance of such technology has provided great convenience to manufacture and design of electronic product. The manufacture cost of the electronic products is greatly reduced since developers only need to perform simulation on the system circuit based on TFT and then can implement the circuit through a certain process. In addition, the products can also be greatly miniaturized by adopting highly integrated circuit design.
Especially for a display panel, SOG can effectively integrate a driving system comprising a gate driver, a data driver, a multiplexer (Mux), a DC-DC converter (DC-DC), a digital to analog converter (DAC), a timing sequence controller (TCON) and so on, such that cost can be reduced greatly, screen bezel can be minimized, and problems of voltage drop on resistor, noise, reliability and so on caused by mutual connection among different driving chips can be solved. In order to implement more system functions, the development of the SOG technology is in direction of much higher integration and much more miniaturization, and the development of the display has the tendency of low cost, energy saving, low weight and thin thickness. The SOG technology has became the inevitable trend of the development of the system circuit.
In the existing display panels, various models requiring to be driven by a ramp signal and comprising DA converter, AD converter and so on are comprised in array substrates. However, a ramp signal generator cannot be effectively integrated by adopting the current SOG technology, and a ramp signal generator additionally arranged will cause area of the driving circuits to be increased greatly, which has a restriction on the further miniaturization of the display apparatus. On the other hand, it is difficult for the existing ramp signal generator to generate a ramp signal output having good linearity, which may dramatically limit the quality of the display apparatus.
SUMMARY
In embodiments of the present disclosure, there are provided a ramp signal generating circuit and signal generator, an array substrate and a display apparatus capable of reducing area of the ramp signal generating circuit and improving linearity of ramp signal.
According to an aspect of the embodiments of the present disclosure, there is provided a ramp signal generating circuit comprising a first shift register, a second shift register, a voltage decreasing unit and a sampling unit; wherein the voltage decreasing unit is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register is connected to the voltage decreasing unit and is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage; the sampling unit has an output terminal and is connected to the voltage decreasing unit; the second shift register is connected to the sampling unit and is configured to control the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit.
According to another aspect of the embodiments of the present disclosure, there is further provided a ramp signal generator comprising the above described ramp signal generating circuit.
In addition, according to another aspect of the embodiments of the present disclosure, there is provided an array substrate comprising a first shift register and a second shift register, wherein the first shift register is configured to generate a gate line scan signal and the second shift register is configured to generate a data line scan signal. The array substrate further comprises: a voltage decreasing unit and a sampling unit, wherein the voltage decreasing unit is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage. The first shift register is connected to the voltage decreasing unit and is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage. The sampling unit has an output terminal and is connected to the voltage decreasing unit. The second shift register is connected to the sampling unit, and is configured to control the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit.
According to another aspect of the embodiments of the present disclosure, there is provided a display apparatus comprising the above described array substrate.
The ramp signal generating circuit, the ramp signal generator, the array substrate and the display apparatus provided in the embodiments of the present disclosure adopt a designed structure comprising two shift register units, a voltage decreasing unit and a sampling unit, adopt different designed signal timing sequences to allow that the two shift register units drive the voltage decreasing unit and the sampling unit respectively, such that the first shift register unit controls the voltage decreasing unit to output voltages which are decreased continuously stage by stage and generated by continuously decreasing a voltage inputted from the first power supply input terminal or a voltage inputted from the second power supply input terminal stage by stage, and meanwhile the second shift register unit controls the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit. Such structured ramp signal generating circuit comprises less component units and has a high integration level in circuit configuration, thus capable of reducing area occupied by the ramp signal generating circuit. In addition, compared to the prior art, such structured ramp signal generating circuit can have a higher sampling frequency and can obtain more voltage stages and a smaller voltage step, thus capable of improving effectively linearity of a ramp signal.



BRIEF DESCRIPTION OF THE DRAWINGS
In order to more clearly describe the technical solutions of the embodiments of the present disclosure or the prior art, drawings necessary for describing the embodiments of the present disclosure or the prior art are simply introduced as follows. It should be obvious for those skilled in the art that the drawings described below are only some embodiments of the present disclosure. Other drawings can be obtained by those skilled in the art based on these drawings without paying creative labor.
FIG. 1 is a schematic structure diagram of a ramp signal generating circuit provided in embodiments of the present disclosure;
FIG. 2 is a schematic structure diagram of circuit connection of a ramp signal generating circuit provided in the embodiments of the present disclosure;
FIG. 3 is a schematic timing sequence diagram of signals when transistors in the ramp signal generating circuit shown in FIG. 2 are N type transistors;
FIG. 4 is a simulated waveform diagram of an output signal of the ramp signal generating circuit shown in FIG. 2;
FIG. 5 is a schematic structure diagram of circuit connection of another ramp signal generating circuit provided in the embodiments of the present disclosure;
FIG. 6 is a simulated waveform diagram of an output signal of the ramp signal generating circuit shown in FIG. 5;
FIG. 7 is a schematic structure diagram of circuit connection of another ramp signal generating circuit provided in the embodiments of the present disclosure;
FIG. 8 is a schematic structure diagram of circuit connection of another ramp signal generating circuit provided in the embodiments of the present disclosure; and
FIG. 9 is a schematic timing sequence diagram of signals when transistors in the ramp signal generating circuit shown in FIG. 7 are P type transistors.



DETAILED DESCRIPTION
Technical solutions in embodiments of the present disclosure will be described below clearly and completely in combination with the accompanying drawings in the embodiments of the present disclosure. Obviously, the embodiments as described are only some of the embodiments of the present disclosure, and are not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments in the present disclosure without paying any inventive labor should fall into the protection scope of the present disclosure.
As shown in FIG. 1, a pixel circuit provided in the embodiments of the present disclosure comprises: a first shift register 11, a second shift register 12, a voltage decreasing unit 13 and a sampling unit 14.
The voltage decreasing unit 13 is connected to a first power supply input terminal Vref1, a second power supply input terminal Vref2 and a ground terminal, and is configured to continuously decrease a voltage inputted from the first power supply input terminal Vref1 and a voltage inputted from the second power supply input terminal Vref2 stage by stage.
The first shift register 11 is connected to the voltage decreasing unit 13, and is configured to control the voltage decreasing unit 13 to output voltages which are decreased continuously stage by stage. Particularly, the voltages outputted by the voltage decreasing unit 13 may be the voltages generated by continuously decreasing the voltage inputted from the first power supply input terminal Vref1 or the voltage inputted from the second power supply input terminal Vref2 stage by stage.
The sampling unit 14 has an output terminal Vo, and is connected to the voltage decreasing unit 13.
The second shift register 12 is connected to the sampling unit 14, and is configured to control the sampling unit 14 to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit 13.
The ramp signal generating circuit provided in the embodiments of the present disclosure adopts a designed structure comprising two shift register units, a voltage decreasing unit and a sampling unit, adopts different designed signal timing sequences to allow that the two shift register units drive the voltage decreasing unit and the sampling unit respectively, such that the first shift register unit controls the voltage decreasing unit to output voltages which are decreased continuously stage by stage and generated by continuously decreasing a voltage inputted from the first power supply input terminal or a voltage inputted from the second power supply input terminal stage by stage, and meanwhile the second shift register unit controls the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit. Such structured ramp signal generating circuit comprises less component units and has a high integration level in circuit configuration, thus capable of reducing area occupied by the ramp signal generating circuit. In addition, compared to the prior art, such structured ramp signal generating circuit can have a higher sampling frequency and can obtain more voltage stages and a smaller voltage step, thus capable of improving effectively linearity of a ramp signal.
The voltage decreasing unit 13 can adopt various known circuit configuration or electric devices capable of decreasing an input voltage stage by stage, and the embodiments of the present disclosure will not limit the structure of the voltage decreasing unit 13.
Particularly, as shown in FIG. 2, the voltage decreasing unit 13 comprises: a plurality of first transistors arranged in a matrix and a plurality of voltage decreasing resistors. As shown in FIG. 2, the first transistors in a first row are represented as M1, M2, . . . , Mn, respectively, and the first transistors are represented uniformly as M to simplify the description hereinafter; the voltage decreasing resistors in a first row are represented as R1, R2, . . . , Rn, respectively, and the voltage decreasing resistors are represented uniformly as R to simplify the description hereinafter.
Gates of the first transistors M located in a same row are connected to an output terminal of the first shift register 11.
First electrodes of the first transistors M located in a same column are connected to an input terminal of the sampling unit 14.
Second electrodes of the first transistors M located in a same row are connected in series, and a voltage decreasing resistor R is connected between the second electrodes of every two adjacent first transistors M.
Except the first transistors located in last two rows, the second electrode of the first transistor located at a last column of each row is connected to the second electrode of the first transistor located at a first column of a row which is two-rows next to the row through a resistor row.
Furthermore, in the ramp signal generating circuit as shown in FIG. 2, the input terminals of the first shift register 11 are connected to a first clock signal CLK1, a second clock signal CLKB1 and a first frame start signal STV1, and is configured to turn on the first transistors M row by row.
The input terminals of the second shift register 12 are connected to a third clock signal CLK2, a fourth clock signal CLKB2 and a second frame start signal STV2, and is configured to, during an ON period of the first transistors M located in a same row, control the sampling unit 14 to sample column by column the voltage at the first electrode of each first transistor M among the first transistors M located in the same row.
In the embodiments of the present disclosure, the shift register unit may particularly be a GOA (Gate Driver on Array) circuit which is constituted by cascaded shift registers. The GOA circuit receives an initially inputted frame start signal STV, and TFTs (Thin Film Transistor) inside the GOA circuit are commonly controlled to be turned on or off according to two clock signals (CLK, CLKB), such that the inputted signal is delivered stage by stage. As an example, the CLKB signal controls signal output of each stage.
Furthermore, as shown in FIG. 2, the sampling unit 14 particularly comprises: a plurality of second transistors. As shown in FIG. 2, the plurality of second transistors are represented as T1, T2, . . . , Tn in a direction from left to right, and the second transistors are uniformly represented as T to simplify the description hereinafter.
Gates of the second transistors T are connected to different output terminals of the second shift register 12, respectively, and first electrodes of the second transistors T are all connected to the output terminal Vo of the sampling unit 14.
A second electrode of each of the second transistors T is connected to the first electrodes of the first transistors M located in a same column.
It should be noted that both the first transistors M and the second transistors T can be N type transistors in the embodiments of the present disclosure. In case that the first transistors M and the second transistors T are N type transistors, the first electrodes of the transistors may be sources and the second electrodes of the transistors may be drains.
The transistors adopted in the embodiments of the present disclosure can be Thin Film Transistors, Field Effect Transistors or other devices possessing same characteristics. Since the source and the drain of each of the transistors adopted herein are symmetric, there is no distinction between the source and the drain. In the embodiments of the present disclosure, in order to distinguish the two electrodes other than the gate of a transistor, one of the two electrodes is referred to as the source and the other is referred to as the drain. In addition, depending on the characteristics of a transistor, the transistor can be divided into N type transistor or P type transistor. The following embodiments are described by taking N type transistors as an example, and other embodiments implemented by P type transistors can be easily conceived by those skilled in the art without paying creative labor, and thus should be enclosed in the protection scope defined by the embodiments of the present disclosure.
As can be seen from the ramp signal generating circuit as shown in FIG. 2, the voltage decreasing unit 13 can be constituted by 2n row-circuits which can be divided into two independent resistor strings. Here, a forward scanning direction refers to a direction from left to right, in each row-circuit through which a current flows in the forward scanning direction, a drain of a TFT transistor M is connected between every two adjacent resistors. In other words, the voltage decreasing unit 13 comprises 2n rows in which n rows are resistor rows and the other n rows are transistor rows. In each of the resistor rows, only resistors are arranged, while in each of the transistor rows, resistors and first transistors are arranged alternately. Each of the transistor rows comprises n first transistors M and n voltage decreasing resistors R which are arranged alternately, and each of the resistor rows comprises n voltage decreasing resistors R. For example, each of odd-numbered rows among the 2n rows comprises n first transistors M and n voltage decreasing resistors R, and each of even-numbered rows among the 2n rows comprises n voltage decreasing resistors R, such that the respective row-circuits each of which comprises TFT transistors M are arranged with a row inserted between two adjacent row-circuits and there is a resistor row between two transistor rows each of which comprises TFT transistors M. For example, as shown in FIG. 2, except a first row and a last row, two resistor rows and two transistor rows are arranged alternately. Here, in each transistor row, the gates of the TFT transistors M are connected to the output signal of an external GOA1 circuit, a drain of a TFT transistor M is connected between every two adjacent resistors, sources of the TFT transistors M located in a same column are connected together to the drain of the TFT transistor T located in the same column, the gates of the TFT transistors T are connected to the output signals of a GOA2 circuit, and sources of the TFT transistors T are connected to the output terminal Vo.
In order to keep the description in the present disclosure consistent, in the following description, the transistor rows are described as a first row, . . . a nth row, and the resistor rows are not sorted. Particularly, as shown in FIG. 2, in the voltage decreasing unit 13, the second electrode of the first transistor M located at a first row and a first column is connected to the first power supply input terminal Vref1 through a voltage decreasing resistor R, the second electrode of the first transistor M located at the first row and a last column is connected to the second electrode of the first transistor M located at a third row and the first column through a row of voltage decreasing resistors R; the second electrode of the first transistor M located at a second row and the first column is connected to the second power supply input terminal Vref2 through a row of voltage decreasing resistors R, the second electrode of the first transistor M located at the second row and the last column is connected to the second electrode of the first transistor M located at a fourth row and the first column through a row of voltage decreasing resistors R; and the second electrode of the first transistor M located at a ith row and the last column is connected to the second electrode of the first transistor M located at a (i+2)th row and the first column through a row of voltage decreasing resistors R, and the second electrode of the first transistor M located at a (i+1)th row and the last column is connected to the second electrode of the first transistor M located at a (i+3)th row and the first column through a row of voltage decreasing resistors R, wherein i is an odd number. As shown in FIG. 2, in each transistor row, a current flows in a direction from left to right.
The plurality of voltage decreasing resistors R as shown in FIG. 2 are all same, the plurality of first transistors M are all same, and the voltage inputted from the first power supply input terminal Vref1 and the voltage inputted from the second power supply input terminal Vref2 are same.
Such structured ramp signal generating circuit can be used to generate a ramp signal. The timing sequence for the driving signals can be as shown in FIG. 3, and the particular process for generating a ramp signal can comprise two steps of delivering signal and sampling signal.
During the step of delivering signal, a DC input signal is input from one end of the resistors R1 located in the first row through the first power supply input terminal Vref1. As shown in FIG. 3, the GOA1 circuit is controlled by the clock signals CLK1 and CLKB1, wherein the CLK1 and the CLKB1 have opposite phases. A first output terminal of the GOA1 circuit firstly outputs a signal VoR1 to turn on the TFT transistors M1 ̃Mn located in the first row in the voltage decreasing circuit 13. The clock cycle of the GOA1 circuit is n times of that of the GOA2 circuit, such that the GOA2 circuit controlled by CLK2 and CLKB2 can turn on the TFT transistors T1 ̃Tn in the sampling unit 14 sequentially when the TFT transistors M located in the first row are turned on by the GOA1 circuit, wherein CLK2 and CLKB2 have opposite phases. Since the respective resistors are all same and the respective TFT transistors are all same, the voltage signal will be decreased sequentially and evenly. In the following description, the n resistor rows will be sorted separately or will not be sorted, and the n resistor rows and the n transistor rows are not sorted together. When Vref1 outputs the VoR1 signal to the first TFT transistor row, Vref2 outputs a signal to a first resistor row synchronously. When the signal of Vref1 is delivered to a second resistor row by the first TFT transistor row, the GOA1 circuit outputs a VoR2 signal to a second TFT transistor row to turn on the TFT transistors in this row, and meanwhile the GOA2 circuit turn on the transistors T1 ̃Tn sequentially. In this manner, signal is delivered to the nth row, row by row, until the tail end of the resistor Rn located in the nth row is connected to the ground terminal.
It should be noted that: in the embodiments of the present disclosure, the clock cycle of the GOA circuit particularly refers to the time length during which a high level or a low level is outputted continuously. The expression of “the clock cycle of the GOA1 circuit is n times of that of the GOA2 circuit” can be understood that the time length during which the GOA1 circuit outputs a high level continuously is n times of the time length during which the GOA2 circuit outputs a high level continuously. That is, during the time length during which the GOA1 circuit continuously outputs a high level to one row (or one column), the GOA2 circuit outputs a high level for the n columns (or n rows) sequentially.
During the step of sampling signal, when the resistors R1 ̃Rn and the TFT transistors M1 ̃Mn located in the first transistor row operate, the TFT transistors T1 ̃Tn are turned on by the GOA2 circuit sequentially (for example, from left to right in FIG. 2). The drain of each of the TFT transistors T is connected to the source of the TFT transistor M located in a column corresponding to the TFT transistor T, the source of the TFT transistor T is connected to the output signal Vo, such that Vo samples and shows, in chronological order, ramp voltage signals which are generated by the resistors R and the TFT transistors M located in the first transistor row and decrease linearly. When the signal of Vref1 delivers a voltage signal to the second resistor row, the GOA1 circuit outputs the VoR2 signal to the second TFT transistor row to turn on the TFT transistors in this row, at this time, Vo continuously samples ramp voltage signals which are generated by the resistors R and the TFT transistors M located in the second transistor row and decrease linearly. A decreasing ramp signal is successfully sampled until the sampled ramp voltage signal generated by the nth row is decreased to 0. In such manner, ramp signals can be sampled recurrently.
Signal simulation of the output signal Vo of such ramp signal generating circuit can be as shown in FIG. 4. As can be seen from FIG. 4, the GOA1 circuit outputs the high level from the first output terminal to the nth output terminal sequentially during a complete frame scanning period, as shown by VoR1 (the first output terminal), VoR2 (the second output terminal) and VoRn (the nth output terminal) in FIG. 4, such that a complete decreasing ramp signal is successfully sampled. During the time period of the high level of VoR1, one scanning is achieved by the output signals VoC1 ̃VoCn of the GOA2 circuit; when the high level of VoR2 comes, a second scanning is achieved by the output signal VoC1 ̃VoCn; and so on until the frame scanning period ends. As shown in the signal simulation diagram, the ramp signal generating circuit provided in the embodiments of the present disclosure can generate a decreasing ramp waveform having good linearity.
It should be explained that: the row number and the column number of the matrix of the transistors M in the embodiments of the present disclosure can be selected according to actual requirements. It should be easily conceived that when the row number and the column number of the transistors M are increased, the linearity of the ramp signal can be further improved by increasing the number of the scan output terminals of the GOA circuit and increasing the frequency of sampling on the voltage signals.
In the above embodiments, the description is given by taking the following case as an example: the first power supply input terminal Vref1 is connected to the second electrode of the first transistor M1 located at the first transistor row and the first column; the second power supply input terminal Vref2 is connected to the second electrode of the first transistor M1 located at the second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor Mn located at the last second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor Mn located at the last transistor row and the last column is connected to the ground terminal.
Alternatively, the first power supply input terminal Vref1 can be connected to the second electrode of the first transistor Mn located at the last transistor row and the last column; the second power supply input terminal Vref2 can be connected to the second electrode of the first transistor Mn located at the last second transistor row and the last column through a resistor row connected in series; the second electrode of the first transistor M1 located at the second transistor row and the first column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor M1 located at the first transistor row and the first column is connected to the ground terminal.
Alternatively, the first power supply input terminal Vref1 can be connected to the second electrode of the first transistor M1 located at the last transistor row and the first column; the second power supply input terminal Vref2 can be connected to the second electrode of the first transistor M1 located at the last second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor Mn located at the second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor Mn located at the first transistor row and the last column is connected to the ground terminal.
Particularly, as shown in FIG. 5, the first transistor M1 located at the first transistor row and the first column is connected to the ground terminal through the resistor R1, and the resistor R located at the first resistor row and the last column is connected to the ground terminal; the first transistor located at the nth transistor row and the last column and the resistor Rn are connected to the DC input signal Vref2, and the resistor located at the nth resistor row and the first column is connected to the DC input signal Vref1, such structured ramp signal generating circuit can generate an increasing ramp signal waveform. Such structured ramp signal generating circuit also can adopt the signals as shown in FIG. 3 as driving signals, the operation process thereof can also be divided into two sub-processes of delivering signal and sampling signal, and the operation principle thereof is similar to that of the decreasing ramp signal generating circuit as shown in FIG. 2 only with the difference that the voltage is increasing.
Signal simulation of the output signal Vo of such ramp signal generating circuit can be as shown in FIG. 6. From the simulation result, the GOA1 circuit outputs the high level from the first output terminal to the nth output terminal sequentially during a complete frame scanning period, as shown by VoR1 (the first output terminal), VoR2 (the second output terminal) and VoRn (the nth output terminal) in FIG. 6, such that a complete increasing ramp signal is successfully sampled. As shown in the signal simulation diagram, the ramp signal generating circuit provided in the embodiments of the present disclosure can generate an increasing ramp waveform having a good linearity.
It should be explained that, in the embodiments of the present disclosure, the sum of the resistance values of all of the voltage decreasing resistors R located in each single transistor row is same and is equal to the total resistance value of each single resistor row. Here, the signal inputted from the first power supply input terminal Vref1 and the signal inputted from the second power supply input terminal Vref2 are same. In this manner, it can be ensured that the potential at the tail end of a resistor row generated after a signal flows through the resistor row is equal to the potential at the tail end of a transistor row comprising TFT transistors generated after another signal flows through the transistor row. Furthermore, after the signal flows through the resistor row, it is then inputted to a first column of a next transistor row comprising TFT transistors, such that it can be ensured that successive variation of voltage signals can be achieved while keeping unidirectional scanning of the second shift register.
For example, in the circuit as shown in FIG. 2, it can be ensured that the total resistance value of each single resistor row is equal to the sum of the resistance values of all of the voltage decreasing resistors R located in each single transistor row by adopting a matrix of resistors constituted by resistors having a same resistance value and connected in series, which has a relative simple circuit configuration and can be designed and implemented easily.
In the above embodiments, the description is given by taking the case that the first transistors M and the second transistors T are N type transistors as an example. Besides, the ramp signal generating circuit provided in the embodiments of the present disclosure can also adopt P type TFTs. When the first transistors M and the second transistors T are all P type transistors, the corresponding decreasing ramp signal generating circuit and the corresponding increasing ramp signal generating circuit are as shown in FIG. 7 and FIG. 8, respectively. FIG. 9 is a circuit timing sequence diagram for driving the ramp signal generating circuit shown in FIG. 7 or FIG. 8, and the description for the corresponding principle is omitted but can be obtained by referring to the above description for the ramp signal generating circuit having the configuration adopting the N type TFTs.
Such structured ramp signal generating circuit comprises less component units and has a high integration level in circuit configuration, thus capable of reducing area occupied by the ramp signal generating circuit. In addition, compared to the prior art, such structured ramp signal generating circuit can have a higher sampling frequency and can obtain more voltage stages and a smaller voltage step, thus capable of improving effectively linearity of a ramp signal.
Furthermore, taking account of the limited driving capability of the signal outputted from the output terminal Vo of the sampling unit 14 in the above ramp signal generating circuit, an amplifying unit 15 can be additionally arranged inside or outside of the ramp signal generating circuit, and an input terminal of the amplifying unit 15 can be connected to the output terminal Vo of the sampling unit 14 for amplifying power of the voltage outputted from the sampling unit 14.
For example, in the ramp signal generating circuit as shown in FIG. 2, the amplifying unit 15 can particularly adopt a power amplifier or other circuits possessing the same function, and no limitation is given to the construction of the amplify unit 15 in the embodiments of the present disclosure.
The ramp signal generating circuit provided in the embodiments of the present disclosure further has advantages that the arrangement and connection manner of the resistors in the matrix is improved, there is no wiring between adjacent rows even if the operation procedure of the GOA2 circuit adopts unidirectional scanning by supplying the input signals by two power supply input terminals Vref1 and Vref2 and changing the circuit of the resistor matrix, and furthermore a perfect linearity of the ramp signal and a low noise level can be obtained.
In the embodiments of the present disclosure, there is further provided a ramp signal generator comprising the above described ramp signal generating circuit.
Such ramp signal generator can be used as a signal source individually or combined with other devices, and can be widely applied in various devices or circuit structures requiring ramp signal driving. The structure of the ramp signal generating circuit has been described in the above embodiments, and repeated description will be omitted.
The ramp signal generator provided in the embodiments of the present disclosure comprises the ramp signal generating circuit which adopts a designed structure comprising two shift register units, a voltage decreasing unit and a sampling unit, adopts different designed signal timing sequences to allow that the two shift register units drive the voltage decreasing unit and the sampling unit respectively, such that the first shift register unit controls the voltage decreasing unit to output voltages which are decreased continuously stage by stage and generated by continuously decreasing a voltage inputted from the first power supply input terminal or a voltage inputted from the second power supply input terminal stage by stage, and the second shift register unit controls the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit. Such structured ramp signal generating circuit comprises less component units and has a high integration level in circuit configuration, thus capable of reducing area occupied by the ramp signal generating circuit. In addition, compared to the prior art, such structured ramp signal generating circuit can have a higher sampling frequency and can obtain more voltage stages and a smaller voltage step, thus capable of improving effectively linearity of a ramp signal.
The ramp signal generating circuit provided in the embodiments of the present disclosure can be further applied to an array substrate structure in a display panel. The array substrate in the prior art mostly adopts a circuit structure comprising a first shift register and a second shift register.
The first shift register and the second shift register are configured to input gate line scan signals and data line scan signals to the pixel units in the display area, respectively. Such pixel array structure can reduce peripheral wiring of the display apparatus so as to achieve the narrow bezel design of a display apparatus.
Furthermore, the above described ramp signal generating circuit can be implemented on the array substrate, wherein the first shift register and the second shift register which are configured to input the gate line scan signals and the data line scan signals to the pixel units in the display area respectively can be used as the first shift register unit and the second shift register unit in the ramp signal generating circuit respectively. The array substrate can further particularly comprise: a voltage decreasing unit and a sampling unit, the voltage decreasing unit is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage. The first shift register unit is connected to the voltage decreasing unit and is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage. The sampling unit has an output terminal and is connected to the voltage decreasing unit. The second shift register unit is connected to the sampling unit, and is configured to control the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit.
In such structured array substrate, the ramp signal generating circuit is formed by integrating the voltage decreasing unit and the sampling unit on the array substrate and using the existing two shift register on the array substrate. In such manner, the ramp signal generating function can be achieved without adding many additional devices on the surface of the array substrate, such that area of the driving circuit of the display panel can be effectively controlled and the narrow bezel design of the display apparatus can be ensured.
The configuration of the ramp signal generating circuit has been described in detail in the above embodiments of the present disclosure, and repeated description will be omitted herein.
The array substrate provided in the embodiments of the present disclosure comprises the ramp signal generating circuit which adopts a designed structure comprising two shift register units, a voltage decreasing unit and a sampling unit, adopts different designed signal timing sequences to allow that the two shift register units drive the voltage decreasing unit and the sampling unit respectively, such that the first shift register unit controls the voltage decreasing unit to output voltages which are decreased continuously stage by stage and generated by continuously decreasing a voltage inputted from the first power supply input terminal or a voltage inputted from the second power supply input terminal stage by stage, and the second shift register unit controls the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit. Such structured ramp signal generating circuit comprises less component units and has a high integration level in circuit configuration, thus capable of reducing area occupied by the ramp signal generating circuit. In addition, compared to the prior art, such structured ramp signal generating circuit can have a higher sampling frequency and can obtain more voltage stages and a smaller voltage step, thus capable of improving effectively linearity of a ramp signal.
A display apparatus provided in the embodiments of the present disclosure comprises the above described array substrate.
It should be explained that the display apparatus provided in the embodiments of the present disclosure may be any product or component having display function comprising liquid crystal display panel, electronic paper, OLED panel, liquid crystal television, liquid crystal display, digital frame, cell phone, tablet computer and so on.
The structure of the array substrate has been described in detail in the above embodiments of the present disclosure, and repeated description is omitted herein.
Such structured display apparatus comprises the array substrate comprising a ramp signal generating circuit, which adopts a designed structure comprising two shift register units, a voltage decreasing unit and a sampling unit, adopts different designed signal timing sequences to allow that the two shift register units drive the voltage decreasing unit and the sampling unit respectively, such that the first shift register unit controls the voltage decreasing unit to output voltages which are decreased continuously stage by stage and generated by continuously decreasing a voltage inputted from the first power supply input terminal or a voltage inputted from the second power supply input terminal stage by stage, and the second shift register unit controls the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit. Such structured ramp signal generating circuit comprises less component units and has a high integration level in circuit configuration, thus capable of reducing area occupied by the ramp signal generating circuit. In addition, compared to the prior art, such structured ramp signal generating circuit can have a higher sampling frequency and can obtain more voltage stages and a smaller voltage step, thus capable of improving effectively linearity of a ramp signal.
Those ordinary skilled in the art can understand that all or part of procedures implementing the above method embodiments of the present disclosure may be implemented through computer program instructing related hardware. The computer program may be stored in a computer readable storage medium, and performs the steps in the above method embodiments of the present disclosure when being executed. The computer readable storage medium may comprise various media capable of storing program codes for example, a ROM, a RAM, a magnetic disk, an optical disk, and so on.
The above are only some particular implementations of the present disclosure, and the protection scope of the present disclosure is not limited thereto. It will be obvious that those skilled in the art may conceive of variations and alternatives in the technical scope disclosure in the embodiments of the present disclosure. Such variations and alternatives are intended to be comprised within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be defined according to the protection scope of the accompanying claims.

## Claims

1. A ramp signal generating circuit comprising:
a first shift register, a second shift register, a voltage decreasing sub-circuit and a sampling sub-circuit;
wherein the voltage decreasing sub-circuit is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal, and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage;
the first shift register is connected to the voltage decreasing sub-circuit and is configured to control the voltage decreasing sub-circuit to output voltages which are decreased continuously stage by stage;
the sampling sub-circuit has an output terminal and is connected to the voltage decreasing sub-circuit; and
the second shift register is connected to the sampling sub-circuit and is configured to control the sampling sub-circuit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing sub-circuit.

2. The ramp signal generating circuit of claim 1, wherein the voltage decreasing sub-circuit comprises: a plurality of first transistors arranged in a matrix and a plurality of voltage decreasing resistors;
gates of the first transistors located in a same row are connected to an output terminal of the first shift register;
first electrodes of the first transistors located in a same column are connected to an input terminal of the sampling sub-circuit;
second electrodes of the first transistors located in a same row are connected in series and one of the voltage decreasing resistors is connected between the second electrodes of every two adjacent first transistors,
except the first transistors located in the last two rows, the second electrode of the first transistor located at a last column of each row is connected to the second electrode of the first transistor located at a first column of a row which is two-rows next to the row through a resistor row.

3. The ramp signal generating circuit of claim 2, wherein
input terminals of the first shift register are connected to a first clock signal, a second clock signal and a first frame start signal, and are configured to turn on the first transistors row by row;
input terminals of the second shift register are connected to a third clock signal, a fourth clock signal and a second frame start signal, and are configured to, during an ON period of the first transistors located in a same row, control the sampling sub-circuit to sample column by column the voltage at the first electrode of each of the first transistors located in the same row.

4. The ramp signal generating circuit of claim 2, wherein the sampling sub-circuit comprises: a plurality of second transistors;
gates of the second transistors are connected to different output terminals of the second shift register, and first electrodes of the second transistors are connected to an output terminal of the sampling sub-circuit;
a second electrode of each of the second transistors is connected to the first electrodes of the first transistors located in a same column.

5. The ramp signal generating circuit of claim 4, wherein
both the first transistors and the second transistors are N type transistors, or both the first transistors and the second transistors are P type transistors;
when the first transistors and the second transistors are N type transistors, the first electrodes of the transistors are sources and the second electrodes of the transistors are drains.

6. The ramp signal generating circuit of claim 2, wherein
the first power supply input terminal is connected to the second electrode of the first transistor located at the first transistor row and the first column in the voltage decreasing sub-circuit; the second power supply input terminal is connected to the second electrode of the first transistor located at the second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the last second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the last transistor row and the last column is connected to the ground terminal; or
the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the last column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the last column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the first column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the first column is connected to the ground terminal; or
the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the first column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the last column is connected to the ground terminal.

7. The ramp signal generating circuit of claim 2, wherein
a sum of resistance values of all of the voltage decreasing resistors located in each single transistor row is the same and is equal to a total resistance value of each single resistor row;
a signal inputted from the first power supply input terminal and a signal inputted from the second power supply input terminal are the same.

8. The ramp signal generating circuit of claim 1, further comprising:
an amplifying sub-circuit having an input terminal connected to the output terminal of the sampling sub-circuit and being configured for amplifying power of the voltage outputted from the sampling sub-circuit.

9. An array substrate comprising a first shift register and a second shift register, wherein the first shift register is configured to generate gate line scan signals and the second shift register is configured to generate data line scan signals, the array substrate further comprising:
a voltage decreasing sub-circuit and a sampling sub-circuit,
wherein the voltage decreasing sub-circuit is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal, and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage;
the first shift register is connected to the voltage decreasing sub-circuit and is configured to control the voltage decreasing sub-circuit to output voltages which are decreased continuously stage by stage;
the sampling sub-circuit has an output terminal and is connected to the voltage decreasing sub-circuit; and
the second shift register is connected to the sampling sub-circuit and is configured to control the sampling sub-circuit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing sub-circuit.

10. The array substrate of claim 9, wherein the voltage decreasing sub-circuit comprises: a plurality of first transistors arranged in a matrix and a plurality of voltage decreasing resistors;
gates of the first transistors located in a same row are connected to an output terminal of the first shift register;
first electrodes of the first transistors located in a same column are connected to an input terminal of the sampling sub-circuit;
second electrodes of the first transistors located in a same row are connected in series and one of the voltage decreasing resistors is connected between the second electrodes of every two adjacent first transistors,
except the first transistors located in the last two rows, the second electrode of the first transistor located at a last column of each row is connected to the second electrode of the first transistor located at a first column of a row which is two-rows next to the row through a resistor row.

11. The array substrate of claim 10, wherein
input terminals of the first shift register are connected to a first clock signal, a second clock signal and a first frame start signal, and are configured to turn on the first transistors row by row;
input terminals of the second shift register are connected to a third clock signal, a fourth clock signal and a second frame start signal, and are configured to, during an ON period of the first transistors located in a same row, control the sampling sub-circuit to sample column by column the voltage at the first electrode of each of the first transistors located in the same row.

12. The array substrate of claim 9, wherein the sampling sub-circuit comprises: a plurality of second transistors;
gates of the second transistors are connected to different output terminals of the second shift register, and first electrodes of the second transistors are connected to an output terminal of the sampling sub-circuit;
a second electrode of each of the second transistors is connected to the first electrodes of the first transistors located in a same column.

13. The array substrate of claim 12, wherein
both the first transistors and the second transistors are N type transistors, or both the first transistors and the second transistors are P type transistors;
when the first transistors and the second transistors are N type transistors, the first electrodes of the transistors are sources and the second electrodes of the transistors are drains.

14. The array substrate of claim 10, wherein
the first power supply input terminal is connected to the second electrode of the first transistor located at the first transistor row and the first column in the voltage decreasing sub-circuit; the second power supply input terminal is connected to the second electrode of the first transistor located at the second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the last second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the last transistor row and the last column is connected to the ground terminal; or
the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the last column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the last column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the first column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the first column is connected to the ground terminal; or
the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the first column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the last column is connected to the ground terminal.

15. The array substrate of claim 10, wherein
a sum of resistance values of all of the voltage decreasing resistors located in each single transistor row is the same and is equal to a total resistance value of each single resistor row;
a signal inputted from the first power supply input terminal and a signal inputted from the second power supply input terminal are the same.

16. The array substrate of claim 9, wherein the ramp signal generating circuit further comprises:
an amplifying sub-circuit having an input terminal connected to the output terminal of the sampling sub-circuit and being configured for amplifying power of the voltage outputted from the sampling sub-circuit.

17. A display apparatus comprising the array substrate of claim 9.

18. The display apparatus of claim 17, wherein the voltage decreasing sub-circuit comprises: a plurality of first transistors arranged in a matrix and a plurality of voltage decreasing resistors;
gates of the first transistors located in a same row are connected to an output terminal of the first shift register;
first electrodes of the first transistors located in a same column are connected to an input terminal of the sampling sub-circuit;
second electrodes of the first transistors located in a same row are connected in series and one of the voltage decreasing resistors is connected between the second electrodes of every two adjacent first transistors,
except the first transistors located in the last two rows, the second electrode of the first transistor located at a last column of each row is connected to the second electrode of the first transistor located at a first column of a row which is two-rows next to the row through a resistor row;
wherein the first power supply input terminal is connected to the second electrode of the first transistor located at the first transistor row and the first column in the voltage decreasing sub-circuit; the second power supply input terminal is connected to the second electrode of the first transistor located at the second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the last second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the last transistor row and the last column is connected to the ground terminal; or
the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the last column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the last column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the first column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the first column is connected to the ground terminal; or
the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the first column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the last column is connected to the ground terminal.

19. The display apparatus of claim 18, wherein
input terminals of the first shift register are connected to a first clock signal, a second clock signal and a first frame start signal, and are configured to turn on the first transistors row by row;
input terminals of the second shift register is connected to a third clock signal, a fourth clock signal and a second frame start signal, and are configured to, during an ON period of the first transistors located in a same row, control the sampling sub-circuit to sample column by column the voltage at the first electrode of each of the first transistors located in the same row.

20. The display apparatus of claim 17, wherein
a sum of resistance values of all of the voltage decreasing resistors located in each single transistor row is the same and is equal to a total resistance value of each single resistor row;
a signal inputted from the first power supply input terminal and a signal inputted from the second power supply input terminal are the same.