# Patent

## Title
Semiconductor device including buffer circuit and level shifter circuit, and electronic device including the same

## Abstract

To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device and an electronic device.
Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a memory device, a method for driving any of them, and a method for manufacturing any of them.
In this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like that can function by utilizing semiconductor characteristics. An example of the semiconductor device is a semiconductor element such as a transistor or a diode. Another example of the semiconductor device is a circuit including a semiconductor element. Another example of the semiconductor device is a device provided with a circuit including a semiconductor element.
2. Description of the Related Art
The following semiconductor devices have attracted attention: a semiconductor device that is capable of retaining data using a transistor including an oxide semiconductor (OS) in a semiconductor layer (hereinafter referred to as an OS transistor); and a semiconductor device that is capable of retaining data using an OS transistor and a transistor including silicon (Si) in a semiconductor layer (hereinafter referred to as a Si transistor) in combination (see Patent Documents 1 and 2).
REFERENCE


    [Patent Document 1] Japanese Published Patent Application No. 2012-39059
    [Patent Document 2] Japanese Published Patent Application No. 2012-256820


SUMMARY OF THE INVENTION
To control on/off of the OS transistor, a signal with a large amplitude is needed. Therefore, a signal whose voltage is raised is output to a gate of the OS transistor. A plurality of power supply voltages are needed for a booster circuit. A semiconductor device is capable of retaining data even without application of a power supply voltage, so that application of a plurality of power supply voltages can be stopped.
In the case where the plurality of power supply voltages are supplied again, however, unintentionally supplying a high-level potential to the gate of the OS transistor might cause loss of the retained data.
An object of one embodiment of the present invention is to provide a novel semiconductor device, a novel electronic device, or the like.
Another object of one embodiment of the present invention is to provide a semiconductor device or the like with a novel structure that can prevent data loss due to malfunction of the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with a novel structure that can reduce power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with a novel structure that can inhibit unintentional output of a high-level potential from a booster circuit that raises the voltage of a signal by being supplied with a plurality of power supply voltages.
Note that the object of one embodiment of the present invention is not limited to the above objects. The objects described above do not disturb the existence of other objects. The other objects are the ones that are not described above and will be described below. The other objects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention solves at least one of the aforementioned objects and the other objects.
One embodiment of the present invention is a semiconductor device including a first buffer circuit, a level shifter circuit, a second buffer circuit, and first to third wirings. The first wiring is configured to supply a first potential. The second wiring is configured to supply a second potential, which is higher than the first potential. The third wiring is configured to supply a third potential, which is lower than the first potential and the second potential. The first buffer circuit is electrically connected to the first wiring and the third wiring. The level shifter circuit and the second buffer circuit are electrically connected to the second wiring and the third wiring. The level shifter circuit includes a first node and a second node. The first node is configured to hold the second potential when a low-level potential is output from the level shifter circuit to the second buffer circuit. The second node is configured to hold the third potential when the low-level potential is output from the level shifter circuit to the second buffer circuit. The level shifter circuit includes a first capacitor and a second capacitor. A first electrode of the first capacitor is electrically connected to the second wiring. A second electrode of the first capacitor is electrically connected to the first node. A first electrode of the second capacitor is electrically connected to the third wiring. A second electrode of the second capacitor is electrically connected to the second node.
In the semiconductor device of one embodiment of the present invention, the level shifter circuit preferably includes a first transistor whose on/off is controlled in accordance with the potential of the first node. The first electrodes and the second electrodes of the first capacitor and the second capacitor preferably overlap with the first transistor.
The semiconductor device of one embodiment of the present invention preferably includes a memory cell. The memory cell includes a second transistor and is configured to store charge depending on data in a node connected to the second transistor that is off. The second buffer circuit is electrically connected to a gate of the second transistor.
The semiconductor device of one embodiment of the present invention preferably includes a memory cell. The memory cell includes a third capacitor. A first electrode of the third capacitor is provided in the same layer as the first electrode of the first capacitor and the first electrode of the second capacitor. The second electrode of the third capacitor is provided in the same layer as the second electrode of the first capacitor and the second electrode of the second capacitor.
In the semiconductor device of one embodiment of the present invention, the first transistor preferably includes silicon in a channel formation region.
In the semiconductor device of one embodiment of the present invention, the second transistor preferably includes an oxide semiconductor in a channel formation region.
Note that other embodiments of the present invention will be described in the following embodiments with reference to drawings.
One embodiment of the present invention can provide a novel semiconductor device, a novel electronic device, or the like.
Alternatively, one embodiment of the present invention can provide a semiconductor device or the like with a novel structure that can prevent data loss due to malfunction of the semiconductor device. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like with a novel structure that can reduce power consumption. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like with a novel structure that can inhibit unintentional output of a high-level potential from a booster circuit that raises the voltage of a signal by being supplied with a plurality of power supply voltages.
Note that the effect of one embodiment of the present invention is not limited to the effects listed above. The effects described above do not disturb the existence of other effects. The other effects are the ones that are not described above and will be described below. The other effects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention has at least one of the aforementioned effects and the other effects. Accordingly, one embodiment of the present invention does not have the aforementioned effects in some cases.



BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B are a block diagram and a circuit diagram that illustrate one embodiment of the present invention.
FIGS. 2A and 2B are a circuit diagram and a timing chart that show one embodiment of the present invention.
FIG. 3 is a timing chart showing one embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating one embodiment of the present invention.
FIGS. 5A and 5B are a circuit diagram and a timing chart that show one embodiment of the present invention.
FIG. 6 is a circuit diagram illustrating one embodiment of the present invention.
FIG. 7 is a circuit diagram illustrating one embodiment of the present invention.
FIG. 8 is a circuit diagram illustrating one embodiment of the present invention.
FIGS. 9A to 9F are circuit diagrams illustrating embodiments of the present invention.
FIG. 10 is a block diagram illustrating one embodiment of the present invention.
FIGS. 11A to 11C are circuit diagrams illustrating embodiments of the present invention.
FIG. 12 is a schematic diagram illustrating one embodiment of the present invention.
FIGS. 13A to 13D are layout diagrams illustrating an embodiment of the present invention.
FIG. 14 is a cross-sectional schematic view illustrating one embodiment of the present invention.
FIG. 15 is a schematic cross-sectional view illustrating one embodiment of the present invention.
FIG. 16 is a block diagram illustrating one embodiment of the present invention.
FIGS. 17A and 17B are circuit diagrams illustrating one embodiment of the present invention.
FIGS. 18A to 18C are circuit diagrams illustrating one embodiment of the present invention.
FIGS. 19A and 19B are circuit diagrams illustrating one embodiment of the present invention.
FIG. 20 is a circuit diagram illustrating one embodiment of the present invention.
FIG. 21 is a circuit diagram illustrating one embodiment of the present invention.
FIG. 22 is a circuit diagram illustrating one embodiment of the present invention.
FIG. 23 is a circuit diagram illustrating one embodiment of the present invention.
FIG. 24 is a block diagram illustrating one embodiment of the present invention.
FIGS. 25A and 25B are a flow chart and a perspective view that show one embodiment of the present invention.
FIGS. 26A to 26E each illustrate an electronic device to which one embodiment of the present invention can be applied.
FIG. 27 is a graph showing one embodiment of the present invention.
FIGS. 28A to 28C are circuit diagrams illustrating embodiments of the present invention.
FIG. 29 is a circuit diagram illustrating one embodiment of the present invention.
FIGS. 30A and 30B are circuit diagrams illustrating an example.
FIGS. 31A and 31B are a block diagram and a timing chart that show an example.
FIGS. 32A, 32B1, 32B2, 32B3, and 32B4 are a circuit diagram and timing charts that show examples.
FIG. 33 shows waveform charts for describing an example.
FIG. 34 shows waveform charts for describing an example.
FIG. 35 shows waveform charts for describing an example.
FIG. 36 shows waveform charts for describing an example.
FIG. 37 shows waveform charts for describing an example.
FIG. 38 shows waveform charts for describing an example.



DETAILED DESCRIPTION OF THE INVENTION
Embodiments and an example will be described below with reference to the drawings. However, the embodiments and example can be implemented with various modes. It will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments and example below.
In this specification and the like, ordinal numbers such as first, second, and third are used in order to avoid confusion among components. Thus, the terms do not limit the number or order of components. In this specification and the like, a “first” component in one embodiment can be referred to as a “second” component in other embodiments or claims. Furthermore, in this specification and the like, a “first” component in one embodiment can be referred to without the ordinal number in other embodiments or claims.
In the drawings, the same components, components having similar functions, components formed of the same material, or components formed at the same time are denoted by the same reference numerals in some cases, and description thereof is not repeated in some cases.
Embodiment 1
In this embodiment, a semiconductor device of one embodiment of the disclosed invention will be described. In particular, the structure of a semiconductor device including an output circuit for outputting a signal to a memory cell will be described in this embodiment.
FIG. 1A illustrates an output circuit 100 and a memory cell MC. The memory cell MC includes a transistor OM. The transistor OM is connected to a wiring BL and a node MN. In the output circuit 100, a signal is input to a terminal IN and output to a wiring WLret connected to a gate of the transistor OM.
Note that the transistor OM has a function as a switch. The transistor OM is preferably a transistor in which a current flowing between the source and drain in the off state (off-state current) is low. A transistor with a low off-state current is preferably a transistor containing an oxide semiconductor in its channel formation region (OS transistor). An OS transistor has the following advantages: the low off-state current thereof; the capability of being formed so as to overlap with a Si transistor; and the like. An OS transistor will be described in detail in an embodiment below.
The memory cell MC controls on/off of the transistor OM to write a voltage depending on data supplied to the wiring BL (data voltage) to a node MN and hold the voltage. In the case where the transistor OM is an n-channel transistor, a high-level potential is supplied to the wiring WLret, which is the gate of the transistor, to turn on the transistor so that a data voltage is written to the node MN. Then, a low-level potential is kept being supplied to the wiring WLret to turn off the transistor so that the data voltage is held.
The output circuit 100 is a circuit for outputting a signal to the wiring WLret. Setting a low-level potential that is supplied to the wiring WLret from the output circuit 100 to a ground potential allows the transistor OM to be kept off even when the operation of the output circuit 100 is intentionally terminated. Alternatively, in the case where a power supply voltage cannot be continuously applied as in a wireless device, the transistor OM can be kept off even when the operation of the output circuit 100 is intermittently terminated. Thus, the data voltage held in the memory cell MC is retained even after the application of the power supply voltage to the output circuit 100 is terminated.
Since the output circuit 100 turns on the transistor to write the data voltage, a signal with a large amplitude is needed. The output circuit 100 obtains a signal with a large amplitude by application of different power supply voltages to a plurality of circuits. The output circuit 100 includes a buffer circuit BUF1, a level shifter circuit LS, and a buffer circuit BUF2, for example.
The buffer circuit BUF1 is connected to a wiring VH1 so that the application of a power supply voltage can be controlled. The level shifter circuit LS and the buffer circuit BUF2 are connected to a wiring VH2 so that the application of a power supply voltage can be controlled. When a power supply voltage is applied, a voltage VDD1 is applied to the wiring VH1, and a voltage VDD2 is applied to the wiring VH2. When the application of a power supply voltage is terminated, a ground voltage is applied to both the wirings VH1 and VH2.
In the case where the application and the termination of a power supply voltage are alternately performed, the potential of each node in the output circuit 100 is not stabilized. Particularly a variation in the potential of a node that is influenced by the wiring VH2 whose voltage is stepped up and down instantaneously causes an unexpected potential variation, and a high-level signal is output to the wiring WLret. Thus, the off state of the transistor OM becomes unstable and the data voltage of the memory cell MC is lost in some cases.
In one embodiment of the present invention, the output circuit 100 has a configuration of a circuit diagram illustrated in FIG. 1B as an example. In FIG. 1B, the buffer circuit BUF1 includes inverter circuits 11 and 12. The level shifter circuit LS includes transistors M1 to M6 and capacitors C1 and C2. The buffer circuit BUF2 includes inverter circuits 13 and 14. Power supply voltages are supplied to the circuits through the wirings VH1 and VH2.
The output circuit 100 illustrated in FIG. 1B has a function of outputting a low-level signal to the wiring WLret by supplying the low-level signal to the terminal IN. The level shifter circuit LS includes a node OUT and a node OUTB. In the level shifter circuit LS, the potential of the node OUT and the potential of the node OUTB are set at a low level and at a high level, respectively, whereby the low-level signal can be stably output to the wiring WLret.
In FIG. 1B, the capacitors C1 and C2 are provided so that the potential of the node OUT and the potential of the node OUTB easily become at a low level and at a high level, respectively, when the potentials of the wirings VH1 and VH2 are increased in order that the power supply voltages are applied. Specifically, the capacitor C1 is provided between the wiring VH2 and the node OUTB, and the capacitor C2 is provided between a ground line and the node OUT.
The configuration in FIG. 1B allows the potential of the node OUTB to be increased to a high-level potential at the timing when the voltage VDD2 is applied to the wiring VH2. The potential of the node OUTB can more reliably turn off the transistor M1 at the same time that the potential of the wiring VH2 is increased because of capacitive coupling caused by the capacitor C1. The potential of the node OUTB is fixed at a high level, whereby a signal output to the wiring WLret through the inverter circuits 13 and 14 can be kept at a low level.
Furthermore, the configuration in FIG. 1B allows the potential of the node OUT to be kept at a low level at the timing when the voltage VDD2 is applied to the wiring VH2. Even when the potential of the node OUT varies because of capacitive coupling caused in the capacitor C2, the variation is negligible.
Thus, the output circuit 100 can suppress unexpected output of a high-level signal to the wiring WLret in application of the power supply voltage and can prevent data loss because of malfunction. The application of the power supply voltage to the output circuit 100 can be stopped, leading to reduction in power consumption.
Note that the transistors M1 to M6 are preferably transistors including silicon in channel formation regions (Si transistors). Adding impurities and the like can reduce variations in threshold voltage caused when the Si transistors are fabricated through the same process. Furthermore, the capacitors C1 and C2 are preferably provided so as to overlap with the transistors M1 to M6. Such a structure can prevent an increase in layout area due to the addition of the capacitors C1 and C2.
Note that the capacitors C1 and C2, which overlap with the transistors M1 to M6, are preferably provided in the same layer as an OS transistor of the memory cell MC. In the case of employing such a structure, it is preferred that one electrode of the capacitor be provided in the same layer as a gate electrode of the OS transistor and the other electrode of the capacitor be provided in the same layer as source and drain electrodes of the OS transistor. Such a structure allows an insulating layer between the electrodes of the capacitor to be formed using the same layer as a gate insulating layer in the OS transistor. The gate insulating layer is thinner than an interlayer insulating layer; thus, the capacitance value per unit area thereof can be increased.
FIG. 2A is a circuit diagram similar to that in FIG. 1B. The operations will be described with reference to the circuit diagram in FIG. 2A and a timing chart shown in FIG. 2B.
In the timing chart shown in FIG. 2B, a signal of the terminal IN is a low-level signal. In the initial state before a time T1, the voltages of the wirings VH1 and VH2 are low-level voltages. At this time, the nodes OUT and OUTB are in an electrically floating state. The wiring WLret is also in an electrically floating state. Note that the potential of the wiring WLret finally becomes at a low level because of a leakage current flowing through the buffer circuit BUF2, or the like, and the wiring WLret is brought into a floating state. Thus, the potential of the wiring WLret is at a low level in FIG. 2B.
At the time T1, the voltages VDD1 and VDD2 are applied to the wirings VH1 and VH2, respectively. An increase in the voltage of the wiring VH1 fixes the outputs of the inverter circuits 11 and 12.
Directly after the time T1, the node OUTB is in an electrically floating state. Thus, an increase in the voltage of the wiring VH2 permits the capacitor C1 to retain stored capacitance C1coupling. That is, capacitive coupling occurs in the capacitor C1. Consequently, the potential of the node OUTB can be increased before the transistors M1 and M2 are turned on. The potential of the node OUTB is set at a high level, and at a time T2, a signal that is output to the wiring WLret, which is an output of the inverter circuits 13 and 14, is fixed at a low level.
In addition, directly after the time T1, the node OUT is in an electrically floating state. Thus, an increase in the voltage of the wiring VH2 permits the capacitor C2 to retain stored capacitance C2coupling. That is, capacitive coupling occurs in the capacitor C2. Consequently, the potential of the node OUT is less likely to be increased with the increase in the voltage of the wiring VH2. After the time T1, when the transistor M6 is turned on, the node OUT is fixed at a low level. The capacitor C2 can suppress unexpected increase in the potential of the node OUT before the transistor M6 is turned on.
Thus, when the application of a power supply voltage for shifting the level of a signal is resumed, the potential of the wiring WLret can be kept at a low level. Therefore, data loss can be prevented from being caused by a high-level potential that is unexpectedly output to the wiring WLret.
Note that in this embodiment, when the potential of the node OUT is set at a low level, the potential of the wiring WLret is at a low level because the buffer circuit BUF2 includes even-numbered stages of inverter circuits (two stages in FIG. 1B). In the case where the buffer circuit BUF2 includes odd-numbered stages of inverter circuits, the potential of the wiring WLret is at a low level when the potential of the node OUT is at a high level. Therefore, the positions of the capacitors C1 and C2 are changed in accordance with the number of stages of the inverter circuits in the buffer circuit BUF2.
To verify the effect of one embodiment of the present invention described above, calculation was performed with a calculator. FIG. 27 is a graph showing variations in the voltage of the wiring WLret when the voltages of the wirings VH1 and VH2 were raised from the ground voltage in the circuit diagram illustrated in FIG. 1A in the case where the capacitors C1 and C2 are provided and the case where the capacitors C1 and C2 are not provided.
As can be seen in FIG. 27, in the case where the capacitors C1 and C2 are not provided (Without C1, C2), the voltage of the wiring WLret varied when the voltages of the wirings VH1 and VH2 rose. In contrast, in the case where the capacitors C1 and C2 are provided (With C1, C2), the voltage of the wiring WLret was constantly 0 V, which is the ground voltage, even while the voltages of the wirings VH1 and VH2 rose. Therefore, providing the capacitors C1 and C2 enabled the potential of the wiring WLret to be kept at a low level.
Embodiment 2
In this embodiment, modification examples of the output circuit described in Embodiment 1, examples of the memory cell MC, an example of a semiconductor device including the memory cell MC, and modification examples of the memory cell MC will be described.
<Modification Examples of Output Circuit>
FIG. 3 to FIG. 8 and FIG. 29 show timing charts and modification examples of circuit configurations that can be employed for the output circuit illustrated in FIGS. 1A and 1B.
FIG. 3 is a timing chart different from that shown in FIG. 2B in that the voltages VDD1 and VDD2 are applied to the wirings V1 and V2, respectively, at respective timings of a time T3 and a time T4. This structure allows the potential of the node OUT to be at a low level more reliably.
FIG. 4 is a circuit diagram different from that in FIG. 1B in the positions of the capacitors C1 and C2 and the number of the inverter circuits in the buffer circuit BUF2 (one inverter circuit is provided in the buffer circuit BUF2 in FIG. 4). In the circuit diagram in FIG. 4, the capacitor C1 is provided between the wiring VH2 and the node OUT, and the capacitor C2 is provided between a ground line and the node OUTB.
The configuration in FIG. 4 allows the potential of the node OUT to be increased to a high-level potential at the timing when the voltage VDD2 is applied to the wiring VH2. The potential of the node OUT can more reliably turn off the transistor M1 at the same time that the potential of the wiring VH2 is increased because of capacitive coupling caused by the capacitor C1. The potential of the node OUT is set to a high-level potential, whereby a signal output to the wiring WLret through the inverter circuit 13 can be kept at a low level.
FIG. 5A is a circuit diagram similar to that in FIG. 4. The operations will be described with reference to the circuit diagram in FIG. 5A and a timing chart in FIG. 5B.
In the timing chart shown in FIG. 5B, a signal of the terminal IN is a low-level signal. In the initial state before a time T5, the voltages of the wirings VH1 and VH2 are low-level voltages. At this time, the nodes OUT and OUTB are in an electrically floating state. The wiring WLret is also in an electrically floating state. Note that the potential of the wiring WLret finally becomes at a low level because of a leakage current flowing through the buffer circuit BUF2, or the like, and the wiring WLret is brought into a floating state. Thus, the potential of the wiring WLret is at a low level in FIG. 5B.
At the time T5, the voltages VDD1 and VDD2 are applied to the wirings VH1 and VH2, respectively. An increase in the voltage of the wiring VH1 fixes the outputs of the inverter circuits 11 and 12.
Directly after the time T5, the node OUT is in an electrically floating state. Thus, an increase in the voltage of the wiring VH2 permits the capacitor C1 to retain stored capacitance C1coupling. Consequently, the potential of the node OUT can be increased before the transistors M4 and M5 are turned on. The potential of the node OUT is set at a high level, and at a time T6, a signal that is output to the wiring WLret, which is an output of the inverter circuit 13, is fixed at a low level.
In addition, directly after the time T5, the node OUTB is in an electrically floating state. Thus, an increase in the voltage of the wiring VH2 permits the capacitor C2 to retain stored capacitance C2coupling. Consequently, the potential of the node OUTB is less likely to be increased with the increase in the voltage of the wiring VH2. After the time T5, when the transistor M3 is turned on, the node OUTB is fixed at a low level. The capacitor C2 can suppress unexpected increase in the potential of the node OUTB before the transistor M3 is turned on.
Thus, when the application of a power supply voltage for shifting the level of a signal is resumed, the potential of the wiring WLret can be kept at a low level. Therefore, data loss can be prevented from being caused by a high-level potential that is output to the wiring WLret.
The configuration of a circuit diagram illustrated in FIG. 6 is different from that illustrated in FIG. 1B in that the transistors M2 and M5 are not provided. Even in the case where the number of transistors is reduced as in FIG. 6, variations in the potentials of the nodes OUT and OUTB can be inhibited. Thus, data loss can be prevented from being caused by a high-level potential output to the wiring WLret, and the number of components of a semiconductor device can be reduced.
The configuration without the transistors M2 and M5 illustrated in FIG. 6 can be used for the configuration of the circuit diagram illustrated in FIG. 4 as illustrated in FIG. 7. That is, the transistors can be omitted also in the configuration where the positions of the capacitors C1 and C2 are changed and the buffer circuit BUF2 includes one inverter circuit. Thus, data loss can be prevented from being caused by a high-level potential output to the wiring WLret, and the number of components of a semiconductor device can be reduced.
Note that when the channel widths of the transistors M4 and M6 are larger than those of the transistors M1 and M3 in the configuration illustrated in FIG. 4, the transistors M4 and M6 function as a buffer, and the buffer circuit BUF2 can be omitted as illustrated in FIG. 8. Thus, data loss can be prevented from being caused by a high-level potential output to the wiring WLret, and the number of components of a semiconductor device can be reduced.
Note that a transistor M7 may be additionally provided as in the configuration illustrated in FIG. 29. The transistor M7 is controlled by a control signal EN so as to be on when the potential of the wiring WLret is a low-level potential. This configuration more reliably allows the potential of the wiring WLret to be a low-level potential.
<Examples of Memory Cell MC>
FIGS. 9A to 9F each illustrate a circuit configuration example that the memory cell MC illustrated in FIG. 1A can have. In the circuit diagrams of memory cells illustrated in FIGS. 9A to 9F, a data voltage is written from a wiring SL or the wiring BL, and controlling the voltages of the wiring WWL and a wiring RWL can control writing or reading out of the data voltage.
A memory cell MC_A illustrated in FIG. 9A includes a transistor 15, the transistor OM, and a capacitor 17. The transistor 15 is a p-channel transistor. Turning off the transistor OM allows a charge depending on the data voltage to be stored in a node FN. The configuration in FIG. 9A can be used for the memory cell MC in FIG. 1A.
A memory cell MC_B illustrated in FIG. 9B includes a transistor 15_A, the transistor OM, and the capacitor 17. The transistor 15_A is an n-channel transistor. Turning off the transistor OM allows a charge depending on the data voltage to be stored in a node FN. The configuration in FIG. 9B can be used for the memory cell MC in FIG. 1A.
A memory cell MC_C illustrated in FIG. 9C includes the transistor 15, a transistor OM_B, and the capacitor 17. The transistor OM_B includes a back gate that can be controlled by a wiring BGL. This configuration enables control of the threshold voltage of the transistor OM_B. Turning off the transistor OM_B allows a charge depending on the data voltage to be stored in the node FN. The configuration in FIG. 9C can be used for the memory cell MC in FIG. 1A.
A memory cell MC_D illustrated in FIG. 9D includes the transistor 15_A, the transistor OM, the capacitor 17, and a transistor 18_A. The transistor 18_A is an n-channel transistor like the transistor 15_A. Turning off the transistor OM allows a charge depending on the data voltage to be stored in the node FN. The configuration in FIG. 9D can be used for the memory cell MC in FIG. 1A. Note that the position of the transistor 18_A may be changed as in the circuit diagram illustrated in FIG. 28A.
A memory cell MC_E illustrated in FIG. 9E includes the transistor 15, the transistor OM, the capacitor 17, and a transistor 18_B. The transistor 18_B and the transistor 15 are p-channel transistors. Turning off the transistor OM allows a charge depending on the data voltage to be stored in the node FN. The configuration in FIG. 9E can be used for the memory cell MC in FIG. 1A. Note that the position of the transistor 18_B may be changed as in the circuit diagram of a memory cell MC_K illustrated in FIG. 28B.
A memory cell MC_F illustrated in FIG. 9F includes the transistor 15, the transistor OM, and the capacitor 17. The transistor 15 is connected to a wiring BL_A, and the transistor OM is connected to a wiring BL_B. In the configuration illustrated in FIG. 9F, for example, a wiring RWL can be used to read out a data voltage, and the wiring WBL can be used to write a data voltage. Turning off the transistor OM allows a charge depending on the data voltage to be stored in the node FN. The configuration in FIG. 9F can be used for the memory cell MC in FIG. 1A. Note that the transistor 18_B may be additionally provided as in the circuit diagram of a memory cell MC_L illustrated in FIG. 28C.
<Example of Block Diagram Including Memory Cell MC>
FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device using the memory cell MC_A in FIG. 9A as the memory cell MC illustrated in FIG. 1A.
A semiconductor device 200 illustrated in FIG. 10 includes a memory cell array 201 provided with a plurality of memory cells MC, the output circuit 100, a row selection driver 202, and a column selection driver 203. Note that in the semiconductor device 200, the memory cells MC are arranged in a matrix of m rows and n columns. In addition, in FIG. 10, a wiring WWL[m−1] and a wiring RWL[m−1] in an (m−1)-th row, a wiring WWL[m] and a wiring RWL[m] in an m-th row, a wiring BL[n−1] and a wiring SL[n−1] in an (n−1)-th column, and a wiring BL[n] and a wiring SL[n] in an n-th column are illustrated as wirings WWL, wirings RWL, wirings BL, and wirings SL.
In the memory cell array 201 illustrated in FIG. 10, the memory cells MC are arranged in a matrix. Note that for components of the memory cell MC, the description of those in FIG. 9A can be referred to.
Note that in the memory cell array 201 illustrated in FIG. 10, the output circuit 100 is provided between the row selection driver 202 for outputting a write word signal and each of the wiring WWL[m−1] and the wiring WWL[m]. Such a configuration enables supply of a signal output from the output circuit 100 to a gate of the transistor OM included in the memory cell MC.
The row selection driver 202 is a circuit that outputs a signal for selecting the memory cell MC in each row. The column selection driver 203 is a circuit that outputs a signal for writing a data voltage to the memory cell MC and reading out the data voltage from the memory cell MC. The row selection driver 202 and the column selection driver 203 include circuits such as a decoder and can output a signal or a data voltage to each row and each column.
<Modification Examples of Memory Cell MC>
FIGS. 11A to 11C illustrate circuit configuration examples different from those in FIGS. 9A to 9F that the memory cell MC illustrated in FIG. 1A can have.
A memory cell MC_G illustrated in FIG. 11A includes the transistor OM and a capacitor 19. The memory cell MC_G controls the voltage of the wiring WWL so that a data voltage is written from the wiring BL to the node FN and the data voltage is read out from the node FN to the wiring BL. Turning off the transistor OM allows a charge depending on the data voltage to be stored in the node FN. The configuration in FIG. 11A can be used for the memory cell MC in FIG. 1A.
A memory cell MC_H illustrated in FIG. 11B includes an SRAM, a transistor OM1, a transistor OM2, a capacitor 19_1, and a capacitor 19_2. The SRAM includes transistors SW1 and SW2 and inverter circuits INV1 and INV2. The memory cell MC_H controls the voltage of the wiring WWL so that the data voltages of the nodes Q and QB of the SRAM are backed up in nodes FN1 and FN2 and the data voltages are recovered from the nodes FN1 and FN2 to the nodes Q and QB. Turning off the transistors OM1 and OM2 allows charges depending on the data voltages to be stored in the nodes FN1 and FN2. The configuration in FIG. 11B can be used for the memory cell MC in FIG. 1A.
A memory cell MC_I illustrated in FIG. 11C includes an SRAM, a transistor OM3, an inverter circuit INV3, a capacitor 19_3, and a transistor SW3. The memory cell MC_I controls the voltages of the wiring WWL and a wiring REN so that the data voltages of the nodes Q and QB of the SRAM are backed up in a node FN3 and the data voltages are recovered from the node FN3 to the nodes Q and QB. Turning off the transistor OM3 allows a charge depending on the data voltage to be stored in the node FN3. The configuration in FIG. 11C can be used for the memory cell MC in FIG. 1A.
As described above, any of a variety of modification examples can be employed as one embodiment of the present invention and operated.
Embodiment 3
In this embodiment, the OS transistor described in the above embodiment will be described.
<Off-State Current Characteristics>
The off-state current of an OS transistor can be reduced by reducing the concentration of impurities in an oxide semiconductor to make the oxide semiconductor intrinsic or substantially intrinsic. The term “substantially intrinsic” refers to a state where an oxide semiconductor has a carrier density lower than 8×1011/cm3, preferably lower than 1×1011/cm3, more preferably lower than 1×1010/cm3, and is higher than or equal to 1×109/cm3. In the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than main components are impurities. For example, hydrogen and nitrogen form donor levels to increase the carrier density.
A transistor using an intrinsic or substantially intrinsic oxide semiconductor has a low carrier density and thus is less likely to have negative threshold voltage. Moreover, because of few carrier traps in the oxide semiconductor, the transistor using the oxide semiconductor has small variations in electrical characteristics and high reliability. Furthermore, the transistor using the oxide semiconductor has an ultra-low off-state current.
Note that the OS transistor with a reduced off-state current can exhibit a normalized off-state current per micrometer of channel width of 1×10−18 A or less, preferably 1×10−21 A or less, more preferably 1×10−24 A or less at room temperature (approximately 25° C.), or 1×10−15 A or less, preferably 1×10−18 A or less, more preferably 1×10−21 A or less at 85° C.
<Off-State Current>
Unless otherwise specified, an off-state current in this specification refers to a drain current of a transistor in the off state (also referred to as a non-conduction state and a cutoff state). Unless otherwise specified, the off state of an n-channel transistor means that the voltage between its gate and source (Vgs: gate-source voltage) is lower than the threshold voltage Vth, and the off state of a p-channel transistor means that the gate-source voltage Vgs is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current that flows when the gate-source voltage Vgs is lower than the threshold voltage Vth.
The off-state current of a transistor depends on Vgs in some cases. For this reason, when there is Vgs at which the off-state current of a transistor is lower than or equal to I, it may be said that the off-state current of the transistor is lower than or equal to I. The off-state current of a transistor may refer to an off-state current at given Vgs, at Vgs in a given range, or at Vgs at which sufficiently low off-state current is obtained.
As an example, the assumption is made of an n-channel transistor where the threshold voltage Vth is 0.5 V and the drain current is 1×10−9 A at a voltage Vgs of 0.5 V, 1×10−13 A at a voltage Vgs of 0.1 V, 1×10−19 A at a voltage Vgs of −0.5 V, and 1×10−22 A at a voltage Vgs of −0.8 V. The drain current of the transistor is 1×10−19 A or lower at a voltage Vgs of −0.5 V or at a voltage Vgs in the range of −0.8 V to −0.5 V; therefore, it may be said that the off-state current of the transistor is 1×10−19 A or lower. Since there is Vgs at which the drain current of the transistor is 1×10−22 A or lower, it may be said that the off-state current of the transistor is 1×10−22 A or lower.
In this specification, the off-state current of a transistor with a channel width W is sometimes represented by a current value in relation to the channel width W or by a current value per given channel width (e.g., 1 μm). In the latter case, the off-state current may be represented with a unit meaning current per length (e.g., A/μm).
The off-state current of a transistor depends on temperature in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-state current may be an off-state current at a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.). When there is Vgs at which the off-state current of a transistor at room temperature, 60° C., 85° C., 95° C., 125° C., a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured, or a temperature at which the semiconductor device or the like is used (e.g., temperature in the range of 5° C. to 35° C.) is lower than or equal to I, it may be said that the off-state current of the transistor is lower than or equal to I.
The off-state current of a transistor depends on the voltage Vds between its drain and source in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current might be an off-state current at Vds at which the reliability of a semiconductor device or the like including the transistor is ensured or Vds used in the semiconductor device or the like including the transistor. When there is Vgs at which the off-state current of a transistor is lower than or equal to I at given Vds, it may be said that the off-state current of the transistor is lower than or equal to I. Here, given Vds is, for example, 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, 20 V, Vds at which the reliability of a semiconductor device or the like including the transistor is ensured, or Vds used in the semiconductor device or the like.
In the above description of off-state current, a drain may be replaced with a source. That is, the off-state current sometimes refers to a current that flows through a source of a transistor in the off state.
In this specification, the term “leakage current” sometimes expresses the same meaning as an off-state current.
In this specification, the off-state current sometimes refers to a current that flows between a source and a drain when a transistor is off, for example.
<Composition of Oxide Semiconductor>
An oxide semiconductor used for the semiconductor layer of the OS transistor preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably contained. A stabilizer for strongly bonding oxygen is preferably contained in addition to In and Zn. As a stabilizer, at least one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al) may be contained.
As another stabilizer, one or more kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may be contained.
The oxide semiconductor layer used for the OS transistor can be formed using, for example, any of the following oxides: indium oxide, tin oxide, zinc oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—Zr—Zn-based oxide, an In—Ti—Zn-based oxide, an In—Sc—Zn-based oxide, an In—Y—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, an In—Lu—Zn-based oxide, an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, and an In—Hf—Al—Zn-based oxide.
For example, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, or In:Ga:Zn=2:1:3, or an oxide with an atomic ratio close to the above atomic ratios can be used.
<Impurities in Oxide Semiconductor>
If an oxide semiconductor film used for a semiconductor layer contains a large amount of hydrogen, the hydrogen and the oxide semiconductor are bonded to each other, so that part of the hydrogen serves as a donor and causes generation of an electron that is a carrier. As a result, the threshold voltage of the transistor shifts in the negative direction. It is therefore preferred that after formation of the oxide semiconductor film, dehydration treatment (dehydrogenation treatment) be performed to remove hydrogen or moisture from the oxide semiconductor film so that the oxide semiconductor film is highly purified to contain impurities as little as possible.
Note that oxygen in the oxide semiconductor film is also reduced by the dehydration treatment (dehydrogenation treatment) in some cases. Therefore, it is preferred that oxygen be added to the oxide semiconductor film to fill oxygen vacancies increased by the dehydration treatment (dehydrogenation treatment).
In this manner, hydrogen or moisture is removed from the oxide semiconductor film by the dehydration treatment (dehydrogenation treatment) and oxygen vacancies therein are filled by the oxygen adding treatment, whereby the oxide semiconductor film can be turned into an i-type (intrinsic) oxide semiconductor film or a substantially i-type (intrinsic) oxide semiconductor film that is extremely close to an i-type oxide semiconductor film. Note that “substantially intrinsic” means that the oxide semiconductor film contains extremely few (close to zero) carriers derived from a donor and has a carrier density of lower than 8×1011/cm3, preferably lower than 1×1011/cm3, more preferably lower than 1×1010/cm3 and higher than or equal to 1×10−9/cm3.
<Structure of Oxide Semiconductor>
Next, the structure of an oxide semiconductor will be described.
In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, the term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. In addition, the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.
In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.
An oxide semiconductor film is classified into a single crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. Alternatively, an oxide semiconductor is classified into a crystalline oxide semiconductor and an amorphous oxide semiconductor, for example.
Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. Examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and a microcrystalline oxide semiconductor.
First, a CAAC-OS film will be described.
A CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.
In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS film, which is obtained using a transmission electron microscope (TEM), a plurality of crystal parts can be observed. However, in the high-resolution TEM image, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.
According to the high-resolution cross-sectional TEM image of the CAAC-OS film observed in the direction substantially parallel to the sample surface, metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer reflects unevenness of a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or the top surface of the CAAC-OS film, and is arranged parallel to the formation surface or the top surface of the CAAC-OS film.
On the other hand, according to the plan high-resolution TEM image of the CAAC-OS film observed in the direction substantially perpendicular to the sample surface, metal atoms are arranged in a triangular or hexagonal arrangement in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.
For example, when the structure of a CAAC-OS including an InGaZnO4 crystal is analyzed by an out-of-plane method using an X-ray diffraction (XRD) apparatus, a peak may appear at a diffraction angle (2θ) of around 31°. This peak is derived from the (009) plane of the InGaZnO4 crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in the direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film.
Note that in analysis of the CAAC-OS film by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 2θ of around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°.
The CAAC-OS film is an oxide semiconductor film with low impurity concentration. The impurity is an element other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor film extracts oxygen from the oxide semiconductor film, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor film. Furthermore, a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor film and causes a decrease in crystallinity when it is contained in the oxide semiconductor film. Note that the impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source.
The CAAC-OS film is an oxide semiconductor having a low density of defect states. In some cases, oxygen vacancies in the oxide semiconductor film serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein, for example.
The state in which impurity concentration is low and density of defect states is low (the number of oxygen vacancies is small) is referred to as a “highly purified intrinsic” or “substantially highly purified intrinsic” state. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Accordingly, the transistor including the oxide semiconductor film has little variation in electrical characteristics and high reliability. Electric charge trapped by the carrier traps in the oxide semiconductor film takes a long time to be released and might behave like fixed electric charge. Thus, the transistor including the oxide semiconductor film having high impurity concentration and a high density of defect states has unstable electrical characteristics in some cases.
With the use of the CAAC-OS film in a transistor, variation in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light is small.
Next, a microcrystalline oxide semiconductor will be described.
A microcrystalline oxide semiconductor film has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the microcrystalline oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. An oxide semiconductor film including a nanocrystal that is a microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm is specifically referred to as a nanocrystalline oxide semiconductor (nc-OS) film. In a high-resolution TEM image of the nc-OS film, for example, a grain boundary is not clearly observed in some cases.
In the nc-OS film, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different crystal parts in the nc-OS film. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film, depending on an analysis method. For example, when the nc-OS film is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than the size of a crystal part, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS film is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a crystal part (the electron diffraction is also referred to as selected-area electron diffraction). Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS film when an electron beam having a probe diameter close to or smaller than the size of a crystal part is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS film, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS film, a plurality of spots is shown in a ring-like region in some cases.
The nc-OS film is an oxide semiconductor film that has high regularity as compared with an amorphous oxide semiconductor film. Therefore, the nc-OS film is likely to have a lower density of defect states than an amorphous oxide semiconductor film. Note that there is no regularity of crystal orientation between different crystal parts in the nc-OS film. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.
Next, an amorphous oxide semiconductor film will be described.
The amorphous oxide semiconductor film is an oxide semiconductor film having disordered atomic arrangement and no crystal part and exemplified by an oxide semiconductor film that exists in an amorphous state, such as quartz.
In a high-resolution TEM image of the amorphous oxide semiconductor film, crystal parts cannot be found.
When the amorphous oxide semiconductor film is subjected to structural analysis by an out-of-plane method with an XRD apparatus, a peak that shows a crystal plane does not appear. A halo pattern is observed when the amorphous oxide semiconductor film is subjected to electron diffraction. Furthermore, a spot is not observed and a halo pattern appears when the amorphous oxide semiconductor film is subjected to nanobeam electron diffraction.
Note that an oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. The oxide semiconductor film having such a structure is specifically referred to as an amorphous-like oxide semiconductor (a-like OS) film.
In a high-resolution TEM image of the a-like OS film, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed. The growth of the crystal part occurs due to the crystallization of the a-like OS film, which is induced by a slight amount of electron beam employed in the TEM observation. In contrast, in the nc-OS film that have good quality, crystallization hardly occurs by a slight amount of electron beam used for TEM observation.
Note that the crystal part size in the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, an InGaZnO4 crystal has a layered structure in which two Ga—Zn—O layers are included between In—O layers. A unit cell of the InGaZnO4 crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Accordingly, the distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Thus, focusing on lattice fringes in the high-resolution TEM image, each of lattice fringes in which the lattice spacing therebetween is greater than or equal to 0.28 nm and less than or equal to 0.30 nm corresponds to the a-b plane of the InGaZnO4 crystal.
Furthermore, the density of an oxide semiconductor film depends on the structure in some cases. For example, when the composition of an oxide semiconductor film is determined, the structure of the oxide semiconductor film can be expected by comparing the density of the oxide semiconductor film with the density of a single crystal oxide semiconductor film having the same composition as the oxide semiconductor film. For example, the density of the a-like OS film is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor film having the same composition. For example, the density of each of the nc-OS film and the CAAC-OS film is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor film having the same composition. Note that it is difficult to deposit an oxide semiconductor film having a density of lower than 78% of the density of the single crystal oxide semiconductor film.
Specific examples of the above description will be given. For example, in the case of an oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS film is higher than or equal to 5.0 g/cm3 and lower than 5.9 g/cm3. For example, in the case of the oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS film and the CAAC-OS film is higher than or equal to 5.9 g/cm3 and lower than 6.3 g/cm3.
Note that there is a possibility that an oxide semiconductor film having a certain composition cannot exist in a single crystal structure. In that case, single crystal oxide semiconductor films with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor film with the desired composition. The density of a single crystal oxide semiconductor film having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductor films with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductor films as possible to calculate the density.
Note that an oxide semiconductor film may be a stack including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.
As described above, the OS transistor has extremely favorable off-state current characteristics.
Embodiment 4
In this embodiment, examples of a schematic diagram of the output circuit described in the above embodiment, layout diagrams illustrating layers thereof, a layout diagram thereof, and a schematic cross-sectional view that corresponds to the layout diagram thereof will be described with reference to FIG. 12, FIGS. 13A to 13D, FIG. 14, and FIG. 15.
FIG. 12 is a schematic diagram of the level shifter circuit LS of the output circuit. A layer 301 including a Si transistor, a wiring layer 302, a layer 303 including a capacitor are illustrated in FIG. 12. The layer 301 and the layer 303 are connected to each other through conductive layers that are provided in openings and the wiring layer 302. As illustrated in FIG. 12, the layer 301, the wiring layer 302, and the layer 303 can be provided so as to overlap with one another. Thus, such a level shifter LS has the advantage: additionally providing a capacitor to prevent data loss due to malfunction of a semiconductor device does not increase the layout area.
FIGS. 13A to 13D illustrate layers in the layout in FIG. 12. FIG. 13A illustrates the positions of conductive layers and openings in a layer including the capacitors C1 and C2. FIG. 13B illustrates the positions of conductive layers and openings in a wiring layer under the layer illustrated in FIG. 13A. FIG. 13C illustrates the positions of conductive layers and openings in a wiring layer under the layer illustrated in FIG. 13B. FIG. 13D illustrates the positions of conductive layers and semiconductor layers included in the transistors M1 to M6, conductive layers corresponding to the wiring VH2 and the ground line, and openings in a layer under the layer illustrated in FIG. 13C. Furthermore, FIG. 13D illustrates terminals IN and INB and nodes OUT and OUTB.
FIG. 14 is a schematic cross-sectional view along dashed-dotted line X1-X2 in FIGS. 13A to 13D. FIG. 15 is a schematic view along dashed-dotted line Y1-Y2 in FIGS. 13A to 13D.
FIG. 14 and FIG. 15 illustrate a substrate 21, an impurity region 23, an impurity region 24, an insulating layer 25, an insulating layer 27, a conductive layer 29, an insulating layer 31, an insulating layer 33, an insulating layer 35, an insulating layer 37, a conductive layer 39, a conductive layer 41, a conductive layer 43, an insulating layer 45, and a conductive layer 47.
The substrate 21 can be, for example, a single crystal silicon substrate (a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate containing silicon carbide or gallium nitride, a silicon on insulator (SOI) substrate, or a glass substrate.
The impurity regions 23 and 24 are regions formed in the semiconductor layer. The semiconductor layer can be formed using an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, or the like. For example, amorphous silicon or microcrystalline germanium can be used. Alternatively, a compound semiconductor such as silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used. FIG. 14 and FIG. 15 illustrate the transistors M3 and M4 having different polarities. In this case, the n-channel transistor and the p-channel transistor are separately formed by introducing different impurities into the impurity regions 23 and 24.
A metal material such as aluminum, copper, titanium, tantalum, or tungsten is preferably used for each of the conductive layers 29, 39, 41, 43, and 47. Alternatively, polycrystalline silicon to which an impurity such as phosphorus is added can be used. As the formation method, any of a variety of film formation methods such as an evaporation method, a PE-CVD method, a sputtering method, and a spin coating method can be used.
Each of the insulating layers 25, 27, 31, 33, 35, 37, and 45 is preferably a single layer or a multilayer including an inorganic insulating layer or an organic insulating layer. The inorganic insulating layer is preferably a single layer or a multilayer formed using a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or the like. The organic insulating layer is preferably a single layer or a multilayer formed using a polyimide, an acrylic resin, or the like. There is no particular limitation on a method for forming each of the insulating layers; for example, a sputtering method, an MBE method, a PE-CVD method, a pulse laser deposition method, or an ALD method can be employed as appropriate.
Note that the conductive layer 43 is preferably provided in the same layer as a gate electrode of an OS transistor in the case where the capacitors C1 and C2 and the OS transistor are formed in the same layer. In addition, the conductive layer 47 is preferably provided in the same layer as a source electrode or a drain electrode of the OS transistor in the case where the capacitors C1 and C2 and the OS transistor are formed in the same layer. Such a structure enables the use of an insulating layer that is the same as a gate insulating layer of the OS transistor as the insulating layer 45 provided between the conductive layers 43 and 47. The gate insulating layer is thinner than the interlayer insulating layer; thus, the capacitors C1 and C2 can have larger capacitances.
Embodiment 5
FIG. 16 is a block diagram of a wireless sensor including the memory cell to which a signal is output from the output circuit that is described in the above embodiments.
A wireless sensor 900 includes an antenna 901, a circuit portion 902, and a sensor 903. The circuit portion 902 has a function of processing a signal received by the antenna 901, a function of generating response data in accordance with the received signal, and a function of sending the response data from the antenna 901. The circuit portion 902 includes, for example, an input/output portion (IN/OUT) 910, an analog portion 920, a memory portion 930, a logic portion 940, and an AD converter 950.
<Input/Output Portion>
The input/output portion 910 includes a rectifier circuit 911, a limiter circuit 912, a demodulation circuit 913, and a modulation circuit 914. FIG. 17A is a circuit diagram illustrating a configuration example of the rectifier circuit 911 and the limiter circuit 912. FIG. 17B is a circuit diagram illustrating a configuration example of the demodulation circuit 913 and the modulation circuit 914.
The rectifier circuit 911 is a circuit that rectifies a signal (carrier wave ANT) input from the antenna 901 and generates a voltage VIN. The voltage VIN is output to the circuits in the analog portion 920.
The limiter circuit 912 is a protection circuit for preventing the voltage VIN from becoming high.
The demodulation circuit 913 is a circuit that demodulates the carrier wave ANT received by the antenna 901. The demodulation circuit 913 generates a demodulated signal DEMOD_OUT and outputs the signal to the analog portion 920.
The modulation circuit 914 is a circuit that modulates the response data (a digital signal) MOD_OUT output from the logic portion 940 and outputs the modulated data with the carrier wave ANT. The modulation method is, for example, the amplitude shift keying (ASK) method.
<Analog Portion>
The analog portion 920 includes a power supply circuit 921, an oscillator circuit 922, a voltage determination circuit 923, a reset circuit 924, and a buffer circuit 925.
FIG. 18A is a block diagram illustrating a configuration example of the power supply circuit 921. The power supply circuit 921 is a circuit that generates an operating voltage for the memory portion 930, the logic portion 940, and the AD converter 950. Here, the power supply circuit 921 generates two operating voltages (VDD and VDD_ADC) from the voltage VIN. The power supply circuit 921 includes a voltage generation circuit 961 that generates a bias voltage BIAS and a reference voltage REF from the voltage VIN, and voltage generation circuits 962 and 963 that generate the operating voltages from the voltage BIAS, the reference voltage REF, and the voltage VIN.
FIG. 18B is a circuit diagram illustrating a configuration example of the voltage generation circuit 961. FIG. 18C is a circuit diagram illustrating a configuration example of the voltage generation circuits 962 and 963.
The oscillator circuit 922 is a circuit that generates a reference clock signal (ORIGIN_CLK) from the voltage VDD generated by the power supply circuit 921. FIG. 19A illustrates a configuration example of the oscillator circuit 922, and FIG. 19B illustrates a configuration example of a voltage generation circuit 971 that generates bias voltages (BIASP, BIASN) of the oscillator circuit 922.
FIG. 20 is a circuit diagram illustrating a configuration example of the voltage determination circuit 923. The voltage determination circuit 923 determines whether the voltage VIN is higher or lower than a predetermined value and generates a digital signal corresponding to the determination result. This digital signal is used as a trigger signal for operating the logic portion 940. The voltages BIAS and REF input to a comparator of the voltage determination circuit 923 are input from the voltage generation circuit 961 of the power supply circuit 921. In the example of FIG. 20, the voltage determination circuit 923 includes the comparator. The comparator generates and outputs a signal VIN_SENSE.
The reset circuit 924 monitors the voltage generated by the power supply circuit 921 and generates a reset signal that resets the logic portion 940. FIG. 21 is a circuit diagram illustrating a configuration example of the reset circuit 924. In this example, the reset circuit 924 detects rising of the voltage VDD and generates a reset signal INI_RESET.
The buffer circuit 925 is a circuit that transmits the signal DEMOD_OUT demodulated in the demodulation circuit 913 to the logic portion 940. FIG. 22 is a circuit diagram illustrating a configuration example of the buffer circuit 925. In the buffer circuit 925, the signal DEMOD_OUT is converted into a signal DEMOD_SIG0 through an inverter in the second stage, and is input to the logic portion 940.
<Memory Portion>
The memory portion 930 includes a charge pump circuit 931 in addition to a memory cell. For the configuration of the memory cell, Embodiment 1 can be referred to.
The charge pump circuit 931 is a circuit that steps up the operating voltage VDD to generate a voltage required to operate the memory portion 930. FIG. 23 is a circuit diagram illustrating a configuration example of the charge pump circuit 931. In the charge pump circuit 931, the operating voltage VDD becomes a stepped-up voltage VMEM to be input to the memory circuit.
The voltage to be applied to the memory portion 930 is generated by the charge pump circuit 931, whereby the power consumption of the wireless sensor 900 can be reduced. The memory portion 930 operates at a higher voltage (2.5 V to 4 V) than other circuits. A configuration where the power supply circuit 921 generates a high voltage in advance and applies the voltage to the memory portion 930 can be used; however, this configuration increases power consumed in the power supply circuit 921, the oscillator circuit 922, or the voltage determination circuit and is not efficient. In contrast, in the configuration of FIG. 16, a low voltage (1.2 V) is generated by the power supply circuit 921 and stepped down or up by the charge pump circuit 931, which is immediately before the memory portion 930, to be used. Therefore, the power consumed by the wireless sensor 900 can be small, which is more efficient.
The output circuit described in Embodiment 1 is used in a driver circuit for driving the memory cell. Voltages are applied to the wiring VH1 and the wiring VH2 of the output circuit from the power supply circuit 921 and the charge pump circuit 931, respectively. The wireless sensor 900 generates a voltage in response to a wireless signal. Therefore, when the supply of a wireless signal is stopped, ground voltages are applied to the wirings VH1 and VH2. The wireless sensor is supplied with a wireless signal again and generates a voltage. Providing the output circuit can inhibit unintentional output of a high-level potential even when voltages are applied to the wirings VH1 and VH2, so that data loss from the memory cell can be prevented.
<Logic Portion>
FIG. 24 is a block diagram illustrating a configuration example of the logic portion 940. The logic portion 940 includes a CRC circuit 981, a decoder circuit 982, a controller 983, an output signal generation circuit 984, a selector circuit 985, a CRC register 986, and a clock generation circuit 987.
The decoder circuit 982 is a circuit that decodes the signal DEMOD_SIG0. The decoded signal is input to the controller 983 and the CRC circuit 981.
The CRC circuit 981 is a circuit that calculates a cyclic redundancy check (CRC) code from an input signal from the decoder circuit 982. The CRC code calculated by the CRC circuit 981 is output to the controller 983.
The controller 983 is a circuit that controls the entire logic portion 940.
The CRC register 986 is a register that functions as a CRC region for storing the CRC code.
The clock generation circuit 987 generates a clock signal used in the logic portion 940 from the signal ORIGIN_CLK.
The memory portion 930 and the CRC register 986 are accessed via the selector circuit 985. The controller 983 and the output signal generation circuit 984 output access request signals (Acc_Rq) to the selector circuit 985. The selector circuit 985 performs writing or reading of memory data (Mem_D) with respect to the memory portion 930 or the CRC register 986 in accordance with the access request signal.
<AD Converter>
The AD converter 950 converts a sensor signal SENSOR with an analog voltage output from the sensor 903 into a digital signal and outputs the signal.
The AD converter 950 has a function of converting the potential of a sensor signal SENSOR, which is an analog value, into a digital value and outputting the digital value to the outside. As the AD converter 950, a flash A/D converter, a successive approximation A/D converter, a multi-slope A/D converter, or a delta-sigma A/D converter can be used.
The wireless sensor described above can perform intermittent operation by receiving a wireless signal, without losing data stored in the memory portion 930.
Embodiment 6
Although the conductive layer and the semiconductor layer described in the above embodiments can be formed by a sputtering method, they may be formed by another method, for example, a thermal CVD method. Examples of a thermal CVD method include a metal organic chemical vapor deposition (MOCVD) method and an atomic layer deposition (ALD) method.
A thermal CVD method has an advantage that no defect due to plasma damage is generated because it does not utilize plasma for forming a film.
Deposition by a thermal CVD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, and a source gas and an oxidizer are supplied to the chamber at a time and react with each other in the vicinity of the substrate or over the substrate.
Deposition by an ALD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then the sequence of the gas introduction is repeated. For example, two or more kinds of source gases are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves). In such a case, a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced at the same time or after the first source gas is introduced such that the source gases are not mixed, and then a second source gas is introduced. Note that in the case where the first source gas and the inert gas are introduced at a time, the inert gas serves as a carrier gas, and the inert gas may also be introduced at the same time as the second source gas. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of the introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first single-atomic layer; then the second source gas is introduced to react with the first single-atomic layer; as a result, a second single-atomic layer is stacked over the first single-atomic layer, so that a thin film is formed. The sequence of the gas introduction is repeated more than once until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of the gas introduction; therefore, an ALD method makes it possible to accurately adjust a thickness and thus is suitable for manufacturing a minute FET.
The conductive film and the semiconductor film described in the above embodiments can be formed by a thermal CVD method such as a MOCVD method or an ALD method. For example, trimethylindium, trimethylgallium, and dimethylzinc are used to form an In—Ga—Zn—Ox film (X>0). Note that the chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Without limitation to the above combination, triethylgallium (chemical formula: Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula: Zn(C2H5)2) can be used instead of dimethylzinc.
For example, when a tungsten film is formed with a deposition apparatus using ALD, a WF6 gas and a B2H6 gas are sequentially introduced multiple times to form an initial tungsten film, and then a WF6 gas and an H2 gas are sequentially introduced multiple times, so that a tungsten film is formed. Note that a SiH4 gas may be used instead of a B2H6 gas.
In the case where an oxide semiconductor film, for example, an InGaZnOx film (X>0) is formed with a deposition apparatus employing an ALD method, an In(CH3)3 gas and an O3 gas are sequentially introduced more than once to form an InO2 layer, a Ga(CH3)3 gas and an O3 gas are sequentially introduced to form a GaO layer, and then a Zn(CH3)2 gas and an O3 gas are sequentially introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an InGaO2 layer, an InZnO2 layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing of these gases. Note that although an H2O gas that is obtained by bubbling with an inert gas such as Ar may be used instead of an O3 gas, it is preferable to use an O3 gas that does not contain H. Instead of an In(CH3)3 gas, an In(C2H5)3 gas may be used. Instead of a Ga(CH3)3 gas, a Ga(C2H5)3 gas may be used. Alternatively, a Zn(CH3)2 gas may be used.
Embodiment 7
In this embodiment, examples where the semiconductor devices described in the foregoing embodiment are used as an electronic component and an electronic device including the electronic component will be described with reference to FIGS. 25A and 25B and FIGS. 26A to 26E.
FIG. 25A shows an example where the semiconductor device described in the foregoing embodiment is used as an electronic component. Note that an electronic component is also referred to as semiconductor package or IC package. For the electronic component, there are various standards and names corresponding to the extraction direction of terminals or the shape of terminals; hence, one example of the electronic component will be described in this embodiment.
A semiconductor device including the transistors described in FIG. 12, FIGS. 13A to 13D, FIG. 14, and FIG. 15 in Embodiment 4 is completed by integrating detachable components on a printed circuit board through an assembly process (post-process).
The post-process can be completed through steps shown in FIG. 25A. Specifically, after an element substrate obtained in the preceding process is completed (Step S1), a back surface of the substrate is ground (Step S2). The substrate is thinned in this step to reduce warpage or the like of the substrate in the preceding process and to reduce the size of the component itself.
A dicing step of grinding the back surface of the substrate to separate the substrate into a plurality of chips is performed. Then, a die bonding step of individually picking up separate chips to be mounted on and bonded to a lead frame is performed (Step S3). To bond a chip and a lead frame in the die bonding step, resin bonding, tape-automated bonding, or the like is selected as appropriate depending on products. Note that in the die bonding step, a chip may be mounted on and bonded to an interposer.
Next, wire bonding for electrically connecting a lead of the lead frame and an electrode on a chip through a metal wire is performed (Step S4). As a metal wire, a silver wire or a gold wire can be used. For wire bonding, ball bonding or wedge bonding can be employed.
A wire-bonded chip is subjected to a molding step of sealing the chip with an epoxy resin or the like (Step S5). With the molding step, the inside of the electronic component is filled with a resin, leading to reduction of damage to the circuit portion and the wire embedded in the component that is caused by external mechanical force as well as reduction of deterioration of characteristics due to moisture or dust.
Subsequently, the lead of the lead frame is plated. Then, the lead is cut and processed into a predetermined shape (Step S6). With the plating process, corrosion of the lead can be prevented, and soldering for mounting the electronic component on a printed circuit board in a later step can be performed with higher reliability.
Next, printing process (marking) is performed on a surface of the package (Step S7). Then, through a final test step (Step S8), the electronic component is completed (Step S9).
The above-described electronic component can include the semiconductor device described in the above embodiment. This allows the electronic component to be less likely to malfunction and to have lower power consumption.
FIG. 25B is a schematic perspective diagram of a completed electronic component. FIG. 25B shows a schematic perspective diagram of a quad flat package (QFP) as an example of the electronic component. An electronic component 700 illustrated in FIG. 25B includes a lead 701 and a circuit portion 703. The electronic component 700 in FIG. 25B is, for example, mounted on a printed circuit board 702. A plurality of electronic components 700 are used in combination and electrically connected to each other over the printed circuit board 702; thus, the completed circuit board 704 can be provided in an electronic device or the like.
Next, descriptions will be given of applications of the above electronic component to electronic devices such as a computer, a portable information terminal (e.g., a mobile phone, a portable game machine, an audio reproducing device, and the like), electronic paper, a television device (also referred to as a television or a television receiver), and a digital video camera.
FIG. 26A illustrates a portable information terminal that includes a housing 801, a housing 802, a first display portion 803a, a second display portion 803b, and the like. The semiconductor device described in the above embodiment is provided inside at least part of the housings 801 and 802. This allows the portable information terminal to be less likely to malfunction and to have lower power consumption.
Note that the first display portion 803a is a touch panel, and for example, as illustrated in the left of FIG. 26A, which of “touch input” and “keyboard input” is performed can be selected by a selection button 804 displayed on the first display portion 803a. Since the selection buttons with a variety of sizes can be displayed, the portable information terminal can be easily used by people of any generation. For example, when “keyboard input” is selected, a keyboard 805 is displayed on the first display portion 803a as illustrated in the right of FIG. 26A. With such a structure, text can be input quickly by keyboard input as in the case of using a conventional information terminal, for example.
One of the first display portion 803a and the second display portion 803b can be detached from the portable information terminal as illustrated in the right of FIG. 26A. Providing the second display portion 803b with a touch input function makes the information terminal convenient to carry because the weight can be further reduced and to operate with one hand while the other hand supports the housing 802.
The portable information terminal illustrated in FIG. 26A has a function of displaying various kinds of data (e.g., a still image, a moving image, and a text image) on the display portion, a function of displaying a calendar, a date, the time, or the like on the display portion, a function of operating or editing the data displayed on the display portion, a function of controlling processing by various kinds of software (programs), and the like. Furthermore, an external connection terminal (an earphone terminal, a USB terminal, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing.
The portable information terminal illustrated in FIG. 26A may transmit and receive data wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an e-book server.
Further, the housing 802 illustrated in FIG. 26A may be equipped with an antenna, a microphone function, or a wireless communication function to be used as a mobile phone.
FIG. 26B illustrates an e-book reader 810 in which electronic paper is incorporated. The e-book reader includes two housings of a housing 811 and a housing 812. The housing 811 and the housing 812 are provided with a display portion 813 and a display portion 814, respectively. The housings 811 and 812 are connected by a hinge portion 815 and can be opened or closed with the hinge portion 815 as an axis. The housing 811 is provided with a power switch 816, an operation key 817, a speaker 818, and the like. At least one of the housing 811 and the housing 812 is provided with a semiconductor device including the PLD described in the above embodiment. This allows the electronic paper to be less likely to malfunction and to have lower power consumption.
FIG. 26C illustrates a television device including a housing 821, a display portion 822, a stand 823, and the like. The television device 820 can operate with a switch of the housing 821 and a remote controller 824. A semiconductor device including the PLD described in the above embodiment is provided in the housing 821 and the remote controller 824. This allows the television device to be less likely to malfunction and to have lower power consumption.
FIG. 26D illustrates a smartphone in which a main body 830 is provided with a display portion 831, a speaker 832, a microphone 833, operation keys 834, and the like. A semiconductor device including the PLD described in the above embodiment is provided in the main body 830. This allows the smartphone to be less likely to malfunction and to have lower power consumption.
FIG. 26E illustrates a digital camera including a main body 841, a display portion 842, an operation switch 843, and the like. A semiconductor device including the PLD described in the above embodiment is provided in the main body 841. This allows the digital camera to be less likely to malfunction and to have lower power consumption.
As described above, any of the semiconductor devices of the above embodiments is provided in the electronic devices described in this embodiment. This allows the electronic devices to be less likely to malfunction and to have lower power consumption.
(Notes on Description in this Specification and the Like)
The following are notes on the description of the above embodiments and the structures in the above embodiments.
<Notes on One Embodiment of the Present Invention Described in Embodiments>
One embodiment of the present invention can be constituted by appropriately combining the structure described in an embodiment with any of the structures described in the other embodiments. In addition, in the case where a plurality of structure examples are described in one embodiment, any of the structure examples can be combined as appropriate.
Note that a content (or part thereof) described in one embodiment can be applied to, combined with, or replaced with another content (or part thereof) described in the same embodiment and/or a content (or part thereof) described in another embodiment or other embodiments.
Note that in each embodiment, a content described in the embodiment is a content described with reference to a variety of diagrams or a content described with a text in this specification.
By combining a diagram (or part thereof) described in one embodiment with another part of the diagram, a different diagram (or part thereof) described in the embodiment, and/or a diagram (or part thereof) described in another embodiment or other embodiments, much more diagrams can be created.
This embodiment describes one embodiment of the present invention. Other embodiments of the present invention are described in the other embodiments. Note that one embodiment of the present invention is not limited to this. That is, various embodiments of the invention are described in this embodiment and the other embodiments, and one embodiment of the present invention is not limited to a particular embodiment. For example, an example in which a channel formation region, source and drain regions, and the like of a transistor such as the transistor OM include an oxide semiconductor is described as one embodiment of the present invention; however, one embodiment of the present invention is not limited to this example. Alternatively, depending on circumstances or conditions, various semiconductors may be included in various transistors, a channel formation region of a transistor, a source region or a drain region of a transistor, or the like of one embodiment of the present invention. Depending on circumstances or conditions, for example, at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, and the like may be included in various transistors, a channel formation region of a transistor, a source region or a drain region of a transistor, or the like of one embodiment of the present invention. Alternatively, depending on circumstances or conditions, an oxide semiconductor is not necessarily included in various transistors, a channel formation region of a transistor, a source region or a drain region of a transistor, or the like of one embodiment of the present invention, for example. Depending on the circumstances or conditions, the transistor such as the transistor OM, the channel formation region of the transistor, the source and drain regions of the transistor, and the like do not necessarily include an oxide semiconductor. The example in which one embodiment of the present invention is applied to a memory cell is described; however, one embodiment of the present invention is not limited thereto. For example, one embodiment of the present invention may be applied to a circuit with another function depending on circumstances or conditions. Furthermore, depending on circumstances or conditions, one embodiment of the present invention is not necessarily applied to a memory cell.
<Notes on Description for Drawings>
In this specification and the like, terms for describing arrangement, such as “over” and “under”, are used for convenience to indicate a positional relation between components with reference to drawings. The positional relation between components is changed as appropriate in accordance with the direction in which each component is described. Therefore, terms for describing arrangement are not limited to the terms used in the description in the specification, and can be appropriately reworded depending on situations.
The term “over” or “below” does not necessarily mean that a component is placed directly on or directly below and directly in contact with another component. For example, the expression “electrode B over insulating layer A” does not necessarily mean that the electrode B is on and in direct contact with the insulating layer A and can include the case where another component is provided between the insulating layer A and the electrode B.
In this specification and the like, components are classified on the basis of the functions, and shown as blocks independent of one another in block diagrams. However, in an actual circuit or the like, it may be difficult to separate components on the basis of the functions, so that one circuit may be associated with a plurality of functions and several circuits may be associated with one function. Therefore, the segmentation of a block in the block diagrams is not limited by any of the components described in the specification, and can be differently determined as appropriate depending on situations.
In the drawings, the size, the layer thickness, or the region has arbitrary magnitude for convenience for the description. Therefore, the scale is not necessarily limited to that illustrated in the drawings. Note that the drawings are schematically illustrated for clarity, and shapes or values are not limited to those illustrated in the drawings. For example, the following can be included: variation in signal, voltage, or current due to noise or difference in timing.
In drawings such as a top view (also referred to as a plan view or a layout view) and a perspective view, some of components might not be illustrated for clarity of the drawings.
<Notes on Expressions that can be Rephrased>
In this specification and the like, in description of connections of a transistor, description of “one of a source and a drain” (or a first electrode or a first terminal), and “the other of the source and the drain” (or a second electrode or a second terminal) are used. This is because a source and a drain of a transistor are interchangeable depending on the structure, operation conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (or drain) terminal, a source (or drain) electrode, or the like as appropriate depending on the situation.
In addition, in this specification and the like, the term such as an “electrode” or a “wiring” does not limit the function of a component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Further, the term “electrode” or “wiring” can also mean a combination of a plurality of “electrodes” or “wirings” formed in an integrated manner.
In this specification and the like, the terms “voltage” and “potential” are interchangeable in appropriate cases. The term “voltage” refers to a potential difference between a given potential and a reference potential. When the reference potential is a ground potential, the term “voltage” can be replaced with the term “potential”. The ground potential does not necessarily mean 0 V. Note that a potential is relative, and a potential supplied to wirings or the like may be changed depending on a reference potential.
In this specification and the like, the terms “film”, “layer”, and the like can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases.
<Notes on Definitions of Terms>
The following are definitions of the terms not described in the above embodiments.
<<Switch>>
In this specification and the like, a switch is an element that is brought into a conduction state or a non-conduction state (is turned on or off) to determine whether to have a current flow therethrough or not. Alternatively, the switch is an element having a function of selecting and changing a current path.
For example, an electrical switch, a mechanical switch, or the like can be used as a switch. That is, any element can be used as a switch as long as it can control a current, without limitation to a certain element.
A transistor (e.g., a bipolar transistor or a MOS transistor), a diode (e.g., a PN diode, a PIN diode, a Schottky diode, a metal-insulator-metal (MIM) diode, a metal-insulator-semiconductor (MIS) diode, or a diode-connected transistor), or a logic circuit in which such elements are combined can be used as an electrical switch.
When a transistor is used as a switch, an “on state” of the transistor refers to a state in which a source and a drain of the transistor are electrically short-circuited. Furthermore, an “off state” of the transistor refers to a state in which the source and drain of the transistor are electrically disconnected. Note that if the transistor operates just as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.
An example of a mechanical switch is a switch formed using a MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). Such a switch includes an electrode which can be moved mechanically, and operates by controlling conduction and non-conduction in accordance with movement of the electrode.
<<Channel Length>>
In this specification and the like, the channel length refers to, for example, a distance between a source and a drain in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate overlap with each other or a region where a channel is formed in a top view of the transistor.
In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
<<Channel Width>>
In this specification and the like, the channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate overlap with each other, or a region where a channel is formed.
In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel region formed in a side surface of a semiconductor is high in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view.
In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, estimation of an effective channel width from a design value requires an assumption that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.
Therefore, in this specification, in a top view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.
Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the values may be different from those calculated using an effective channel width in some cases.
<<Connection>>
In this specification and the like, when it is described that “A and B are connected to each other”, the case where A and B are electrically connected to each other is included in addition to the case where A and B are directly connected to each other. Here, the expression “A and B are electrically connected” means the case where electric signals can be transmitted and received between A and B when an object having any electric action exists between A and B.
Note that, for example, the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z1 and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to a part of Z1 and another part of Z1 is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to a part of Z2 and another part of Z2 is directly connected to Y, can be expressed by using any of the following expressions.
The expressions include, for example, “X, Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) of the transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, “a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided to be connected in this order”. When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.
Other examples of the expressions include, “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor, Z1 is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, and Z2 is on the third connection path”. Other examples of the expressions also include “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least Z1 on a first connection path, the first connection path does not include a second connection path, the second connection path includes a connection path through the transistor, a drain (or a second terminal or the like) of the transistor is electrically connected to Y through at least Z2 on a third connection path, and the third connection path does not include the second connection path”, and “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least Z1 on a first electrical path, the first electrical path does not include a second electrical path, the second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least Z2 on a third electrical path, the third electrical path does not include a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor”. When the connection path in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.
Note that these expressions are only examples and one embodiment of the present invention is not limited to the expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, and a layer).
[Example]
Calculation was performed on the configuration of a wireless sensor using the semiconductor device described in the above embodiment, especially, the configurations of a charge pump circuit and a memory portion. By the calculation, the state of a signal (external signal) input externally when application of a power supply voltage is resumed and a variation in an internal signal that varies in response to the external signal were estimated. Note that a circuit simulator, Smart Spice (manufactured by Silvaco Data Systems Inc.), was used for the calculation.
First, a block diagram of the charge pump circuit and the memory portion will be described. The wireless sensor has the same configuration as the wireless sensor 900 described in Embodiment 5 except for the charge pump circuit and the memory portion.
FIG. 30A is a block diagram of a charge pump circuit 931A and a memory portion 930. The memory portion 930 includes a memory cell array 932, a row driver 933, a column driver 934, a controller 935, and a decoder 936. The row driver 933 includes an output circuit 939 described in the above embodiment.
A power supply control signal (PE), a clock signal (CLK), and a first power supply voltage (VDD) are input to the charge pump circuit 931A. The charge pump circuit 931A outputs a second power supply voltage (VDD_OS) to the output circuit 939 of the row driver 933. The signals PE, VDD, and CLK are external signals.
VDD corresponds to the voltage VDD1 that is applied to the wiring VH1 described in Embodiment 1. VDD is generated based on an input signal received by an antenna of the wireless sensor. VDD_OS corresponds to the voltage VDD2 that is applied to the wiring VH2 described in Embodiment 1.
16-bit data (DATA), a 7-bit address signal (ADDRESS), a precharge control signal (PCE), an output control signal (OE), a write control signal (WE), a read control signal (RE), and a module control signal (CE) are input to the memory portion 930. The signals DATA, ADDRESS, PCE, OE, WE, RE, and CE are external signals.
FIG. 30B is a circuit diagram illustrating the configuration of the output circuit 939 in FIG. 30A. The output circuit 939 includes an AND gate corresponding to the buffer circuit BUF1, a level shifter circuit LS, and an inverter circuit corresponding to the buffer circuit BUF2.
The buffer circuit BUF1 is supplied with VDD, WE, and a selection signal (ADDRESS2) input to a row selected by ADDRESS. The level shifter circuit LS and the buffer circuit BUF2 are supplied with VDD_OS, and supply a signal to the wiring WWL.
FIG. 31A is a circuit diagram of the charge pump circuit 931A. The charge pump circuit 931A includes the charge pump circuit 931 described in Embodiment 5, a clock signal generation circuit 937, an inverter circuit 938A, and a transistor 938B.
The charge pump circuit 931 is supplied with VDD, and clock signals CLK1 and CLK2, and outputs stepped-up VDD_OS. The clock signals CLK1 and CLK2 are signals generated by CLK and PE so as not to overlap with each other. PE is input to a gate of the transistor 938B through the inverter circuit 938A.
FIG. 31B shows a timing chart of the charge pump circuit 931A. After the rise of VDD, PE is set at a high level, CLK oscillates, and VDD_OS rises.
FIG. 32A illustrates a decoder 936, which is a circuit that outputs signals of ADDRESS2 and WE2, and the charge pump circuit 931A, which supplies VDD_OS, in the circuit diagram illustrated in FIG. 30A.
FIGS. 32B1 to 32B4 show conditions for calculation; the conditions of the external signals are different.
FIG. 32B1 is a waveform chart showing that in a period in which VDD rises, PE and CLK, which are boosting control signals, are in an inactive (low-level) state, WE, CE, and the like (WE, CE, etc.), which are control signals for WWL, are in an inactive (low-level) state, and ADDRESS is “0” (at a low level).
FIG. 32B2 is a waveform chart showing that in a period in which VDD rises, PE and CLK, which are boosting control signals, are in an inactive (low-level) state, WE, CE, and the like (WE, CE, etc.), which are control signals for WWL, are placed in an active (high-level) state, and ADDRESS is “0” (at a low level).
FIG. 32B3 is a waveform chart showing that in a period in which VDD rises, PE and CLK, which are boosting control signals, are placed in an active (high-level or oscillating) state, WE, CE, and the like (WE, CE, etc.), which are control signals for WWL, are in an inactive (low-level) state, and ADDRESS is “0” (at a low level).
FIG. 32B4 is a waveform chart showing that in a period in which VDD rises, PE and CLK, which are boosting control signals, are placed in an active (high-level or oscillating) state, WE, CE, and the like (WE, CE, etc.), which are control signals for WWL, are placed in an active (high-level) state, and ADDRESS is “0” (at a low level).
FIG. 33 to FIG. 35 are waveform charts obtained by calculation of the external signals under the conditions that the length of a period in which VDD is increased from 0 V to 1.2 V is 1 μs, 100 μs, and 1 ms in the case of FIG. 32B1.
In the case of FIG. 33 where the length of the period in which VDD is increased from 0 V to 1.2 V is 1 μs, increases in ADDRESS2 and WE2 in the period in which VDD rises was lower than 100 mV. Furthermore, an increase in VDD_OS was as small as under 4 mV. Furthermore, increases in WWL(0) and WWL(1) were as small as under 2 mV.
In the case of FIG. 34 where the length of the period in which VDD is increased from 0 V to 1.2 V is 100 μs, increases in ADDRESS2 and WE2 in the period in which VDD rises was as small as under 50 mV. Furthermore, an increase in VDD_OS was as small as under 3 mV. Furthermore, increases in WWL(0) and WWL(1) were as small as under 1 mV.
In the case of FIG. 35 where the length of the period in which VDD is increased from 0 V to 1.2 V is 1 ms, increases in ADDRESS2 and WE2 in the period in which VDD rises were as small as under 30 mV. Furthermore, an increase in VDD_OS was as small as under 2 mV. Furthermore, increases in WWL(0) and WWL(1) were as small as under 1 mV.
Thus, the configuration including the semiconductor device of one embodiment of the present invention enabled WWL(0) and WWL(1) to be low such that no problem is caused, regardless of the length of the period in which VDD is increased.
FIG. 36 to FIG. 38 are waveform charts obtained by calculation of the external signals under the condition that the length of a period in which VDD was increased from 0 V to 1.2 V is 100 μs in the cases of FIGS. 32B2 to 32B4.
In the case of FIG. 32B2 where the length of the period in which VDD was increased from 0 V to 1.2 V is 100 μs, which is shown in FIG. 36, while VDD rose, ADDRESS2(0) and WE2 were increased from 0 V to 1.2 V, but an increase in ADDRESS2(1) was lower than 50 mV. Furthermore, an increase in VDD_OS was as small as under 3 mV. Furthermore, increases in WWL(0) and WWL(1) were as small as under 1 mV.
In the case of FIG. 32B3 where the length of the period in which VDD was increased from 0 V to 1.2 V is 100 μs, which is shown in FIG. 37, while CLK oscillated and VDD rose, ADDRESS2(0) and WE2 were increased from 0 V to 1.2 V, but an increase in ADDRESS2(1) was as small as under 40 mV. Furthermore, an increase in VDD_OS was as small as under 50 mV until 145 μs passed. Furthermore, increases in WWL(0) and WWL(1) were as small as under 20 mV.
In the case of FIG. 32B4 where the length of the period in which VDD was increased from 0 V to 1.2 V is 100 μs, which is shown in FIG. 38, while CLK oscillated and VDD rose, ADDRESS2(0) and WE2 were increased from 0 V to 1.2 V, but an increase in ADDRESS2(1) was as small as under 40 mV. Furthermore, an increase in VDD_OS was as small as under 50 mV until 145 μs passed. Furthermore, an increase in WWL(0) was as small as under 50 mV and an increase in WWL(1) was as small as under 20 mV.
Thus, the configuration including the semiconductor device of one embodiment of the present invention enabled WWL(0) and WWL(1) to be low such that no problem is caused, until the charge pump circuit operated and VDD_OS rose, in all the cases of FIGS. 32B1 to 32B4.
The calculation results described in this example indicate that unexpected rise of WWL was suppressed regardless of the conditions of the external signals.
This application is based on Japanese Patent Application serial no. 2014-254393 filed with Japan Patent Office on Dec. 16, 2014, the entire contents of which are hereby incorporated by reference.

## Claims

1. A semiconductor device comprising:
a first wiring configured to supply a first potential;
a second wiring configured to supply a second potential, the second potential being higher than the first potential;
a third wiring configured to supply a third potential, the third potential being lower than the first potential and the second potential;
a first buffer circuit electrically connected to the first wiring and the third wiring; and
a level shifter circuit electrically connected to the second wiring and the third wiring, the level shifter circuit comprising a first node, a second node, a first capacitor, a second capacitor, a first transistor and a second transistor,
wherein the first node is configured to hold the second potential when a low-level potential is output from the level shifter circuit,
wherein the second node is configured to hold the third potential when the low-level potential is output from the level shifter circuit,
wherein a first electrode of the first capacitor and one of a source and a drain of the first transistor are electrically connected to the second wiring,
wherein a second electrode of the first capacitor and a gate of the first transistor are electrically connected to the first node,
wherein a first electrode of the second capacitor and one of a source and a drain of the second transistor are electrically connected to the third wiring,
wherein a second electrode of the second capacitor and the other of the source and the drain of the second transistor are electrically connected to the second node, and
wherein the first capacitor and the second capacitor are provided over the first transistor and the second transistor with an insulating layer and a wiring therebetween.

2. The semiconductor device according to claim 1, wherein the third potential is a ground potential.

3. The semiconductor device according to claim 1, wherein a channel formation region of each of the first transistor and the second transistor comprises silicon.

4. The semiconductor device according to claim 1, further comprising a memory cell,
wherein a channel formation region of a transistor of the memory cell comprises an oxide semiconductor, and
wherein the oxide semiconductor comprise indium.

5. The semiconductor device according to claim 1, further comprising a memory cell,
wherein a gate of a transistor of the memory cell is electrically connected to the level shifter circuit.

6. The semiconductor device according to claim 1, further comprising a memory cell,
wherein the memory cell comprises a third capacitor,
wherein a first electrode of the third capacitor is provided in the same layer as the first electrode of the first capacitor and the first electrode of the second capacitor, and
wherein a second electrode of the third capacitor is provided in the same layer as the second electrode of the first capacitor and the second electrode of the second capacitor.

7. An electronic device comprising the semiconductor device according to claim 1.

8. The semiconductor device according to claim 1, further comprising a second buffer circuit electrically connected to the second wiring, the third wiring, and the level shifter circuit.

9. The semiconductor device according to claim 1,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor, and
wherein a gate of the second transistor is electrically connected to the first buffer circuit.

10. The semiconductor device according to claim 1,
wherein the level shifter circuit further comprises a fourth transistor and a fifth transistor,
wherein a gate of the fourth transistor is electrically connected to the second node,
wherein a gate of the fifth transistor is electrically connected to the first buffer circuit,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor, and
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring.

11. A semiconductor device comprising:
a first wiring configured to supply a first potential;
a second wiring configured to supply a second potential, the second potential being higher than the first potential;
a third wiring configured to supply a third potential, the third potential being lower than the first potential and the second potential;
a first buffer circuit electrically connected to the first wiring and the third wiring; and
a level shifter circuit electrically connected to the second wiring and the third wiring, the level shifter circuit comprising a first node, a second node, a first capacitor, a second capacitor, a first transistor, a second transistor, and a third transistor,
wherein the first node is configured to hold the second potential when a low-level potential is output from the level shifter circuit,
wherein the second node is configured to hold the third potential when the low-level potential is output from the level shifter circuit,
wherein a first electrode of the first capacitor and one of a source and a drain of the first transistor are electrically connected to the second wiring,
wherein a second electrode of the first capacitor and a gate of the first transistor are electrically connected to the first node,
wherein a first electrode of the second capacitor and one of a source and a drain of the second transistor are electrically connected to the third wiring,
wherein a second electrode of the second capacitor and the other of the source and the drain of the second transistor are electrically connected to the second node, and
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the first capacitor and the second capacitor are provided over the first transistor, the second transistor, and the third transistor with an insulating layer and a wiring therebetween.

12. The semiconductor device according to claim 11, wherein the third potential is a ground potential.

13. The semiconductor device according to claim 11, wherein a channel formation region of each of the first transistor and the second transistor comprises silicon.

14. The semiconductor device according to claim 11, further comprising a memory cell,
wherein a channel formation region of a transistor of the memory cell comprises an oxide semiconductor, and
wherein the oxide semiconductor comprise indium.

15. The semiconductor device according to claim 11, further comprising a memory cell,
wherein a gate of a transistor of the memory cell is electrically connected to the level shifter circuit.

16. The semiconductor device according to claim 11, further comprising a memory cell,
wherein the memory cell comprises a third capacitor,
wherein a first electrode of the third capacitor is provided in the same layer as the first electrode of the first capacitor and the first electrode of the second capacitor, and
wherein a second electrode of the third capacitor is provided in the same layer as the second electrode of the first capacitor and the second electrode of the second capacitor.

17. An electronic device comprising the semiconductor device according to claim 11.

18. The semiconductor device according to claim 11, further comprising a second buffer circuit electrically connected to the second wiring, the third wiring, and the level shifter circuit.

19. The semiconductor device according to claim 11,
wherein a gate of the second transistor and a gate of the third transistor are electrically connected to the first buffer circuit.

20. The semiconductor device according to claim 11,
wherein the level shifter circuit further comprises a fourth transistor, a fifth transistor, and a sixth transistor,
wherein a gate of the fourth transistor is electrically connected to the second node,
wherein a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the first buffer circuit,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the fifth transistor, and
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring.