# Patent

## Title
Display driver

## Abstract

A display driver is provided which can prevent concentration of currents flowing into a display device and display a high-quality image without uneven luminance. A plurality of delayed clock signals used to apply a plurality of pixel driving voltages to data lines of the display device at respective different timings are generated by a DLL circuit including a variable delay circuit group constituted by variable delay circuits are connected in series, and a phase comparator that detects a phase difference of a delayed clock signal with respect to a reference clock signal and adjusts a delay amount of each of the variable delay circuits so that the phase difference converges to zero.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display driver for driving the display device according to a video signal.
2. Description of the Related Art
A liquid crystal display panel, an example of a display device, includes a plurality of gate lines extending in a horizontal direction of a two-dimensional screen and a plurality of source lines extending in a vertical direction of the two-dimensional screen. The gate lines and the source lines are arranged to intersect each other. A display cell taking charge of a pixel is formed at the intersection between each gate line and each source line. The liquid crystal display panel includes a source driver for applying gradation display voltages corresponding to the luminance levels of pixels expressed by an input video signal to the respective source lines, and a gate driver for applying a scan signal to the gate lines. As a source driver like this, one configured to individually take in a plurality of pieces of display data for a horizontal synchronizing period into a plurality of latches and apply the gradation display voltages corresponding to the pieces of display data taken into the respective latches to the source lines has been proposed (for example, see Japanese Patent Application Laid-Open No. 2004-301946). Such a source driver shifts the take-in timing of the display data by each of the foregoing latches by using delay circuits using element delays of inverter elements, whereby concentration of currents flowing into the source lines is prevented to prevent noise occurring in such a state.
With the delay circuits using the element delays of the inverter elements described above, the delay mounts vary due to manufacturing variations, ambient temperature, etc. The timing at which the gradation display voltages are applied to the display cells via the source lines therefore may fail to coincide with the timing at which the scan signal is applied to the display cells via the gate lines, possibly producing uneven luminance within the display screen.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a display driver which can prevent concentration of currents flowing into the display device and display a high-quality image without uneven luminance.
A display driver according to the present invention is a display driver which drives a display device by applying K (K is an integer greater than or equal to 2) pixel driving voltages corresponding to pixel-by-pixel luminance levels indicated by an image data signal to K data lines of the display device, respectively, the display driver including: a delayed clock generation part configured to generate first to t-th (t is an integer less than or equal to K and greater than or equal to 2) delayed clock signals having phases different from each other and being synchronized with a reference clock signal; an output enable signal generation part configured to generate first to K-th output enable signals on the basis of the first to t-th delayed clock signals; and an output part configured to apply the K pixel driving voltages to the K data lines at respective different timings on the basis of the first to K-th output enable signals, wherein: the delayed clock generation part includes a phase comparator and a variable delay circuit group constituted by first to (t+1)-th variable delay circuits each having a basic delay time which is one (t+1)-th of a period of the reference clock signal are connected in series with each other; the reference clock signal is supplied to the first variable delay circuit; outputs of the first to t-th variable delay circuits in the variable delay circuit group serve as the first to t-th delayed clock signals respectively; and the phase comparator adjusts a delay time of each of the first to t-th variable delay circuits in the variable delay circuit group on the basis of a phase difference between a signal output from the (t+1)-th variable delay circuit and the reference clock signal.
A display driver according to the present invention is a display driver including: a first driver for applying first to K-th (K is n/2 and n is an integer greater than or equal to 2) pixel driving voltages among the first to an n-th pixel driving voltages corresponding to pixel-by-pixel luminance levels indicated by an image data signal to first to K-th data lines of the display device, respectively; and a second driver for applying a (K+1)-th to the n-th pixel driving voltages among the first to n-th pixel driving voltages to (K+1)-th to n-th data lines of the display device, respectively, wherein: the first and second drivers each include a delayed clock generation part configured to generate first to t-th (t is an integer less than or equal to K and greater than or equal to 2) delayed clock signals having phases different from each other and being synchronized with a reference clock signal; an output enable signal generation part configured to generate first to K-th output enable signals on the basis of the first to t-th delayed clock signals; and an output part configured to apply the K pixel driving voltages to the K data lines at respective different timings on the basis of the first to K-th output enable signals, wherein: the delayed clock generation part includes a phase comparator and a variable delay circuit group constituted by first to (t+1)-th variable delay circuits each having a basic delay time which is one (t+1)-th of a period of the reference clock signal are connected in series with each other; the reference clock signal is supplied to the first variable delay circuit; outputs of the first to t-th variable delay circuits in the variable delay circuit group serve as the first to t-th delayed clock signals respectively; and the phase comparator adjusts a delay time of each of the first to t-th variable delay circuits in the variable delay circuit group on the basis of a phase difference between a signal output from the (t+1)-th variable delay circuit and the reference clock signal.
According to the present invention, the timing at which to apply the plurality of pixel driving voltages to the respective data lines of the display device are forcedly made different. This prevents currents flowing into the data lines from concentrating at the same point in time.
Moreover, in the present invention, the plurality of delayed clock signals used to apply the plurality of pixel driving voltages at respective different timings are generated by a DLL circuit that includes the variable delay circuit group in which the variable delay circuits are connected in series and the phase comparator. Such a DLL circuit adjusts the delay amount of each of the variable delay circuits so that a phase difference of each delayed clock signal with respect to the reference clock signal converges to zero. As a result, the timing at which to apply the pixel driving voltages to the data lines can be matched with timing at which a horizontal scan pulse is applied to display cells via a horizontal scan line, regardless of manufacturing variations or ambient temperature. A high-quality image without uneven luminance can thus be displayed.
Consequently, according to the present invention, noise occurring from the concentration of currents flowing into the display device can be suppressed, and a high-quality image without uneven luminance can be displayed regardless of manufacturing variations or ambient temperature.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a display apparatus including a display driver according to the present invention;
FIG. 2 is a block diagram showing an example of an internal configuration of a driver IC 3a; 
FIG. 3 is a block diagram showing an example of an internal configuration of an output delay control part 134;
FIG. 4 is a time chart showing delayed clock signals CL1 to CL(t+1);
FIG. 5 is a circuit diagram showing an internal configuration of a delayed clock generation part 1341;
FIGS. 6A and 6B are diagrams showing an operation of a clock selector 1342;
FIG. 7 is a circuit diagram showing an internal configuration of an output enable signal generation part 1344;
FIG. 8 is a diagram showing a state of shift direction changeover switches SW1 to SWK in an L shift mode;
FIG. 9 is a time chart showing output enable signals EN1 to ENK in the L shift mode;
FIG. 10 is a diagram showing the state of the shift direction changeover switches SW1 to SWK in an R shift mode;
FIG. 11 is a time chart showing the output enable signals EN1 to ENK in the R shift mode;
FIG. 12 is a circuit diagram showing part of an internal configuration of an output part 136; and
FIGS. 13A to 13C are diagrams showing a pattern of output delays in respective delay modes (L shift mode, R shift mode, and V shift mode).



DETAILED DESCRIPTION OF THE EMBODIMENTS
An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a diagram showing a schematic configuration of a display apparatus including a display driver according to the present invention. As shown in FIG. 1, such the display apparatus includes a drive control part 1, scan drivers 2A and 2B, a data driver 3, and a display device 20.
For example, the display device 20 includes a liquid crystal or organic EL panel. The display device 20 includes m (m is a natural number greater than or equal to 2) horizontal scan lines S1 to Sm each extending in a horizontal direction of a two-dimensional screen and n (n is a natural number greater than or equal to 2) data lines D1 to Dn each extending in a vertical direction of the two-dimensional screen. Display cells taking charge of pixels are formed at the intersections of the horizontal scan lines and the data lines.
The drive control part 1 extracts a horizontal synchronizing signal from a video signal and supplies the horizontal synchronizing signal to the scan drivers 2A and 2B as a horizontal synchronizing signal HS. The drive control part 1 also generates an output start signal OS for instructing a start of output of pixel driving voltages and supplies the output start signal OS to the data driver 3 in synchronization with the horizontal synchronizing signal HS. On the basis of the video signal, the drive control part 1 further generates a series of pixel data PD expressing a luminance level of each pixel, for example, in eight bits pixel by pixel. The drive control part 1 supplies the data driver 3 with a pixel data signal PDS that is obtained by superposing clock information RS expressing clock timing on the series of pixel data PD. The drive control part 1 supplies the data driver 3 with an initial setting signal ISS for making an initial setting of each driver IC (to be described later) formed in the data driver 3. For example, the initial setting signal ISS includes output start delay information LI and delay mode information DM. The output start delay information LI specifies an output start delay time from when the foregoing output start signal OS is supplied to when the pixel driving voltages starts actually being output. The delay mode information DM specifies a delay mode (to be described later).
The scan driver 2A is connected to one end of each of the horizontal scan lines S1 to Sm. The scan driver 2B is connected to the other end of each of the horizontal scan lines S1 to Sm. The scan drivers 2A and 2B generate a horizontal scan pulse SP in synchronization with the foregoing horizontal synchronizing signal HS, and apply the horizontal scan pulse SP to each of the horizontal scan lines S1 to Sm of the display device 20 in succession.
The data driver 3 takes in the series of pixel data PD in the pixel data signal PDS. Each time the data driver 3 takes in pixel data PD as much as one horizontal scan line, i.e., n pieces of pixel data PD (n is the total number of data lines), the data driver 3 converts the taken-in n pieces of pixel data PD into pixel driving voltages G1 to Gn having a voltage value corresponding to the respective luminance values to indicate. The data driver 3 applies the pixel driving voltages G1 to Gn to the data lines D1 to Dn of the display device 20 in a delay pattern according to the delay mode specified by the delay mode information DM included in the foregoing initial setting signal ISS.
The data driver 3 includes a plurality of semiconductor integrated circuit (IC) chips having the same circuit configuration. For example, in the embodiment shown in FIG. 1, the data driver 3 includes two driver ICs 3a and 3b which are respective independent semiconductor IC chips.
The driver IC 3a takes in K pieces of pixel data PD corresponding to the first to K-th columns (K=n/2) of the display device 20 from among the n pieces of pixel data PD for one horizontal scan line. The driver IC 3a applies the pixel driving voltages G1 to GK corresponding to the luminance levels indicated by the respective pieces of pixel data PD to the data lines D1 to DK of the display device 20.
The driver IC 3b takes in K pieces of pixel data PD corresponding to the (K+1)-th to n-th columns of the display device 20 from among the n pieces of pixel data PD for one horizontal scan line. The driver IC 3b applies the pixel driving voltages GK+1 to Gn corresponding to the luminance levels indicated by the respective pieces of pixel data PD to the data lines DK+1 to Dn of the display device 20.
As shown in FIG. 1, the driver IC 3a in charge of driving the left area of the screen of the display device 20 and the driver IC 3b in charge of driving the right area of the screen of the display device 20 are arranged along one side of the display device 20.
The driver ICs 3a and 3b include the same circuits. Hereinafter, the configuration formed in each driver IC will be described by extracting the driver IC 3a. 
FIG. 2 is a block diagram showing the circuits formed in the driver IC 3a. As shown in FIG. 2, each driver IC includes a reception part 131, a first data latch part 132, a second data latch part 133, an output delay control part 134, a gradation voltage conversion part 135, and an output part 136.
The reception part 131 takes in a series of pixel data PD from the pixel data signal PDS supplied from the drive control part 1, and supplies K pieces of pixel data P1 to PK to the first data latch part 132 from among the (n pieces of) pixel data PD for one horizontal scan line.
A reference clock generation part 131a arranged in the reception part 131 extracts the clock information RS from the pixel data signal PDS to generate a reference clock signal CK which is synchronized in phase with clock timing indicated by the clock information RS. The reception part 131 supplies the reference clock signal CK to the first data latch part 132, the second data latch part 133, and the output delay control part 134.
The first data latch part 132 takes in the pieces of pixel data P1 to PK supplied from the reception part 131 at timing based on the reference clock signal CK in succession. The first data latch part 132 supplies the pieces of pixel data P1 to PK to the second data latch part 133 as pieces of pixel data R1 to RK, respectively.
The second data latch part 133 takes in the pieces of pixel data R1 to RK supplied from the first data latch part 132 at timing based on the reference clock signal CK. The second data latch part 133 supplies the pieces of pixel data R1 to RK to the gradation voltage conversion part 135 as pieces of pixel data Y1 to YK, respectively.
The gradation voltage conversion part 135 converts the pieces of pixel data Y1 to YK into analog pixel driving voltages V1 to VK having a voltage value corresponding to the respective luminance levels, and supplies the pixel driving voltages V1 to VK to the output part 136.
The output delay control part 134 performs initial setting according to the initial setting signal ISS supplied from the drive control part 1. In the delay mode based on the initial setting, the output delay control part 134 generates K output enable signals EN1 to ENK according to the output start signal OS. The output enable signals EN1 to ENK differ from each other in start timing of an edge.
FIG. 3 is a block diagram showing an example of an internal configuration of the output delay control part 134. As shown in FIG. 3, the output delay control part 134 includes a delayed clock generation part 1341, a clock selector 1342, a delay mode setting part 1343, and an output enable signal generation part 1344.
As shown in FIG. 4, the delayed clock generation part 1341 generates (t+1) number of delayed clock signals CL1 to CL(t+1) (t is a natural number greater than or equal to 2 and less than or equal to K) of which respective front edges have different timing, i.e., different phases based on the reference clock signal CK.
FIG. 5 is a block diagram showing an example of an internal configuration of the delayed clock generation part 1341. For example, as shown in FIG. 5, the delayed clock generation part 1341 includes a delay-locked loop (DLL) circuit that includes (t+1) pieces of variable delay circuits CD1 to CD(t+1) connected in series and a phase comparator PF. For example, as shown in FIG. 5, the variable delay circuits CD1 to CD(t+1) each include a pair of variable delay inverters V1 and V2 connected in series.
The variable delay circuits CD1 to CD(t+1) are each designed to have a basic delay time DLY which is equal to one (t+1)-th of a period TW of the reference clock signal CK shown in FIG. 4. The delay time of each of the variable delay circuits CD1 to CD(t+1) is adjusted according to a delay adjustment signal CTRL to be described later.
The variable delay circuit CD1 delays the reference clock signal CK by the basic delay time DLY to generate a delayed clock signal CL1, and supplies the delayed clock signal CL1 to the variable delay circuit CD2. The variable delay circuit CD2 delays the delayed clock signal CL1 by the basic delay time DLY to generate a delayed clock signal CL2, and supplies the delayed clock signal CL2 to the variable delay circuit CD3. Similarly, the variable delay circuit CDX (X is a natural number of 3 to t) delays a delayed clock signal CL(X−1) supplied from the variable delay circuit CD(X−1) as a previous stage by the basic delay time DLY to generate a delayed clock signal CLX, and supplies the delayed clock signal CLX to the variable delay circuit CD(X+1) as a subsequent stage. The variable delay circuits CD3 to CDt generate and supply delayed clock signals CL2 to CLt to the variable delay circuits CD as the respective subsequent stages.
The variable delay circuit CD(t+1) as a final stage delays the delayed clock signal CLt by the basic delay time DLY to generate a delayed clock signal CL(t+1), and supplies the delayed clock signal CL(t+1) to the phase comparator PF. As shown in FIG. 4, if the actual delay times of the respective variable delay circuits CD1 to CD(t+1) are equal to the basic delay time DLY, the delayed clock signal CL(t+1) has the same phase as that of the reference clock signal CK.
The phase comparator PF compares the phases of the reference clock signal CK and the delayed clock signal CL(t+1), and generates the delay adjustment signal CTRL which indicates the phase difference therebetween. The phase comparator PF supplies the delay adjustment signal CTRL to each of the variable delay circuits CD1 to CD(t+1). As a result, the variable delay circuits CD1 to CD(t+1) each adjust their own delay time at the current point in time in a leading direction or a lagging direction as much as the phase difference indicated by the delay adjustment signal CTRL.
In short, the delayed clock generation part 1341 generates the delayed clock signals CLh (h is an integer of 1 to (t+1)) of which the respective front edges lag behind a front edge of the reference clock signal CK by h·DLY, i.e., the delayed clock signals CL1 to CL(t+1) shown in FIG. 4 in synchronization with the reference clock signal CK. In the delayed clock generation part 1341, the delay time of each of the delayed clock signals CL1 to CL(t+1) is adjusted by the delay adjustment signal CTRL generated by the phase comparator PF to be constantly equal to the basic delay time DLY regardless of manufacturing variations and ambient temperature.
The delayed clock generation part 1341 supplies the clock selector 1342 with the delayed clock signals CL1 to CLt among the delayed clock signals CL1 to CL(t+1) generated as described above.
The clock selector 1342 sends out the delayed clock signals CL1 to CLt to respective corresponding clock lines LL according to a correspondence relationship between each of the delayed clock signals CL1 to CLt and each of the clock lines LL1 to LLt based on the delay mode information DM included in the initial setting signal ISS. The delay mode information DM specifies any one of an L shift mode (first shift mode), an R shift mode (second shift mode), and a V shift mode (third shift mode).
More specifically, if the delay mode information DM indicates the L shift mode, the clock selector 1342 sends out the delayed clock signals CL1 to CLt to the clock lines LL1 to LLt according to a one-to-one correspondence relationship shown in FIG. 6A. If the delay mode information DM indicates the R shift mode, the clock selector 1342 sends out the delayed clock signals CLt to CL1 to the clock lines LL1 to LLt according to a one-to-one correspondence relationship shown in FIG. 6B. If the delay mode information DM indicates the V shift mode, the clock selector 1342 of the driver IC 3a sends out the delayed clock signals CL1 to CLt to the clock lines LL1 to LLt according to the one-to-one correspondence relationship shown in FIG. 6A. The clock selector 1342 of the driver IC 3b sends out the delayed clock signals CLt to CL1 to the clock lines LL1 to LLt according to the one-to-one correspondence relationship shown in FIG. 6B.
The clock selector 1342 does not necessarily need to send out all the delayed clock signals CL1 to CLt to the clock lines LL1 to LLt. For example, the clock selector 1342 may send out odd-numbered (or even-numbered) delayed clock signals CL among the delayed clock signals CL1 to CLt to the clock lines LL1 to LLt according to a one-to-two correspondence relationship. In essence, the clock selector 1342 may send out a specific plurality of delayed clock signals CL among the delayed clock signals CL1 to CLt to the clock lines LL1 to LLt.
The delay mode setting part 1343 shown in FIG. 3 initially stores the output start delay information LI and the delay mode information DM indicated by the initial setting signal ISS supplied from the drive control part 1 into a built-in register (not shown).
If the delay mode specified by the delay mode information DM is the L shift mode, the delay mode setting part 1343 supplies a switch signal C1 having a logical level of 0 to the output enable signal generation part 1344. If the delay mode is the R shift mode, the delay mode setting part 1343 outputs the switch signal C1 having a logical level of 1 to the output enable signal generation part 1344.
If the delay mode is the V shift mode, the delay mode setting part 1343 of the driver IC 3a supplies the switch signal C1 having a logical level of 0 to the output enable signal generation part 1344 as with the case where the delay mode is the L shift mode. If the delay mode is the V shift mode, the delay mode setting part 1343 of the driver IC 3b supplies the switch signal C1 having a logical level of 1 to the output enable signal generation part 1344 as with the case where the delay mode is the R shift mode.
The delay mode setting part 1343 generates an output start signal OP which transitions from a state of having a logical level of 0 (or 1) to a state of having a logical level of 1 (or 0) at a point in time when the output start delay time indicated by the output start delay information LI has elapsed since the reception of the output start signal OS transmitted from the drive control part 1. The delay mode setting part 1343 supplies the output start signal OP to the output enable signal generation part 1344.
The output enable signal generation part 1344 includes a shift register including K pieces of D flip-flops DF1 to DFK which take in and supply the output start signal OP to the D flip-flops as the subsequent stages or the previous stages.
A configuration of the output enable signal generation part 1344 serving as the shift register mentioned above will be described below by using a case where K is twice the number of clock lines LL1 to LLt, i.e., 2·t as an example. As shown in FIG. 3, the clock terminals of the D flip-flops DF1 to DFK/2 among the D flip-flops DF1 to DFK are connected to the clock lines LL1 to LLt, respectively. The clock terminals of the D flip-flops DF(K/2)+1 to DFK among the D flip-flops DF1 to DFK are connected to the clock lines LL1 to LLt, respectively.
As shown in FIG. 7, aside from the D flip-flops DF1 to DFK, the output enable signal generation part 1344 includes shift direction changeover switches SW1 to SWK for switching a shift direction.
In FIG. 7, the D flip-flops DF1 to DFK are connected in series via the shift direction changeover switches SW arranged at the respective previous stages. The outputs of the D flip-flops DF1 to DFK serve as the output enable signals EN1 to ENK, respectively.
The shift direction changeover switch SW1 selects either one of the output start signal OP and the output enable signal EN2 output from the D flip-flop DF2 according to the switch signal C1, and supplies the selected signal to the D flip-flop DF1. The shift direction changeover switch SWr (r is a natural number of 2 to (K−1)) selects either one of the output enable signal ENr−1 output from the D flip-flop DFr−1 and the output enable signal ENr+1 output from the D flip-flop DFr+1 according to the switch signal C1, and supplies the selected signal to the D flip-flop DFr. The shift direction changeover switch SWK selects either one of the output start signal OP and the output enable signal ENK−1 output from the D flip-flop DFK−1 according to the switch signal C1, and supplies the selected signal to the D flip-flop DFK.
Specifically, if the delay mode specified by the delay mode information DM is the L shift mode, as shown in FIG. 8, the shift direction changeover switch SW1 selects and supplies the output start signal OP to the D flip-flop DF1 according to the switch signal C1 having a logical level of 0. In the L shift mode, as shown in FIG. 8, the shift direction changeover switch SWS (S is an natural number of 2 to K) selects and supplies the output enable signal ENS−1 output from the D flip-flop DFS−1 to the D flip-flop DFS.
As a result, in the L shift mode, the output start signal OP is initially taken into the D flip-flop DF1 in synchronization with the delayed clock signal CL1 shown in FIG. 4. The output start signal OP is subsequently shifted to and taken into the D flip-flops DF in order of DF2, DF3, . . . , DFK−1, and DFK in synchronization with the delayed clock signals CL2 to CLt, respectively. In the L shift mode, the D flip-flops DF1 to DFK thus generate the output enable signals ENh (h is an integer of 1 to (t+1)), of which the respective front edges lag behind the front edge of the output start signal OP by h·DLY, according to the output start signal OP. That is, the D flip-flops DF1 to DFK generate the output enable signals EN1 to ENK shown in FIG. 9.
If the delay mode is the R shift mode, as shown in FIG. 10, the shift direction changeover switch SWK selects and supplies the output start signal OP to the D flip-flop DFK according to the switch signal C1 having a logical level of 1. In the R shift mode, the shift direction changeover switch SWJ (J is a natural number of 1 to (K−1)) selects and supplies the output enable signal ENJ+1 output from the D flip-flop DFJ+1 to the D flip-flop DFJ.
As a result, in the R shift mode, the output start signal OP is initially taken into the D flip-flop DFK in synchronization with the delayed clock signal CL1 shown in FIG. 4. The output start signal OP is subsequently shifted to and taken into the D flip-flops DF in order of DFK−1, DFK−2, . . . , DF2, and DF1 in synchronization with the delayed clock signals CL2 to CLt, respectively. In the R shift mode, the D flip-flops DF1 to DFK thus generate the output enable signals ENh (h is an integer of 1 to (t+1)), of which the respective front edges lag behind the front edge of the output start signal OP by (K−h+1)·DLY, according to the output start signal OP. That is, the D flip-flops DF1 to DFK generate the output enable signals EN1 to ENK shown in FIG. 11.
If the delay mode is the V shift mode, the output enable signal generation part 1344 of the driver IC 3a performs the operation of the L shift mode described above to generate the output enable signals EN1 to ENK shown in FIG. 9. Moreover, in the V shift mode, the output enable signal generation part 1344 of the driver IC 3b performs the operation of the R shift mode described above to generate the output enable signals EN′ to ENK shown in FIG. 11.
With the configuration described above, the output delay control part 134 generates the output enable signals EN1 to ENK shown in FIG. 9 or 11, of which the respective front edges lag behind the front edge of the output start signal OP by h·DLY (h is an integer of 1 to (t+1)), according to the delay mode indicated by the initial setting signal ISS. The output delay control part 134 supplies the output enable signals EN1 to ENK to the output part 136.
As shown in FIG. 12, the output part 136 includes transistors Q1 to QK serving as transmission gates. The pixel driving voltage V1 to VK supplied from the gradation voltage conversion part 135 are supplied to the source terminals of the transistors Q1 to QK, respectively. The drain terminals of the transistors Q1 to QK are connected to K pieces of data lines D of the display device 20, respectively.
The output enable signals EN1 to ENK are independently supplied to the gate terminals of the transistors Q1 to QK, respectively. The transistors Q1 to QK are independently controlled on/off based on the output enable signals EN1 to ENK, respectively. More specifically, if the output enable signal ENj (j is a natural number of 1 to K) indicates a logical level of 0, the transistor Qj turns off. If the output enable signal ENj indicates a logical level of 1, the transistor Qj turns on, whereby the pixel driving voltage V is applied to the data line Dj of the display device 20 as the pixel driving voltage Gj.
An operation of the data driver 3 including the driver ICs 3a and 3b having the foregoing configuration will be described below with respect to each of the following L shift mode, R shift mode, and V shift mode.
[L Shift Mode]
In the L shift mode, the drive control part 1 supplies the driver ICs 3a and 3b with the initial setting signal ISS that includes the delay mode information DM specifying the L shift mode. Here, the drive control part 1 supplies the driver IC 3a with the initial setting signal ISS that includes the output start delay information LI indicating an output delay time of 0. The drive control part 1 supplies the driver IC 3b with the initial setting signal ISS that includes the output start delay information LI indicating an output delay time of T1. For example, the output delay time T1 is the time from when the output start signal OS is supplied to when the last pixel driving voltage G to be applied to the driver IC 3a starts to be applied.
Consequently, in the L shift mode, as shown in FIG. 13A, the driver IC 3a first applies the pixel driving voltages G1 to GK of which the application timing is delayed in order of G1, G2, G3, . . . , GK to the data lines D1, D2, D3, . . . , DK of the display device 20 in succession. After the output delay time T1 has elapsed since the supply of the output start signal OS, the driver IC 3b applies the pixel driving voltages GK+1 to Gn of which the application timing is delayed in order of GK+1, GK+2, GK+3, . . . , Gn to the data lines DK+1, DK+2, DK+3, . . . , Dn of the display device 20 in succession.
[R Shift Mode]
In the R shift mode, the drive control part 1 supplies the driver ICs 3a and 3b with the initial setting signal ISS that includes the delay mode information DM specifying the R shift mode. Here, the drive control part 1 supplies the driver IC 3a with the initial setting signal ISS that includes the output start delay information LI indicating an output delay time of T1. The drive control part 1 supplies the driver IC 3b with the initial setting signal ISS that includes the output start delay information LI indicating an output delay time of 0. For example, the output delay time T1 is the time from when the output start signal OS is supplied to when the last pixel driving voltage G to be applied to the driver IC 3b starts to be applied.
Consequently, in the R shift mode, as shown in FIG. 13B, the driver IC 3b first applies the pixel driving voltage Gn to GK+1 of which the application timing is delayed in order of Gn, Gn-1, Gn-2, . . . , GK+1 to the data lines Dn, Dn-1, Dn-2, . . . , DK+1 of the display device 20 in succession. After the output delay time T1 has elapsed since the supply of the output start signal OS, the driver IC 3a applies the pixel driving voltages GK to G1 of which the application timing is delayed in order of GK, GK−1 GK−2, . . . , G1 to the data lines DK, DK−1, DK−2, . . . , D1 of the display device in succession.
[V Shift Mode]
In the V shift mode, the drive control part 1 supplies the driver IC 3a with the initial setting signal ISS that includes the delay mode information DM specifying the L shift mode and the output start delay information LI indicating an output delay time of 0. The drive control part 1 supplies the driver IC 3b with the initial setting signal ISS that includes the delay mode information DM specifying the R shift mode and the output start delay information LI indicating an output delay time of 0.
As a result, in the V shift mode, as shown in FIG. 13C, the driver IC 3a applies the pixel driving voltages G1 to GK of which the application timing is delayed in order of G1, G2, G3, . . . , GK to the data lines D1, D2, D3, . . . , DK of the display device 20 in succession. In parallel with such an operation of the driver IC 3a, as shown in FIG. 13C, the driver IC 3b applies the pixel driving voltages Gn to GK+1 of which the application timing is delayed in order of Gn, Gn-1, Gn-2, . . . , GK+1 to the data lines Dn, Dn-1, Dn-2, . . . , DK+1 of the display device 20 in succession.
Here, the display cells belonging to the horizontal scan line S to which the horizontal scan pulse SP is applied among the horizontal scan lines S1 to Sm of the display device 20 perform display with luminances corresponding to the pixel driving voltages G applied to the respective data lines D1 to Dn.
As described above, the data driver 3 forcedly shifts the timing at which to apply the pixel driving voltages G to the respective data lines D as shown in FIG. 13A, 13B, or 13C. This can prevent the currents flowing into the data lines from concentrating at the same point in time. As a result, noise occurring in such a state can be suppressed.
If the display device 20 has a large screen size, the horizontal scan lines S extending in the horizontal direction of the two-dimensional screen, in particular, increase in wiring resistance. To reduce the load of the scan driver due to the wiring resistance, the display apparatus shown in FIG. 1 includes the scan drivers (2A and 2B) arranged at both ends of the horizontal scan lines S. On each of the horizontal scan lines S1 to Sm, the delay amount of the horizontal scan pulse SP due to the wiring resistance increases as the position gets farther from both the scan drivers 2A and 2B, i.e., as the position approaches the screen center. If the scan drivers 2A and 2B apply the horizontal scan pulse SP to a horizontal scan line S, the horizontal scan pulse SP reaches the intersection with the data line Dn/2 (or D(n/2)+1) belonging to the screen center area with a delay with respect to the horizontal scan pulse SP arising at the intersection with the data line D1 (or Dn) belonging to the left (or right) end area of the screen.
According to the V shift mode, the closer the data lines D are located to the screen center, the more the application timing of the pixel driving voltages G can be delayed to follow the delay time which is a time period for the horizontal scan pulse SP to reach each data line D. As a result, the application timing of the horizontal scan pulse SP and that of the pixel driving voltages G can be matched with each other.
To shift the output timing of the pixel driving voltages G1 to Gn to the display device 20 as shown in FIGS. 13A to 13C, the output delay control part 134 shown in FIG. 3 is configured to generate the delayed clock signals CL1 to CLt having phases different from each other by the delayed clock generation part 1341. In the delayed clock generation part 1341, the variable delay circuits CD1 to CD(t+1) for delaying a signal by using their element delay (basic delay time DLY) are connected in series as shown in FIG. 5. The reference clock signal CK is supplied to the variable delay circuit CD′ as a first stage. Consequently, as shown in FIG. 4, the delayed clock signals CL1 to CL(t+1) of which the respective front edges lag behind the front edge of the reference clock signal CK by h·DLY (h is an integer of 1 to (t+1)) are obtained as the outputs of the respective variable delay circuits CD1 to CD(t+1).
The relationship of the basic delay time DLY to the period TW of the reference clock signal CK is given by:

TW=(t+1)·DLY. 

If the actual delay amount of each of the variable delay circuits CD1 to CD(t+1) is equal to the basic delay time DLY, the design value, then the phase of the delayed clock signal CL(t+1) coincides with that of the reference clock signal CK. However, the element delay amounts of the variable delay circuits CD1 to CD(t+1) vary due to manufacturing variations, ambient temperature, etc.
The delayed clock generation part 1341 then detects a phase difference between the phase of the reference clock signal CK and that of the delayed clock signal CL(t+1) by using the phase comparator PF. On the basis of the delay adjustment signal CTRL indicating the phase difference, the delayed clock generation part 1341 adjusts the delay amount of each of the variable delay circuits CD1 to CD(t+1) so that the phase difference converges to zero.
Consequently, according to the output delay control part 134 including the delayed clock generation part 1341, the element delay amounts of the variable delay circuits CD1 to CD(t+1) can always be maintained to the constant basic delay time DLY even if the element delay amounts vary due to manufacturing variations, ambient temperature, etc.
In such a manner, the application timing of the pixel driving voltages to the data lines can be matched with the application timing of the horizontal scan pulse to the display cells via the horizontal scan lines regardless of manufacturing variations or ambient temperature. As a result, a high-quality image without uneven luminance can be displayed.
As described above, the driver ICs 3a and 3b included in the data driver 3 each include the following a delayed clock generation part (1341), an output enable signal generation part (1344) and an output part (136). The delayed clock generation part generates first to t-th delayed clock signals (CL1 to CLt) having phases different from each other on the basis of the reference clock signal (CK). The output enable signal generation part generates first to K-th output enable signals (EN1 to ENK) on the basis of the first to t-th delayed clock signals. The output part apply K pixel driving voltages (G1 to GK) to the K data lines at respective different timings on the basis of the first to K-th output enable signals. The delayed clock generation part includes a phase comparator (PF) and a variable delay circuit group constituted by first to (t+1)-th variable delay circuits (CD1 to CDt+1) each having a basic delay time (DLY) which is one (t+1)-th of a period (TW) of the reference clock signal are connected in series with each other. The reference clock signal is supplied to the variable delay circuit (CD1) as the first stage in the variable delay circuit group. The outputs of the respective variable delay circuits (CD1 to CDt) as first to t-th stages in the variable delay circuit group serve as the first to t-th delayed clock signals. The phase comparator then adjusts the delay time of each of the variable delay circuits in the variable delay circuit group on the basis of a phase difference between the signal (CLt+1) output from the variable delay circuit (CDt+1) as a (t+1)-th stage and the reference clock signal.
With such a configuration, noise occurring from the concentration of currents flowing into the display device can be suppressed, and a high-quality image without uneven luminance can be displayed regardless of manufacturing variations or ambient temperature.
This application is based on Japanese Patent Application No. 2014-171670 which is herein incorporated by reference.

## Claims

1. A display driver which drives a display device, by applying K (K is an integer greater than or equal to 2) pixel driving voltages corresponding to pixel-by-pixel luminance levels indicated by an image data signal to K data lines of said display device, respectively, said driver comprising:
a delayed clock generation part configured to generate first to t-th (t is an integer less than or equal to K and greater than or equal to 2) delayed clock signals having phases different from each other and being synchronized with a reference clock signal;
an output enable signal generation part configured to generate first to K-th output enable signals on the basis of said first to t-th delayed clock signals, wherein said output enable signal generation part includes a shift register including first to K-th flip-flops connected in series, wherein said first to K-th flip-flops are each supplied with any one of said first to t-th delayed clock signals, and wherein outputs of said first to K-th flip-flops serve as said first to K-th output enable signals respectively; and
an output part configured to apply the K pixel driving voltages to the K data lines at respective different timings on the basis of said first to K-th output enable signals,
wherein:
said delayed clock generation part includes a phase comparator and a variable delay circuit group constituted by first to (t+1)-th variable delay circuits each having a basic delay time which is one (t+1)-th of a period of said reference clock signal are connected in series with each other;
said reference clock signal is supplied to the first variable delay circuit;
outputs of the first to t-th variable delay circuits in said variable delay circuit group serve as said first to t-th delayed clock signals respectively; and
said phase comparator adjusts a delay time of each of the first to t-th variable delay circuits in the variable delay circuit group on the basis of a phase difference between a signal output from the (t+1)-th variable delay circuit and said reference clock signal.

2. The display driver according to claim 1, wherein each of the first to t-th variable delay circuits is a variable delay element having an element delay of said basic delay time.

3. The display driver according to claim 2, wherein
said shift register has
a first shift mode in which to shift an output start signal in said first to K-th flip-flops in order of the first flip-flop, the second flip-flop, the third flip-flop, . . . , the (K−1)-th flip-flop, and the K-th flip-flop, whereby timing to apply the pixel driving voltages to the data lines is delayed in order of the first output enable signal, the second output enable signal, the third output enable signal, . . . , the (K−1)-th output enable signal, and the K-th output enable signal, and
a second shift mode in which to shift said output start signal in said first to K-th flip-flops in order of the K-th flip-flop, the (K−1)-th flip-flop, . . . , the third flip-flop, the second flip-flop, the first flip-flop, whereby the timing to apply the pixel driving voltages to the data lines is delayed in order of the K-th output enable signal, the (K−1)-th output enable signal, . . . , the third output enable signal, the second output enable signal, and the first output enable signal,
the driver further comprising a delay mode setting part for setting which to make an operation in, said first shift mode or said second shift mode.

4. The display driver according to claim 1, wherein
said shift register has
a first shift mode in which to shift an output start signal in said first to K-th flip-flops in order of the first flip-flop, the second flip-flop, the third flip-flop, . . . , the (K−1)-th flip-flop, and the K-th flip-flop, whereby timing to apply the pixel driving voltages to the data lines is delayed in order of the first output enable signal, the second output enable signal, the third output enable signal, . . . , the (K−1)-th output enable signal, and the K-th output enable signal, and
a second shift mode in which to shift said output start signal in said first to K-th flip-flops in order of the K-th flip-flop, the (K−1)-th flip-flop, . . . , the third flip-flop, the second flip-flop, the first flip-flop, whereby the timing to apply the pixel driving voltages to the data lines is delayed in order of the K-th output enable signal, the (K−1)-th output enable signal, . . . , the third output enable signal, the second output enable signal, and the first output enable signal,
the driver further comprising a delay mode setting part for setting which to make an operation in, said first shift mode or said second shift mode.

5. A display driver which drives a display device, comprising:
a first driver for applying first to K-th (K is n/2 and n is an integer greater than or equal to 2) pixel driving voltages among the first to an n-th pixel driving voltages corresponding to pixel-by-pixel luminance levels indicated by an image data signal to first to K-th data lines of the display device, respectively; and
a second driver for applying a (K+1)-th to the n-th pixel driving voltages among said first to n-th pixel driving voltages to (K+1)-th to n-th data lines of the display device, respectively, wherein:
the first and second drivers each include
a delayed clock generation part configured to generate first to t-th (t is an integer less than or equal to K and greater than or equal to 2) delayed clock signals having phases different from each other and being synchronized with a reference clock signal;
an output enable signal generation part configured to generate first to K-th output enable signals on the basis of said first to t-th delayed clock signals, wherein said output enable signal generation part includes a shift register including first to K-th flip-flops connected in series, wherein said first to K-th flip-flops are each supplied with any one of said first to t-th delayed clock signals, and wherein outputs of said first to K-th flip-flops serve as said first to K-th output enable signals respectively; and
an output part configured to apply the K pixel driving voltages to the K data lines at respective different timings on the basis of said first to K-th output enable signals,
wherein:
said delayed clock generation part includes a phase comparator and a variable delay circuit group constituted by first to (t+1)-th variable delay circuits each having a basic delay time which is one (t+1)-th of a period of said reference clock signal are connected in series with each other;
said reference clock signal is supplied to the first variable delay circuit;
outputs of the first to t-th variable delay circuits in said variable delay circuit group serve as said first to t-th delayed clock signals respectively; and
said phase comparator adjusts a delay time of each of the first to t-th variable delay circuits in the variable delay circuit group on the basis of a phase difference between a signal output from the (t+1)-th variable delay circuit and said reference clock signal.

6. The display driver according to claim 5, wherein each of the first to t-th variable delay circuits is a variable delay element having an element delay of said basic delay time.

7. The display driver according to claim 6, wherein
said shift register has
a first shift mode in which to shift an output start signal in said first to K-th flip-flops in order of the first flip-flop, the second flip-flop, the third flip-flop, . . . , the (K−1)-th flip-flop, and the K-th flip-flop, whereby timing to apply the pixel driving voltages to the data lines is delayed in order of the first output enable signal, the second output enable signal, the third output enable signal, . . . , the (K−1)-th output enable signal, and the K-th output enable signal, and
a second shift mode in which to shift said output start signal in said first to K-th flip-flops in order of the K-th flip-flop, the (K−1)-th flip-flop, . . . , the third flip-flop, the second flip-flop, the first flip-flop, whereby the timing to apply the pixel driving voltages to the data lines is delayed in order of the K-th output enable signal, the (K−1)-th output enable signal, . . . , the third output enable signal, the second output enable signal, and the first output enable signal,
the driver further comprising a delay mode setting part for setting which to make an operation in, said first shift mode or said second shift mode.

8. The display driver according to claim 5, wherein
said shift register has
a first shift mode in which to shift an output start signal in said first to K-th flip-flops in order of the first flip-flop, the second flip-flop, the third flip-flop, . . . , the (K−1)-th flip-flop, and the K-th flip-flop, whereby timing to apply the pixel driving voltages to the data lines is delayed in order of the first output enable signal, the second output enable signal, the third output enable signal, . . . , the (K−1)-th output enable signal, and the K-th output enable signal, and
a second shift mode in which to shift said output start signal in said first to K-th flip-flops in order of the K-th flip-flop, the (K−1)-th flip-flop, . . . , the third flip-flop, the second flip-flop, the first flip-flop, whereby the timing to apply the pixel driving voltages to the data lines is delayed in order of the K-th output enable signal, the (K−1)-th output enable signal, . . . , the third output enable signal, the second output enable signal, and the first output enable signal,
the driver further comprising a delay mode setting part for setting which to make an operation in, said first shift mode or said second shift mode.