# Patent

## Title
Constant current source with threshold voltage and channel length modulation compensation

## Abstract

A constant current source with threshold voltage and channel length modulation comprises a set of cascade transistors and a compensation circuit electrically connected to the set of cascade transistors so as to form a feedback circuit, in which the set of cascade transistors including a first MOS transistor and a second MOS transistor, and the compensation circuit comprises a third MOS transistor, a fourth MOS transistor, a sixth MOS transistor and a seventh MOS transistor. The gate terminal of the third MOS transistor is connected to the gate terminal of the second MOS transistor. The fourth MOS transistor is connected to the third MOS transistor in serial, and the gate terminal of the fourth MOS transistor is connected to the gate terminal of the first MOS transistor, and the second terminal of the fourth MOS transistor is connected to a current-supplying circuit. The gate terminals of the sixth and seventh MOS transistors are electrically connected to the current-supplying circuit, and a current is generated by mirroring flows through the third MOS transistor.

## Background
BACKGROUND OF THE INVENTION
(A) Field of the Invention
The present invention relates to a constant current source with threshold voltage and channel length modulation compensation, and more particularly to a current source that is applicable to digital-to-analog converter (DAC).
(B) Description of the Related Art
DAC is the most commonly used circuit in integrated circuit (IC) design fields, and can usually be categorized into active component type and passive component type. Passive DAC applies resistors or capacitors to complete such a circuit design. Because the passive components have a larger chip thereon, the matching between these passive components has to be taken into consideration. Furthermore, they need to be accompanied with high-efficiency operational amplifiers to have a good performance, so most current circuit designs do not adopt passive components and tend to adopt active components.
The active components generally can be divided into weighted current source, current cell matrix and switched-current modes in the design field of the DAC circuit. All of the above three modes of the active components have current sources formed by a plurality of current source cells, and make use of some switch components to switch current source cells so as to have various signal conversions.
As shown in FIG. 1, a circuit diagram of a conventional 10-digit DAC, the circuit adopts binary-weighted current source for a design mode. The DAC includes 1023 current source cells 11 and ten weighted current source I0, 2I1, 4I0, . . . , and 512I0 formed by current source cells 11. The output signal can obtain 10-digit resolution by controlling the ten switches 12.
However, because the aforementioned circuit makes use of more than one thousand current source cells 11, the homogeneities of the current source cells 11 output current are very important; otherwise, it is impossible to obtain a DAC with a high resolution or high yield ratio.
FIG. 2 is a circuit diagram of a conventional current source cell. The output current I1 of a current source cell 20 can be formulated by the following formula: 



  
    
      
        
          I
          1
        
        =
        
          
            K
            1
          
          ⁢
          
            
              W
              1
            
            
              L
              1
            
          
          ⁢
          
            
              (
              
                
                  V
                  a
                
                -
                
                  V
                  th
                
              
              )
            
            2
          
        
      
    
    
      
        (
        
          Formula
          ⁢
          
            
          
          ⁢
          1
        
        )
      
    
  




wherein K1=μnCox/2, μn is electron mobility, Cox is the capacitor value of the unit area, W1 is the channel width of a Metal Oxide Semiconductor (MOS) transistor M1, L1 is the channel length of the MOS transistor M1, Va is the bias voltage of the gate terminal and Vth is the threshold voltage.

From Formula 1, current I1 is variable with the threshold voltage Vth of the MOS transistor M1, so it is unacceptable for a high resolution DAC. In addition, not only the threshold voltage Vth may shift with the manufacture process conditions, but also the great current source cells of a DAC may have a poor PSRR (Power Supply Rejection Ratio; PSRR), which results in a distorted conversion.
To obtain a DAC with a better PSRR, another current source cell 30 is disclosed by Taiwan Patent No.230,284, as shown in FIG. 3. The output current I2 of the current source cell 30 can be simplified into the following formula: 



  
    
      
        
          I
          2
        
        =
        
          
            K
            2
          
          ⁢
          
            
              W
              2
            
            
              L
              2
            
          
          ⁢
          
            
              (
              
                V
                R1
              
              )
            
            2
          
          ⁢
          
            (
            
              1
              +
              
                λ
                ⁢
                
                  
                
                ⁢
                
                  V
                  DS2
                
              
            
            )
          
        
      
    
    
      
        (
        
          Formula
          ⁢
          
            
          
          ⁢
          2
        
        )
      
    
  




wherein K2 is a constant coefficient same in physical meaning as K1 in Formula 1, W2 is the channel width of MOS transistor M2, L2 is the channel length of a MOS transistor M2, VR1 is a first reference voltage; VDS2 is the relative voltage between the base electrode and source electrode of the MOS transistor M2, and λ is a coefficient and the whole term (1+λVDS2) expresses the effect of channel length modulation.

Referring to the formula 2, because VR1 is a constant value, the output current I2 is in proportion to VDS2. However, VDS2 is also variable with the variance of the threshold voltage Vth of the MOS transistor M1. Compared with the current source cell 20 in FIG. 2, the relation between output current I2 and Vth is rewritten in the power of one from the power of two, so the PSRR of the current source cell 30 is likely to be slightly improved.
However, the current source cell 30 in FIG. 3 still cannot meet the requirements of a high resolution DAC. Therefore, a current source with a lower PSRR is progressively demanded for a DAC field to solve all aforementioned disadvantages in DAC.
SUMMARY OF THE INVENTION
The first objective of the present invention is to provide a constant current source with threshold voltage and channel length modulation compensation. A compensation circuit is added in the circuit of a current source cell, and enables a robustness performance in a whole current source that possesses a superior PSRR.
The second objective of the invention is to provide a current source with optimal circuit design. By adjusting corresponding parameters to minimize the variance of an output current, the current source can be widely applied in the DAC circuit design.
In order to achieve these objectives, the present invention discloses a constant current source with threshold voltage and channel length modulation, which includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor. Each of the MOS transistors has a gate terminal, a first terminal and a second terminal. The first terminal of the second MOS transistor is coupled to a loading impedance, and its second terminal is coupled to the first terminal of the first MOS transistor. The gate terminal and the first terminal of the third MOS transistor are coupled together to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage. The gate terminal and second terminal of the fifth MOS transistor are respectively coupled to a second reference voltage and a third reference voltage, and its first terminal is coupled to the gate terminal and first terminal of the third MOS transistor.
The above-mentioned constant current source uses three reference voltages for current compensation, which is controlled by voltage mode. Moreover, a constant current source using current mode is also revealed here to meet specific requirements.
A constant current source with threshold voltage and channel length modulation, using current mode, comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a sixth MOS transistor and a seventh MOS transistor, among which the first, second and third MOS transistors are essentially equivalent to the above design of voltage mode, i.e., those transistors and the above ones are of the substantially same circuits. The fourth MOS transistor has a gate terminal, a first terminal and a second terminal, wherein the gate terminal and the first terminal are electrically connected to the gate terminal of the first MOS transistor and the second terminal of the third MOS transistor, whereas the second terminal is electrically connected to a current-supplying circuit. The sixth MOS transistor has a gate terminal, a first terminal and a second terminal, wherein the gate terminal is electrically connected to the current-supplying circuit, whereas the second terminal is electrically connected to the first terminal of the third MOS transistor and the gate terminal of the second MOS transistor. The seventh MOS transistor has a gate terminal, a first terminal and a second terminal, wherein the gate terminal and the first terminal is connected to the current-supplying circuit, whereas the second terminal is connected to the first terminal of the sixth MOS transistor. A current is generated between the third and sixth MOS transistors by the current-supplying circuit, and the current is self-compensated to be constant.
Through the design of the current mode, multiple constant current sources with threshold voltage and channel length modulation compensation can be applied to specific requirements, for instance, a binary-weighted current source or a DAC, with a view to overcoming the problem of insufficient driving force. In addition, the current is insensitive to temperature, and therefore the influence of variation of process or power can be diminished.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described according to the appended drawings in which:
FIG. 1 is a circuit diagram of a conventional 10-digit DAC;
FIG. 2 is a circuit diagram of a conventional current source cell;
FIG. 3 is another circuit diagram of a conventional current source cell;
FIG. 4 is a circuit diagram of a current source cell of the first embodiment in accordance with the present invention;
FIG. 5 shows quadratic curves of Formula 4 in accordance with the present invention;
FIG. 6 is a circuit diagram of a current source cell of the second embodiment in accordance with the present invention;
FIG. 7 shows the relation of current and temperature of the current source cell in accordance with the present invention;
FIG. 8 shows a current cell of the second embodiment applied to a binary-weighted current source; and
FIG. 9 shows a current cell of the second embodiment applied to a DAC.



PREFERRED EMBODIMENT OF THE PRESENT INVENTION
FIG. 4 is a circuit diagram of a current source cell in accordance with the present invention. The current source cell 40 of the present invention includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor Mb, a fourth MOS transistor Mc and a fifth MOS transistor Mp. In addition, a MOS transistor M3 and a MOS transistor M4 can be added to the circuit as a switch circuit 41 that can control the direction of an input current. Furthermore, the voltage VDD of the first power supply is together coupled to the source electrodes of the P-type MOS transistor M3 and MOS transistor M4. The first MOS transistor MI and the second MOS transistor M2 form a set of cascade transistors 42. The third MOS transistor Mb, the fourth MOS transistor Mc and the fifth MOS transistor Mp form a compensation circuit 43 that can reduce the influences of threshold voltage of the set of cascade transistors 42 on the output current I1.
The drain electrode of the second MOS transistor M2 is coupled to the drain electrode of the P-type switch circuit 41. The gate terminal and drain electrode of the third transistor Mb are connected with each other to form a diode, and all are together coupled to the gate terminal of the second MOS transistor M2. The gate terminal of the fourth MOS transistor Mc is coupled to its drain electrode to form a diode, and is also coupled with the gate terminal of the fourth MOS transistor M1. The fourth MOS transistor Mc, the third MOS transistor Mb and the fifth MOS transistor Mp of the compensation circuit 43 are connected in a series to form a reference current Ib. The source electrode of fourth MOS transistor Mc is coupled to a first reference voltage Vr1, while the gate terminal and source electrode of the fifth transistor Mp are respectively coupled to the second reference voltage Vr2 and the third reference voltage Vr3.
The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor Mb, the fourth MOS transistor Mc and the fifth MOS transistor Mp can be N-type MOS transistors (N channel) or P-type MOS transistors (P channel). However, if the polarities of the MOS transistors in FIG. 4 are changed, the connections of the source electrode and the drain electrode should interchange, and the polarity of the bias voltage applied on a gate terminal should also be changed. To simplify all relative descriptions, the drain electrode and the source electrode of each MOS transistor is defined as a first terminal and a second terminal, respectively. The definitions of the first terminal and the second terminal depend on the polarities of the MOS transistor that is adopted.
In order to obtain the optimal compensation result of the threshold voltage and the channel length modulation on the cell current source 40, the transistor parameters can be controlled during the manufacture process to reach desired physical characteristics. First, the threshold voltage Vth2 of the second MOS transistor M2 should be decreased to be as low as possible, and the threshold voltages of the second MOS transistor M2 and the third transistor Mb should be kept in consistency (Vthb=Vth2). On the other hand, if the threshold voltages Vth2 and Vthb are decreased, the current Ib passing through the channel of third transistor Mb becomes larger. The fifth transistor Mp can be regarded as a resistor with constant resistance. The bias voltage Vb applied on the gate terminal of the third transistor Mb is decreased, when the current Ib becomes larger. Finally, the decrease of bias-voltage Vb can result in the decrease of bias-voltage VGS2 between the gate terminal and second terminal of the second MOS transistor M2, and a predetermined compensation effect is achieved this way.
In other words, the present invention has a feedback circuit formed by the third MOS transistor Mb and the fourth MOS transistor Mc of the compensation circuit 43 and the first MOS transistor M1 and the second MOS transistor M2 of the cascaded transistor 42 to achieve a low PSRR function.
Output current I1 can be formulated by the following formula: 



  
    
      
        
          I
          1
        
        =
        
          
            K
            1
          
          ⁢
          
            
              W
              1
            
            
              L
              1
            
          
          ⁢
          
            
              (
              
                V
                r1
              
              )
            
            2
          
          ⁢
          
            (
            
              1
              +
              
                λ
                ⁢
                
                  
                
                ⁢
                
                  V
                  DS1
                
              
            
            )
          
        
      
    
    
      
        (
        
          Formula
          ⁢
          
            
          
          ⁢
          3
        
        )
      
    
  




wherein K1 is a constant as the same physical meaning as K1 in formula 1, W1 is the channel width of the first MOS transistor M1, L1 is the channel length of the MOS transistor M1, Vr1 is the first reference voltage; VDS1 is the relative voltage between the drain electrode and source electrode of the first MOS transistor M1, λ is a coefficient and the whole term (1+λVDS1) expresses the effect of the channel length modulation.

The VDS1 can be denoted by the following formula: 



  
    
      
        
          
            
              
                V
                DS1
              
              ⁢
              
              =
              
                
                  V
                  b
                
                -
                
                  V
                  th2
                
                -
                
                  V
                  OD2
                
              
            
          
        
        
          
            
              
              ⁢
              
                =
                
                  
                    V
                    r3
                  
                  -
                  
                    
                      
                        
                          k
                          b
                        
                        ⁡
                        
                          (
                          
                            
                              V
                              GSb
                            
                            -
                            
                              V
                              thb
                            
                          
                          )
                        
                      
                      2
                    
                    ×
                    
                      R
                      on
                    
                  
                  -
                  
                    V
                    th2
                  
                  -
                  
                    V
                    OD2
                  
                
              
            
          
        
        
          
            
              
              ⁢
              
                =
                
                  
                    
                      -
                      
                        k
                        b
                      
                    
                    ⁢
                    
                      R
                      on
                    
                    ⁢
                    
                      V
                      th2
                      2
                    
                  
                  +
                  
                    
                      (
                      
                        
                          2
                          ×
                          
                            k
                            b
                          
                          ⁢
                          
                            V
                            GSb
                          
                          ⁢
                          
                            R
                            on
                          
                        
                        -
                        1
                      
                      )
                    
                    ×
                    
                      V
                      th2
                    
                  
                  +
                  
                    V
                    R3
                  
                  -
                
              
            
          
        
        
          
            
                    
              ⁢
              
                
                  
                    k
                    b
                  
                  ⁢
                  
                    R
                    on
                  
                  ⁢
                  
                    V
                    GSb
                    2
                  
                
                -
                
                  V
                  OD2
                
              
            
          
        
        
          
            
              
              ⁢
              
                =
                
                  
                    V
                    th2
                    2
                  
                  -
                  
                    
                      (
                      
                        
                          2
                          ⁢
                          
                            V
                            GSb
                          
                        
                        -
                        
                          1
                          
                            
                              k
                              b
                            
                            ⁢
                            
                              R
                              on
                            
                          
                        
                      
                      )
                    
                    ⁢
                    
                      V
                      th2
                    
                  
                  +
                  
                    V
                    GSb
                    2
                  
                  -
                  
                    V
                    OD2
                  
                
              
            
          
        
      
    
    
      
        (
        
          Formula
          ⁢
          
            
          
          ⁢
          4
        
        )
      
    
  




wherein Vth2 is the threshold voltage of the second MOS transistor M2, VOD2 (VOD2=VGS2−Vth2) is the over-driving voltage of the second MOS transistor M2, Kb is the parameter of the third MOS transistor Mb, VGSb is the bias voltage between the gate terminal and second terminal of the third MOS transistor Mb and Ron is the equivalent resistance of the fifth MOS transistor Mp.

Formula 4 is finally simplified as the quadratic parabolic curve of the Vth2 and VDS1, and the most insensitive design range of VDS1 to Vth2 can be obtained through the quadratic parabolic curve. It is determined by 



  
    
      ∂
      
        V
        DS1
      
    
    
      ∂
      
        V
        th2
      
    
  
  =
  
    
      0
      ⇒
      
        
          V
          th2
        
        ⁡
        
          (
          
            V
            
              
                DS1
                ′
              
              ⁢
              min
            
          
          )
        
      
    
    =
    
      
        V
        GSb
      
      -
      
        1
        
          2
          ⁢
          
            k
            b
          
          ⁢
          
            R
            on
          
        
      
    
  




wherein Vth2(VDS1,min) is the corresponding value of Vth when VDS1 is a minimum.

FIG. 5 shows quadratic curves of formula 4 in accordance with the present invention. Curve 1 represents the relation between VDS1 and Vth2 when the compound parameter Kb×Ron approximates infinity. The curve 2 represents the relation between VDS1 and Vth2 when the compound parameter Kb×Ron equals VGSh/2. The curve 1 and curve 2 are based on two extra conditions, and a common practical condition is shown as represented by the curve 3. The optimal design is considered to obtain the Kb×Ron value corresponding to the central symmetry point of the curve 3, because even if Vth2 is varied within ±10% around the central symmetry point, the minimal variance of VDS1 can be obtained, i.e., MIN ΔVDS1.
The most robust current source cell can be obtained through the above-described optimal design considerations. Then, we can use a computer to further analyze and simulate the performances of the optimal current source cell by a Monte-Carlo method. The simulation conditions can assume that Vth1, Vth2, Vthb, Vthc and Vthp all have their Gaussian distribution with ±10% (=3σ) variances, and the variable range of the power supply voltage VDD is from 2.7V to 3.9V. Then, we can obtain 0.15% PSRR as a good performance in comparison with conventional technologies.
The above-mentioned current source cell 40 uses three reference voltages for current compensation, which is controlled under voltage mode. When multiple current source cells 40 are employed at the same time, the total required current is larger. For instance, if a current source cell 40 needs 5 microamperes (μA) and is applied to a 10-bit circuit, a current of 5120 μA (5×210=5120) in total is needed, i.e., approximately 5 milliamperes (mA).
FIG. 6 shows another embodiment of the present invention, in which a current source cell 60 is compensated under current mode. The circuit of the current source cell 60 is similar to that illustrated in FIG. 4, but is upside down and poles of some transistors are opposite to that in FIG. 4, and the fifth MOS transistor Mp in FIG. 4 is replaced with a sixth MOS transistor M6 and a seventh MOS transistor M7. A switch circuit 61 consisted of the MOS transistors M3 and M4 is able to control current direction, and a source voltage VDD is coupled to the sources of the MOS transistors M3 and M4. The first and second MOS transistors M1 and M2 form a set of cascade transistors 62, whereas the third MOS transistor Mb, the fourth MOS transistor Mc, the sixth MOS transistor M6 and the seventh MOS transistor M7 form a compensation circuit 63. The gate terminal and the drain terminal of the third MOS transistor Mb are coupled, so as to function as a type of diode, and the gate terminal of Mb is further coupled to the gate terminal of the second MOS transistor M2. The drain terminal of the second MOS terminal M2 is coupled to the switch circuit 61. The gate terminal of the fourth MOS transistor Mc is coupled to its drain terminal to act as a diode, and is further coupled to the gate terminal of the first MOS transistor M1. The fourth MOS transistor Mc, the third MOS transistor Mb, the sixth MOS transistor M6 and the seventh MOS transistor M7 in the compensation circuit 63 are connected, and the source terminal of the fourth MOS transistor Mc, the gate terminal of the sixth MOS transistor M6 and the gate and source terminals of the seventh MOS transistor M7 are coupled to a current-supplying circuit 64. The current-supplying circuit 64 shown in FIG. 6 is illustrative only, and can be substituted by another essentially equivalent circuit in practice.
Through mapping, the current-supplying circuit 64 can generate a current Id accompanying with a bias voltage between the third MOS transistor Mb and the sixth MOS transistor M6 in the current source cell 60. Accordingly, the effect is equivalent to that of the three reference voltages under voltage mode.
The fourth MOS transistor Mc and the first MOS transistor MI are located at essentially equivalent positions in layout, and thus the threshold voltages of them are almost the same. Therefore, when the threshold voltage of the first MOS transistor MI is decreased, the threshold voltage of the fourth MOS transistor Mc is decreased as well. As a result, the current Id flowing through the third MOS transistor Mb and the sixth MOS transistor M6 is increased. Meanwhile, because the voltages between the gate and source terminals of the sixth and seventh MOS transistors M6 and M7 are not changed, the voltages of the drain terminals of the sixth and seventh MOS transistors M6 and M7 are increased relatively. Accordingly, the bias voltages between the gate and source terminals of the third and fourth MOS transistors Mb and Mc are decreased, and thus the current Id is decreased. In other words, the current source cell 60 has the capability of current stabilization by itself, so it can perform compensation automatically.
In comparison with voltage mode, the case of current mode can automatically adjust current by itself. When multiple current source cells are employed, the current source cell 60 using current mode can overcome the problem of current loss that may occur under voltage mode. Therefore, it is unnecessary to add (an) amplifier(s) in the circuit to provide larger driving capability.
Moreover, because the current Id in the current source cell 60 has the capability of compensation, it can be sustained to be constant. In comparison with voltage mode, the current source cell 60 is insensitive to temperature, i.e., having lower temperature coefficient (TC) number. The test result of the current source cell 60 in relation to temperature is shown in FIG. 7, in which the curves are categorized into three groups respectively representing the cases of the VDD of 3.6V, 3.3V and 3V from top to bottom. The current variation of each group within a range of 100° C. is defined as the temperature coefficient. As shown in FIG. 7, the current varies by approximately 0.0024 μA from 0 to 100° C. in each group, so the temperature coefficient TC=0.0024 μA/100° C. Apparently, the current source cell 60 has superior stability to temperature. In addition, based on experiments, the entire current variation can be controlled below 0.65% even if the variation of PSRR and various current due to different threshold voltage are added, and thus the interference of the variations of process and power can be effectively diminished.
FIG. 8 shows a binary-weighted current source 80, which employs current source cells of current mode. The binary-weighted current source 80 comprises a first current-supplying circuit 81, a first current source cell 82, a second current-supplying circuit 83 and a second current source cell 84, which are all connected in series. The circuits of the first and second current source cells 82 and 84 are identical or similar to that of the current source cell 60 in FIG. 6. The first current-supplying circuit 81 provides the required current of the first current source cell 82. The output current of the first current source cell 82 flows through the second current-supplying circuit 83 and is transmitted to the second current source cell 84 to provide the required current of the second current source cell 84. Because the current source cells 82 and 84 can perform current compensation by themselves, the output current can be sustained to be constant and the insufficient driving capability problem can be overcome. The binary-weighted current source 80 can generate from one to three times amount of current, depending on different output positions. For instance, the first current source cell 82 is weighted once, and the second current source cell 84 is weighted twice. Therefore, it is unnecessary to make a circuit of triple area, so the cost can be effectively reduced.
FIG. 9 shows the constant current source 60 applied to a DAC, in which a DAC 90 comprises a current-supplying circuit 91, multiple current source cells 60 as shown in FIG. 6, a series of resistors 93 and a de-glitch circuit 94. The switch circuit 61 of each current source cell 60 is connected to the series of resistors 93, whereas an end of the series of resistors 93 is connected to the de-glitch circuit 94. In the case of a 12-bit circuit, 4096 (212) current source cells 60 have to be connected, so as to reach the high transform efficiency.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by persons skilled in the art without departing from the scope of the following claims.

## Claims

1. A constant current source with threshold voltage and channel length modulation, comprising:
a set of cascade transistors including a first MOS transistor and a second MOS transistor; and
a compensation circuit electrically connected to the first MOS transistor and the second MOS transistor so as to form a feedback circuit, the compensation circuit comprising:
a third MOS transistor whose gate terminal is connected to a gate terminal of the second MOS transistor;
a fourth MOS transistor connected to the third MOS transistor in serial and having a gate terminal, a first terminal and a second terminal, wherein the gate terminal of the fourth MOS transistor is connected to a gate terminal of the first MOS transistor, and the second terminal of the fourth MOS transistor is connected to a current-supplying circuit; and
a fifth MOS transistor and a sixth MOS transistor, wherein the gate terminals of the fifth and sixth MOS transistors are electrically connected to the current-supplying circuit, and current is generated by mirroring flows through the third MOS transistor.

2. The constant current source with threshold voltage and channel length modulation of claim 1, wherein the third and fourth MOS transistors function as a diode.

3. A constant current source with threshold voltage and channel length modulation, comprising:
a first MOS transistor having a gate terminal, a first terminal and a second terminal;
a second MOS transistor having a gate terminal, a first terminal and a second terminal, wherein the second terminal is electrically connected to the first terminal of the first MOS transistor;
a third MOS transistor having a gate terminal, a first terminal and a second terminal, wherein the gate and first terminals are electrically connected to the gate terminal of the second MOS transistor;
a fourth MOS transistor having a gate terminal, a first terminal and a second terminal, wherein the gate terminal and the first terminal are electrically connected to the gate terminal of the first MOS transistor and the second terminal of the third MOS transistor, whereas the second terminal is electrically connected to a current-supplying circuit;
a fifth MOS transistor having a gate terminal, a first terminal and a second terminal, wherein the gate terminal is electrically connected to the current-supplying circuit, and the second terminal is electrically connected to the first terminal of the third MOS transistor; and
a sixth MOS transistor having a gate terminal, a first terminal and a second terminal, wherein the gate and first terminals are connected to the current-supplying circuit, and the second terminal is connected to the first terminal of the fifth MOS transistor.

4. The constant current source with threshold voltage and channel length modulation of claim 3, wherein the second terminal of the first MOS transistor is used for outputting current from the constant current source.

5. The constant current source with threshold voltage and channel length modulation of claim 3, wherein the second MOS transistor is electrically connected to a source voltage through a switch circuit.

6. The constant current source with threshold voltage and channel length modulation of claim 5, wherein the switch circuit comprises two MOS transistors, the second terminals of the two MOS transistors are connected to the first terminal of the second MOS transistor, and the first terminals of the two MOS transistors are connected to the source voltage.

7. The constant current source with threshold voltage and channel length modulation of claim 3, which is applied to a binary-weighted current source.

8. The constant current source with threshold voltage and channel length modulation of claim 3, which is applied to a digital-to-analog converter.