# Patent

## Title
Switched capacitor circuit with reduced common-mode variations

## Abstract

A circuit with a common-mode dual output includes a feedback circuit connected to alternate the states of the dual output between an average output level and a desired common-mode level. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is connected to the feedback circuit to adjust the signal offset level.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electronic circuits and, more particularly, to electronic circuits which include switched capacitor circuitry.
2. Description of the Related Art
For high performance signal conditioning systems, most analog circuits use dual output differential amplifiers. Differential amplifiers amplify the difference between positive and negative input signals and allow the rejection of noise from the substrate and clock signals coupled to the amplifier. However, differential amplifiers also amplify the average of the positive and negative input signals which is generally referred to as the common-mode.
The common-mode limits the common-mode rejection ratio (CMRR) which is defined as the ratio of the differential mode gain to the common-mode gain. Hence, the CMRR can be increased by decreasing the common-mode gain. In differential amplifiers, the common-mode gain can be reduced by including a common-mode feedback loop. In some differential amplifiers, the feedback loop can include switched capacitor circuits as disclosed in U.S. Pat. No. 6,400,301 or as disclosed in D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons, New York, 1997, Pgs 287–291.
Switched capacitor circuits typically include a number of switches coupled to capacitors where the switches are configured to alternately store and transfer charge between the capacitors. When the switched capacitor circuit is coupled to the differential amplifier, the capacitors can sense the average or common-mode of the output and then compare the average with a desired common-mode. The difference between the average common-mode and the desired common-mode can be used in a feedback loop which drives the difference to zero.
The switches are designed to alternate between two phases or operational modes to control the amplification of the input signals. In some applications, the amplifier is active during a first phase so the common-mode in a second phase is not as critical. However, it may still be desired to control the common-mode during both phases for several reasons. One reason is that the common-mode in the second phase should settle to the common-mode in the first phase to minimize any delays.
Another reason is that in some applications, both the first and second phases are used to amplify the signal. This is often referred to as “amplifier sharing” where it is desired to have the same common-mode for both phases so that the amplification is constant. Hence, it is desired to have the same common-mode when switching between phases to minimize the dependence of the output signal on the common-mode.
The common-mode level at the amplifier's output can vary due to changes in the common-mode feedback circuit. Small errors within the common-mode feedback circuit are multiplied by the common-mode error gain to provide a common-mode error that varies from one clock phase to the next. These common-mode variations reduce the available signal range for differential amplifiers which is further reduced as circuit supply voltages are reduced. Hence, the common-mode and the common-mode error gain are a concern for low power and portable electronic applications.
BRIEF SUMMARY OF THE INVENTION
In one aspect of the present invention, a circuit with a common-mode dual output includes a common-mode circuit with an output portion. A common-mode corrector circuit is connected to alternate the states of the output portion between an average output level and a desired common-mode level. The difference between the average output level and the desired common-mode level is proportional to a signal offset level. An error correcting circuit is connected to the common-mode corrector circuit to adjust the signal offset level.
In another aspect of the present invention, an integrated circuit includes a differential amplifier circuit with an output portion and a current sinking portion. The output portion includes dual outputs which provide an average output level. A common-mode feedback circuit is coupled to the output portion to provide a desired common-mode level in a first operational mode and generates a feedback signal proportional to the difference between the average output level and the desired common-mode level in a second operational mode. The feedback signal is coupled to the current sinking portion. An impedance matching circuit is connected to the feedback circuit to adjust the feedback signal.
In other aspects of the present invention, a switched capacitor amplifier provides an output signal in response to an input signal and corrects the average output level of the output signal in accordance with a desired common-mode level. The switched capacitor amplifier includes a differential amplifier with an output portion and a current sinking portion where the output portion provides the output signal. A switched capacitor common-mode feedback circuit is coupled between the output portion and the current sinking portion where the feedback circuit is configured to alternate the states of the output portion between the average output level on a precharging capacitor and the desired common-mode level on a common-mode feedback capacitor in response to alternating clock cycles. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is coupled to the feedback circuit to reduce the signal offset level. The impedance matching circuit includes a charge balancing switch configured to reduce feedthrough between the differential amplifier and the feedback circuit.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified block diagram of a signal conditioning system in accordance with the present invention;
FIG. 2 is a simplified circuit schematic diagram of the signal conditioning system illustrated in FIG. 1;
FIG. 3 is a graph illustrating a common-mode signal of the circuit illustrated in FIG. 2 as a function of time for capacitances cflya and cflyb equal to ccmfba/10 and ccmfbb/10, respectively, and capacitances cflya and cflyb equal to ccmfba and ccmfbb, respectively.
FIG. 4 is a graph illustrating the common-mode signal of the circuit illustrated in FIG. 2 as a function of time for different configurations of capacitors C1 and C2;
FIG. 5 is a graph illustrating the common-mode signal of the circuit illustrated in FIG. 2 as a function of time for different configurations of switch M11;
FIG. 6 is a graph illustrating the common-mode signal of the circuit illustrated in FIG. 2 as a function of time for different processing, power supply, and temperature conditions where switch M11, is three-quarters sized and the circuit excludes capacitors C1 and C2; and
FIG. 7 is a graph illustrating the common-mode signal of the circuit illustrated in FIG. 2 as a function of time for different processing, power supply, and temperature conditions where switch M11, is one-half sized and the circuit includes capacitors C1 and C2.



DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 illustrates a simplified block diagram of a signal conditioning system 10 in accordance with the present invention. System 10 can be included in a signal conditioning system such as an operational amplifier, an analog to digital converter, a digital to analog converter, or a similar circuit where it is desired to amplify the difference between two signals.
In one embodiment, system 10 includes a common-mode circuit 14 coupled to a common-mode corrector circuit 18 through an output port 13. Circuit 14 is also coupled to common-mode corrector circuit 18 through an error correcting circuit 22. A biasing circuit 16 is coupled to common-mode circuit 14 and common-mode corrector circuit 18 to provide power and to set an operating point for common-mode circuit 14.
Port 13 includes differential output terminals Vo+ and Vo− which provide respective differential output signals vo+ and vo− in response to differential input signals vi+ and vi− at terminals Vi+ and Vo−. It should be noted that here and in the following discussion, a physical terminal or component included in system 10 will be indicated with a capital letter and a signal or a measurable value will be indicated with a lower case letter. For example, the differential output terminals are referred to as Vo+ and Vo− while signals at the respective differential output terminals are referred to as vo+ and vo−.
The average of the output signals measured on terminals Vo+ and Vo− is commonly known as the common-mode signal or level, and will be denoted as vcmavg. The desired common-mode signal or level at a terminal Vcm will be referred to as vcm and the difference between signals Vcmavg and vcm (i.e. Vcmavg−Vcm) will be referred to as the common-mode variation.
In the following discussion, it should be noted that it is typically desired to drive signal Vcmavg to be equal to signal vcm during the operation of common-mode circuit 14 so that the difference is zero and, consequently, the common-mode variation is reduced. It is also typically desired to reduce the changes in the common-mode variation when switching from one phase or operational mode to another.
In accordance with the invention, error correcting circuit 22 can be configured to reduce changes in the common-mode variation when switching between phases by balancing the load coupled to terminals Vo+ and Vo− and by correcting for charge injection errors. Further, common-mode corrector circuit 18 is configured to compare signal vcmavg with signal vcm and provide a feedback signal vFB at a terminal VFB coupled to circuit 14 where signal vFB is proportional to signal vcmavg. It should be noted that in other embodiments, common-mode corrector circuit 18 can provide a feedforward signal or another signal which is proportional to signal vcmavg and the use of a feedback signal in this embodiment is for illustrative purposes only.
FIG. 2. illustrates a simplified circuit schematic diagram of one embodiment of signal conditioning system 10 illustrated in FIG. 1. In this embodiment, common-mode circuit 14 includes n-MOS transistors M1a and M1b connected as a differential amplifier pair. Further, output port 13 is provided by the drains of transistors M1a and M1b, which form differential output terminals Vo+ and Vo−. A power source VDD is coupled to transistors M1a and M1b through p-MOS transistors M2a and M2b, respectively. Transistors M2a and M2b each include a control terminal coupled to biasing circuit 16 and provide a biasing current equal to ibias/2 to respective transistors M1a and M1b.
A current sinking portion 11 includes a current sinking n-MOS transistor M0 that sinks a current i0 from transistors M1a and M1b to current return 12. Transistor M0 includes a drain coupled to the sources of transistors M1a and M1b through a terminal Vd and a source connected to a current return 12. Further, a control terminal of transistor M0 is connected to common-mode corrector circuit 18 and error correcting circuit 22 at terminal VFB.
It should be -noted that current sinking portion 11 can include more than one transistor in some embodiments. This is exemplified in FIG. 2 by current sink 15 which includes parallel n-MOS transistors 17 and 19. The control terminal of transistor 19 is connected to terminal VFB while the control terminal of transistor 17 is connected to terminal Vbias. Current sink 15 can be substituted for current sinking portion 11 as indicated by substitution arrow 21.
The embodiment with current sink 15 may be desired to adjust the operating characteristics of common-mode circuit 14. The number of parallel transistors determines the gate capacitance of current sinking portion 11 and the operating frequency of circuit 14. However, only one transistor is illustrated in current sinking portion 11 for simplicity and ease of discussion.
In accordance with the invention, bias circuit 16 includes a diode connected n-MOS transistor M3 where the source is coupled to reference potential 12 and the drain is coupled to a current source Ibias which provides current ibias. Current source Ibias is also coupled to the drain of a diode connected p-MOS transistor M4 where the source of transistor M4 is coupled to power supply VDD and the control terminal is coupled to the control terminals of transistors M2a and M2b.
In operation, transistor M4 is configured to mirror bias current ibias to transistors M2a and M2b. Further, transistor M3 is configured to provide a bias signal vbias at a terminal Vbias connected to a control terminal of transistor M3. It should be noted that signal vbias is used to bias transistor M0 through common-mode corrector circuit 18 and error correcting circuit 22 and, consequently, signal vbias determines the amount of current sunk (i.e. current i0) by transistor M0.
In this embodiment, current return 12 can include a voltage terminal with a reference potential. However, in the embodiment illustrated in FIG. 2, current return 12 is illustrated as a ground terminal (i.e. AC and DC ground), with the potential difference between current return 12 and power supply VDD, connected to the sources of transistors M2a, M2b, and M4, driving system 10.
It should also be noted that above and in the following discussion, the polarity of the various transistors included in system 10 can be changed from n-MOS to p-MOS or from p-MOS to n-MOS. Further, system 10 can include bipolar junction transistors or other types of field effect transistors. Hence, the type and the polarity of the transistors included in system 10 are chosen for simplicity and ease of discussion and are not meant to limit the scope of the invention.
In this embodiment, common-mode corrector circuit 18 includes a switched capacitor network. In particular, common-mode corrector circuit 18 includes a switch M10 coupled between terminal Vbias and a terminal Vb. Further, terminal Vcm is coupled to terminals Vc+ and Vc− through switches M8 and M9, respectively.
In accordance with the invention, terminal Vc− is coupled to terminal Vo− through a switch M5 and terminal Vc+ is coupled to terminal Vo+ through a switch M6. Further, terminal Vb is coupled to terminal VFB through a switch M7. A precharging capacitor Cflya is connected between terminals Vb and Vc+ and a precharging capacitor Cflyb is connected between terminals Vb and Vc−. Further, a common-mode feedback capacitor Ccmfba is connected between terminals VFB and Vo+ and a common-mode feedback capacitor Ccmfbb is connected between terminals VFB and Vo−. It should be noted that precharging capacitors Cflya and Cflyb are often referred to as “flying” capacitors because they are configured to provide charge storage and charge transfer in response to alternating phases or operational modes.
In this embodiment, error correcting circuit 22 includes a switch M11, coupled between common-mode corrector circuit 18 and the control terminal of current sinking transistor M0. Circuit 22 further includes a balancing capacitor C1 and a balancing capacitor C2 coupled between reference potential 12 and terminals Vb and Vbias, respectively. It should be noted that the source and drain of switch M11 are connected together so that switch M11 is configured to behave as a “dummy” switch, as will discussed in more detail below.
In some embodiments, at least one of charge balancing capacitors C1 and C2 can include a transistor such as a MOS transistor. This realization is exemplified in FIG. 2 by MOS transistors 26 and 32 which are substituted for charge balancing capacitors C1 and C2, respectively, as indicated by respective substitution arrows 28 and 34.
In this embodiment, switches M5 through M11 include n-MOS transistors with gates coupled to alternately switching clocks. In particular, the gates of switches M8, M9, M10, and M11 are coupled to a clock 1 which provides a clock signal φ1 and the gates of switches M5, M6, and M7 are coupled to a clock 2 which provides a clock signal φ2. It should be noted that clocks 1 and 2 correspond to output signal phases or operational modes which can be provided by phase coupled clock signals. For example, clocks 1 and 2 can provide respective signals φ1 and φ2 which include non-overlapping square clock pulses.
In operation, signal vcmavg is formed by transistors M0, M1a, M1b, M2a and M2b and is set by the difference between the currents sourced by transistors M2a and M2b (i.e. current ibias) and the current sunk by transistor M0 (i.e. current i0). The sum of the currents sourced by M2a and M2b can be different from current i0 because of processing variations in the various components included in common-mode circuit 102 (i.e. transistors M1a, M1b, M2a, and M2b) and temperature and power supply variations.
Processing variations correspond to chip-to-chip differences that occur when fabricating a large number of chips. It is well known that in a fabrication run some chips will have a higher maximum operating frequency (i.e. a fast process) or a lower maximum operating frequency (i.e. a slow process) than a desired operating frequency because of physical variations (i.e. variations in gate area, film thickness, doping concentration, etc.) in the elements included in system 10. For example, physical variations can be caused because transistors M2a and M2b are p-MOS transistors which are typically fabricated during a different step from n-MOS transistors M0, M1a, M1b, M3, and M4.
Temperature variations can be caused by the environment surrounding system 10 and power supply variations can include voltage changes in power source VDD. Controlling variations in power source VDD is desirable because circuits are being scaled to lower operating voltages for portable and other applications. For example, in some embodiments power source VDD can be a battery which typically discharges over time. In other embodiments, variations in power source VDD can be from the imperfect regulation of power source VDD in line powered applications.
The balancing of signal vcmavg with signal vcm occurs when common-mode corrector circuit 18 couples output terminals Vo+ and Vo− to the gate of current sinking transistor M0 to adjust a gate bias of transistor M0 in response to the difference between signals Vcmavg and vcm. The coupling is proportional to feedback signal VFB and controls or drives the common-mode signal vcmavg to equal signal Vcm.
In operation, when signal φ1 is high and signal φ2 is low (i.e. switches M8, M9, M10, and M11 are on and switches M5, M6, and M7 are off), charge proportional to the difference between signals vcm and vbias is stored on capacitors Cflya and Cflyb. Further, when signal φ1 is low and signal φ2 is high (i.e. switches M8, M9, M10, and M11 are off and switches M5, M6, and M7 are on) the charge stored on capacitors Cflya and Cflyb is transferred to capacitors Ccmfba and Ccmfbb, respectively. Hence, signals vcmavg and vcm can be compared by alternately clocking the group of switches including M5 through M7 and the group of switches including M8 through M11.
It should also be noted that in this embodiment the gate of switch M11, is coupled to clock 1 because common-mode circuit 14 is inactive when signal φ2 is high and signal φ1 is low. In particular, circuit 14 is typically inactive when switches M5, M6, and M7 are on because circuit 14 is configured for operation in a switched capacitor environment so that transistors M1a and M1b are active during a system transfer mode when switches M8, M9, M10, and M11 are on. In other embodiments, circuit 14 can be active when either φ1 or φ2 are high to provide amplifier sharing.
An example of the common-mode error gain can be illustrated when signal φ1 is high and signal φ2 is low. If an error signal is sensed (i.e. the common-mode variation is not equal to zero) by the control terminal of transistor M0, then there will be a high gain between signal VFB and the common-mode signal at output terminals Vo+ and Vo−. The error signal will be scaled by a value that is proportional to the ratio of capacitance cgs(M0) divided by the sum of capacitances ccmfba and ccmfbb where cgs(M0) is the total capacitance, including parasitic capacitances, between the control terminal and source of transistor M0. However, when signal φ1 is low and signal φ2 is high, the error signal is scaled by a factor proportional to capacitance cgs(M0) divided by the sum of capacitances Ccmfba, ccmfbb, cflya, and Cflyb.
The change in the common-mode error gain when switching between signals φ1, and φ2 causes “charge hopping” where signal Vcmavg is a function of both signals φ1 l and φ2. Hence, the common-mode error gain depends on parasitic capacitances and the common-mode variations caused by phase-to-phase gain variations depend on capacitances cflya and Cflyb.
Charge injection errors can be caused by currents flowing through parasitic capacitances of the transistors and switches included in system 10. Charge injection errors can also be caused by changes in the channel charge under a transistor gate as the transistor switches between the off and on state. It should be noted that the parasitic capacitances allow a control signal at a control terminal or gate of a transistor to be coupled to a corresponding transistor source or drain, the coupling resulting in a parasitic charge or current flow. The control signal coupling is referred to as feedthrough and occurs when charge is injected between the gate and the source or drain.
The parasitic capacitances illustrated in FIG. 2 are shown in phantom by indicating the relevant component with broken lines. For example, switch M7 has a parasitic gate to drain capacitance cgd7 with an injected charge qgd7 and a parasitic gate to source capacitance cgs7 with an injected charge qgs7. Further, switch M10 has a parasitic gate to drain capacitance cgd10 with an injected charge qgd10 and a parasitic gate to source capacitance cgs10 with an injected charge qgs10. Switch M11, has a parasitic gate to drain capacitance cgd11 with an injected charge qgd11 and a parasitic gate to source capacitance cgs11 with an injected charge qgs11 and transistor M3 has parasitic gate capacitance cgs(M3). It should be noted that the injected charge corresponds to electrons where it is conventional to define positive current flow to be in a direction opposite to the direction of electron flow.
If capacitors C1 and C2 are excluded from system 10, then the impedance to reference potential 12 for terminals Vb, VFB, and Vbias, will depend on the impedances through parasitic capacitors Cgs(M0) Cgs(M3), Cgs7, Cgd7, Cgd10, and Cgs10. By including capacitors C1 and C2 in system 10, however, the impedance to reference potential 12 for terminals Vb, VFB, and Vbias will depend more on the impedances through capacitors C1 and C2 and less on the parasitic impedances and, consequently, will be more constant as a function of time.
In accordance with the invention, the common-mode error gain and the charge injection errors can be minimized by configuring common-mode error correcting circuit 22. In particular, capacitances c1 and c2 can be chosen to reduce the charge injection error and the variations in the common-mode error gain by setting the impedance to reference potential 12 for terminals VFB, Vb, and Vbias to a desired value. Further, switch M11 can be configured to reduce the charge injection error by selecting capacitances cgs11 and cgd11 so that the charge injection is balanced between MO and common-mode corrector circuit 18.
In this embodiment, switch M11 is configured by choosing its gate area to be proportional to the gate area of switch M7. For example, when switch M11 is “half-sized”, then its gate area is one-half the size of the gate area of switch M7. Similarly, when switch M11 is “full sized”, then its gate area is equal to the gate area of switch M7 and when switch M11 is “three-quarters sized”, then its gate area is three-quarters the size of the gate area of switch M7.
Capacitors C1 and C2 provide impedance matching between terminals Vb and VBias and adjacent terminals such as terminal VFB. Hence, capacitances c1 and c2 can be chosen to match an impedance of terminal Vb to an impedance of terminal Vbias when switching between signals φ1 and φ2. When terminals Vb and Vbias are impedance matched with the rest of system 10, an equal or balanced charge is transferred between terminals Vb and Vbias and each adjacent terminal when clocking switches M5 through M11.
When choosing capacitances c1 and c2, the common-mode error gain when signal φ1 is high is proportional to capacitance cgs (M0) divided by the sum of capacitances ccmfba and ccmfbb Further, the common-mode error gain when signal φ2 is high is proportional to the sum of capacitances cgs (M0) and c1 divided by the sum of capacitances ccmfba, ccmfbb, cflya, cflyb. Thus, for the common-mode error gain to remain constant, the error gain when signal φ1 is high should be equal to the error gain when signal φ2 is high so that: 



  
    
      
        
          
            
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A solution to Equation (1) can be obtained when capacitances cgs (M0) and c1 are equal and when capacitance ccmfba equals capacitance cflya and capacitance ccmfbb equals capacitance cflyb so that: 



  
    
      
        
          
            
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It should be noted that in some embodiments without capacitance c1 in Equation (1), capacitances cflya and cflyb would need to be smaller in order to decrease the common-mode variations when switching between signals φ1 and φ2. For example, in some designs, capacitances cflya and cflyb are chosen to be equal to capacitances ccmfba/10 and ccmfbb/10, respectively. However, when capacitances cflya and cflyb are made smaller it takes more time to correct for the common-mode variation because it will take more clock cycles to move charge from terminals Vcm and Vbias to capacitors Ccmfba and Ccmfbb. Hence, it is desirable to increase capacitances Cflya and Cflyb to increase the charge transfer rate from terminals Vcm and Vbias to capacitors Ccmfba and Ccmfbb so that it takes less time (i.e. fewer clock cycles) to drive signal vcmavg to vcm.
FIG. 3 illustrates a graph 50 of signal vcmavg of system 10 verses time for two different values of capacitances cflya and cflyb. A curve 52 corresponds to the case where capacitances cflya=ccmfba/10, cflyb=ccmfbb/10, and cgs (M0)=c1 and a curve 54 corresponds to the case where capacitances cflya=ccmfba, cflyb=ccmfbb and cgs (M0)=c1. Also shown in FIG. 3 is a curve 42 that corresponds to a steady-state condition in which system 10 does not include capacitors c1 and c2 or switch M11 and capacitances cflya=ccmfba/10 and cflyb=ccmfbb/10. In this example, the desired common-mode signal vcm is 850 mV or 0.850 volts, although signal vcm can be chosen to be another desired value.
As shown in FIG. 3, the common-mode signal can be corrected to the desired common-mode signal faster when capacitances cflya and cflyb are larger (i.e. curve 54) because curve 54 converges to curve 42 quicker than curve 52. Hence, capacitors Cflya and Cflyb can transfer more charge in a given time from terminal Vcm to capacitors Ccmfba and Ccmfbb, respectively.
Hence, one advantage of using capacitor C1 is that capacitances cflya and cflyb can be increased by choosing a value for capacitor C1 so that Equation (2) is satisfied. For example, capacitances cflya and cflyb can be made equal to capacitances ccmfba and ccmfbb, respectively, and capacitance cg(M0) can be equal to capacitance c1.
It is anticipated that capacitance cflya can be within a range between one half to one times a capacitance of ccmfba and that capacitance cflyb can be within a range between one half to one times a capacitance ccmfbb to minimize common-mode variations and to maximize the charge transfer rate. It should be noted, however, that capacitances cflya and cflyb can have values outside these ranges in other embodiments.
Capacitances c1 and c2 can be chosen to balance the parasitic currents injected by switches M7 and M10 and transistors M0 and M3 to minimize the charge injection errors. As an example, if bias circuit 16 has a medium impedance through capacitor cgs (M3) common-mode circuit 14 has a low impedance through capacitor cgs (M0), and terminal Vb has a high impedance to current return 12, then charges will preferentially flow towards terminal Vbias when signal φ1 goes high and signal φ2 goes low.
Hence, when signal φ1 goes low and signal φ2 goes high, the magnitude of charge qgs11 will be equal to charge qgd11 because the source and drain of switch M11 are connected together (i.e. switch M11 is a dummy switch). The magnitude of charge qgd7 will be greater than charge qgs7 and the magnitude of charge qgd10 will be less than charge qgs10. Charge qgd7 can be made equal to qgs11+qgd11 by sizing switch M11 to have an area and width equal to one-half of the area and width of switch M7 and by choosing the impedance between reference potential 12 and terminals VFB and Vb to be equal. The relative magnitudes of the injected charges are indicated by the size of the arrows representing the corresponding charges. Further, the directions of the arrows indicate that most of the charge flow will be towards terminal Vbias.
As another example, if signal φ1 goes low and signal φ2 goes high, then the magnitude of charge qgs11 will be equal to charge qgd11, the magnitude of charge qgd7 will be greater than charge qgs7, and the magnitude of charge qgd10 will be less than charge qgs10. Further, the direction of the corresponding arrows will be the opposite as that indicated in FIG. 2 because most of the charge will flow away from terminal Vbias.
If terminal Vbias has the same impedance through capacitor cgs (M3) as capacitor cgs (M0), however, then the magnitudes of the injected charge flow will be the same through the parasitic capacitances because the impedances will be equal or balanced. Hence, the size of the arrows representing the charge flow will be equal.
The charge or current balancing of the injected charges provides less common-mode variations and gain errors. To provide minimal common-mode gain and charge injection errors, it is anticipated that capacitances c1 and cgs (M0) can be equal so that the injected charge is balanced or split evenly between terminals Vb and VFB. It is also anticipated that the sum of capacitances cgs (M3) and c2 can be equal to capacitance cgs (M0) so that charge is balanced or split evenly between terminals Vb and Vbias.
The common-mode variation can be illustrated by considering the following examples. It should be noted that in these examples, the desired common-mode level vcm is equal to 850 mV and the graphs show the value of signal vcmavg as a function of time or clock signals φ1 and φ2. In the following examples, it is typically desired to have signal vcmavg equal to signal vcm and to have signal vcmavg be the same when switching between clocks 1 and 2.
If signal vcmavg is the same when switching between clocks 1 and 2, then Vcmavg when clock 1 is high (i.e. vcmavg(φ1)) will be equal to vcmavg when clock 2 is high (i.e. vcmavg(φ2)). Hence, a measure of the common-mode variations and the error gain for various configurations of error correcting circuit 22 can be determined by comparing the difference and the average of signals vcmavg (φ1) and vcmavg ((φ2) where, in these examples, the average should be 850 mV.
FIG. 4 illustrates a graph 40 of signal vcmavg of system 10 verses clocks signals φ1 and φ2. In FIG. 4, curve 42 corresponds to signal vcmavg without balancing capacitors C1 and C2 or switch M11. A curve 44 corresponds to signal vcmavg with capacitor C2 and without both capacitor C1 and switch M11. A curve 46 corresponds to signal vcmavg with capacitor C1 and without both capacitor C2 and switch M11. A curve 48 corresponds to signal vcmavg with both capacitors C1 and C2 and without switch M1.
The common-mode variation and the average variation between clock signals φ1 and φ1 for curves 42, 44, 46, and 48 are shown in Table 1. It can be seen from Table 1 and graph 40 that capacitances c1 and c2 shift curve 42 towards the desired common-mode signal vcm (i.e. 850 mV) where capacitor C1 has slightly more of an affect than capacitor C2 because it is shifted closer to 850 mV. When capacitors C1 and C2 are both included, the common-mode level is shifted even closer to 850 mV. Hence, capacitors C1 and C2 can reduce the difference between vcmavg(φ1) and vcmavg (φ2) and move the average of signals vcmavg(φ1) and vcmavg (φ2) closer to 850 mV.







TABLE 1







Common-mode variations for graph 40.












Graph 40





  
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    cm
    avg
  
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Curve 42

897 mV
863 mV
350 mV
880 mV


Curve 44
C2
896 mV
861 mV
350 mV
879 mV


Curve 46
C1
875 mV
853 mV
220 mV
864 mV


Curve 48
C1, C2
873 mV
851 mV
220 mV
862 mV









FIG. 5 illustrates a graph 60 of signal vcmavg of system 10 verses clock signals φ1 and φ2. In FIG. 5, a curve 62 corresponds to signal vcmavg with a half-sized switch M11, a curve 64 corresponds to signal vcmavg with a full-sized switch M11, and a curve 66 corresponds to signal vcmavg with a three-quarters sized switch M11. It should be noted that capacitors C1 and C2 are not included in system 10 for the curves in FIG. 5 to illustrate the effects of switch M11.
The common-mode variation and the average variation between clocks φ1 and φ1 for curves 42, 62, 64, and 66 are shown in Table 2. It can be seen from Table 2 and graph 62 that adding switch M11 shifts curve 42 toward the desired common-mode signal vcm (i.e. 850 mV) and decreases the common-mode gain errors (i.e. vcmavg(φ1)−vcmavg(φ2)) between clocks φ1 and φ2. As the area of switch M11 in increased to a three-quarters sized switch, signal vcmavg(φ1) approaches vcmavg(φ2). For a full-sized switch, vcmavg(φ1) becomes less than vcmavg(φ2) indicating that the optimum size in some embodiments is between a three-quarters sized switch and a full-sized switch. Hence, when switch M11, is three-quarters sized, the common-mode gain error is less than the full-sized and half-sized cases (see curve 66). Thus, by optimizing the size of switch M11, the difference between vcmavg(φ1) and vcmavg(φ2) can be reduced and the average of signals vcmavg(φ1) and vcmavg(φ2) can be moved closer to 850 mV.







TABLE 2







Common-mode variations for graph 60.












Graph 60





  
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Curve 42

897 mV
863 mV
350 mV
880 mV


Curve 62
Half size
874 mV
861 mV
 13 mV
868 mV


Curve 64
Full size
847 mV
858 mV
−11 mV
853 mV


Curve 66
3⁄4 size
862 mV
860 mV
 2 mV
861 mV









In a typical manufacturing process, a circuit can be fabricated on a large number of individual substrates. It is well known that variations in the performance of the circuit can occur from one substrate to another where, in general, the variations are caused by variations in the semiconductor processing. For example, a particular film, such as an oxide or a conductive material, can be thicker on one substrate compared to another. The doping density can also vary throughout the manufacturing process which can affect the number of carriers in a particular region.
Hence, processing variations can cause differences in the performance of system 10 when manufacturing copies of it on the same or separate substrates. For example, when testing a large number of circuits, an average or nominal performance will be obtained where some circuits can run at a higher maximum possible frequency and others can run at a lower maximum possible frequency. The performance can affect the values of the common-mode level and variation. The performance can also affect the range of values for the common-mode level and variation.
It is desired to have the common-mode level and variation constant from one circuit to another when fabricating a large number of circuits. It is also desired to have the range of values for the common-mode level and variation narrow so that the performance of each individual circuit will be approximately the same for all conditions.
The differences in performance due to processing variations can be represented by simulating system 10 using a “fast model” or a “slow model”. The fast model represents the performance of system 10 when system 10 has be subject to processing variations that lead to a higher maximum possible operating frequency. The slow model represents the performance of system 10 when system 10 has been subject to processing variations that lead to a lower maximum possible operating frequency. It is generally desired to be able to operate system 10 at both high and low temperatures without significantly degrading the performance. One cause of performance degradation is an increased variation in the common-mode levels.
For this discussion, an operating temperature range between 125° C. and −40° C. is used as a benchmark where 125° C. is the expected highest operating temperature of system 10 and −40° C. is the expected lowest operating temperature. A temperature of 55° C. is used as the nominal temperature which represents the expected average operating temperature of system 10. It should be noted that these temperatures are chosen for illustrative purposes only and are not meant to limit the scope of the invention.
It should also be noted that in one embodiment, system 10 is fabricated with silicon-based circuitry. However, system 10 can be fabricated using other material systems. Examples of other material systems include III–V semiconductor materials, such as gallium arsenide, gallium nitride, or aluminum nitride. Other examples include germanium, silicon germanium, or silicon carbide.
FIG. 6 illustrates a graph 80 showing the effects of processing, power supply, and temperature variations for system 10 where capacitors C1 and C2 are excluded and switch M11, is three-quarters sized.
In FIG. 6, a curve 82 corresponds to a fast process at a temperature of 125° C. where VDD=2 volts. A curve 84 corresponds to the nominal process at a temperature of 55° C. where VDD=1.8 volts and a curve 86 corresponds to a slow process at a temperature of −40° C. where VDD=1.6 volts.
Curves 86 and 82 are chosen to represent the best and worst case responses, respectively, over process, power, and temperature variations and graph 84 represents the typical response under nominal or normal operating conditions.
For curve 86, the difference between signals vcmavg(φ1) and vcmavg(φ2) is about −2 mV and the average is around 849 mV. For curve 82, the difference between signals vcmavg(φ2) and cmavg(φ2) is about 10 mV and the average is around 883 mV. For curve 84, the difference between signals vcmavg(φ1) and vcmavg(φ2) is about 1 mV and the average is around 862 mV.







TABLE 3







Common-mode variations for graph 80.












Graph 80





  
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Curve 42

897 mV
863 mV
350 mV
880 mV


Curve 82
Fast
888 mV
878 mV
 10 mV
883 mV


Curve 84
Nom.
862 mV
861 mV
 1 mV
862 mV


Curve 86
Slow
848 mV
850 mV
 −2 mV
849 mV









The common-mode variations and the average variation between clock signals φ1 and φ1 for curves 42, 82, 84, and 86 are shown in Table 3. It can be seen from Table 3 and graph 80 that the average of vcmavg for clock signals φ1 and φ2 is expected to be in a range from 883 mV to 849 mV when fabricating a large number of circuits. Further, when fabricating a large number of circuits, the difference between vcmavg(φ1) and vcmavg(φ2) is expected to be in a range from −2 mV to 10 mV.
FIG. 7 illustrates a graph 70 of signal vcmavg of system 10 verses clock signals φ1 and φ2 when system 10 includes capacitors C1 and C2 and switch M11, where switch M11, is one-half sized. A curve 72 corresponds to a fast process at a temperature of 125° C. where VDD=2 volts. A curve 74 corresponds to the nominal process at a temperature of 55° C. where VDD=1.8 volts. A curve 76 corresponds to a slow process at a temperature of −30° C. where VDD=1.6 volts.







TABLE 4







Common-mode variations for graph 70.












Graph 70





  
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Curve 42

897 mV
863 mV
350 mV
880 mV


Curve 72
Fast
858 mV
851 mV
 7 mV
855 mV


Curve 74
Nom.
852 mV
845 mV
 7 mV
849 mV


Curve 76
Slow
844 mV
842 mV
 2 mV
843 mV









The common-mode variation and the average common-mode variation between clock signals φ1 and φ2 for curves 42, 72, 74, and 76 are shown in Table 4. The values in Table 4 can be compared to the values in Table 3 to illustrate the improvement in the difference and the average of vcmavg(φ1) and vcmavg(φ2) when switching between clock signals φ1 and φ2. It can be seen from Table 4 and graph 70 that the average of vcmavg for clock signals φ1 and φ2 is expected to be in a range from 855 mV to 843 mV when fabricating a large number of circuits. Further, when fabricating a large number of circuits, the difference between vcmavg(φ1) and vcmavg(φ2) is expected to be in a range from 2 mV to 7 mV.
Hence, by optimizing the area of switch M11, and by including capacitors C1 and C2, the average of vcmavg(φ1) and vcmavg(φ2) can be closer to the desired value of 850 mV when fabricating a large number of circuits. Further, the difference between vcmavg(φ1) and vcmavg(φ2) can be significantly reduced. Thus, the effects of processing variations commonly found in the manufacturing process can be minimized so that each circuit will have a similar performance.
Thus, a circuit with a common-mode dual output has been disclosed. The circuit can include a common-mode circuit with an output portion coupled to a common-mode corrector circuit. An error correcting circuit is connected to the common-mode corrector circuit to improve the performance.
The error correcting circuit can include capacitors C1 and C2 and switch M11 which can be configured to reduce variations in the common-mode level of the circuit when switching between two operational modes. Capacitors C1 and C2 and switch M11 can also be configured to reduce the range of values for the common-mode level and variation when fabricating a large number of circuits. Further, by including capacitor C1, capacitor Cfly can be made larger so that the common-mode level can be corrected to the desired common-mode level with fewer clock cycles.
The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.

## Claims

1. A circuit with a common-mode dual output comprising:
a common-mode circuit with an output portion;
a common-mode corrector circuit connected to alternate the states of said output portion between an average output level and a desired common-mode level, the difference between the average and desired levels being proportional to a signal offset level; and
an error correcting circuit connected to said common-mode corrector circuit to adjust the signal offset level;
wherein said common-mode corrector circuit further includes:
a common-mode voltage terminal connected to said output portion through a first pair of switches, said first pair of switches being responsive to alternating clock cycles which alternate the states of said output portion;
a bias terminal providing a bias level, said bias terminal being connected to a first control terminal in said common-mode circuit through a second pair of switches, said second pair of switches being responsive to the alternating clock cycles;
a precharging capacitor which stores the difference between the desired common-mode level and the bias level during a first clock cycle in the alternating clock cycles; and
a common-mode capacitor which stores the average output level during the first clock cycle, said common-mode capacitor and said precharging capacitor being connected in parallel during a second clock cycle in the alternating clock cycles.

2. The circuit of claim 1, wherein said error correcting circuit includes a first capacitor coupled to said comon-mode corrector circuit to reduce the difference between the average and desired levels.

3. The circuit of claim 2, wherein said first capacitor provides impedance matching to said bias terminal and control terminal during the first and second clock cycles, respectively.

4. The circuit of claim 1, wherein said error correcting circuit includes a second capacitor coupled to said bias terminal to reduce the difference between the average and desired levels.

5. The circuit of claim 2, wherein said error correcting circuit is configured to impedance match said bias terminal and control terminal with a terminal of said precharging capacitor.

6. The circuit of claim 1, wherein a capacitance of said precharging capacitor is chosen to be proportional to a capacitance of said first capacitor.

7. The circuit of claim 1, wherein said error correcting circuit includes a switch configured to reduce charge injection between said common-mode circuit and said common-mode corrector circuit.

8. The circuit of claim 1, wherein:
said precharging capacitor is coupled to said output portion; and
said common-mode circuit includes a differential amplifier pair of transistors and a current sinking transistor that includes said bias terminal and that sinks a current from said transistors.

9. The circuit of claim 8, wherein said error correcting circuit includes a transistor switch coupled between said bias terminal and said precharging capacitor to reduce charge injection errors during said first clock cycle.

10. The circuit of claim 1, wherein said error correcting circuit includes a first capacitor coupled to said precharging capacitor and to said common-mode capacitor to reduce the difference between the average and desired levels.

11. An integrated circuit, comprising:
a differential amplifier circuit with an output portion and a current sinking portion, said output portion including dual outputs which provide an average output level;
a common-mode feedback circuit coupled to said output portion, said feedback circuit providing a desired common-mode level in a first operational mode and generating a feedback signal proportional to the difference between the average output level and the desired common-mode level in a second operational mode, the feedback signal being coupled to said current sinking portion; and
an impedance matching circuit connected to said feedback circuit to adjust the feedback signal;
wherein the desired common-mode signal is provided to a precharging capacitor in the first operational mode, said precharging capacitor including a terminal coupled to said impedance matching circuit.

12. The integrated circuit of claim 11, wherein said impedance matching circuit is configured to reduce charge injection in said terminal when switching between the first and second operational modes.

13. The integrated circuit of claim 12, wherein said terminal is coupled to a bias terminal during the first operational mode and is coupled to said current sinking portion during the second operational mode.

14. The integrated circuit of claim 13, wherein said impedance matching circuit is configured to impedance match said terminal with at least one of said bias terminal and said current sinking portion when switching between the first and second operational modes, respectively.

15. The integrated circuit of claim 14, further including a switch configured to provide charge balancing between said current sinking portion and said feedback circuit.

16. The integrated circuit of claim 15, wherein an area of said switch is chosen to obtain a desired charge injection level through said switch.

17. The integrated circuit of claim 15, wherein said switch includes a field effect transistor with a control terminal coupled with the first operational mode.

18. A switched capacitor amplifier which provides an output signal in response to an input signal and corrects the average output level of the output signal in accordance with a desired common-mode level, said amplifier comprising:
a differential amplifier with an output portion and a current sinking portion, said output portion providing the output signal;
a switched capacitor common-mode feedback circuit coupled between said output portion and said current sinking portion, said feedback circuit being configured to alternate the states of said output portion between the average output level on a precharging capacitor and the desired common-mode level on a commonmode feedback capacitor in response to alternating clock cycles, the difference between the average and desired levels being proportional to a signal offset level;
an impedance matching circuit coupled to said feedback circuit to adjust the signal offset level, said impedance matching circuit including a charge balancing switch configured to reduce feedthrough between said differential amplifier and said feedback circuit.

19. The amplifier of claim 18, wherein said precharging capacitor is connected in parallel to said common-mode feedback capacitor during one cycle in the alternating clock cycles.

20. The amplifier of claim 18, wherein said impedance matching circuit includes a first capacitor configured to reduce a common-mode gain error in said differential amplifier.

21. The amplifier of claim 18, wherein a capacitance of said precharging capacitor is chosen to be in a range from one-half to one times a capacitance of said common-mode feedback capacitor.

22. The amplifier of claim 18, wherein said charge balancing switch includes a field effect transistor with a gate capacitance chosen to provide a desired feedthrough current.

23. The amplifier of claim 18, wherein a capacitance of said charge balancing switch is proportional to a desired charge injection level between said current sinking portion and said feedback circuit.

24. The amplifier of claim 18, wherein said impedance matching circuit includes a first capacitor coupled to a terminal of said precharging capacitor.

25. The amplifier of claim 24, wherein said first capacitor provides a balanced charge transfer between said terminal and a bias terminal during a first clock, cycle in the alternating clock cycles.

26. The amplifier of claim 25, wherein said first capacitor provides a balanced charge transfer between said terminal and said current sinking portion during a second clock cycle in the alternating clock cycles.

27. The amplifier of claim 26, wherein said impedance matching circuit includes a second capacitor coupled to said bias terminal, said second capacitor providing a balanced charge transfer between said bias terminal and said terminal when swi tching between the first and second clock cycles.

28. The amplifier of claim 27, wherein said second capacitor has a capacitance proportional to the sum of a capacitance of said current sinking portion and a capacitance of a bias circuit connected to said bias terminal.

29. The integrated circuit of claim 11, wherein said current sinking portion responds to the feedback signal to adjust the average output signal.