# Patent

## Title
Amplification-type solid-state image pickup device incorporating plurality of arrayed pixels with amplification function

## Abstract

An amplification-type solid-state image pickup device of the present invention repeats, in every frame, a signal level readout period, a first reset period, a reset level readout period, a second reset period, and a third reset period in this order. In the first reset period and the third reset period, a MOS transistor for reset is set to execute a soft reset operation with a sub-threshold current, while in the second reset period, the MOS transistor for reset is set to execute a hard reset operation so as to fix the potential of a photon-electron conversion region to a drain potential. This makes it possible to reduce both reset noise and image retention with a simple constitution.

## Background
This Nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2003-190171 filed in Japan on Jul. 2nd 2003 and Patent Application No. 2003-357652 filed in Japan on October 17th, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an amplification-type solid-state image pickup device, and more specifically relates to an amplification-type solid-state image pickup device incorporating a plurality of arrayed pixels with an amplification function.
There has been proposed an amplification-type solid-state image pickup device having a pixel portion in which each pixel has an amplification function and a scanning circuit disposed around the pixel portion, the pixel portion being scanned by the scanning circuit so that each pixel data is read out. Particularly, there is known an APS (Active Pixel Sensor)-type image sensor having a pixel constitution composed of a CMOS that offers advantage in integrating the pixel constitution with peripheral driver circuit and signal processing circuit.
Generally, the APS-type image sensor is constituted such that a photon-electron conversion portion, an amplification portion, a pixel selection portion and a reset portion are provided in one pixel. The photon-electron conversion portion is typically formed from a photo diode (PD), while the amplification portion, the pixel selection portion and the reset portion are formed from three to four MOS-type transistors (Tr).
In FIG. 14, there is shown a constitution of an APS-type image sensor of a (PD+3Tr) type composed of one photodiode (PD) and three MOS transistors (Tr) (to simplify the drawing, the pixel portion shown therein is composed of only 2 rows and 2 columns (4 pixels)). In FIG. 14, there are shown an amplification MOS transistor 201, a reset MOS transistor 202, a pixel selection MOS transistor 203, a photon-electron conversion photodiode 204, a signal line 205, a power line 206, a pixel selection line 207 and a reset gate line 280. The MOS transistors 203 and 202 are respectively driven by a vertical scanning circuit (I) 221 and a vertical scanning circuit (IIo) 222 through the pixel selection line 207 and the reset gate line 280. The signal line 205 is connected to the MOS transistor 230 that supplies a constant-current load (a voltage of VL1 is applied as a gate bias voltage), and the output voltage is sent to a horizontal signal line 236 through an amplifier (amplification-type MOS transistor) 231 and a MOS transistor 232. The MOS transistor 232 is driven by a horizontal scanning circuit 234 through a horizontal clock line 235. The horizontal signal line 236 is connected to a MOS transistor 233 that supplies a constant-current load (a voltage of VL2 is applied as a gate bias voltage), and the output voltage is lead to an output OS through an amplifier 237.
As shown in FIG. 15 with the above-described pixel constitution, if VDD<φRH where a channel potential below the reset gate is set to φRH and a reset drain voltage is set to VDD when a gate (reset gate) of the reset transistor 202 is in ON state, then a voltage of the photodiode 204 is reset to VDD when the reset gate is in ON state. However, after the reset gate is turned off, the photodiode suffers from noise ΔNrn expressed in electron number as shown in the following equation (1).

ΔNrn=(kTCp)1/2/q  (1)

wherein k represents a Boltzman's constant, T represents an absolute temperature, Cp represents the capacity of the photodiode and a region connected thereto, and q represents an elementary charge. As is clear from the equation (1), the reset noise is dependent on the capacity Cp and rises as Cp increases.

As is clear from FIG. 14, Cp includes not only the capacity of the photodiode itself but also the gate capacity of the amplification MOS transistor 201 and their reciprocal connection capacity. Because of this, the above-constituted pixel requires reduction in the reset noise ΔNrn.
In order to reduce the reset noise, a soft reset operation as described below has been proposed (see, e.g., “Analysis and enhancement of low-light level performance of photodiode-type CMOS active pixel imagers operated with sub-threshold reset” by Bedabrata Pain et al. in IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, June 1999, p140–143). More specifically, as shown in FIG. 16, if VDD>φRH when the gate (reset gate) of the reset transistor 202 is in ON state, then the potential of the photodiode 204 is reset to a sub-threshold region in the vicinity of φRH. In this case, after the reset gate is turned off, the photodiode suffers from noise ΔNrn expressed in electron number as shown in the following equation (2).

ΔNrn=(kTCp/2)1/2/q  (2)

In this case, the noise expressed in electron number is reduced to (1⁄2)1/2=0.71 of the noise in the equation (1).
However, if the potential of the reset drain 206 is fixed to VDD by the soft reset operation, leakage in the reset gate due to sub-threshold current disables the potential of the photodiode from being fixed, substantially causing image retention for as a very long period of time as not less than 10 frames.
In order to avoid the phenomenon of image retention, a method of performing a hard reset operation before the soft reset operation has been proposed. FIG. 17 shows its circuit constitution, and FIG. 18 shows its operation timing. In this method, before the soft reset operation, the reset drain potential is once set to a potential (VDD−Δφm) lower than φRH. This fixes the potential of the photodiode to (VDD−Δφm) so that the potential of the photodiode displaced by the leakage due to the sub-threshold current is fixed with respect to each storage period, thereby preventing the image retention from occurring.
As shown in FIG. 17, the circuit constitution in this case is different from the circuit constitution shown in FIG. 14 in the point that not a DC (Direct Current) but a pulsed potential VP(i) is applied to a power line 310. More specifically, the potential VP(i) is changed between two values by transistors 311, 312 and the pulse VPo(i). That is, when VPo(i) is in low level, the transistor 311 is turned on to make VP(i)=VDD. When VPo(i) is in high level, the transistor 311 is turned off, and applied to the power line 310 is a voltage decreased from VDD by a potential drop portion Δφm of the transistor 312 as shown below.

VP(i)=VDD−Δφm

As shown in FIG. 18, a reset period (T11+T12) is set when RS(i) becomes high level. In the former half period T11, VP(i)=VDD−Δφm, so that setting VDD−Δφm<φRH fixes the potential of the photodiode to (VDD−Δφm). This means that the hard reset operation is performed. Next, in the latter half period T12, VP(i)=VDD, so that setting VDD>φRH allows the soft reset operation of the photodiode. Herein, signal level read is executed before the reset period (T11+T12), while reset level read is executed after the reset period (T11+T12).
However, although in the method of executing the hard reset operation before the soft reset operation described with reference to FIGS. 17 and 18, image retention can be avoided, the reset noise is, as shown in the equation (2), at best reduced to 0.71 times the level of the noise in electron number generated in the typical reset operation, which is the noise level insufficient for high-resolution image sensors.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an amplification-type solid-state image pickup device capable of reducing both reset noise and image retention with a simple constitution.
Another object of the present invention is to provide an amplification-type solid-state image pickup device capable of reducing both reset noise and image retention with a simple constitution as well as retaining linearity of output signals against incident optical signals.
In order to accomplish the above objects, an amplification-type solid-state image pickup device in the present invention comprises:
a plurality of arrayed pixels, each of the pixels being composed of at least a photon-electron conversion region, a field effect transistor for signal amplification for amplifying signals expressed by potentials of the photon-electron conversion region, a field effect transistor for reset for discharging charges in the photon-electron conversion region to a drain, and a field effect transistor for pixel selection; and
a control portion for executing control so that with respect to each frame in each of the pixels, there are repeated in the following order
a signal level readout period in which a potential level of the photon-electron conversion region is read through the field effect transistor for signal amplification,
a first reset period in which the field effect transistor for reset executes a soft reset operation with a sub-threshold current,
a reset level readout period in which a potential level of the photon-electron conversion region reached by the soft reset operation in the first reset period is read through the field effect transistor for signal amplification,
a second reset period in which the field effect transistor for reset executes a hard reset operation so as to fix the potential of the photon-electron conversion region to a drain potential, and
a third reset period in which the field effect transistor for reset executes a soft reset operation with a sub-threshold current.
The term “frame” herein refers to a fundamental period of a cyclic operation of the solid-state image pickup device, and in the case of two-dimensional image sensors, it is equivalent to a period for scanning one screen.
In the amplification-type solid-state image pickup device of the present invention, a reset operation which is executed at the end in a preceding frame (a frame immediately before a noticed frame) is a soft reset operation in the third reset period. Therefore, in the signal level readout period in the noticed frame (indicating the frame that is noticed), the potential level obtained by charges stored in the photon-electron conversion region is read out after the soft reset operation is executed in the preceding frame (a signal read out at this point is referred to as a “read out signal level”).
Next, in the first reset period, the field effect transistor for reset is set to execute a soft reset operation with a sub-threshold current.
Next, in the reset level readout period, the potential level of the photon-electron conversion region reached by the soft reset operation in the first reset period is read out through the field effect transistor for signal amplification (a signal read out at this point is referred to as a “readout reset level”). In the soft reset operation, due to memory effect, a correlation is developed between reset noise after the last soft reset operation in the preceding frame and reset noise after the first soft reset operation in the noticed frame. Accordingly, performing Correlated Double Sampling (CDS) between, for example, the readout signal level and readout reset level leads to reduction in reset noise.
Next, in the second reset period, the field effect transistor for reset is set to execute a hard reset operation so as to fix the potential of the photon-electron conversion region to a drain potential. Since the potential of the photodiode in the photon-electron conversion region is fixed to a drain potential, the problem of the image retention can be solved in this stage.
After this, in the third reset period, the field effect transistor for reset is set to execute a soft reset operation with a sub-threshold current. The charges stored in the photon-electron conversion region after execution of the soft reset operation are read out in a succeeding frame (indicating a frame immediately after the noticed frame).
In such a case, the problem of the image retention has already been solved in the second reset period, and therefore image retention is confined to one frame. Therefore, the image retention is decreased and becomes substantially negligible.
Further, the present invention is characterized in that the control portion executes control so that the signal level readout period, the first reset period, the reset level readout period, the second reset period and the third reset period are repeated in this order. Such control can be easily implemented by, for example, a CPU (Central Processing Unit). Therefore, the amplification-type solid-state image pickup device of the present invention is easily constituted without the necessity of using specific component parts or the like.
Thus, according to the amplification-type solid-state image pickup device of the present invention, both the reset noise and the image retention can be reduced with a simple constitution.
It is to be noted that in the first reset period and the third reset period, in order to set, for example, an N channel-type field effect transistor for reset to execute a soft reset operation, it is preferable that the gate potential of the field effect transistor for reset be high, the drain potential be high, and the channel potential in the field effect transistor for reset when the gate is in high potential state be lower than the drain potential when the drain potential is in high level.
Further, in the second reset period, in order to set, for example, an N channel-type field effect transistor for reset to execute a hard reset operation, it is preferable that the drain potential of the field effect transistor for reset become low level while the gate potential stays high, and the channel potential in the field effect transistor for reset when the gate potential is in high level be higher than the drain potential when the drain potential is in low level.
Further, in the reset level readout period, it is preferable that the drain potential of, for example, an N channel-type field effect transistor for reset be in high state and the gate potential of the field effect transistor for reset be in low state.
Further, in the case where the gate potential of the N channel-type field effect transistor for reset has two high states of a first high state and a second high state, it is preferably that the gate potential is set to the first high state in the first reset period and set to the second high state in the second reset period and the third reset period.
An amplification-type solid-state image pickup device in one embodiment further comprises a correlated double sampling portion for performing a correlated double sampling operation on between a signal read out in the signal level readout period and a signal read out in the reset level readout period.
In the amplification-type solid-state image pickup device in this one embodiment, a correlated double sampling portion performs the correlated double sampling operation on between a signal read out in the signal level readout period (readout signal level) and a signal read out in the reset level readout period (readout reset level) This allows further reduction in reset noise.
In an amplification-type solid-state image pickup device of one embodiment,
a plurality of the pixels are arrayed in matrix form,
gates of the field effect transistors for reset are each connected on a row basis to reset gate lines extending in row direction, and
there is provided a first scanning circuit for sequentially applying two pulsed driving voltages to the gates of the field effect transistors for reset on a row basis through the reset gate lines.
According to the amplification-type solid-state image pickup device in this one embodiment, the gate potentials of the field effect transistors for reset can be controlled on a row basis by the first scanning circuit.
In an amplification-type solid-state image pickup device in one embodiment,
one terminals of the field effect transistors for pixel selection are each connected on a column basis to signal lines extending in column direction,
gates of the field effect transistors for pixel selection are each connected on a row basis to pixel selection lines extending in row direction, and
there is provided a second scanning circuit for sequentially applying two pulsed driving voltages to the gates of the field effect transistors for pixel selection on a row basis through the pixel selection lines.
In the amplification-type solid-state image pickup device in this one embodiment, the gate potentials of the field effect transistors for pixel selection are controlled on a row basis by the second scanning circuit. Signals from selected pixels are outputted through the signal lines.
In an amplification-type solid-state image pickup device in one embodiment,
drains of the field effect transistors for reset are each connected on a column basis to drain lines extending in column direction, and
there is provided a voltage application portion for applying two pulsed driving voltages to the drains of the field effect transistors for reset through the drain lines.
In the amplification-type solid-state image pickup device in this one embodiment, the drain potentials of the field effect transistors for reset are controlled by the voltage application portion.
In an amplification-type solid-state image pickup device in one embodiment, drains of the field effect transistors for amplification are each connected on a column basis to the drain lines.
In the amplification-type solid-state image pickup device in this one embodiment, the drain potentials of the field effect transistors for amplification are controlled by the voltage application portion.
In an amplification-type solid-state image pickup device in one embodiment,
drains of the field effect transistors for reset are each connected on a row basis to reset drain lines extending in row direction, and
there is provided a third scanning circuit for sequentially applying two pulsed driving voltages to the drains of the field effect transistors for reset on a row basis through the reset drain lines.
In the amplification-type solid-state image pickup device in this one embodiment, the drain potentials of the field effect transistors for reset are controlled on a row basis by the third scanning circuit.
An amplification-type solid-state image pickup device in one embodiment further comprises a voltage setting portion for setting voltages V1, V2 and V4 so as to satisfy a relation

|V1−Vt|≧|V2−Vt|>|V4−Vt|  (3)

wherein V1 denotes a gate voltage of the field effect transistor for reset in the first reset period, V2 denotes a gate voltage of the field effect transistor for reset in the second reset period and the third reset period, V4 denotes a gate voltage of the field effect transistor for reset in periods other than the first and second reset periods, and Vt denotes a threshold gate voltage of the field effect transistor for reset.
The symbol |a| in the equation (3) refers to an absolute value of a.
Further, since Vt is contained in the equation (3), the present invention can be specified even if the field effect transistor for reset is either P channel-type or N channel-type.
In the amplification-type solid-state image pickup device in this one embodiment, the reset operation executed at the end in the preceding frame is a soft reset operation in the third reset period. Since the soft reset operation is executed in succession to the hard reset operation, a potential of the photon-electron conversion region reached by the soft reset operation always stays constant regardless of the intensity of incident light.
After lapse of a period for storing charges in a photon-electron conversion region (this period refers to “optical signal storage period”) in succession to the third reset period in the preceding frame, a potential level (readout signal level) obtained by the charges stored in the photon-electron conversion region is read out in the signal level readout period in a noticed frame.
Next, in the first reset period, the field effect transistor for reset is set to execute a soft reset operation with a sub-threshold current. With the relation of |V1−Vt|≧|V2−Vt| in effect, the potential of the photon-electron conversion region reached by the soft reset operation stays constant regardless of the intensity of incident light (i.e., a charge amount stored in the photon-electron conversion region during the optical signal storage period) as with the case of executing the soft reset operation in succession to the hard reset operation.
Next, in the reset level readout period, the potential level (readout reset level) of the photon-electron conversion region reached by the soft reset operation in the first reset period is read out through the field effect transistor for signal amplification. In the soft reset operation, due to memory effect, a correlation is developed between reset noise after the last soft reset operation in the preceding frame and reset noise after the first soft reset operation in the noticed frame. Accordingly, performing Correlated Double Sampling (CDS) between, for example, the readout signal level and readout reset level leads to reduction in reset noise.
Furthermore, as described before, both the potential of the photon-electron conversion region reached by the soft reset operation in the third reset period in the preceding frame and the potential (readout reset level) of the photon-electron conversion region reached by the soft reset operation in the first reset period in the noticed frame stay constant regardless of the intensity of incident light (i.e., a charge amount stored in the photon-electron conversion region during the optical signal storage period). Therefore, a pixel output signal expressed by a difference between the readout signal level and the readout reset level can be linearly changed with respect to the intensity of incident light.
Next, in the second reset period, the field effect transistor for reset is set to execute a hard reset operation so as to fix the potential of the photon-electron conversion region to a drain potential. Since the potential in the photon-electron conversion region is fixed to a drain potential, the problem of the image retention can be solved in this stage.
After this, in the third reset period, the field effect transistor for reset is set to execute a soft reset operation with a sub-threshold current. The charges stored in the photon-electron conversion region after execution of the soft reset operation are read out in a succeeding frame (indicating a frame immediately after the noticed frame).
In such a case, the problem of the image retention has already been solved in the second reset period, and therefore image retention is confined to one frame. Therefore, the image retention is decreased and becomes substantially negligible.
Further, this one embodiment is characterized in that the control portion executes control so that the signal level readout period, the first reset period, the reset level readout period, the second reset period and the third reset period are repeated in this order while the relation of |V1−Vt|≧|V2−Vt|>|V4−Vt| is maintained by the voltage setting portion. Such control can be easily implemented by, for example, a CPU (Central Processing Unit). Therefore, the amplification-type solid-state image pickup device of the present invention is easily constituted without the necessity of using specific component parts or the like.
Thus, according to the amplification-type solid-state image pickup device in this one embodiment, both the reset noise and the image retention can be reduced with a simple constitution, and a pixel output signal can be linearly changed with respect to the intensity of incident light.
In an amplification-type solid-state image pickup device in one embodiment,
the voltage setting portion sets a value of |V1−V2| to be larger than a specified value so that a potential of the photon-electron conversion region immediately after the first reset period stays constant regardless of intensity of incident light to the photon-electron conversion region.
The term “specified value” herein refers to a difference ΔV1 between a channel potential and a potential of the photon-electron conversion region reached in the third reset period (when the reset gate potential is V2).
In the amplification-type solid-state image pickup device in this one embodiment, both the potential of the photon-electron conversion region reached by the third soft reset operation in the preceding frame and the potential (readout reset level) of the photon-electron conversion region reached by the first reset operation in the noticed frame securely stay constant regardless of the intensity of incident light (i.e., a charge amount stored in the photon-electron conversion region during the optical signal storage period). Therefore, a pixel output signal expressed by a difference between the readout signal level and the readout reset level can be linearly changed with respect to the intensity of incident light.
In an amplification-type solid-state image pickup device in one embodiment, the voltage setting portion sets a value of |V2−V4| within a specified range so that potential change of the photon-electron conversion region with respect to intensity of incident light is linear if the intensity of incident light is low whereas the potential change is logarithmic if the intensity of incident light is high.
If the value of |V2−V4| is sufficiently large, then signal charges that are photon-electron converted during the optical signal storage period are linearly stored in the photon-electron conversion region. More precisely, the amplification-type solid-state image pickup device exhibits a linear photon-electron conversion characteristic substantially in the entire region of the incident light intensity. If the value of |V2−V4| is sufficiently small, then a sub-threshold operation is taken place and the potential of the photon-electron conversion region is logarithmically changed with respect to the intensity of incident light. More precisely, the amplification-type solid-state image pickup device exhibits a logarithmic photon-electron conversion characteristic substantially in the entire region of the incident light intensity. Within the range of the value of |V2−V4|, a sub-threshold operation is taken place in a region high in the intensity of incident light and the logarithmic photon-electron conversion characteristic is exhibited, whereas in the region low in the intensity of incident light, the linear photon-electron conversion characteristic is exhibited. Accordingly, in the amplification-type solid-state image pickup device in one embodiment, as described above, the value of |V1−V2| is set within a specified range by the voltage setting portion so that potential change of the photon-electron conversion region with respect to intensity of incident light is linear if the intensity of incident light is low whereas the potential change is logarithmic if the intensity of incident light is high. This allows application of the amplification-type solid-state image pickup device either to logarithmic conversion-type image sensors and linear conversion-type image sensors.
An amplification-type solid-state image pickup device in one embodiment further comprises a correlated double sampling portion for performing a correlated double sampling operation on between a signal read out in the signal level readout period and a signal read out in the reset level readout period.
In the amplification-type solid-state image pickup device in this one embodiment, the correlated double sampling portion performs a correlated double sampling operation on between a signal read out in the signal level readout period (readout signal level) and a signal read out in the reset level readout period (readout reset level) This allows further reduction in reset noise.
In an amplification-type solid-state image pickup in one embodiment,
a plurality of the pixels are arrayed in matrix form,
gates of the field effect transistors for reset are each connected on a row basis to reset gate lines extending in row direction, and
the voltage setting portion includes a first scanning circuit for sequentially applying three pulsed driving voltages that are said V1, V2 and V4 to the gates of the field effect transistors for reset on a row basis through the reset gate lines.
According to the amplification-type solid-state image pickup device in this one embodiment, the gate potentials of the field effect transistors for reset can be controlled on a row basis by the first scanning circuit.
In an amplification-type solid-state image pickup device in one embodiment,
one terminals of the field effect transistors for pixel selection are each connected on a column basis to signal lines extending in column direction,
gates of the field effect transistors for pixel selection are each connected on a row basis to pixel selection lines extending in row direction, and
there is provided a second scanning circuit for sequentially applying two pulsed driving voltages to the gates of the field effect transistors for pixel selection on a row basis through the pixel selection lines.
In the amplification-type solid-state image pickup device in this one embodiment, the gate potentials of the field effect transistors for pixel selection are controlled on a row basis by the second scanning circuit. Signals from selected pixels are outputted through the signal lines.
In an amplification-type solid-state image pickup device in one embodiment,
drains of the field effect transistors for reset are each connected on a column basis to drain lines extending in column direction, and
there is provided a voltage application portion for applying two pulsed driving voltages to the drains of the field effect transistors for reset through the drain lines.
In the amplification-type solid-state image pickup device in this one embodiment, the drain voltages of the field effect transistor for reset are controlled by the voltage application portion.
In an amplification-type solid-state image pickup device in one embodiment, drains of the field effect transistors for amplification are each connected on a column basis to the drain lines.
In the amplification-type solid-state image pickup device in this one embodiment, the drain potentials of the field effect transistor for amplification are controlled by the voltage application portion.
In an amplification-type solid-state image pickup device in one embodiment,
drains of the field effect transistors for reset are each connected on a row basis to reset drain lines extending in row direction, and
there is provided a third scanning circuit for sequentially applying two pulsed driving voltages to the drains of the field effect transistors for reset on a row basis through the reset drain lines.
In the amplification-type solid-state image pickup device in this one embodiment, the drain potentials of the field effect transistors for reset are controlled on a row basis by the third scanning circuit.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1A is a view exemplifying the circuit constitution of a two-dimensional image sensor;
FIG. 1B is a view showing an modified example of the image sensor shown in FIG. 1A;
FIG. 2 is a view showing a circuit constitution of a pixel in an APS-type image sensor in one embodiment of the present invention;
FIG. 3 is a view showing operation timing of a given pixel in the image sensor;
FIG. 4 is a schematic view showing change in potential of the photodiode in a pixel in conformity to the operation shown in FIG. 3;
FIG. 5A is a view showing analyzed operation of the pixel;
FIG. 5B is a view showing analyzed change in potential ψPD of a photodiode corresponding to the timing shown in FIG. 5A;
FIG. 6 is a view showing analyzed change in potential of the photodiode in the pixel;
FIG. 7 is a view showing the response of the pixel against incident light;
FIG. 8A is a view showing operation timing of a given pixel in an APS-type image sensor in one embodiment of the present invention;
FIG. 8B is a view showing potential ψPD of a photodiode corresponding to the timing shown in FIG. 8A;
FIG. 9 is a schematic view showing change in potential of the photodiode in the pixel;
FIG. 10 is a view showing the response of the pixel against incident light;
FIG. 11 is a view showing change in response of the pixel against incident light with varied reset gate potentials;
FIG. 12 is a view exemplifying a circuit for producing reset gate potential φRG for the pixel.
FIG. 13 is a view showing operation timing of the circuit shown in FIG. 12;
FIG. 14 is a view showing the circuit constitution of a conventional APS-type image sensor including four pixels;
FIG. 15 is a view showing a potential gained by a hard reset operation of the pixel in the image sensor;
FIG. 16 is a view showing a potential gained by a soft reset operation of the pixel in the image sensor;
FIG. 17 is a view showing a modified example of the circuit constitution of a conventional APS-type image sensor; and
FIG. 18 is a view showing operation timing of the image sensor.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The amplification-type solid-state image pickup device of the present invention will be described hereinbelow in detail in conjunction with the embodiment with reference to the drawings.
Although description will be given of the case where an N channel-type transistor (threshold gate voltage Vt=0 for simplification) is adopted below, the present invention is not limited to this, and therefore the same discussion is applicable to the case where a P channel-type transistor is adopted by reversing voltage polarity.
(First Embodiment)
FIG. 1A shows the circuit constitution of an APS (Active Pixel Sensor)-type two-dimensional image sensor in one embodiment of the present invention. Although the image sensor incorporates a plurality of pixels disposed in matrix form, only two pixels 10 of two rows by one column are shown for easier understanding. Row direction corresponds to horizontal direction while column direction corresponds to vertical direction.
As shown in FIG. 2, each pixel 10 is composed of one photodiode (PD) 4 serving as a photon-electron conversion region, and three N channel-type MOS transistors (Tr) 1, 2, 3 (PD+3Tr type), more specifically, a MOS transistor for signal amplification 1, a MOS transistor for reset 2, and a MOS transistor for pixel selection 3.
The anode of the photodiode 4 is grounded and the cathode is connected to the MOS transistor for signal amplification 1. The MOS transistor for signal amplification 1 amplifies a signal representing a potential of the photodiode 4 (cathode potential, same in the following description). The MOS transistor for pixel selection 3 is disposed in between the MOS transistor for signal amplification 1 and a signal line 5 and serves for selection of the pixel. The MOS transistor for reset 2 is disposed in between the cathode of the photodiode 4 and a drain line 6, and serves for discharging charges of the photodiode 4 (charges in a cathode region, i.e., electrons, same in the following description) to a drain.
As shown in FIG. 1A, gates of the MOS transistors for reset 2 are each connected on a row basis to reset gate lines 8 extending in row direction. Two pulsed driving voltages φRG are sequentially applied to the gates of the MOS transistors for reset 2 on a row basis through the reset gate lines 8 by an unshown first scanning circuit. This enables gate potentials of the MOS transistors for reset 2 to be controlled on a row basis. It is to be noted that reference numeral (i), (i+1), . . . denote row numbers. The drains of the MOS transistors for reset 2 are each connected on a column basis to a drain line 6 extending in column direction. Two pulsed driving voltages Vp (that is a signal φRD shown in later described FIG. 3) are applied to the drains of the MOS transistors for reset 2 through the drain line 6 by an unshown voltage application portion. This enables the drain potentials of the MOS transistors for reset 2 to be controlled.
Moreover in this example, the drains of the MOS transistors for amplification 1 are also each connected on a column basis to the drain line 6 and share the drain line 6 with the MOS transistors for reset 2 (or it is also acceptable that the drain line 6 is not shared as described later). This enables the drain potentials of the MOS transistors for amplification 1 to be controlled by the driving voltage Vp.
Further, the gates of the MOS transistors for pixel selection 3 are each connected on a row basis to pixel selection lines 7 extending in row direction. Two pulsed driving voltages φSEL are sequentially applied to the gates of the MOS transistors for pixel selection 3 on a row basis through the pixel selection lines 7 by an unshown second scanning circuit. This enables gate potentials of the MOS transistors for pixel selection 3 to be controlled on a row basis. One terminals of the MOS transistors for pixel selection 3 (the terminals opposite to the MOS transistors for signal amplification 1) are each connected on a column basis to vertical signal lines 5 extending in column direction. A signal from a selected pixel is outputted through the vertical signal line 5.
The vertical signal line 5 is connected to a MOS transistor 30 that supplies a constant-current load (a voltage of VL1 is applied as a gate bias voltage as shown in FIG. 2).
A signal Vout outputted through the vertical signal line 5 is led to a correlated double sampling circuit 500. The correlated double sampling circuit 500 obtains a difference between a later-described readout signal level and readout reset level.
The overall operation of the two-dimensional image sensor is controlled by a CPU (Central Processing Unit) 90 serving as a control portion. In the case of a two-dimensional matrix disposition, the operation is typically performed on a row basis in one horizontal scanning period after another, and therefore if pixels are treated collectively, the operation is performed on the basis of one horizontal scanning period. However, in the view from a specified pixel, the operation is always performed per frame.
FIG. 3 shows operation timing of a given pixel by the control of the CPU 90. Herein, φSEL denotes a signal applied to the pixel selection line 7, φRG denotes a signal applied to the reset gate line 8, φRD denotes a signal applied to the drain line 6, ψPD denotes a potential of the photodiode 4, and Vout denotes a potential of the vertical signal line 5. A period for scanning one screen is expressed as a frame F. It is to be noted that reference numeral (n), (n+1), . . . represent frame numbers, and a preceding frame (indicating a frame immediately before a noticed frame) is referred to as F(n) and the noticed frame (indicating the frame that is noticed) as F (n+1).
The two-dimensional image sensor repeats, in every frame F, a signal level readout period TS1, a first reset period TR1, a reset level readout period TS2, a second reset period TR2, and a third reset period TR3 in this order. In the first reset period TR1 and the third reset period TR3, the MOS transistor for reset 2 is set to execute a soft reset operation, while in the second reset period TR2, the MOS transistor for reset 2 is set to execute a hard reset operation (as for bias setting, description will be given later).
Hereinbelow, description will be given focusing on the frame F(n+1).
i) First, in the signal level readout period TS1, a signal φSEL becomes high and the MOS transistor for pixel selection 3 is turned on. As a consequence, a potential level of the photodiode 4 is read out as a signal Vout to the signal line 5 through the MOS transistor for signal amplification 1 and the MOS transistor for pixel selection 3.
Herein, the reset operation executed at the end in the preceding frame F(n) is a soft reset operation in the third reset period TR3. Therefore, in the signal level readout period TS1 of the noticed frame F(n+1), read out is a potential level reached by charges stored in the photodiode 4 after the soft reset operation executed in the preceding frame F(n) (a signal read out at this point is referred to as a “readout signal level”).
ii) Next, in the first reset period TR1, the signal φSEL becomes low and the MOS transistor for pixel selection 3 is turned off. Then, the MOS transistor for reset 2 is set to execute a soft reset operation with a sub-threshold current.
iii) Next, in the reset level readout period TS2, the signal φSEL becomes high and the MOS transistor for pixel selection 3 is turned on. As a consequence, a potential level of the photodiode 4 is read out as a signal Vout to the signal line 5 through the MOS transistor for signal amplification 1 and the MOS transistor for pixel selection 3.
Herein, the potential level of the photodiode 4 is increased by the soft reset operation in the first reset period TR1 from the potential level after the signal level readout period TS1. Therefore, the increased potential level of the photodiode 4 is read out (a signal read out at this point is referred to as a “readout reset level”). In the soft reset operation, due to memory effect, a correlation is developed between reset noise after the last soft reset operation in the preceding frame F(n) and reset noise after the first soft reset operation in the noticed frame F(n+1). Accordingly, if Correlated Double Sampling (CDS) operation is performed to obtain a difference Veff between the readout signal level and the readout reset level, the reset noise is drastically reduced.
iv) Next, in the second reset period TR2, the signal φSEL becomes low and the MOS transistor for pixel selection 3 is turned off. Then, the MOS transistor for reset 2 is set to execute a hard reset operation so as to fix the potential of the photodiode 4 to a drain potential. Since the potential in the photodiode 4 is fixed to a drain potential, the problem of the image retention can be solved in this stage.
v) After that, in the third reset period TR3, the MOS transistor for reset 2 is set to execute a soft reset operation with a sub-threshold current. The charges stored in the photodiode 4 after execution of the soft rest operation is further read out in a frame immediately after the frame F(n+1).
In such a case, the problem of the image retention has already been solved in the second reset period TR2, and therefore image retention is confined to one frame. Therefore, the image retention is decreased and becomes substantially negligible.
Further, such control as repeating, in every frame F, the signal level readout period TS1, the first reset period TR1, the reset level readout period TS2, the second reset period TR2, and the third reset period TR3 in this order can be easily implemented by the CPU 90. Therefore, the two-dimensional image sensor is easily constituted without the necessity of using specific component parts or the like.
In first reset period TR1 and the third reset period TR3, in order to set an N channel-type MOS transistor for reset 2 to execute a soft reset operation, it is preferable that the gate potential of the MOS transistor for reset be high, the drain potential be high, and the channel potential ψRG (H) in the MOS transistor for reset 2 when the gate is in high potential state be lower than the drain potential ψRD (H) when the drain line 6 is in high level. It is to be noted that reference numeral (L) denotes a low level while (H) denotes a high level (same in the following description).
Further, in the reset level readout period TS2, in order to set an N channel-type MOS transistor for reset to execute a hard reset operation, it is preferable that the drain potential of the MOS transistor for reset become low level while the gate potential stay high, and channel potential ψRG (H) in the MOS transistor for reset when the gate potential is in high level be higher than the drain potential ψRD (L) when the drain line 6 is in low level.
More specifically, the relation of the following equation (4) should be satisfied.

ψRD(L)<ψRG(H)<ψRD(H)  (4)

Further, in the reset level readout period TS2, it is preferable that the drain potential of the N channel-type MOS transistor for reset 2 be in high state and the gate potential of the MOS transistor for reset 2 be in low state.
FIG. 4 is a schematic view showing change in potential of the photodiode 4 in a pixel in conformity to the operation shown in FIG. 3. It is to be noted that in FIG. 4, the potential is higher toward downside.
As shown in the drawing, the potential of the photodiode 4 in the last soft reset operation (third reset period TR3) in the preceding frame F(n) is set to a level SR2(n). By the charges stored according to optical input, the potential of the photodiode 4 becomes a level Sig(n+1) during signal readout (signal level readout period TS1) in the noticed frame F(n+1). During the first soft reset operation (first reset period TR1) after that, the potential of the photodiode 4 becomes SR1(n+1). Since a noise correlation is present between SR1(n) and SR1(n+1), reset noise can be drastically reduced if a difference is obtained as shown below:

Sig(n+1)−SR1(n+1)

After that, during hard reset operation (second reset period TR2), the potential of the photodiode 4 becomes HR(n+1), and image retention for one frame is deleted and is not carried over to the succeeding frames. More precisely, image retention is confined to one frame. During the last soft reset operation (third reset period TR3), the potential of the photodiode 4 becomes SR2(n+1). This is a reset operation for the succeeding frame.

Although in the above example, the drains of the MOS transistors for amplification 1 and the drains of the MOS transistors for reset 2 are each connected on a column basis to a shared drain line 6, the present invention is not limited thereto and therefore individual lines may be provided as shown in FIG. 1B. In the example of FIG. 1B, the drains of the MOS transistors for reset 2 are each connected on a row basis to reset drain lines 61 extending in row direction. Two pulsed driving voltages φRD are sequentially applied to the drains of the MOS transistors for reset 2 on a row basis through the reset drain lines 61 by an unshown third scanning circuit. This enables drain potentials of the MOS transistors for reset 2 to be controlled on a row basis. The drains of the MOS transistors for amplification 1 are each connected on a column basis to a drain line 62 extending in column direction. A DC voltage VD is applied to the drain of the MOS transistor for amplification 1 through the drain line 62. The circuit of FIG. 1B operates similarly to the circuit described with reference to FIGS. 3 and 4 except that the drain voltage of the MOS transistor for amplification 1 is fixed to VD.
Further, it should naturally be understood that field effect transistors other than the N channel-type MOS transistor can also be used as the transistors 1, 2 and 3.
(Second Embodiment)
In the aforementioned method in which the soft reset operation and hard reset operation are combined, image retention and reset noise are avoidable. However, there is the possibility that linearity of output signals with respect to incident optical signals might be damaged.
As shown in FIG. 5A and FIG. 5B in details, due to a sub-threshold current during the third reset period TR3, the photodiode potential ψPD (A) immediately after the period TR3 in the preceding frame F(n) becomes lower by ΔV1 (see FIG. 6) than the channel potential ψRG (H) obtained by the reset gate potential RG (H). The photodiode potential immediately before the first reset period TR1 in the noticed frame F(n+1) drops due to the charges generated by an incident optical signal during optical signal storage period TCHG after the third reset period TR3 in the preceding frame F(n). If the potential drop amount is not less than ΔV1, then the photodiode potential immediately after the first reset period TR1 in the noticed frame becomes ψPD (B) that is equal to ψPD (A).
However, if the potential drop amount during optical signal storage period TCHG is 0 because of, for example, the absence of incident optical signals, then the photodiode potential immediately before the first reset period TR1 in the noticed frame F(n+1) stays ψPD (A). Due to the sub-threshold current generated during the first reset period TR1 in the noticed frame F(n+1), the photodiode potential becomes ψPD (C) that is lower than the above stated ψPD (A) by ΔV2 (see FIG. 6). Moreover, if an incident light signal is small and so potential drop during the optical signal storage period TCHG is in the range from 0 to ΔV1, then the photodiode potential immediately after the first reset period TR1 in the noticed frame F(n+1) becomes a value between ψPD (B) and ψVPD (C)
FIG. 7 shows change in photodiode potential immediately after the first reset period TR1 in the noticed frame when incident light intensity is varied. It is to be noted that the photodiode potential immediately before the first reset period TR1 in the noticed frame is expressed by ψPD (S) as a readout signal level. Also the photodiode potential immediately after the first reset period TR1 in the noticed frame is expressed by ψPD (R) as a reset level. In this case, a pixel output signal Veff is expressed in the following equation (5):

Veff=ψPD(R)−ψPD(S)  (5)

As shown in FIG. 7, with ψPD (A) as an initial value, ψPD (S) linearly decreases in proportion to the increase in incident light intensity. If the incident light intensity is not less than P0 with which ψPD (S) changes from ψPD (A) by an amount of not less than ΔV1, then ψPD (R) becomes a constant value ψPD (B). However, if the incident light intensity is not more than P0, then ψPD (R) increases as the incident light intensity decreases and becomes ψPD (C), that is larger by ΔV2 than ψPD (A), when the incident light intensity reaches 0. Therefore, the pixel output signal Veff is linearly changed with respect to the incident light intensity if the incident light intensity is not less than P0, whereas the pixel output signal Veff is not linearly changed with respect to the incident light intensity if the incident light intensity is not more than P0. More precisely, when the incident light intensity is low (when the incident light intensity is in the range from 0 to P0), output signals cannot maintain linearity against incident optical signals.
Accordingly, in the following embodiment, description will be given of an amplification-type solid-state image pickup device capable of reducing both reset noise and image retention with a simple constitution as well as retaining linearity of output signals against incident optical signals.
This embodiment is different from the previous embodiment in the point that three pulsed driving voltages φRG, which take three values of V1, V2 and V4 (shown in FIG. 8) as described later, are applied to the gates of the MOS transistors for reset 2 through the reset gate lines 8. Other points are the same as the previous embodiment.
FIG. 12 shows the constitution of a reset gate voltage generation circuit serving as a voltage setting portion for generating the driving voltages φRG. The reset gate voltage generation circuit is composed of P channel-type MOS transistors 301, 302 and an N channel-type MOS transistor 303, one terminals of which are each connected to a node 311, and an N channel-type MOS transistor 304 connected in series to the transistor 303. The other terminals of the P channel-type MOS transistors 301, 302 are respectively connected to voltage supplies V1 and V2. The other terminal of the N channel-type MOS transistor 304 is connected to a voltage supply V4. The back gates of the P channel-type MOS transistors 301, 302 are each connected to a voltage supply VD, while the back gates of the N channel-type MOS transistors 303, 304 are each connected to the ground (0 potential). The relation of the voltages V1, V2, V4 and VD supplied by each supply voltage is VD>V1>V2>V4>0.
Control pulse signals φR1 taking the above stated two values, VD and 0, are applied to the gates of the P channel-type MOS transistor 301 and the N channel-type MOS transistor 303, while control pulse signals φR2 taking the above stated two values, VD and 0, are applied to the gates of the P channel-type MOS transistor 302 and the N channel-type MOS transistor 303.
The CPU 90 shown in FIG. 1A sequentially applies the control pulse signals φR1 and φR2 in conformity to the timing shown in FIG. 13, by which pulsed driving voltages φRG taking tree voltage values, V1, V2 and V4, are outputted from the node 311.
FIG. 8A shows operation timing of a given pixel by the control of the CPU 90. Herein, φSEL represents a signal applied to the pixel selection line 7, φRG represents a signal applied to the reset gate line 8, and φRD represents a signal applied to the drain line 6. FIG. 8B shows change in potential ψPD of the photodiode 4 in conformity to the timing shown in FIG. 8A. A period for scanning one screen is expressed as a frame F. It is to be noted that as with the previous embodiment, reference numeral (n), (n+1), . . . represent frame numbers, and a preceding frame is referred to as F(n) and a succeeding noticed frame as F (n+1).
The two-dimensional image sensor repeats, in every frame F, a signal level readout period TS1, a first reset period TR1, a reset level readout period TS2, a second reset period TR2, and a third reset period TR3 in this order. In the first reset period TR1 and the third reset period TR3, the MOS transistor for reset 2 is set to execute a soft reset operation, while in the second reset period TR2, the MOS transistor for reset 2 is set to execute a hard reset operation. Moreover, values of the reset gate potential φRG are V1 in the first reset period TR1, V2 in the second and third reset period TS2, and V4 in other period TR3.
Hereinbelow, description will be given focusing on the frame F(n+1).
i) First, in the signal level readout period TS1, a signal φSEL becomes high and the MOS transistor for pixel selection 3 is turned on. As a consequence, a potential level of the photodiode 4 is read out as a signal Vout to the signal line 5 through the MOS transistor for signal amplification 1 and the MOS transistor for pixel selection 3.
Herein, the reset operation executed at the end in the preceding frame F(n) is a soft reset operation in the third reset period TR3. (reset gate potential φRG=V2). Since the soft reset operation is executed in succession to the hard reset operation, the potential ψPD (A) of the photodiode 4 reached by the soft reset operation always stays constant regardless of the intensity of incident light (see the potential diagram in FIG. 9).
After lapse of an optical signal storage period TCHG for storing charges in the photodiode 4 in succession to the third reset period TR3 in the preceding frame F(n), a potential level ψPD (S) obtained by the charges stored in the photodiode 4 is read out in the signal level readout period TS1 in the noticed frame F(n+1) (the signal read out at this point is referred to as a “readout signal level”).
ii) Next, in the first reset period TR1, the signal φSEL becomes low and the MOS transistor for pixel selection 3 is turned off. Then, the MOS transistor for reset 2 is set to execute a soft reset operation with a sub-threshold current (reset gate potential φRG=V1).
With the relation of V1≧V2, the potential ψPD (D) of the photodiode 4 reached by the soft reset operation stays constant regardless of the intensity of incident light (i.e., a charge amount stored in photodiode 4 during the optical signal storage period TCHG) as with the case of executing the soft reset operation in succession to the hard reset operation.
It is to be noted that in order to ensure the independency of the photodiode potential ψPD (D) from the incident light intensity, a value of |V1−V2| should preferably be set larger than a difference ΔV1 between a channel potential ψ (V2) in the third reset period TR3 (when reset gate potential φRG=V2) and a potential ψPD (A) reached by the photodiode 4.
iii) Next, in the reset level readout period TS2, the signal φSEL becomes high and the MOS transistor for pixel selection 3 is turned on. As a consequence, a potential level ψPD (R) of the photodiode 4 is read out to the signal line 5 through the MOS transistor for signal amplification 1 and the MOS transistor for pixel selection 3. The signal ψPD (R) read out at this point is referred to as a “readout reset level”.
Herein, in the soft reset operation, due to memory effect, a correlation is developed between reset noise after the last soft reset operation in the preceding frame F(n) and reset noise after the first soft reset operation in the noticed frame F(n+1). Accordingly, if Correlated Double Sampling (CDS) operation is performed to obtain a difference Veff (this is called a “pixel output signal) between the readout signal level ψPD (S) and the readout reset level ψPD (R), the reset noise is drastically reduced. It is to be noted that in this case, the pixel output signal Veff is expressed in the following equation:

Veff=φPD(R)−ψPD(S)

Furthermore, as described before, both the potential of the photodiode 4 reached by the soft reset operation in the third reset period TR3 in the preceding frame F(n) and the potential (readout reset level) of the photodiode 4 reached by the soft reset operation in the first reset period TR1 in the noticed frame stay constant regardless of the intensity of incident light (i.e., a charge amount stored in the photodiode 4 during the optical signal storage period TCHG). Therefore, as shown in FIG. 10, a pixel output signal Veff expressed by a difference between the readout signal level ψPD (S) and the readout reset level ψPD (R) can be linearly changed with respect to the intensity of incident light.
iv) Next, in the second reset period TR2, the signal φSEL becomes low and the MOS transistor for pixel selection 3 is turned off. Then, the MOS transistor for reset 2 is set to execute a hard reset operation so as to fix the potential of the photodiode 4 to a drain potential. Since the potential in the photodiode 4 is fixed to a drain potential, the problem of the image retention can be solved in this stage.
v) After that, in the third reset period TR3, the MOS transistor for reset 2 is set to execute a soft reset operation with a sub-threshold current (reset gate potential φRG=V2). The charges stored in the photodiode 4 after execution of the soft rest operation is further read out in the frame immediately after the frame F(n+1).
In such a case, the problem of the image retention has already been solved in the second reset period TR2, and therefore image retention is confined to one frame. Therefore, the image retention is decreased and becomes substantially negligible.
Further, such control as repeating, in every frame F, the signal level readout period TS1, the first reset period TR1, the reset level readout period TS2, the second reset period TR2, and the third reset period TR3 in this order can be easily implemented by the CPU 90. Therefore, the two-dimensional image sensor is easily constituted without the necessity of using specific component parts or the like.
Although in the above example, the drains of the MOS transistors for amplification 1 and the drains of the MOS transistors for reset 2 are each connected on a column basis to a shared drain line 6, the present invention is not limited thereto and therefore individual lines may be provided as shown in FIG. 1B. In the example of FIG. 1B, the drains of the MOS transistors for reset 2 are each connected on a row basis to reset drain lines 61 extending in row direction. Two pulsed driving voltages φRD are sequentially applied to the drains of the MOS transistors for reset 2 on a row basis through the reset drain lines 61 by an unshown third scanning circuit. This enables drain potentials of the MOS transistors for reset 2 to be controlled on a row basis. The drains of the MOS transistors for amplification 1 are each connected on a column basis to a drain line 62 extending in column direction. A DC voltage VD is applied to the drain of the MOS transistor for amplification 1 through the drain line 62. The circuit of FIG. 1B operates similarly to the circuit described with reference to FIGS. 8A, 8B, 9 and 10 except that the drain voltage of the MOS transistor for amplification 1 is fixed to VD.
Further, it should naturally be understood that field effect transistors other than the N channel-type MOS transistor can also be used as the transistors 1, 2 and 3.
A difference |V2−V4| between V2 and V4, the values taken by the reset gate potential φRG shown in FIG. 8A, can be set arbitrarily. If the value of |V2−V4| is sufficiently large, then signal charges that are photon-electron converted during the optical signal storage period TCHG are linearly stored in the photodiode 4. More precisely, the amplification-type solid-state image pickup device exhibits a linear photon-electron conversion characteristic substantially in the entire region of the incident light intensity as shown by a reference numeral 80 in FIG. 11. If the value of |V2−V4| is dropped and falls within a certain range, then a sub-threshold operation is taken place in a region high in the intensity of incident light as shown by a reference numeral 81 in FIG. 11, and the potential of the photodiode 4 is logarithmically changed with respect to the intensity of incident light. More precisely, the amplification-type solid-state image pickup device is characterized by exhibiting both the linear photon-electron conversion characteristic substantially and logarithmic photon-electron conversion characteristic. If the value of |V2−V4| is sufficiently small, then a sub-threshold operation is taken place substantially in the entire region of the incident light intensity and the potential of the photodiode 4 is logarithmically changed with respect to the intensity of incident light. More precisely, the amplification-type solid-state image pickup device exhibits the logarithmic photon-electron conversion characteristic substantially in the entire region of the incident light intensity. Thus, if the value of |V2−V4| is set within a certain range, a sub-threshold operation is taken place in a region high in the intensity of incident light and the logarithmic photon-electron conversion characteristic is exhibited, whereas in the region low in the intensity of incident light, the linear photon-electron conversion characteristic is exhibited. This allows application of the amplification-type solid-state image pickup device either to logarithmic conversion-type image sensors and linear conversion-type image sensors.
It is to be understood that different reset gate potential φRG may be allotted to the second reset period TR2 and the third reset period TR3, and in such a case, the reset gate potential φRG in the third reset period TR3 may be set at V3 (provided that V3≠V2). In this case, the effects of the present invention can be achieved if the following two equations are satisfied:

|V1−Vt|≧|V2−Vt|≧|V4−Vt|

|V1−Vt|≧|V3−Vt|≧|V4|Vt|

This makes it possible to reduce both reset noise and image retention with a simple constitution as well as retaining linearity of output signals against incident optical signals. If the same reset gate potential φRG (V3=V2) is allotted to the second reset period TR2 and the third reset period TR3 like the above-stated embodiment, then a circuit for generating the reset gate potential φRG can be simplified.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

## Claims

1. An amplification-type solid-state image pickup device, comprising:
a plurality of arrayed pixels, each of the pixels being composed of at least a photon-electron conversion region, a field effect transistor for signal amplification for amplifying signals expressed by potentials of the photon-electron conversion region, a field effect transistor for reset for discharging charges in the photon-electron conversion region to a drain, and a field effect transistor for pixel selection; and
a control portion for executing control so that with respect to each frame in each of the pixels, there are repeated in the following order
a signal level readout period in which a potential level of the photon-electron conversion region is read through the field effect transistor for signal amplification,
a first reset period in which the field effect transistor for reset executes a soft reset operation with a sub-threshold current,
a reset level readout period in which a potential level of the photon-electron conversion region reached by the soft reset operation in the first reset period is read through the field effect transistor for signal amplification,
a second reset period in which the field effect transistor for reset executes a hard reset operation so as to fix the potential of the photon-electron conversion region to a drain potential, and
a third reset period in which the field effect transistor for reset executes a soft reset operation with a sub-threshold current.

2. The amplification-type solid-state image pickup device as defined in claim 1, further comprising
a correlated double sampling portion for performing a correlated double sampling operation on between a signal read out in the signal level readout period and a signal read out in the reset level readout period.

3. The amplification-type solid-state image pickup device as defined in claim 1, wherein
a plurality of the pixels are arrayed in matrix form,
gates of the field effect transistors for reset are each connected on a row basis to reset gate lines extending in row direction, and
there is provided a first scanning circuit for sequentially applying two pulsed driving voltages to the gates of the field effect transistors for reset on a row basis through the reset gate lines.

4. The amplification-type solid-state image pickup device as defined in claim 3, wherein
one terminals of the field effect transistors for pixel selection are each connected on a column basis to signal lines extending in column direction,
gates of the field effect transistors for pixel selection are each connected on a row basis to pixel selection lines extending in row direction, and
there is provided a second scanning circuit for sequentially applying two pulsed driving voltages to the gates of the field effect transistors for pixel selection on a row basis through the pixel selection lines.

5. The amplification-type solid-state image pickup device as defined in claim 3, wherein
drains of the field effect transistors for reset are each connected on a column basis to drain lines extending in column direction, and
there is provided a voltage application portion for applying two pulsed driving voltages to the drains of the field effect transistors for reset through the drain lines.

6. The amplification-type solid-state image pickup device as defined in claim 5, wherein
drains of the field effect transistors for amplification are each connected on a column basis to the drain lines.

7. The amplification-type solid-state image pickup device as defined in claim 3, wherein
drains of the field effect transistors for reset are each connected on a row basis to reset drain lines extending in row direction, and
there is provided a third scanning circuit for sequentially applying two pulsed driving voltages to the drains of the field effect transistors for reset on a row basis through the reset drain lines.

8. The amplification-type solid-state image pickup device as defined in claim 1, further comprising a voltage setting portion for setting voltages V1, V2 and V4 so as to satisfy a relation


|V1−Vt|≧|V2−Vt|≧|V4−Vt|


wherein V1 denotes a gate voltage of the field effect transistor for reset in the first reset period, V2 denotes a gate voltage of the field effect transistor for reset in the second reset period and the third reset period, V4 denotes a gate voltage of the field effect transistor for reset in periods other than the first and second reset periods, and Vt denotes a threshold gate voltage of the field effect transistor for reset.

9. The amplification-type solid-state image pickup device as defined in claim 8, wherein
the voltage setting portion sets a value of |V1−V2| to be larger than a specified value so that a potential of the photon-electron conversion region immediately after the first reset period stays constant regardless of intensity of incident light to the photon-electron conversion region.

10. The amplification-type solid-state image pickup device as defined in claim 8, wherein
the voltage setting portion sets a value of |V2−V4| within a specified range so that potential change of the photon-electron conversion region with respect to intensity of incident light is linear if the intensity of incident light is low whereas the potential change is logarithmic if the intensity of incident light is high.

11. The amplification-type solid-state image pickup device as defined in claim 8, further comprising
a correlated double sampling portion for performing a correlated double sampling operation on between a signal read out in the signal level readout period and a signal read out in the reset level readout period.

12. The amplification-type solid-state image pickup device as defined in claim 8, wherein
a plurality of the pixels are arrayed in matrix form,
gates of the field effect transistors for reset are each connected on a row basis to reset gate lines extending in row direction, and
the voltage setting portion includes a first scanning circuit for sequentially applying three pulsed driving voltages that are said V1, V2 and V4 to the gates of the field effect transistors for reset on a row basis through the reset gate lines.

13. The amplification-type solid-state image pickup device as defined in claim 12, wherein
one terminals of the field effect transistors for pixel selection are each connected on a column basis to signal lines extending in column direction,
gates of the field effect transistors for pixel selection are each connected on a row basis to pixel selection lines extending in row direction, and
there is provided a second scanning circuit for sequentially applying two pulsed driving voltages to the gates of the field effect transistors for pixel selection on a row basis through the pixel selection lines.

14. The amplification-type solid-state image pickup device as defined in claim 12, wherein
drains of the field effect transistors for reset are each connected on a column basis to drain lines extending in column direction, and
there is provided a voltage application portion for applying two pulsed driving voltages to the drains of the field effect transistors for reset through the drain lines.

15. The amplification-type solid-state image pickup device as defined in claim 14, wherein
drains of the field effect transistors for amplification are each connected on a column basis to the drain lines.

16. The amplification-type solid-state image pickup device as defined in claim 12, wherein
drains of the field effect transistors for reset are each connected on a row basis to reset drain lines extending in row direction, and
there is provided a third scanning circuit for sequentially applying two pulsed driving voltages to the drains of the field effect transistors for reset on a row basis through the reset drain lines.