# Patent

## Title
Load control device for a light-emitting diode light source

## Abstract

A method for controlling an amount of power delivered to an electrical load may include controlling an average magnitude of a load current towards a target load current that ranges from a maximum rated current to a minimum rated current in a normal mode, and controlling the average magnitude of the load current below the minimum rated current in a burst mode. The burst mode may include at least one burst mode period that comprises a first time period associated with an active state and a second time period associated with an inactive state. During the burst mode, the method may include regulating a peak magnitude of the load current towards the minimum rated current during the active state, and stopping the generation of at least one drive signal during the inactive state to control the average magnitude of the load current to be less than the minimum rated current.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of Non-Provisional application Ser. No. 14/974,853, filed Dec. 18, 2015, and patented as U.S. Pat. No. 9,538,600, issued Jan. 3, 2017, which is a continuation of U.S. Non-Provisional application Ser. No. 14/536,491, filed on Nov. 7, 2014, and patented as U.S. Pat. No. 9,247,608, issued Jan. 26, 2016, which claims the benefit of U.S. Provisional Application No. 62/032,229 filed on Aug. 1, 2014, and U.S. Provisional Application No. 61/901,480, filed on Nov. 8, 2013, all of which are incorporated by reference herein in their entirety.


BACKGROUND
Light-emitting diode (LED) light sources (i.e., LED light engines) are often used in place of or as replacements for conventional incandescent, fluorescent, or halogen lamps, and the like. LED light sources may comprise a plurality of light-emitting diodes mounted on a single structure and provided in a suitable housing. LED light sources are typically more efficient and provide longer operational lives as compared to incandescent, fluorescent, and halogen lamps. In order to illuminate properly, an LED driver control device (i.e., an LED driver) must be coupled between an alternating-current (AC) source and the LED light source for regulating the power supplied to the LED light source. The LED driver may regulate either the voltage provided to the LED light source to a particular value, the current supplied to the LED light source to a specific peak current value, or may regulate both the current and voltage.
LED light sources are typically rated to be driven via one of two different control techniques: a current load control technique or a voltage load control technique. An LED light source that is rated for the current load control technique is also characterized by a rated current (e.g., approximately 350 milliamps) to which the peak magnitude of the current through the LED light source should be regulated to ensure that the LED light source is illuminated to the appropriate intensity and color. In contrast, an LED light source that is rated for the voltage load control technique is characterized by a rated voltage (e.g., approximately 15 volts) to which the voltage across the LED light source should be regulated to ensure proper operation of the LED light source. Typically, each string of LEDs in an LED light source rated for the voltage load control technique includes a current balance regulation element to ensure that each of the parallel legs has the same impedance so that the same current is drawn in each parallel string.
It is known that the light output of an LED light source can be dimmed. Different methods of dimming LEDs include a pulse-width modulation (PWM) technique and a constant current reduction (CCR) technique. Pulse-width modulation dimming can be used for LED light sources that are controlled in either a current or voltage load control mode/technique. In pulse-width modulation dimming, a pulsed signal with a varying duty cycle is supplied to the LED light source. If an LED light source is being controlled using the current load control technique, the peak current supplied to the LED light source is kept constant during an on time of the duty cycle of the pulsed signal. However, as the duty cycle of the pulsed signal varies, the average current supplied to the LED light source also varies, thereby varying the intensity of the light output of the LED light source. If the LED light source is being controlled using the voltage load control technique, the voltage supplied to the LED light source is kept constant during the on time of the duty cycle of the pulsed signal in order to achieve the desired target voltage level, and the duty cycle of the load voltage is varied in order to adjust the intensity of the light output. Constant current reduction dimming is typically only used when an LED light source is being controlled using the current load control technique. In constant current reduction dimming, current is continuously provided to the LED light source, however, the DC magnitude of the current provided to the LED light source is varied to thus adjust the intensity of the light output. Examples of LED drivers are described in greater detail in commonly-assigned U.S. Pat. No. 8,492,987, issued Jul. 23, 2010, and U.S. Patent Application Publication No. 2013/0063047, published Mar. 14, 2013, both entitled LOAD CONTROL DEVICE FOR A LIGHT-EMITTING DIODE LIGHT SOURCE, the entire disclosures of which are hereby incorporated by reference.
SUMMARY
As described herein, a method may be used to control the amount of power delivered to an electrical load in a normal mode and in a burst mode. The method may include controlling a magnitude of a load current conducted through the electrical load to control the amount of power delivered to the electrical load, for example, by controlling an average magnitude of the load current conducted through the electrical load. In the normal mode, the method may include regulating the average magnitude of the load current towards a target load current. The target load current may range from a maximum rated current to a minimum rated current. In the burst mode, the method may include controlling the load current in an active state and in an inactive state to regulate the average magnitude of the load current below the minimum rated current. The burst mode may comprise periods of the active state and periods of the inactive state. For example, the method may include regulating a peak magnitude of the load current towards the minimum rated current during the first period using a feedback signal generated by a control loop. Regulation of the load current may stop during a second period such that the average magnitude of the load current is below the minimum rated current.
A method may be used to control the amount of power delivered to an electrical load in a normal mode and in a burst mode. The method may include controlling a magnitude of a load current conducted through the electrical load to control the amount of power delivered to the electrical load. The method may include controlling an average magnitude of the load current conducted through the electrical load. In the burst mode, the method may include controlling the load current in an active state and in an inactive state to regulate the average magnitude of the load current below the minimum rated current. The burst mode may comprise periods of the active state and periods of the inactive state. The duration of the active state of the burst mode period may be determined based on a burst duty cycle. In the normal mode, the method may include holding the burst duty cycle and adjusting the target load current according to a target amount of power to be delivered to the electrical load. In the burst mode, the method may include adjusting the burst duty cycle and/or the target load current. For example, in the burst mode, the method may include determining a current offset that ranges from a minimum current offset to a maximum current offset based on the burst duty cycle and the target amount of power to be delivered to the electrical load and adjusting the target load current by the current offset.
A method may be used to control the amount of power delivered to an electrical load in a normal mode and in a burst mode. The method may include controlling an average magnitude of the load current conducted through the electrical load. In the normal mode, the method may include regulating the average magnitude of the load current between a maximum rated current and a minimum rated current. In the burst mode, the method may include regulating a peak magnitude of the load current towards a target load current during a first period of the burst mode and stopping regulating the load current during a second period of the burst mode such that the average magnitude of the load current is below the minimum rated current. The method may include increasing the magnitude of the load current from an initial current to the target load current over a ramp time period at a beginning of the first period of the burst mode.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified block diagram of a light-emitting diode (LED) driver for controlling the intensity of an LED light source.
FIG. 2 is an example plot of a target load current of the LED driver of FIG. 1 as a function of a target intensity.
FIG. 3 is an example plot of a burst duty cycle of the LED driver of FIG. 1 as a function of the target intensity.
FIG. 4 is an example state diagram illustrating the operation of a load regulation circuit of the LED driver of FIG. 1 when operating in a burst mode.
FIG. 5 is a simplified schematic diagram of an isolated forward converter and a current sense circuit of an LED driver.
FIG. 6 is an example diagram illustrating a magnetic core set of an energy-storage inductor of a forward converter.
FIG. 7 shows example waveforms illustrating the operation of a forward converter and a current sense circuit when the intensity of an LED light source is near a high-end intensity.
FIG. 8 shows example waveforms illustrating the operation of a forward converter and a current sense circuit when the intensity of an LED light source is near a low-end intensity.
FIG. 9 is an example plot of a relationship between an offset time and a target intensity of an LED driver.
FIG. 10 is an example plot of an alternative relationship between the offset time and the target intensity of an LED driver.
FIG. 11 shows example waveforms illustrating the operation of a forward converter of an LED driver when operating in a burst mode.
FIG. 12A is a diagram of an example waveform illustrating the load current LOAD when a load regulation circuit is operating in a burst mode.
FIG. 12B is a diagram of an example waveform illustrating the load current LOAD when a load regulation circuit is operating in a burst mode.
FIG. 12C is example waveforms illustrating an example of how a load control circuit may determine the current offset when holding the active state period constant during burst mode.
FIG. 13 is an example of a plot relationship between a target load current and the burst duty cycle, and the target intensity of a light source.
FIG. 14A is an example waveform illustrating an overshoot in a load current conducted through a light source.
FIG. 14B is an example waveform illustrating control of a rise time of a load current conducted through a light source at the beginning of each active state period during burst mode.
FIGS. 15A, 15B, 16, 17A, 17B, and 18 are simplified flowcharts of example procedures for operating a forward converter of an LED driver in a normal mode and a burst mode.



DETAILED DESCRIPTION
FIG. 1 is a simplified block diagram of a load control device, e.g., a light-emitting diode (LED) driver 100, for controlling the amount of power delivered to an electrical load, such as, an LED light source 102 (e.g., an LED light engine), and thus the intensity of the electrical load. The LED light source 102 is shown as a plurality of LEDs connected in series but may comprise a single LED or a plurality of LEDs connected in parallel or a suitable combination thereof, depending on the particular lighting system. The LED light source 102 may comprise one or more organic light-emitting diodes (OLEDs). The LED driver 100 may comprise a hot terminal H and a neutral terminal that are adapted to be coupled to an alternating-current (AC) power source (not shown).
The LED driver 100 may comprise a radio-frequency (RFI) filter circuit 110, a rectifier circuit 120, a boost converter 130, a load regulation circuit 140, a control circuit 150, a current sense circuit 160, a memory 170, a communication circuit 180, and/or a power supply 190. The RFI filter circuit 110 may minimize the noise provided on the AC mains. The rectifier circuit 120 may generate a rectified voltage VRECT.
The boost converter 130 may receive the rectified voltage VRECT and generate a boosted direct-current (DC) bus voltage VBUS across a bus capacitor CBUS. The boost converter 130 may comprise any suitable power converter circuit for generating an appropriate bus voltage, such as, for example, a flyback converter, a single-ended primary-inductor converter (SEPIC), a Ćuk converter, or other suitable power converter circuit. The boost converter 120 may operate as a power factor correction (PFC) circuit to adjust the power factor of the LED driver 100 towards a power factor of one.
The load regulation circuit 140 may receive the bus voltage VBUS and control the amount of power delivered to the LED light source 102, for example, to control the intensity of the LED light source 102 between a low-end (i.e., minimum) intensity LLE (e.g., approximately 1-5%) and a high-end (i.e., maximum) intensity LHE (e.g., approximately 100%). An example of the load regulation circuit 140 may be an isolated, half-bridge forward converter. An example of the load control device (e.g., LED driver 100) comprising a forward converter is described in greater detail in commonly-assigned U.S. patent application Ser. No. 13/935,799, filed Jul. 5, 2013, entitled LOAD CONTROL DEVICE FOR A LIGHT-EMITTING DIODE LIGHT SOURCE, the entire disclosure of which is hereby incorporated by reference. The load regulation circuit 140 may comprise, for example, a buck converter, a linear regulator, or any suitable LED drive circuit for adjusting the intensity of the LED light source 102.
The control circuit 150 may be configured to control the operation of the boost converter 130 and/or the load regulation circuit 140. An example of the control circuit 150 may be a controller. The control circuit 150 may comprise, for example, a digital controller or any other suitable processing device, such as, for example, a microcontroller, a programmable logic device (PLD), a microprocessor, an application specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The control circuit 150 may generate a bus voltage control signal VBUS-CNTL, which may be provided to the boost converter 130 for adjusting the magnitude of the bus voltage VBUS. The control circuit 150 may receive a bus voltage feedback control signal VBUS-FB from the boost converter 130, which may indicate the magnitude of the bus voltage VBUS.
The control circuit 150 may generate drive control signals VDRIVE1, VDRIVE2. The drive control signals VDRIVE1, VDRIVE2 may be provided to the load regulation circuit 140 for adjusting the magnitude of a load voltage VLOAD generated across the LED light source 102 and the magnitude of a load current ILOAD conducted through the LED light source 120, for example, to control the intensity of the LED light source 120 to a target intensity LTRGT. The control circuit 150 may adjust an operating frequency for and/or a duty cycle DCINV (e.g., an on time TON) of the drive control signals VDRIVE1, VDRIVE2 to adjust the magnitude of the load voltage VLOAD and/or the load current ILOAD.
The current sense circuit 160 may receive a sense voltage VSENSE generated by the load regulation circuit 140. The sense voltage VSENSE may indicate the magnitude of the load current ILOAD. The current sense circuit 160 may receive a signal-chopper control signal VCHOP from the control circuit 150. The current sense circuit 160 may generate a load current feedback signal VI-LOAD, which may be a DC voltage indicating the average magnitude IAVE of the load current ILOAD. The control circuit 150 may receive the load current feedback signal VI-LOAD from the current sense circuit 160 and control the drive control signals VDRIVE1, VDRIVE2 accordingly. For example, the control circuit 150 may control the drive control signals VDRIVE1, VDRIVE2 to adjust a magnitude of the load current ILOAD to a target load current ITRGT to thus control the intensity of the LED light source 102 to the target intensity LTRGT (e.g., using a control loop).
The load current ILOAD may be the current that is conducted through the LED light source 120. The target load current ITRGT may be the current that the control circuit 150 would ideally like to conduct through the LED light source 120 (e.g., based at least on the load current feedback signal VI-LOAD). The control circuit 150 may be limited to specific levels of granularity in which it can control the current conducted through the LED light source 120 (e.g., due to inverter cycle lengths, etc.), so the control circuit 150 may not always be able to achieve the target load current ITRGT. For example, FIGS. 2 and 13 illustrate the current conducted through an LED light source as a linear graph (at least in parts), and as such, illustrate the target load current ITRGT since the load current ILOAD itself may not actually follow a true linear path. Further, non-ideal reactions of the LED light source 120 (e.g., an overshoot in the load current ILOAD, for example, as shown in FIG. 14A) may cause the load current ILOAD to deviate from the target load current ITRGT. In the ideal situation, the load current ILOAD is approximately equal to the target load current ITRGT.
The control circuit 150 may be coupled to the memory 170. The memory 170 may store operational characteristics of the LED driver 100 (e.g., the target intensity LTRGT, the low-end intensity LLE, the high-end intensity LHE, etc.). The communication circuit 180 may be coupled to, for example, a wired communication link or a wireless communication link, such as a radio-frequency (RF) communication link or an infrared (IR) communication link. The control circuit 150 may be configured to update the target intensity LTRGT of the LED light source 102 and/or the operational characteristics stored in the memory 170 in response to digital messages received via the communication circuit 180. The LED driver 100 may be operable to receive a phase-control signal from a dimmer switch for determining the target intensity LTRGT for the LED light source 102. The power supply 190 may receive the rectified voltage VRECT and generate a direct-current (DC) supply voltage VCC for powering the circuitry of the LED driver 100.
FIG. 2 is an example plot of the target load current ITRGT as a function of the target intensity LTRGT. The magnitude of the load current ILOAD may only be regulated to values between a maximum rated current IMAX and a minimum rated current IMIN, for example, due to hardware limitations of the load regulation circuit 140 and the control circuit 150. Thus, the target load current ITRGT may only be adjusted between the maximum rated current IMAX and the minimum rated current IMIN. When the target intensity LTRGT is between the high-end intensity LHE (e.g., approximately 100%) and a transition intensity LTRAN (e.g., approximately 5%), the control circuit 150 may operate the load regulation circuit 140 in a normal mode in which an average magnitude IAVE of the load current ILOAD is controlled to be equal to the target load current ITRGT. In the normal mode, the control circuit 150 may adjust the average magnitude IAVE of the load current ILOAD to the target load current ITRGT in response to the load current feedback signal VI-LOAD, e.g., using closed loop control. The control circuit 150 may adjust the target load current ITRGT between the maximum rated current IMAX and the minimum rated current IMIN in the normal mode, for example, as shown in FIG. 2.
FIG. 3 is an example plot of a burst duty cycle DCBURST (e.g., an ideal burst duty cycle DCBURST-IDEAL) as a function of the target intensity LTRGT. When the target intensity LTRGT is between the high-end intensity LHE (e.g., approximately 100%) and a transition intensity LTRAN (e.g., approximately 5%), the control circuit 150 may be configured to operate the load regulation circuit 140 to set the burst duty cycle DCBURST equal to a maximum duty cycle DCMAX (e.g., approximately 100%). To adjust the target intensity LTRGT below the transition intensity LTRAN, the control circuit 150 may be configured to operate the load regulation circuit 140 in a burst mode to reduce the average magnitude IAVE of the load current ILOAD to be less the minimum rated current IMIN. For example, to adjust the target intensity LTRGT below the transition intensity LTRAN, the control circuit 150 may be configured to operate the load regulation circuit 140 to reduce the burst duty cycle DCBURST below the maximum duty cycle DCMAX. For example, the load regulation circuit 140 may adjust the burst duty cycle DCBURST between the maximum duty cycle DCMAX (e.g., approximately 100%) and a minimum duty cycle DCMIN (e.g., approximately 20%). In the burst mode, a peak magnitude IPK of the load current ILOAD may be equal to the target current ITRGT (e.g., the minimum rated current IMIN). For example, the peak magnitude IPK of the load current ILOAD may be equal to the minimum rated current IMIN during an active state of the burst mode.
With reference to FIG. 3, the burst duty cycle DCBURST may refer to an ideal burst duty cycle DCBURST-IDEAL, which may include an integer portion DCBURST-INTEGER and/or a fractional portion DCBURST-FRACTIONAL. The integer portion DCBURST-INTEGER may be characterized by the percentage of the ideal burst duty cycle DCBURST-IDEAL that includes complete inverter cycles (i.e., an integer value of inverter cycles). The fractional portion DCBURST-FRACTIONAL may be characterized by the percentage of the ideal burst duty cycle DCBURST-IDEAL that includes a fraction of an inverter cycle. As described herein, the control circuit 150 (e.g., via the load regulation circuit 140) may be configured to adjust the number of inverter cycles only by an integer number (i.e., by DCBURST-INTEGER) and not a fractional amount (i.e., DCBURST-FRACTIONAL). Therefore, the example plot of FIG. 3 may illustrate an ideal curve showing the adjustment of the ideal burst duty cycle DCBURST-IDEAL from a maximum duty cycle DCMAX to a minimum duty cycle DCMIN when the target intensity LTRGT is below the transition intensity LTRAN. Nonetheless, unless defined differently, burst duty cycle DCBURST may refer to the integer portion DCBURST-INTEGER of the ideal burst duty cycle DCBURST-IDEAL, for example, if the control circuit 150 is not be configured to operate the burst duty cycle DCBURST at fractional amounts.
FIG. 4 is an example state diagram illustrating the operation of the load regulation circuit 140 in the burst mode. During the burst mode, the control circuit 150 may periodically control the load regulation circuit 140 into an active state and an inactive state, e.g., in dependence upon a burst duty cycle DCBURST and a burst mode period TBURST (e.g., approximately 4.4 milliseconds). For example, the active state period (TACTIVE) may be equal to the burst duty cycle (DCBURST) times the burst mode period (TBURST) and the inactive state period (TINACTIVE) may be equal to one minus the burst duty cycle (DCBURST) times the burst mode period (TBURST). That is, TACTIVE=DCBURST·TBURST and TINACTIVE (1−DCBURST)·TBURST.
In the active state of the burst mode, the control circuit 150 may generate (e.g., actively generate) the drive control signals VDRIVE1, VDRIVE2 to adjust the magnitude (e.g., the peak magnitude IPK) of the load current LOAD, e.g., using closed loop control. For example, in the active state of the burst mode, the control circuit 150 may generate the drive signals VDRIVE1, VDRIVE2 to adjust the magnitude of the load current ILOAD to be equal to a target load current ITRGT (e.g., the minimum rated current IMIN) in response to the load current feedback signal VI-LOAD.
In the inactive state of the burst mode, the control circuit 150 may freeze the control loop and may not generate the drive control signals VDRIVE1, VDRIVE2, for example, such that the magnitude of the load current ILOAD drops to approximately zero amps. While the control loop is frozen (e.g., in the inactive state), the control circuit 150 may not adjust the values of the operating frequency for and/or the duty cycle DCINV in response to the load current feedback signal VI-LOAD (e.g., even though the control circuit 150 is not presently generating the drive signals VDRIVE1, VDRIVE2). For example, the control circuit 150 may store the present duty cycle DCINV (e.g., the present on time TON) of the drive control signals VDRIVE1, VDRIVE2 in the memory 170 prior to (e.g., immediately prior to) freezing the control loop. Accordingly, when the control loop is unfrozen (e.g., when the control circuit 150 enters the active state), the control circuit 150 may continue to generate the drive control signals VDRIVE1, VDRIVE2 using the operating frequency for and/or the duty cycle DCINV from the previous active state.
The control circuit 150 may be configured to adjust the burst duty cycle DCBURST using an open loop control. For example, the control circuit 150 may be configured to adjust the burst duty cycle DCBURST as a function of the target intensity LTRGT, for example, when the target intensity LTRGT is below the transition intensity LTRAN. The control circuit 150 may be configured to linearly decrease the burst duty cycle DCBURST as the target intensity LTRGT is decreased below the transition intensity LTRAN (e.g., as shown in FIG. 3), while the target load current ITRGT is held constant at the minimum rated current IMIN (e.g., as shown in FIG. 2). Since the control circuit 150 changes between the active state and the inactive state in dependence upon the burst duty cycle DCBURST and the burst mode period TBURST (e.g., as shown in the state diagram of FIG. 4), the average magnitude IAVE of the load current ILOAD may be a function of the burst duty cycle DCBURST (e.g., IAVE=DCBURST·IMIN). During the burst mode, the peak magnitude IPK of the load current LOAD may be equal to the minimum rated current IMIN, but the average magnitude IAVE of the load current ILOAD may be less than the minimum rated current IMIN.
FIG. 5 is a simplified schematic diagram of a forward converter 240 and a current sense circuit 260 of an LED driver (e.g., the LED driver 100 shown in FIG. 1). The forward converter 240 may be an example of the load regulation circuit 140 of the LED driver 100 shown in FIG. 1. The current sense circuit 260 may be an example of the current sense circuit 160 of the LED driver 100 shown in FIG. 1.
The forward converter 240 may comprise a half-bridge inverter circuit having two field effect transistors (FETs) Q210, Q212 for generating a high-frequency inverter voltage VINV from the bus voltage VBUS. The FETs Q210, Q212 may be rendered conductive and non-conductive in response to the drive control signals VDRIVE1, VDRIVE2. The drive control signals VDRIVE1, VDRIVE2 may be received from the control circuit 150. The drive control signals VDRIVE1, VDRIVE2 may be coupled to the gates of the respective FETs Q210, Q212 via a gate drive circuit 214 (e.g., which may comprise part number L6382DTR, manufactured by ST Microelectronics). The control circuit 150 may generate the inverter voltage VINV at a constant operating frequency for (e.g., approximately 60-65 kHz) and thus a constant operating period TOP. However, the operating frequency for may be adjusted under certain operating conditions. The control circuit 150 may be configured to adjust a duty cycle DCINV of the inverter voltage VINV to control the intensity of an LED light source 202 towards the target intensity LTRGT.
In a normal mode of operation, when the target intensity LTRGT of the LED light source 202 is between the high-end intensity LHE and the transition intensity LTRAN, the control circuit 150 may adjust the duty cycle DCINV of the inverter voltage VINV to adjust the magnitude (e.g., the average magnitude IAVE) of the load current ILOAD towards the target load current ITRGT. As previously mentioned, the magnitude of the load current ILOAD may vary between the maximum rated current IMAX and the minimum rated current IMIN (e.g., as shown in FIG. 2). At the minimum rated current IMIN (e.g., at the transition intensity LTRAN), the inverter voltage VINV may be characterized by a transition operating frequency fOP-T, a transition operating period TOP-T, and a transition duty cycle DCINV-T.
When the target intensity LTRGT of the LED light source 202 is below the transition intensity LTRAN, the control circuit 150 may be configured to operate the forward converter 240 in a burst mode of operation. In one or more embodiments, the control circuit 150 may use power (e.g., a transition power) and/or current (e.g., a transition current) as a threshold to determine when to operate in burst mode (e.g., instead of intensity). In the burst mode of operation, the control circuit 150 may be configured to switch the forward converter 240 between an active mode (e.g., in which the control circuit 150 actively generates the drive control signals VDRIVE1, VDRIVE2 to regulate the peak magnitude IPK of the load current ILOAD to be equal to the minimum rated current IMIN) and an inactive mode (e.g., in which the control circuit 150 freezes the control loop and does not generate the drive control signals VDRIVE1, VDRIVE2), for example, as shown in the state diagram of FIG. 4. In the burst mode, the control circuit 150 may change the forward converter 240 between the active state and the inactive state in dependence upon a burst duty cycle DCBURST and a burst mode period TBURST (e.g., as shown in FIG. 4) and adjust the burst duty cycle DCBURST as a function of the target intensity LTRGT, which is below the transition intensity LTRAN (e.g., as shown in FIG. 3). In the normal mode and in the active state of the burst mode, the forward converter 240 may be characterized by a turn-on time TTURN-ON and a turn-off time TTURN-OFF. The turn-on time TTURN-ON may be a time period from when the drive control signals VDRIVE1, VDRIVE2 are driven until the respective FET Q210, Q212 is rendered conductive. The turn-off time TTURN-OFF may be a time period from when the drive control signals VDRIVE1, VDRIVE2 are driven until the respective FET Q210, Q212 is rendered non-conductive.
The inverter voltage VINV is coupled to the primary winding of a transformer 220 through a DC-blocking capacitor C216 (e.g., which may have a capacitance of approximately 0.047 g), such that a primary voltage VPRI is generated across the primary winding. The transformer 220 may be characterized by a turns ratio nTURNS (i.e., N1/N2), which may be approximately 115:29. A sense voltage VSENSE may be generated across a sense resistor R222, which may be coupled in series with the primary winding of the transformer 220. The FETs Q210, Q212 and the primary winding of the transformer 220 may be characterized by parasitic capacitances CP1, CP2, CP3, respectively. The secondary winding of the transformer 220 may generate a secondary voltage. The secondary voltage may be coupled to the AC terminals of a full-wave diode rectifier bridge 224 for rectifying the secondary voltage generated across the secondary winding. The positive DC terminal of the rectifier bridge 224 may be coupled to the LED light source 202 through an output energy-storage inductor L226 (e.g., which may have an inductance of approximately 10 mH), such that the load voltage VLOAD may be generated across an output capacitor C228 (e.g., which may have a capacitance of approximately 3 g).
The current sense circuit 260 may comprise an averaging circuit for producing the load current feedback signal VI-LOAD. The averaging circuit may comprise a low-pass filter comprising a capacitor C230 (e.g., which may have a capacitance of approximately 0.066 uF) and a resistor R232 (e.g., which may have a resistance of approximately 3.32 kΩ). The low-pass filter may receive the sense voltage VSENSE via a resistor R234 (e.g., which may have a resistance of approximately 1 kΩ). The current sense circuit 160 may comprise a transistor Q236 (e.g., a FET as shown in FIG. 5) coupled between the junction of the resistors R232, R234 and circuit common. The gate of the transistor Q236 may be coupled to circuit common through a resistor R238 (e.g., which may have a resistance of approximately 22 kΩ). The gate of the transistor Q236 may receive the signal-chopper control signal VCHOP from the control circuit 150. An example of the current sense circuit 260 may be described in greater detail in commonly-assigned U.S. patent application Ser. No. 13/834,153, filed Mar. 15, 2013, entitled FORWARD CONVERTER HAVING A PRIMARY-SIDE CURRENT SENSE CIRCUIT, the entire disclosure of which is hereby incorporated by reference.
FIG. 6 is an example diagram illustrating a magnetic core set 290 of an energy-storage inductor (e.g., the output energy-storage inductor L226 of the forward converter 240 shown in FIG. 5). The magnetic core set 290 may comprise two E-cores 292A, 292B, and may comprise part number PC40EE16-Z, manufactured by TDK Corporation. The E-cores 292A, 292B may comprise respective outer legs 294A, 294B and inner legs 296A, 296B. Each inner leg 296A, 296B may be characterized by a width wLEG (e.g., approximately 4 mm). The inner leg 296A of the first E-core 292A may comprise a partial gap 298A (i.e., the magnetic core set 290 is partially-gapped), such that the inner legs 296A, 296B are spaced apart by a gap distance dGAP (e.g., approximately 0.5 mm). The partial gap 298A may extend for a gap width wGAP (e.g., approximately 2.8 mm) such that the partial gap 298A extends for approximately 70% of the leg width wLEG of the inner leg 296A. In one or more embodiments, both of the inner legs 296A, 296B may comprise partial gaps. The partially-gapped magnetic core set 290 (e.g., as shown in FIG. 6) may allow the output energy-storage inductor L226 of the forward converter 240 (e.g., shown in FIG. 5) to maintain continuous current at low load conditions (e.g., near the low-end intensity LLE).
FIG. 7 shows example waveforms illustrating the operation of a forward converter and a current sense circuit, for example, the forward converter 240 and the current sense circuit 260 shown in FIG. 5. For example, the forward converter 240 may generate the waveforms shown in FIG. 7 when operating in the normal mode and in the active state of the burst mode as described herein. As shown in FIG. 7, a control circuit (e.g., the control circuit 150) may drive the respective drive control signals VDRIVE1, VDRIVE2 high to approximately the supply voltage VCC to render the respective FETs Q210, Q212 conductive for an on time TON at different times (i.e., the FETs Q210, Q212 are conductive at different times). When the high-side FET Q210 is conductive, the primary winding of the transformer 220 may conduct a primary current IPRI to circuit common through the capacitor C216 and sense resistor R222. After (e.g., immediately after) the high-side FET Q210 is rendered conductive (at time t1 in FIG. 7), the primary current IPRI may conduct a short high-magnitude pulse of current due to the parasitic capacitance CP3 of the transformer 220 as shown in FIG. 7. While the high-side FET Q210 is conductive, the capacitor C216 may charge, such that a voltage having a magnitude of approximately half of the magnitude of the bus voltage VBUS is developed across the capacitor. Accordingly, the magnitude of the primary voltage VPRI across the primary winding of the transformer 220 may be equal to approximately half of the magnitude of the bus voltage VBUS (i.e., VBUS/2). When the low-side FET Q212 is conductive, the primary winding of the transformer 220 may conduct the primary current IPRI in an opposite direction and the capacitor C216 may be coupled across the primary winding, such that the primary voltage VPRI may have a negative polarity with a magnitude equal to approximately half of the magnitude of the bus voltage VBUS.
When either of the high-side and low-side FETs Q210, Q212 are conductive, the magnitude of an output inductor current IL conducted by the output inductor L226 and the magnitude of the load voltage VLOAD across the LED light source 202 may increase with respect to time. The magnitude of the primary current IPRI may increase with respect to time while the FETs Q210, Q212 are conductive (e.g., after an initial current spike). When the FETs Q210, Q212 are non-conductive, the output inductor current IL and the load voltage VLOAD may decrease in magnitude with respective to time. The output inductor current IL may be characterized by a peak magnitude IL-PK and an average magnitude IL-AVG, for example, as shown in FIG. 7. The control circuit 150 may increase and/or decrease the on times TON of the drive control signals VDRIVE1, VDRIVE2 (e.g., and the duty cycle DCINV of the inverter voltage VINV) to respectively increase and decrease the average magnitude IL-AVG of the output inductor current IL, and thus respectively increase and decrease the intensity of the LED light source 202.
When the FETs Q210, Q212 are rendered non-conductive, the magnitude of the primary current IPRI may drop toward zero amps (e.g., as shown at time t2 in FIG. 7 when the high-side FET Q210 is rendered non-conductive). However, a magnetizing current IMAG may continue to flow through the primary winding of the transformer 220 due to the magnetizing inductance LMAG of the transformer. When the target intensity LTRGT of the LED light source 102 is near the low-end intensity LLE, the magnitude of the primary current IPRI may oscillate after either of the FETs Q210, Q212 is rendered non-conductive, for example, due to the parasitic capacitances CP1, CP2 of the FETs, the parasitic capacitance CP3 of the primary winding of the transformer 220, and/or any other parasitic capacitances of the circuit, such as, parasitic capacitances of the printed circuit board on which the forward converter 240 is mounted.
The real component of the primary current IPRI may indicate the magnitude of the secondary current ISEC and thus the intensity of the LED light source 202. However, the magnetizing current IMAG (i.e., the reactive component of the primary current IPRI) may also flow through the sense resistor R222. The magnetizing current IMAG may change from a negative polarity to a positive polarity when the high-side FET Q210 is conductive, change from a positive polarity to a negative polarity when the low-side FET Q212 is conductive, and remain constant when the magnitude of the primary voltage VPRI is zero volts, for example, as shown in FIG. 7. The magnetizing current IMAG may have a maximum magnitude defined by the following equation:




  
    I
    
      MAG
      ⁢
      
        -
      
      ⁢
      MAX
    
  
  =
  
    
      
        
          V
          BUS
        
        ·
        
          T
          HC
        
      
      
        4
        ·
        
          L
          MAG
        
      
    
    .
  




where THC may be the half-cycle period of the inverter voltage VINV, i.e., THC=TOP/2. As shown in FIG. 7, the areas 250, 252 are approximately equal, such that the average value of the magnitude of the magnetizing current IMAG is zero during the period of time when the magnitude of the primary voltage VPRI is greater than approximately zero volts (e.g., during the ton time TON as shown in FIG. 7).

The current sense circuit 260 may determine an average the primary current IPRI during the positive cycles of the inverter voltage VINV, i.e., when the high-side FET Q210 is conductive (e.g., during the on time TON). The load current feedback signal VI-LOAD, which may be generated by the current sense circuit 260, may have a DC magnitude that is the average value of the primary current IPRI when the high-side FET Q210 is conductive. Because the average value of the magnitude of the magnetizing current IMAG is approximately zero during the period of time that the high-side FET Q210 is conductive (e.g., during the on time TON), the load current feedback signal VI-LOAD generated by the current sense circuit indicates the real component (e.g., only the real component) of the primary current IPRI during the on time TON.
When the high-side FET Q210 is rendered conductive, the control circuit 150 may drive the signal-chopper control signal Vamp low towards circuit common to render the transistor Q236 of the current sense circuit 260 non-conductive for a signal-chopper time TCHOP. The signal-chopper time TCHOP may be approximately equal to the on time TON of the high-side FET Q210, for example, as shown in FIG. 7. The capacitor C230 may charge from the sense voltage VSENSE through the resistors R232, R234 while the signal-chopper control signal VCHOP is low, such that the magnitude of the load current feedback signal VI-LOAD is the average value of the primary current IPRI and thus indicates the real component of the primary current during the time when the high-side FET Q210 is conductive. When the high-side FET Q210 is not conductive, the control circuit 150 drives the signal-chopper control signal Vamp high to render the transistor Q236 conductive. Accordingly, the control circuit 150 is able to accurately determine the average magnitude of the load current ILOAD from the magnitude of the load current feedback signal VI-LOAD since the effects of the magnetizing current IMAG and the oscillations of the primary current IPRI on the magnitude of the load current feedback signal VI-LOAD are reduced or eliminated completely.
As the target intensity LTRGT of the LED light source 202 is decreased towards the low-end intensity LLE and the on times TON of the drive control signals VDRIVE1, VDRIVE2 get smaller, the parasitic of the load regulation circuit 140 (i.e., the parasitic capacitances CP1, CP2 of the FETs Q210, Q212, the parasitic capacitance CP3 of the primary winding of the transformer 220, and/or other parasitic capacitances of the circuit) may cause the magnitude of the primary voltage VPRI to slowly decrease towards zero volts after the FETs Q210, Q212 are rendered non-conductive.
FIG. 8 shows example waveforms illustrating the operation of a forward converter and a current sense circuit (e.g., the forward converter 240 and the current sense circuit 260) when the target intensity LTRGT is near the low-end intensity LLE, and when the forward converter 240 is operating in the normal mode and the active state of the burst mode. The gradual drop off in the magnitude of the primary voltage VPRI may allow the primary winding of the transformer 220 to continue to conduct the primary current IPRI, such that the transformer 220 may continue to deliver power to the secondary winding after the FETs Q210, Q212 are rendered non-conductive, for example, as shown in FIG. 8. The magnetizing current IMAG may continue to increase in magnitude after the on time TON of the drive control signal VDRIVE1 (e.g., and/or the drive control signal VDRIVE2). Accordingly, the control circuit 150 may increase the signal-chopper time TCHOP to be greater than the on time TON. For example, the control circuit 150 may increase the signal-chopper time TCHOP (e.g., during which the signal-chopper control signal Vamp is low) by an offset time TOS when the target intensity LTRGT of the LED light source 202 is near the low-end intensity LLE.
FIG. 9 is an example plot of a relationship between the offset time TOS and the target intensity LTRGT of the LED light source 202, for example, when the target intensity LTRGT is near the low-end intensity LLE, and when the forward converter 240 is operating in the normal mode and the active state of the burst mode (e.g., as shown in FIG. 8). The control circuit 150 may adjust the value of the offset time TOS as a function of the target intensity LTRGT of the LED light source 202. For example, the control circuit 150 may adjust the value of the offset time TOS linearly with respect to the target intensity LTRGT when the target intensity LTRGT is below a threshold intensity LTH (e.g., approximately 10%) and above a transition intensity LTRAN (e.g., approximately 5%). Above the threshold intensity LTH, the offset time TOS may be held constant, for example, at approximately zero microseconds. Below the transition intensity LTRAN, the offset time TOS may be held constant at a maximum offset time TOS-MAX, for example, because the target load current ITRGT may be held constant at the minimum rated current IMIN below the transition intensity LTRAN.
FIG. 10 is an example plot of a relationship (e.g., an alternate relationship) between the offset time TOS and the target intensity LTRGT of the LED light source 202, for example, when the target intensity LTRGT is near the low-end intensity LLE, and when the forward converter 240 is operating in the normal mode and the active state of the burst mode (e.g., as shown in FIG. 8). The control circuit 150 may adjust the value of the offset time TOS as a function of the target intensity LTRGT of the LED light source 202. For example, the control circuit 150 may adjust the value of the offset time TOS between the high-end intensity LHE and the transition intensity LTRAN, for example, as shown in FIG. 10. For example, the control circuit 150 may use the following equation:




  
    
      T
      OS
    
    =
    
      
        
          
            V
            BUS
          
          4
        
        ·
        
          C
          PARASITIC
        
      
      
        
          
            
              
                T
                ON
              
              +
              
                T
                
                  OS
                  ⁢
                  
                    -
                  
                  ⁢
                  PREV
                
              
            
            
              T
              HC
            
          
          ·
          
            I
            
              MAG
              ⁢
              
                -
              
              ⁢
              MAX
            
          
        
        +
        
          
            
              K
              RIPPLE
            
            
              n
              TURNS
            
          
          ·
          
            I
            LOAD
          
        
      
    
  
  ,




where TOS-PREV may be the previous value of the offset time. KRIPPLE may be the dynamic ripple ratio of the output inductor current IL (e.g., which may be a function of the load current ILOAD). For example, KRIPPLE may be determined according to the following equation:

KRIPPLE=IL-PK/IL-AVG,

and CPARASITIC may be the total parasitic capacitance between the junction of the FETs Q210, Q212 and circuit common. Below the transition intensity LTRAN, the offset time TOS may be held constant at a maximum offset time TOS-MAX.

FIG. 11 shows example waveforms illustrating the operation of a forward converter when operating in a burst mode (e.g., the forward converter 240 shown in FIG. 5). The inverter circuit of the forward converter 240 may generate the inverter voltage VINV during the active state (e.g., for length of an active state period TACTIVE as shown in FIG. 11), for example, such that the magnitude of the load current ILOAD may be regulated to the minimum rated current IMIN. The inverter voltage VINV may not be generated during the inactive state, e.g., for an inactive state period TINACTIVE. The active state may begin on a periodic basis at a burst mode period TBURST (e.g., approximately 4.4 milliseconds). The active state period TACTIVE and inactive state period TINACTIVE may be characterized by durations that are dependent upon a burst duty cycle DCBURST. For example, TACTIVE=DCBURST·TBURST and TINACTIVE=(1−DCBURST)·TBURST. The average magnitude IAVE of the load current ILOAD may be dependent on the burst duty cycle DCBURST. For example, the average magnitude IAVE of the load current ILOAD may equal the burst duty cycle DCBURST times the load current ILOAD (e.g., IAVE=DCBURST·ILOAD), which in one example may be the minimum load current IMIN (e.g., IAVE=DCBURST·IMIN).
The burst duty cycle DCBURST may be controlled to adjust the average magnitude IAVE of the load current ILOAD. For example, the burst mode period TBURST may be held constant and the length of the active state period TACTIVE may be varied to adjust the duty cycle DCBURST, which in turn may vary the average magnitude IAVE of the load current ILOAD. The active state period TACTIVE may be held constant, and the length of burst mode period TBURST may be varied to adjust the burst duty cycle DCBURST, which in turn may vary the average magnitude IAVE of the load current ILOAD. Accordingly, as the burst duty cycle DCBURST is increased, the average magnitude IAVE of the load current ILOAD may increase, and as the burst duty cycle DCBURST is decreased, the average magnitude IAVE of the load current ILOAD may decrease.
FIG. 12A is a diagram of an example waveform 1200 illustrating the load current ILOAD when a load regulation circuit (e.g., the load regulation circuit 140) is operating in a burst mode, for example, as the target intensity LTRGT of a light source (e.g., the LED light source 202) is increased (e.g., from the low-end intensity LLE). A control circuit (e.g., the control circuit 150 of the LED driver 100 shown in FIG. 1 and/or the control circuit 150 controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 5) may adjust the length of the active state period TACTIVE of the burst mode period TBURST by adjusting the burst duty cycle DCBURST. Adjusting the length of the active state period TACTIVE may adjust the average magnitude IAVE of the load current LOAD, and in turn the intensity of the light source.
The active state period TACTIVE of the load current ILOAD may have a length that is dependent upon the length of an inverter cycle of the inverter circuit of the load regulation circuit (i.e., the operating period Top). For example, referring to FIG. 11, the active state period TACTIVE may comprise six inverter cycles, and as such, has a length that is equal to the duration of the six inverter cycles. The control circuit may adjust (i.e., increase or decrease) the active state periods TACTIVE by adjusting the number of inverter cycles in the active state period TACTIVE. As such, the control circuit may adjust the active state periods TACTIVE by predetermined time intervals that correspond to the length of an inverter cycle of the inverter circuit of the load regulation circuit, for example, the transition operating period TOP-T (e.g., approximately 12.8 microseconds). Therefore, the active state period TACTIVE may be characterized by one or more inverter cycles, and may be adjusted by adjusting a number of inverter cycles per active state period TACTIVE. As such, the average magnitude IAVE of the load current ILOAD may be adjusted by predetermined increments, for example, corresponding to a change in load current ILOAD due to an increase or decrease of an inverter cycle per active state period TACTIVE.
One or more burst mode periods TBURST of the load regulation circuit may be characterized by active state periods TACTIVE that comprise the same number of inverter cycles. In the example of FIG. 12A, three burst mode periods TBURST 1202, 1204, 1206 may be characterized by equivalent active state periods TACTIVE1 (i.e., active state periods TACTIVE1 that have the same number of inverter cycles). The active state period TACTIVE2 of the burst mode period TBURST 1208 may be larger than the active state periods TACTIVE1 of the other burst mode periods TBURST 1202, 1204, 1206. In other words, the active state period TACTIVE2 during the burst mode period TBURST 1208 may be increased as compared to the active state periods TACTIVE1 during the burst mode periods TBURST 1202, 1204, 1206. As such, the average magnitude IAVE of the load current ILOAD may be increased in accordance with the additional inverter cycle(s) of the active state period TACTIVE2 during the burst mode period TBURST 1208. Therefore, the control circuit may adjust (i.e., increase or decrease) the average magnitude IAVE of the load current ILOAD by adjusting the active state period TACTIVE by increments of one or more inverter cycles.
FIG. 12B is a diagram of an example waveform 1210 illustrating the load current ILOAD when a load regulation circuit (e.g., the load regulation circuit 140) is operating in a burst mode, for example, as the target intensity LTRGT of a light source (e.g., the LED light source 202) is increased (e.g., from the low-end intensity LLE). As noted herein, a control circuit (e.g., the control circuit 150 of the LED driver 100 shown in FIG. 1 and/or the control circuit 150 controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 5) may adjust the average magnitude IAVE of the load current ILOAD by adjusting the active state period TACTIVE (i.e., the number of inverter cycles per active state period TACTIVE). When adjusting only the active state period TACTIVE (e.g., and in turn the burst duty cycle DCBURST) near the low-end intensity LLE, the adjustment of the average magnitude IAVE of the load current ILOAD may cause changes in the intensity of the lighting load that are visibly perceptible to the user (e.g., as shown in FIG. 12A).
The control circuit may also adjust (i.e., increase or decrease) the magnitude of the load current ILOAD between and/or during adjustments of the active state period TACTIVE while in the burst mode, for example, to adjust the average magnitude IAVE of the load current ILOAD with finer granularity as compared to adjusting only the active state period TACTIVE (e.g., to provide finer tuning of the intensity of the lighting load). The control circuit may adjust (i.e., increase or decrease) the magnitude of the load current ILOAD by adjusting the target load current ITRGT and by controlling the inverter circuit to regulate the load current ILOAD to the target load current ITRGT during the active state periods TACTIVE, for example, as described herein. The control circuit may adjust the load current ILOAD linearly, variably as a function of the average magnitude IAVE of the load current LOAD, and/or by predetermined amounts. As such, the control circuit may ease the transitions between adjustments of the active state period TACTIVE by adjusting the load current ILOAD.
The control circuit may adjust the target load current ITRGT by a current offset IOS, for example, between adjustments of the active state period TACTIVE and/or when adjusting the active state period TACTIVE. The current offset IOS may range (i.e., vary) between a minimum current offset IOS-MIN and a maximum current offset IOS-MAX, for example, based on the burst duty cycle DCBURST. The value of the current offset IOS may be determined based on the minimum rated current IMIN, the target current ITRGT, the target intensity LTRGT, the burst duty cycle DCBURST, and/or the active state period TACTIVE. The current offset IOS may be variable between burst mode periods TBURST having the same active state period TACTIVE and/or between burst mode periods TBURST having the different active state periods TACTIVE.
Referring to FIG. 12B, the control circuit may increase the intensity of the light source at a constant rate. The control circuit may hold the active state period TACTIVE of two or more burst mode periods TBURST constant, and may adjust the load current ILOAD of the active state periods TACTIVE of the two or more burst mode periods TBURST, for example, by a consistent or varying current offset IOS. For example, the control circuit may hold the active state period TACTIVE1 (i.e., the number of inverter cycles of the active state period TACTIVE1) of the burst mode periods TBURST 1212, 1214, 1216 constant as shown in FIG. 12B. The control circuit may set the load current ILOAD during the active state period TACTIVE1 of the burst mode period TBURST 1212 to the minimum rated current IMIN. The control circuit may increase the load current ILOAD of the active state period TACTIVE1 of the burst mode period TBURST 1214 by a current offset IOS-1 while holding the active state period TACTIVE1 constant. The control circuit may then increase the load current ILOAD of the active state period TACTIVE1 of the burst mode period TBURST 1216 by a current offset IOS-2 while holding the active state period TACTIVE1 constant. The current offset IOS-2 may be greater than the current offset IOS-1. The current offset IOS-2 may be equal to, greater than, or less than twice the current offset IOS-1. For example, the current offset IOS-2 may be equal to twice the current offset IOS-1 if the intensity of the light source is being increased at a constant rate. The control circuit may increase the average magnitude IAVE of the load current ILOAD during the burst mode periods TBURST 1212, 1214, 1216 while holding the active state period TACTIVE1 constant.
The control circuit may adjust the active state period TACTIVE and the load current LOAD of a subsequent burst mode period TBURST. For example, the control circuit may increase the active state period TACTIVE2 of the burst mode period TBURST 1218 and decrease the load current ILOAD of the active state period TACTIVE2 of the burst mode period TBURST 1218. The control circuit may increase the active state period TACTIVE2 of the burst mode period TBURST 1218 by one inverter cycle, and may set the load current ILOAD of the active state period TACTIVE2 of the burst mode period TBURST 1218 to the minimum rated current IMIN. Although the load current ILOAD of the active state period TACTIVE2 of the burst mode period TBURST 1218 is decreased, the average magnitude IAVE of the load current ILOAD is increased due to the increase in the active state period TACTIVE2. As such, the control circuit may control (e.g., increase or decrease) the average magnitude IAVE of the load current ILOAD with finer granularity by adjusting both the load current ILOAD and the active state period TACTIVE during burst mode.
When increasing the active state period TACTIVE, the average magnitude IAVE of the load current ILOAD may be increased due to the application of the load current ILOAD for a greater duration of the burst mode period TBURST. For example, this may be illustrated by 1250 in FIG. 12B. When increasing the load current ILOAD during burst mode periods TBURST having the same active state period TACTIVE, the load current ILOAD may be increased in excess of the minimum load current IMIN by the current offset IOS (e.g., which may vary between the minimum current offset IOS-MIN and the maximum current offset IOS-MAX). As such, the average magnitude IAVE of the load current ILOAD may be increased due to the application of the current offset IOS in excess of the minimum load current IMIN for the active state period TACTIVE, for example, as illustrated by 1230 and 1240 in FIG. 12B.
When determining the value of the current offset IOS for a particular burst mode period TBURST, the control circuit may ensure that the change (e.g., increase or decrease) in the average magnitude IAVE of the load current ILOAD due to the application of the current offset IOS does not exceed the change (e.g., increase or decrease) in the average magnitude IAVE of the load current LOAD due to the application of the load current ILOAD for a greater duration of time during the burst mode period TBURST (i.e., an increase in the active state period TACTIVE). For example, referring to FIG. 12B, the control circuit may determine the current offset IOS-1 such that the change in the average magnitude IAVE of the load current ILOAD 1230 due to the current offset IOS-1 is less than the change in the average magnitude IAVE of the load current ILOAD 1240 due to the current offset IOS-2. Similarly, the control circuit may determine the current offset IOS-2 such that the change in the average magnitude IAVE of the load current ILOAD 1240 due to the current offset IOS-2 is greater than the change in the average magnitude IAVE of the load current ILOAD 1230 due to the current offset IOS-1 and is less than the increase in the average magnitude IAVE of the load current ILOAD 1250 due to the application of the load current ILOAD for a greater duration of time during the burst mode period TBURST (i.e., the difference between the active state period TACTIVE1 and the active state period TACTIVE2). This may allow the control circuit may ease the transitions between adjustments of the active state period TACTIVE (e.g., from the active state period TACTIVE1 to the active state period TACTIVE2) by adjusting the load current ILOAD by a current offset IOS.
FIG. 12C shows example waveforms 1260, 1280 illustrating an example of how a load control circuit (e.g., the control circuit 150 of the LED driver 100 shown in FIG. 1 and/or the control circuit 150 controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 5) may determine the current offset IOS when holding the active state period TACTIVE constant during burst mode, for example, as the target intensity LTRGT of a light source (e.g., the LED light source 202) is increased from the low-end intensity LLE. As noted herein, the burst duty cycle DCBURST (i.e., DCBURST-INTEGER) and in turn the active state period TACTIVE may be characterized by one or more inverter cycles.
Referring to example waveform 1260, the active state period TACTIVE1 of the burst mode period TBURST 1262 may be characterized by two inverter cycles 1266. In a subsequent burst mode period TBURST 1264, the control circuit may determine to adjust the average magnitude IAVE of the load current LOAD, for example, in accordance with the target intensity ITRGT. For example, the control circuit may determine to increase the active state period TACTIVE3 of the burst mode period TBURST 1264 by less than one inverter cycle to achieve the increase in the average magnitude IAVE of the load current ILOAD. As such, the active state period TACTIVE3 of the burst mode period TBURST 1264 may be characterized by two inverter cycles 1266 and a fractional portion 1268 of a third inverter cycle 1266, where for example, the increase in the average magnitude IAVE of the load current ILOAD during the burst mode period TBURST 1264 may be due to the fractional portion 1268 of the third inverter cycle 1266.
As described herein, the ideal burst duty cycle DCBURST-IDEAL of a burst mode period TBURST may be characterized by an integer portion DCBURST-INTEGER and/or a fractional portion DCBURST-FRACTIONAL. For example, the ideal burst duty cycle DCBURST-IDEAL may follow the ideal curve shown in FIG. 3 (e.g., the ideal burst duty cycle DCBURST-IDEAL may result in the active state period TACTIVE3). The integer portion DCBURST-INTEGER may be characterized by the percentage of the ideal burst duty cycle DCBURST-IDEAL that includes complete inverter cycles. The fractional portion DCBURST-FRACTIONAL may be characterized by the percentage of the ideal burst duty cycle DCBURST-IDEAL that includes a fraction of an inverter cycle. For example, as shown in FIG. 12C, the ideal burst duty cycle DCBURST-IDEAL of the burst mode period TBURST 1262 may include an integer portion DCBURST-INTEGER 1270 (which may be characterized by two inverter cycles 1266), but not include a fractional portion DCBURST-FRACTIONAL. The ideal burst duty cycle DCBURST-IDEAL of the burst mode period TBURST 1264 may include an integer portion DCBURST-INTEGER 1270 (which may be characterized by two inverter cycles 1266) and a fractional portion DCBURST-FRACTIONAL 1272 (which may be characterized by the fractional portion 1268 of the third inverter cycle 1266).
However, the control circuit may be configured to adjust the number of inverter cycles only by an integer number (i.e., by complete inverter cycles) and not by a fractional amount. Therefore, the control circuit may be unable to increase the active state period TACTIVE3 of the burst mode period TBURST 1264 by the fractional portion 1268 and in turn increase the burst duty cycle DCBURST of the burst mode period TBURST 1264 by the fractional portion DCBURST-FRACTIONAL 1272 to increase the average magnitude IAVE of the load current ILOAD. The control circuit may adjust the magnitude of the load current ILOAD by the current offset IOS to compensate for not being able to adjust the number of inverter cycles by a fractional amount, for example, as described with reference to FIG. 15.
As noted above, during burst mode, the control circuit may increase the load current LOAD of an active state period TACTIVE by a current offset IOS in order to increase the average magnitude IAVE of the load current ILOAD to achieve the target intensity LTRGT. The control circuit may determine the current offset IOS based on the fractional portion DCBURST-FRACTIONAL of the ideal burst duty cycle DCBURST-IDEAL for the burst mode period TBURST, for example, assuming that the control circuit could in fact adjust the number of inverter cycles by a fractional amount. For example, referring to the waveform 1280, the control circuit may determine the current offset IOS-1 based on the fractional portion DCBURST-FRACTIONAL 1272 of the ideal burst duty cycle DCBURST-IDEAL of the burst mode period TBURST 1264 from waveform 1260. That is, the control circuit may determine the current offset IOS-1 such that an increase 1274 in the load current ILOAD over the active state period TACTIVE due to the current offset IOS-1 may be equal to (i.e., result in the same adjustment to the average magnitude IAVE of the load current ILOAD) the fractional portion DCBURST-FRACTIONAL 1272. Therefore, the control circuit may adjust the magnitude of the load current ILOAD by the current offset IOS (e.g., current offset IOS-1) to compensate for not being able to adjust the number of inverter cycles by a fractional amount (e.g., the fractional portion DCBURST-FRACTIONAL 1272).
FIG. 13 is an example of a plot relationship between the target load current ITRGT and the burst duty cycle DCBURST, and the target intensity LTRGT of a light source (e.g., the LED light source 202), for example, when a load regulation circuit (e.g., the load regulation circuit 140) is operating in a burst mode and when the load current ILOAD of the light source is near the low-end intensity LLE. Graph 1300 is an example plot of a relationship between the target load current ITRGT and the target intensity LTRGT of the light source. Graph 1310 is an example plot of a relationship between the burst duty cycle DCBURST (i.e., the integer portion of the ideal burst duty cycle DCBURST-INTEGER) and the target intensity LTRGT of the light source. In the graph 1300 and 1310, the target intensity may range from the transition intensity LTRAN to the low-end intensity LLE.
A control circuit (e.g., the control circuit 150 of the LED driver 100 shown in FIG. 1 and/or the control circuit 150 controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 5) may determine the magnitude of the target load current ITRGT and/or the burst duty cycle DCBURST during burst mode, for example, based on the target intensity LTRGT. The control circuit may determine the target intensity LTRGT, for example, via a digital message received via the communication circuit 180, via a phase-control signal received from a dimmer switch, and/or the like. The target intensity LTRGT may be constant or may be changing (e.g., fading) from one intensity level to another. The control circuit may determine the burst duty cycle DCBURST based on the target intensity LTRGT. After determining the burst duty cycle DCBURST, the control circuit may determine the target load current ITRGT that may be used with the burst duty cycle DCBURST such that the light source is driven to the target intensity LTRGT. The control circuit may determine the burst duty cycle DCBURST and/or the target load current ITRGT by calculating the values in real-time (e.g., as described with reference to FIG. 15) and/or retrieving the values from memory (e.g., via a lookup table or the like).
The control circuit may apply a particular burst duty cycle DCBURST (i.e., DCBURST-INTEGER) for a range of target intensities LTRGT. The control circuit may determine the target load current ITRGT across the range of target intensities LTRGT for the particular burst duty cycle DCBURST, for example, according to a target load current ITRGT profile. The target load current ITRGT profile may vary linearly across the range of target intensities LTRGT for the particular burst duty cycle DCBURST. The target load current ITRGT profile that may be applied across the range of target intensities LTRGT associated with a burst duty cycle DCBURST may be different for different burst duty cycles DCBURST. For example, the target load current ITRGT may be adjusted from the minimum rated current IMIN to the minimum rated current IMIN plus the current offset IOS, and the current offset IOS may range from the minimum current offset IOS-MIN to the maximum current offset IOS-MAX based on the burst duty cycle DCBURST. For example, the larger the burst duty cycle DCBURST, then the smaller range of current offsets IOS may be used in the target load current ITRGT profile, and vice versa. This may be done because the minimum rated current IMIN divided by the burst duty cycle DCBURST (i.e., IMIN/DCBURST) may be larger at smaller burst duty cycle DCBURST values. Further, this may be done because the user's sensitively to changes in intensity of the light source may be increased at lower light levels and a more granular adjustment of intensity of the lighting load may be desired at low-end.
Referring to FIG. 13, if the control circuit determines that the target intensity LTRGT falls within the range 1301, then the control circuit may determine to set the burst duty cycle DCBURST (i.e., DCBURST-INTEGER) to DCMAX, and the control circuit may determine to set the target load current ILOAD according to the target load current ILOAD profile 1321. The target load current ILOAD profile 1321 may range from the minimum rated current IMIN plus the minimum current offset IOS-MIN to the minimum rated current IMIN based on the target intensity LTRGT. As noted above, the control circuit may determine the burst duty cycle DCBURST and/or the target load current ITRGT by calculating the values in real-time and/or retrieving the values from memory.
If the control circuit determines that the target intensity LTRGT falls within the range 1302, then the control circuit may determine to set the burst duty cycle DCBURST to 1312 (e.g., which may be less than the DCMAX, and the control circuit may determine to set the target load current ILOAD according to the target load current ILOAD profile 1322. Similarly, if the control circuit determines that the target intensity LTRGT falls within one of the target intensity ranges 1303-1307, then the control circuit may determine to set the burst duty cycle DCBURST to one of 1313-1317 and determine to set the target load current ILOAD according to one of the target load current LOAD profiles 1323-1327, respectively. The maximum target current for consecutive target load current ILOAD profiles may change by a constant amount (e.g., as shown in FIG. 13) or may change by varying amounts (e.g., increase as the target intensity range gets smaller). Further, more or less than seven burst duty cycles DCBURST (i.e., DCMAX through DCMIN) may be provided between the transition intensity LTRAN and the low-end intensity LLE.
When the LED driver is driving a high-power LED light source, the LED light source may conduct larger amounts of current through the LED driver, which may affect the operation of the LED driver when dimming to the low-end intensity LLE (e.g., approximately 1%). For example, the larger current conducted by the high-power LED light source may cause the load current ILOAD to overshoot the minimum rated current IMIN at the beginning of each active state period TACTIVE.
FIG. 14A shows an example waveform 1400 illustrating an overshoot 1402 in the load current LOAD, for example, when the LED driver is controlling a high-power LED light source. The overshoot 1402 may be the additional current in excess of the target load current ITRGT. For example, the target load current ITRGT is the minimum rated current IMIN in FIG. 14B. Stated another way, the overshoot 1402 may be characterized by the rise in the magnitude of the load current LOAD above the target load current ITRGT at the beginning of the active state period TACTIVE. Since the LED driver determines the burst duty cycle DCBURST (e.g., and thus the length of the active state period TACTIVE) using open loop control, the overshoot (e.g., the overshoot 1402) may cause the LED driver to deliver more power to the LED light source than intended. In turn, the overshoot 1402 may cause the average load current IAVG to increase in excess of what was intended, and thus the intensity of the LED driver may be greater than intended (e.g., greater than approximately 1%). In addition, the sharp rise in the magnitude of the load current ILOAD at the beginning of the active state period TACTIVE (i.e., the overshoot 1402) may cause audible noise (e.g., buzzing) in the magnetic components of the load regulation circuit of the LED driver (e.g., in the transformer 220 and/or the inductor L226 of the load regulation circuit 240 shown in FIG. 5).
Accordingly, the control circuit of the LED driver may be configured to control the rise time of the load current ILOAD at the beginning of each active state period TACTIVE. FIG. 14B shows an example waveform 1450 illustrating control of the rise time of the load current ILOAD at the beginning of each active state period TACTIVE. The control circuit 150 may detect an overshoot of the load current LOAD, for example, based on the load current ILOAD as determined by the load regulation circuit, based on the sense voltage VSENSE, based on the load current feedback signal VI-LOAD, and/or the like. The control circuit 150 may determine to control the rise time of the load current ILOAD at the beginning of an active state period TACTIVE. For example, the control circuit 150 may determine to control the rise time of the load current ILOAD to prevent the overshoot from continuing to occur. In one or more embodiments, the control circuit 150 may determine to control the rise time of the load current ILOAD at any time during operation and/or for any reason, for example, the control circuit 150 may be preconfigured to control of the rise time of the load current ILOAD at the beginning of each active state period TACTIVE. The control circuit 150 may determine the on times TON of the drive control signals VDRIVE1, VDRIVE2 for controlling the inverter circuit of the forward converter 240 (e.g., using the load current feedback signal VI-LOAD). The control circuit 150 may be configured to increase (e.g., ramp up) the load current ILOAD from an initial current IINIT to the target load current ITRGT (e.g., the minimum rated current IMIN or to the minimum rated current IMIN plus the current offset IOS) over a ramp time period TRAMP, for example, as shown in FIG. 14B. For example, the ramp time period TRAMP may be approximately 200 microseconds. In addition, the initial current IINIT may be approximately 40% of the rated minimum current IMIN, but could range from zero amps to slightly less than the rated minimum current IMIN.
Since the magnitude of the load current ILOAD is less than the minimum rated current IMIN during the ramp time period TRAMP, the control circuit 150 does not regulate the magnitude of the load current ILOAD in response to the load current feedback signal VI-LOAD during the ramp time period TRAMP. After freezing the control loop during the inactive state period TINACTIVE, the control circuit 150 may maintain the control loop in the frozen state while the control circuit is adjusting the on times TON of the drive control signals VDRIVE1, VDRIVE2 to ramp the load current ILOAD up to the target load current ITRGT during the ramp time period TRAMP. After the ramp time period TRAMP, the control circuit waits for a wait time period TWAIT (e.g., approximately 200 microseconds) before beginning to regulate the magnitude of the load current ILOAD during a regulation time period TREG. As such, the control loop may be frozen for the duration of the inactive state period TINACTIVE, the ramp time period TRAMP, and the wait time period TWAIT, and the control loop may be unfrozen (active) during the regulation time period TREG. Ramping up the load current ILOAD during the active state TACTIVE of the burst mode may prevent the load current ILOAD from overshooting the minimum rated current IMIN at the beginning of each active state period TACTIVE. The wait time period TWAIT may be used to allow for the load current ILOAD to stabilize. In one or more embodiments, the wait time period TWAIT may be omitted.
FIG. 14B may not be to scale. For example, in one or more embodiments, the ramp time period TRAMP may be approximately one quarter of a pulse width (e.g., approximately 200 microseconds), the wait time period TWAIT may be approximately one quarter of a pulse width (e.g., approximately 200 microseconds), and the regulation time period TREG may be approximately one half of a pulse width (e.g., approximately 200 microseconds). The invention is not so limited, and the ramp time period TRAMP, the wait time period TWAIT, and the regulation time period TREG may be in different proportions of the pulse width.
The target intensity LTRGT may be associated with a target amount of power delivered to the electrical load. For example, although the example illustrated in FIGS. 2 and 3 are with relation to target intensity LTRGT, the control circuit (e.g., control circuit 150) may be configured to adjust the target load current ITRGT to control the target amount of power delivered to the electrical load and/or the control circuit may be configured to adjust the burst duty cycle DCBURST in response to the target amount of power when operating in the burst mode. For example, the control circuit may be configured to adjust the burst duty cycle DCBURST linearly with respect to the target amount of power when operating in the burst mode. Further, the control circuit may be configured to operate in the burst mode when the target amount of power is less than a transition amount of power. The transition amount of power may be power delivered to the electrical load when the electrical load is controlled to be the transition intensity LTRAN.
FIGS. 15A, 15B, 16, 17A, 17B and 18 are simplified flowcharts of example procedures for operating a forward converter in a normal mode and a burst mode. The procedures of FIGS. 15A, 15B, 16, 17A, 17B, and 18 may be executed by a control circuit of a load control device (e.g., the control circuit 150 of the LED driver 100 shown in FIG. 1 and/or the control circuit 150 controlling the forward converter 240 and the current sense circuit 260 shown in FIG. 5).
FIG. 15A is a simplified flowchart of an example target intensity procedure 1500 that may be executed when the target intensity LTRGT is adjusted at 1510 (e.g., in response to digital messages received via the communication circuit 180). The control circuit may determine if it is operating the forward converter in the burst mode at 1512 (e.g., the target intensity LTRGT is between the high-end intensity LHE and the transition intensity LTRAN, i.e., LTRAN<LTRGT<LHE). If the control circuit determines it is not operating the forward converter in the burst mode (e.g., but rather in the normal mode) at 1512, then the control circuit may determine and set the target load current ITRGT as a function of the target intensity LTRGT at 1514 (e.g., as shown in FIG. 2). The control circuit may then set the burst duty cycle DCBURST equal to a maximum duty cycle DCMAX (e.g., approximately 100%) at 1516 (e.g., as shown in FIG. 3), and the control circuit may exit the target intensity procedure 1500.
If the control circuit determines that it is operating the forward converter in the burst mode at 1512 (e.g., the target intensity LTRGT is below the transition intensity LTRAN, i.e., LTRGT<LTRAN), then the control circuit may set the target load current ITRGT to a minimum value (e.g., to the minimum rated current IMIN) at 1518 (e.g., as shown in FIG. 2). The control circuit may then determine and set the burst duty cycle DCBURST as a function of the target intensity LTRGT at 1520 (e.g., using open loop control as shown in FIG. 3), and the control circuit may exit the target intensity procedure 1500.
FIG. 15B is a simplified flowchart of an example target intensity procedure 1550 that may be executed when the target intensity LTRGT is adjusted at 1560 (e.g., in response to digital messages received via the communication circuit 180). The control circuit may determine if it is operating the forward converter in the burst mode at 1562 (e.g., the target intensity LTRGT is between the high-end intensity LHE and the transition intensity LTRAN, i.e., LTRAN<LTRGT<LHE). If the control circuit determines that it is not operating the forward converter in the burst mode (e.g., but rather in the normal mode), then the control circuit may determine and set the target load current ITRGT as a function of the target intensity LTRGT at 1564 (e.g., as shown in FIG. 2). The control circuit may then set the burst duty cycle DCBURST equal to a maximum duty cycle DCMAX (e.g., approximately 100%) at 1566 (e.g., as shown in FIG. 3), and the control circuit may exit the target intensity procedure 1550.
If the control circuit determines that it is operating the forward converter in the burst mode at 1562 (e.g., the target intensity LTRGT is below the transition intensity LTRAN, i.e., LTRGT<LTRAN), then the control circuit may determine the burst duty cycle DCBURST and target load current ITRGT for one or more burst mode periods TBURST (e.g., using open loop control) at 1568. For example, the control circuit may determine the burst duty cycle DCBURST and/or the target load current ITRGT by calculating the values in real-time (e.g., as described with reference to FIG. 16) and/or retrieving the values from memory (e.g., via a lookup table or the like). The control circuit may determine the burst duty cycle DCBURST and target load current ITRGT for a plurality of burst mode periods TBURST that may be used when adjusting the intensity of the light load to the target intensity LTRGT, for example, as described with reference to FIG. 12B and/or FIG. 13. The control circuit may then set the burst duty cycle DCBURST and target load current ITRGT for each of the plurality of burst mode periods TBURST at 1570, for example, until the intensity of the lighting load equals the target intensity LTRGT, and the control circuit may exit the target intensity procedure 1550.
FIG. 16 is a simplified flowchart of an example target load current ITRGT procedure 1600. The target load current ITRGT procedure 1600 may be executed periodically (e.g., every 66 microseconds). In one or more embodiments, the target load current ITRGT procedure 1600 may be executed during 1568 of the target intensity procedure 1550. The control circuit may determine the burst duty cycle DCBURST (e.g., ideal burst duty cycle DCBURST-IDEAL, integer portion of the ideal burst duty cycle DCBURST-INTEGER, and/or fractional portion of the ideal burst duty cycle DCBURST-FRACTIONAL), the current offset IOS, and target load current ITRGT for controlling the lighting load at the beginning of every burst mode period TBURST, for example, using the target load current ITRGT procedure 1600. The target load current ITRGT procedure 1600 may begin at 1602 where the control circuit may determine the target intensity LTRGT. The control circuit may determine the target intensity LTRGT, for example, via a digital message received via the communication circuit 180, via a phase-control signal received from a dimmer switch, and/or the like. The target intensity LTRGT may be constant or may be changing from one intensity level to another.
After determining the target intensity LTRGT, the control circuit may determine the ideal burst duty cycle DCBURST-IDEAL at 1604. The ideal burst duty cycle DCBURST-IDEAL may be adjusted linearly as the target intensity LTRGT is adjusted between the low end intensity LLE and the transition intensity LTRAN. For example, the control circuit may determine the ideal burst duty cycle DCBURST-IDEAL based on the target intensity LTRGT using the graph of FIG. 3. The ideal burst duty cycle DCBURST-IDEAL may include an integer portion DCBURST-INTEGER and/or a fractional portion DCBURST-FRACTIONAL, for example, as described with reference to FIG. 12C.
The control circuit may determine the integer portion of the ideal burst duty cycle DCBURST-INTEGER at 1606. For example, the control circuit may determine the integer portion of the burst duty cycle DCBURST-INTEGER by rounding the ideal duty cycle DCBURST-IDEAL down to the next closest integer value using the following equation:

DCBURST-INTEGER=Round-Down(DCBURST-IDEAL).

The control circuit may determine the fractional portion of the ideal burst duty cycle DCBURST-FRACTIONAL at 1608. For example, the control circuit may determine the fractional portion of the ideal burst duty cycle DCBURST-FRACTIONAL by subtracting the integer portion of the burst duty cycle DCBURST-INTEGER from the ideal burst duty cycle DCBURST-IDEAL, for example, using the following equation:

DCBURST-FRACTIONAL=DCBURST-IDEAL−DCBURST-INTEGER.

As noted herein, the fractional portion of the ideal burst duty cycle DCBURST-FRACTIONAL may be characterized by the percentage of the ideal burst duty cycle DCBURST-IDEAL that includes a fraction of an inverter cycle. And since the control circuit may be configured to adjust the number of inverter cycles only by an integer number and not a fractional amount (i.e., by DCBURST-FRACTIONAL), the control circuit may determine the current offset IOS for the burst mode period TBURST such that an increase in the load current ILOAD due to the current offset IOS may be equal to (i.e., result in the same adjustment to the average magnitude IAVE of the load current ILOAD) the fractional portion DCBURST-FRACTIONAL.
The control circuit may determine the average current IDUTY generated during a burst mode period TBURST having a burst duty cycle DCBURST-CYCLE that comprises one inverter cycle using the minimum rated current IMIN at 1610. The minimum rated current IMIN may be the peak current when the target intensity LTRGT is less than the transition intensity LTRAN, for example, as shown in FIG. 2. For example, the control circuit may determine the average current IDUTY that is generated during a burst mode period TBURST having a burst duty cycle DCBURST-CYCLE that comprises one inverter cycle, for example according to the following equation:

IDUTY=IMIN/DCBURST-CYCLE.

The control circuit may determine the current offset IOS according to the amount of current IDUTY generated during a burst duty cycle DCBURST-CYCLE that comprises one inverter cycle and the fractional portion of the ideal burst duty cycle DCBURST-FRACTIONAL at 1612. For example, the control circuit may multiply the fractional portion of the ideal burst duty cycle DCBURST-FRACTIONAL by the average current IDUTY generated during a burst mode period TBURST having a burst duty cycle DCBURST-CYCLE that comprises one inverter cycle to determine the current offset IOS, for example, according to the following equation:

IOS=IDUTY·DCBURST-FRACTIONAL.

After determining the current offset IOS, the control circuit may add the current offset IOS to the minimum rated current IMIN to determine the target current ITRGT for the target intensity LTRGT at 1614, and the control circuit may exit the target load current ITRGT procedure 1600. Since the control circuit may be configured to adjust the number of inverter cycles by an integer number and not a fractional amount, the control circuit may operate in burst mode by using the integer portion of the burst duty cycle DCBURST-INTEGER, and by using the current offset IOS in lieu of the fractional portion of the ideal burst duty cycle DCBURST-FRACTIONAL. As such, the control circuit may control the load current ILOAD to achieve the target intensity although it may not be able to operate at the ideal burst duty cycle DCBURST-IDEAL.
In one or more embodiments, the control circuit may determine a scaled target intensity LSCALED and use the scaled target intensity LSCALED in lieu of the target intensity LTRGT when determining the ideal burst duty cycle DCBURST-IDEAL during the target load current ITRGT procedure 1600. For example, the may determine and use the scaled target intensity LSCALED when the low-end intensity LLE and/or the minimum burst duty cycle DCMIN are not zero (e.g., when the low-end intensity LLE is approximately in the range of 0.1%-1%). The scaled target intensity LSCALED may be based on the target intensity LTRGT, the minimum burst duty cycle DCMIN, and the maximum burst duty cycle DCMAX. For example, the control circuit may determine the scaled target intensity LSCALED using the following equation:




  
    L
    SCALED
  
  =
  
    
      
        
          (
          
            
              L
              TRGT
            
            -
            
              L
              LE
            
          
          )
        
        ·
        
          (
          
            
              
                L
                TRAN
              
              ·
              
                DC
                MAX
              
            
            -
            
              
                L
                TRAN
              
              ·
              
                DC
                MIN
              
            
          
          )
        
      
      
        (
        
          
            L
            TRAN
          
          -
          
            L
            LE
          
        
        )
      
    
    +
    
      
        L
        TRAN
      
      ·
      
        
          DC
          MIN
        
        .
      
    
  




After determining the scaled target intensity LSCALED, the control circuit may determine the ideal burst duty cycle DCBURST-IDEAL based on the scaled target intensity LSCALED, for example, at 1604, and the target load current ITRGT procedure 1600 may proceed as described herein. For example, the control circuit may determine the ideal burst duty cycle DCBURST-IDEAL based on the scaled target intensity LSCALED using the following equation:

DCBURST=(LSCALED/LTRAN)*TBURST 

FIG. 17A is a simplified flowchart of an example control loop procedure 1700, which for example, may be executed periodically (e.g., every 66 microseconds). The control loop procedure 1700 may begin at 1710. For example, the control circuit may execute the control loop procedure 1700 to adjust the on time TON of the drive control signals VDRIVE1, VDRIVE2 (e.g., and thus the duty cycle DCINV of the inverter voltage VINV) in response to the magnitude of the load current LOAD determined from the load current feedback signal VI-LOAD received from the current sense circuit. The control circuit may determine if it is operating the forward converter in the normal mode at 1712. If not, then the control circuit may determine if it is operating the forward converter in the active state of burst mode at 1714. If the control circuit is operating the forward converter in the normal mode or in the active state of burst mode, then the control circuit may adjust the on time TON of the drive control signals VDRIVE1, VDRIVE2 in response to the load current feedback signal VI-LOAD. For example, the control circuit may determine if the magnitude of the load current ILOAD is too high at 1716 (e.g., ILOAD>ITRGT). If the magnitude of the load current ILOAD is too high, the control circuit may decrease the on time TON of the drive control signals VDRIVE1, VDRIVE2 at 1718. For example, at 1718, the control circuit may decrease the on time TON by a predetermined amount or by an amount dependent upon the magnitude of the error between the target load current ITRGT and the magnitude of the load current ILOAD. After decreasing the on time TON of the drive control signals VDRIVE1, VDRIVE2, the control circuit may exit the control loop procedure 1700.
If the control circuit determines that the magnitude of the load current ILOAD is not too high at 1716, then the control circuit may determine whether the magnitude of the load current ILOAD is too low at 1720 (e.g., ILOAD<ITRGT). If the control circuit may determines that the magnitude of the load current ILOAD is too low, the control circuit may increase the on time TON of the drive control signals VDRIVE1, VDRIVE2 at 1722. For example, at 1722, the control circuit may increase the on time TON by a predetermined amount or by an amount dependent upon the magnitude of the error between the target load current ITRGT and the magnitude of the load current ILOAD. After increasing the on time TON of the drive control signals VDRIVE1, VDRIVE2, the control circuit may exit the control loop procedure 1700. If the control circuit determines that the magnitude of the load current ILOAD is not too high at 1716 and is not too low at 1720, the control circuit may exit the control loop procedure 1700.
If the control circuit is operating the forward converter in the inactive state of the burst mode, the control circuit may exit the control loop procedure 1700 without adjusting the on time TON of the drive control signals VDRIVE1, VDRIVE2. Accordingly, the control circuit may freeze the control loop when in the inactive state of the burst mode by not adjusting the on time TON of the drive control signals VDRIVE1, VDRIVE2 in response to the average magnitude IAVE of the load current ILOAD. If the magnitude of the load current ILOAD is approximately zero amps during the inactive state, the control circuit may maintain the on time TON of the drive control signals VDRIVE1, VDRIVE2 (e.g., as stored in the memory 170) to be equal to the last value of the on time from the previous active state. The control circuit may control the magnitude of the load current to the minimum rated current IMIN during the next active state.
FIG. 17B is a simplified flowchart of an example control loop procedure 1750, which for example, may be executed periodically (e.g., every 66 microseconds). For example, the control loop procedure 1750 may be executed by the control circuit to avoid overshoot in the load current LOAD at the beginning of each active state period TACTIVE by ramping up the load current ILOAD (e.g., as shown in FIG. 14B). The control loop procedure 1750 may begin at 1760. The control circuit may determine if it is operating the forward converter in the normal mode at 1762. If not, then the control circuit may determine if it is operating the forward converter in the active state of burst mode at 1764. If the control circuit is operating the forward converter in the active state of the burst mode at 1764, the control circuit may then determine at 1765 if it should be presently regulating the load current (e.g., if it is operating in the regulation time period TREG as shown in FIG. 14B).
If the control circuit is operating the forward converter in the normal mode or in the regulation time period TREG of the active state of burst mode, then the control circuit may adjust the on time TON of the drive control signals VDRIVE1, VDRIVE2 in response to the load current feedback signal VI-LOAD. For example, the control circuit may determine if the magnitude of the load current ILOAD is too high at 1766 (e.g., ILOAD>ITRGT). If the magnitude of the load current ILOAD is too high, the control circuit may decrease the on time TON of the drive control signals VDRIVE1, VDRIVE2 at 1768. For example, at 1768, the control circuit may decrease the on time TON by a predetermined amount or by an amount dependent upon the magnitude of the error between the target load current ITRGT and the magnitude of the load current ILOAD. After decreasing the on time TON of the drive control signals VDRIVE1, VDRIVE2, the control circuit may exit the control loop procedure 1750.
If the control circuit determines that the magnitude of the load current ILOAD is not too high at 1766, then the control circuit may determine whether the magnitude of the load current ILOAD is too low at 1770 (e.g., ILOAD<ITRGT). If the control circuit may determines that the magnitude of the load current ILOAD is too low, the control circuit may increase the on time TON of the drive control signals VDRIVE1, VDRIVE2 at 1772. For example, at 1772, the control circuit may increase the on time TON by a predetermined amount or by an amount dependent upon the magnitude of the error between the target load current ITRGT and the magnitude of the load current ILOAD. After increasing the on time TON of the drive control signals VDRIVE1, VDRIVE2, the control circuit may exit the control loop procedure 1750. If the control circuit determines that the magnitude of the load current ILOAD is not too high at 1766 and is not too low at 1770, the control circuit may exit the control loop procedure 1750.
If the control circuit is operating the forward converter in the inactive state of the burst mode at 1764, the control circuit may exit the control loop procedure 1750 without adjusting the on time TON of the drive control signals VDRIVE1, VDRIVE2. Accordingly, the control circuit may freeze the control loop when in the inactive state of the burst mode by not adjusting the on time TON of the drive control signals VDRIVE1, VDRIVE2 in response to the average magnitude IAVE of the load current ILOAD. If the magnitude of the load current ILOAD is approximately zero amps during the inactive state, the control circuit may maintain the on time TON of the drive control signals VDRIVE1, VDRIVE2 (e.g., as stored in the memory 170) to be equal to the last value of the on time from the previous active state.
If the control circuit is operating the forward converter in the active state of the burst mode at 1764, but is not in the regulation time period TREG at 1765, the control circuit may adjust the on time TON of the drive control signals VDRIVE1, VDRIVE2 using open loop control at 1774 to ramp up the load current at the beginning of each active state time period TACTIVE (e.g., during the ramp time period TRAMP as shown in FIG. 14B). The control circuit may also wait for the wait time period TWAIT before once again beginning to adjust the on time TON of the drive control signals VDRIVE1, VDRIVE2 in response to the average magnitude IAVE of the load current ILOAD during the next regulation time period TREG. Accordingly, the control circuit may maintain the control loop frozen when not in the regulation time period TREG in the active state of the burst mode. The control circuit may control the magnitude of the load current to the minimum rated current IMIN during the next regulation time period TREG.
FIG. 18 is a simplified flowchart of an example drive signal procedure 1800, for example, which may be executed periodically. The drive signal procedure 1800 may begin at 1810. The drive signal procedure 1800 may be executed periodically in accordance with the operating period Top of the inverter voltage VINV of the forward converter 240. For example, the control circuit may execute the drive signal procedure 1800 to generate the drive control signals VDRIVE1, VDRIVE2 using the on time TON determined during the control loop procedure 1700 of FIG. 17A or the control loop procedure 1750 of FIG. 17B. The control circuit may determine whether it is operating the forward converter in the normal mode at 1812. If not, then the control circuit may determine whether it is operating the forward converter in the active state of the burst mode at 1814. If the control circuit is operating the forward converter in the normal mode or in the active state of the burst mode, the control circuit may determine whether the high-side FET Q210 or the low-side FET Q212 should be controlled at 1816. If the control circuit determines that it should control the high-side FET Q210 at 1816, the control circuit may drive the first drive control signal VDRIVE1 high to approximately the supply voltage VCC for the on time TON at 1818.
The control circuit may determine the magnitude of the load current ILOAD from the load current feedback signal VI-LOAD. The control circuit may determine if the target intensity LTRGT is greater than or equal to the threshold intensity LTH at 1820. If so, the control circuit may set the signal-chopper time TCHOP equal to the on time TON at 1822. If the control circuit determines that the target intensity LTRGT is less than the threshold intensity LTH at 1820, the control circuit may determine the offset time TOS in response to the target intensity LTRGT at 1824 (e.g., using one or more of the relationships shown in FIGS. 9 and 10). The control signal may set the signal-chopper time TCHOP equal to the sum of the on time TON and the offset time TOS at 1826.
Next, the control circuit may drive the signal-chopper control signal Vamp low towards circuit common for the signal-chopper time TCHOP at 1828. The control circuit may sample the averaged load current feedback signal VI-LOAD at 1830. The control circuit may calculate the magnitude of the load current ILOAD using the sampled value at 1832. For example, the control circuit may calculate the magnitude of the load current ILOAD at 1832 using the following equation:




  
    
      I
      LOAD
    
    =
    
      
        
          n
          TURNS
        
        ·
        
          V
          
            I
            ⁢
            
              -
            
            ⁢
            LOAD
          
        
        ·
        
          T
          HC
        
      
      
        
          R
          SENSE
        
        ·
        
          (
          
            
              T
              CHOP
            
            -
            
              T
              DELAY
            
          
          )
        
      
    
  
  ,




where TDELAY is the total delay time due to the turn-on time and the turn-off time of the FETs Q210, Q212 (e.g., TDELAY=TTURN-ON−TTURN-OFF), which may be equal to approximately 200 microseconds. Finally, the control circuit may exit the drive signal procedure 1800 after determining the magnitude of the load current ILOAD.

If the control circuit determines that it should control the low-side FET Q212 at 1816, the control circuit may drive the second drive control signal VDRIVE2 high to approximately the supply voltage VCC for the on time TON at 1834. The control circuit may exit the drive signal procedure 1800 without the control circuit driving the signal-chopper control signal Vamp low or determining the magnitude of the load current ILOAD from the load current feedback signal VI-LOAD. If the control circuit determines that it is operating the forward converter in the burst mode at 1812 and in the inactive state at 1814, the control circuit may exit the drive signal procedure 1800 without generating the drive control signals VDRIVE1, VDRIVE2.
One or more of the embodiments described herein (e.g., as performed by a load control device) may be used to decrease the intensity of a lighting load and/or increase the intensity of the lighting load. For example, one or more embodiments described herein may be used to adjust the intensity of the lighting load from on to off, off to on, from a higher intensity to a lower intensity, and/or from a lower intensity to a higher intensity. For example, one or more of the embodiments described herein (e.g., as performed by a load control device) may be used to fade the intensity of a light source from on to off (i.e., the low-end intensity LLE may be equal to 0%) and/or to fade the intensity of the light source from off to on.
Although described with reference to an LED driver, one or more embodiments described herein may be used with other load control devices. For example, one or more of the embodiments described herein may be performed by a variety of load control devices that are configured to control of a variety of electrical load types, such as, for example, a LED driver for driving an LED light source (e.g., an LED light engine); a screw-in luminaire including a dimmer circuit and an incandescent or halogen lamp; a screw-in luminaire including a ballast and a compact fluorescent lamp; a screw-in luminaire including an LED driver and an LED light source; a dimming circuit for controlling the intensity of an incandescent lamp, a halogen lamp, an electronic low-voltage lighting load, a magnetic low-voltage lighting load, or another type of lighting load; an electronic switch, controllable circuit breaker, or other switching device for turning electrical loads or appliances on and off; a plug-in load control device, controllable electrical receptacle, or controllable power strip for controlling one or more plug-in electrical loads (e.g., coffee pots, space heaters, other home appliances, and the like); a motor control unit for controlling a motor load (e.g., a ceiling fan or an exhaust fan); a drive unit for controlling a motorized window treatment or a projection screen; motorized interior or exterior shutters; a thermostat for a heating and/or cooling system; a temperature control device for controlling a heating, ventilation, and air conditioning (HVAC) system; an air conditioner; a compressor; an electric baseboard heater controller; a controllable damper; a humidity control unit; a dehumidifier; a water heater; a pool pump; a refrigerator; a freezer; a television or computer monitor; a power supply; an audio system or amplifier; a generator; an electric charger, such as an electric vehicle charger; and an alternative energy controller (e.g., a solar, wind, or thermal energy controller). A single control circuit may be coupled to and/or adapted to control multiple types of electrical loads in a load control system.

## Claims

1. A method for controlling an amount of power delivered to an electrical load, the method comprising:
receiving a load current feedback signal that indicates an average magnitude of a load current through the electrical load;
generating at least one drive signal for controlling the load current;
adjusting an operational characteristic of the at least one drive signal in response to the load current feedback signal in order to control the amount of power delivered to the electrical load towards a target amount of power;
controlling the average magnitude of the load current towards a target load current that ranges from a maximum rated current to a minimum rated current in a normal mode; and
controlling the average magnitude of the load current below the minimum rated current in a burst mode, wherein the burst mode includes at least one burst mode period that comprises a first time period associated with an active state and a second time period associated with an inactive state;
wherein, during the burst mode, the method further comprises adjusting the operational characteristic of the at least one drive signal to regulate a peak magnitude of the load current towards approximately the minimum rated current in response to the load current feedback signal during the active state, and stopping generating the at least one drive signal while maintaining the operational characteristic of the at least one drive signal constant during the inactive state to control the average magnitude of the load current to be less than the minimum rated current when in the burst mode.

2. The method of claim 1, further comprising:
adjusting a burst duty cycle to maintain the average magnitude of the load current below the minimum rated current;
wherein a duration of the first time period associated with the active state is determined based on the burst duty cycle.

3. The method of claim 2, further comprising:
during the burst mode, regulating the peak magnitude of the load current to the minimum rated current during the active state in a first burst mode period and to the minimum rated current plus a current offset during the active state in a second burst mode period.

4. The method of claim 3, wherein the current offset ranges from a minimum current offset to a maximum current offset based on the burst duty cycle and the target amount of power.

5. The method of claim 4, further comprising:
increasing the load current from an initial current to the minimum rated current plus the current offset over a ramp time period at a beginning of the first time period.

6. The method of claim 2, wherein adjusting a burst duty cycle further comprises adjusting the burst duty cycle in response to the target amount of power during the burst mode.

7. The method of claim 2, wherein adjusting a burst duty cycle further comprises adjusting the burst duty cycle linearly with respect to the target amount during the burst mode.

8. The method of claim 2, wherein controlling the average magnitude of the load current below the minimum rated current in a burst mode further comprises controlling the average magnitude of the load current below the minimum rated current in the burst mode when the target amount of power is less than a transition amount of power that is associated with the minimum rated current.

9. The method of claim 2, further comprising:
regulating the average magnitude of the load current by adjusting the burst duty cycle and the target load current during the burst mode.

10. The method of claim 1, wherein the operational characteristic of the at least one drive signal comprises a duty cycle or an operating frequency of the at least one drive signal.

11. The method of claim 1, further comprising:
adjusting a duty cycle of the at least one drive signal to regulate the average magnitude of the load current to the target load current in response to the load current feedback signal in the normal mode; and
adjusting the duty cycle of the at least one drive signal to regulate the peak magnitude of the load current to the minimum rated current in response to the load current feedback signal in the active state during the burst mode.

12. The method of claim 1, further comprising:
increasing the load current from an initial current to the minimum rated current over a ramp time period at a beginning of the first time period.

13. A method for controlling an amount of power delivered to an electrical load, the method comprising:
controlling an average magnitude of a load current through the electrical load in a normal mode and in a burst mode, wherein the burst mode comprises at least one burst mode period that comprises a first time period associated with an active state and a second time period associated with an inactive state, and a duration of the first time period associated with the active state is determined based on a burst duty cycle; and
during the normal mode, adjusting a target load current based on a targeted amount of power to be delivered to the electrical load to regulate the average magnitude of the load current while holding the burst duty cycle constant;
wherein, during the burst mode, the method further comprises, based on the target amount of power, adjusting the burst duty cycle and adjusting the target load to regulate the average magnitude of the load current, wherein adjusting the target load current comprises:
determining a current offset that ranges from a minimum current offset to a maximum current offset based on the burst duty cycle and the target amount of power; and
adjusting the target load current by the current offset.

14. The method of claim 13, further comprising:
during the burst mode, decreasing the target load current during consecutive burst mode periods while holding the burst duty cycle constant to decrease the average magnitude of the load current; and
decreasing the burst duty cycle and increasing the target load current in a succeeding burst mode period to decrease the average magnitude of the load current during the burst mode.

15. The method of claim 13, further comprising:
during the burst mode, increasing the target load current during consecutive burst mode periods while holding the burst duty cycle constant to increase the average magnitude of the load current; and
increasing the burst duty cycle and decreasing the target load current in a succeeding burst mode period to increase the average magnitude of the load current during the burst mode.

16. The method of claim 13, wherein determining the current offset based on the burst duty cycle and the target amount of power comprises determining the current offset based on a fractional portion of an ideal burst duty cycle during the burst mode.

17. The method of claim 13, further comprising:
in the normal mode, regulating the average magnitude of the load current to the target load current that ranges from a maximum rated current to a minimum rated current; and
in the burst mode, controlling the average magnitude of the load current below the minimum rated current.

18. The method of claim 13, wherein the normal mode is characterized by the burst duty cycle being equal to approximately 100%.

19. The method of claim 13, further comprising:
stopping regulating the load current during the second time period.

20. The method of claim 13, further comprising:
increasing the load current from an initial current to a minimum rated current plus the current offset over a ramp time period at a beginning of the first time period.

21. A method for controlling an amount of power delivered to an electrical load, the method comprising:
adjusting an average magnitude of a load current in a normal mode and in a burst mode;
regulating the average magnitude of the load current between a maximum rated current and a minimum rated current in the normal mode;
regulating the average magnitude of the load current below the minimum rated current in the burst mode by regulating a peak magnitude of the load current towards a target load current during a first time period of the burst mode and stopping regulating the load current during a second time period of the burst mode; and
increasing the load current from an initial current to the target load current over a ramp time period at a beginning of the first time period of the burst mode.

22. The method of claim 21, further comprising:
receiving a load current feedback signal that indicates the average magnitude of the load current;
generating at least one drive signal for controlling the load current; and
adjusting an operational characteristic of the at least one drive signal in response to the load current feedback signal.

23. The method of claim 22, further comprising:
during the burst mode, adjusting the operational characteristic of the at least one drive signal to regulate the peak magnitude of the load current towards approximately the minimum rated current in response to the load current feedback signal during at least a portion of the first time period.

24. The method of claim 23, further comprising:
stopping generating the at least one drive signal during the burst mode to control the average magnitude of the load current to be less than the minimum rated current; and
maintaining the operational characteristic of the at least one drive signal constant during the second time period of the burst mode.

25. The method of claim 24, further comprising:
maintaining the operational characteristic of the at least one drive signal constant while increasing the load current from the initial current to the target load current over the ramp time period during the burst mode.

26. The method of claim 25, further comprising:
adjusting the operational characteristic of the at least one drive signal to regulate the peak magnitude of the load current towards approximately the minimum rated current in response to the load current feedback signal after the ramp time period during the first time period of the burst mode.

27. The method of claim 26, further comprising:
waiting for a wait time period after the ramp time period; and
after the wait time period, adjusting the operational characteristic of the at least one drive signal to regulate the peak magnitude of the load current towards approximately the minimum rated current in response to the load current feedback signal.

28. The method of claim 21, wherein the target load current comprises one of the minimum rated current or the minimum rated current plus a current offset.

29. The method of claim 28, wherein the current offset ranges from a minimum current offset to a maximum current offset based on a burst duty cycle and a target amount of power to be delivered to the electrical load.