!1 .

NASA Contractor Report 185126

__'_ Advanced Modulation Technology

Development for Earth Station

Demodulator Applications

R.C. Davis, J.V. Wernlund, J.A. Gann,

J.F. Roesch, T. Wright, and R.D. Crowley

Harris Corporation GCSD

Melbourne, Florida

July 1989

¢

6

Prepared for

Lewis Research Center

Under Contract NAS3-24681

National Aeronautics and

Space Administration

{NASA-CR- 1851 26) ADVANCED MODULATION

TECHNOLOGY DEVELOPMENT FOR EARTH STATION

DEMODULATOR APPLICATIONS Final Report

CHarEis COrpo)_ 282 p CSCL 09F

G3/I 7

ti89-26880

Unclas

0224576
INTRODUCTION

This report is prepared by Harris Government Communications

Systems Division for NASA Lewis Research Center under contract

NAS3-24681. This report is written in response to SOW paragraph 3.7.3,

Final Report. The purpose of this document is to provide a summary of the

entire contractual efforts, pertinent results, and a compilation of the task

reports.

1.0 Task I Report

The Task I Report describes the refinement of the proposed

downlink modulation system design concept. It develops in detail the

specific modulation scheme used, the conceptual design for the Earth

station demodulator hardware implementation, and an assessment of the

impact of future technology on system performance.

.0 Task III Breadboard Evaluation Report

This report describes the test results for the A/D converter

breadboard developed during Task III and was written in response to SOW

paragraph 2.3.5. Task III was the breadboard development phase of the

program.

.0  ̧ Task V Design Review Package

This section contains the material presented at the Task V

final design review. This material is in vu-graph format and describes the

POC Model Demodulator and the Special Test Equipment (STE) detailed

design. Included are descriptions of the design and layout, functional

performance, size, weight, power, and results of functional performance

analyses.

4.0 Coded 16-ary CPFSK Coherent Demodulator Paper

This section contains a paper which was published in the

Proceedings of the Mobile Satellite Conference, sponsored by the Jet

Propulsion Laboratory. It is a summary of the conceptual design and

design implementation for the modulation system developed in response to

the requirements of this contract.
5 0 Task VII Report

The Task VII Report provides the results of POC Model Testing

and Analyses. The purpose of this document is to present the results of

the tests conducted in accordance with the POC Model Test Plan and

Procedure developed in response to SOW subtask 2.5.3. The POC Model Test

Plan and Procedure is included in the Task VII Report. This report also

provides recommendations for the development of an engineering model

demodulator using further advanced implementation technology, based on

analyses of test results.

ii
CONTENTS

TASK I REPORT by Richard D. Crowley ..................

HIGH SPEED A/D CONVERTER BREADBOARD EVALUATION REPORT

by James F. Roesch, Jr ........................ 54

TASK V REVIEW by Richard D. Crowley, Robert C. Davis, and

James A. Gann ............................ 81

DEVELOPMENT FOR A CODED 16-ARY CPSFK COHERENT DEMODULATOR

by Ken Clark, Robert Davis, and Jim Roesch .............. ]78

TASK VII REPORT ............................ 184

Page

]

iii
NAS3-24681

ADVANCED MODULATION TECHNOLOGY DEVELOPMENT

TASK I REPORT

APRIL 4, 1986

HARRIS CORP. GCSD

P. O. BOX 91000

MELBOURNE, FL 32902

SUBMITTED BY:

RICHARD D. CROWLEY

PREPARED FOR:

NASA LEWIS RESEARCH CENTER

CLEVELAND, OH 44135

|
i. DETAILED DEVELOPMENT OF THE MODULATION SCHEME ............ 3

i.i Modulation Scheme Comparisons .................... 3

1.2 Rationale for the Scheme Selected .................. ]4

1.3 Detailed Description of the Modulation Scheme Developed ....... ]7

1.4 A Description of the Method and Estimated Speed of Independent Burst

Acquisitions ............................ 2 ]

2. CONCEFI_AL DESIGN OF DOWNLINK MODLKATION HARDWARE .......... 33

2.1 Downlink Modulation System Conceptual Design ............ 33

2.2 Theoretical Performance Characteristics and Operating Conditions of

the Downlink Modulation System Design Concept ............ 35

2.2.1 Bandwidth Efficiency ....................... 36

37 2.2.2 Power Efficiency .........................

2.2.3 Bit Error Rate Performance .................... 38

2.3 "Ility" Data ............................ 4]

2.3.1 Producibility - Special Features for Lowering Costs when Produced

in Quantity ............................ 4]

2.3.2 An Estimate of Recurring Costs .................. 44

2.3.3 Reliability ............................ 45

2.3.4 Maintainability .... ...................... 45

2.4 Overview of Special Test Equipment ................. 46

3. TECHNOLOGY ASSESSMENT AND DESIGN IMPACT ............. 47

3.1 Current Versus Future Technology ................. 47

3.2 Hardware Techniques which Represent an Advancement in the

State-of-the-Art in Modulation Technology ............. 49

3.3 The Impact of Technology on System Performance ........... 50

3.4 Advantages and Disadvantages of Implementation Technologies .... 5]
i

V

i. D_DL_;_B_(_'I_._ON_

This section of the task one report details the development of the

modulation scheme chosen to fulfill the requirements given in the Statement

of Work (SOW).

I.i Modulation Scheme Comparisons

The selection of the modulation/coding scheme proposedbyHarris, and

the corresponding implementation thereof has been basedprimarily on:

i. Demodulator simplicity

2. Achieving a transmitted spectral shape whose power outside of the

.5 bit rate point is 20 dB down from the desired signal power

3. Achieving a 5 x 10-7 bit error rate performance with the required

Eb/No as close as feasibly possible to that of QPSK

4. Operating through a non-linear T_T

5. Utilizing a coding scheme that creates minimal spectral spreading

and yet is powerful enough to meet the 5 x 10-7 bit error rate

Careful attention has been paid to performproper tradeoffs based on

these criteria that would substantiate the proposed modulation/coding scheme

and its implementation. The intent of this section is to sunm_rize the most

important of these tradeoffs.

A wide assortment of bandwidth efficient modulation techniques exist

within the industry [i]. Some of these, like Minimum Shift Keying (MSK),

have been developed [2] within the industry in general whereas others like

Continuous Phase Frequency Shift Keying (CPFSK) have been specifically

developed at Harris [3].

The first categorization of these techniques occurs when considering

the envelope variations of the transmitted waveform. Techniques that impart

3
data onto a carrier through its phase or frequency, are constant envelope

signals whereas a signaling scheme that imparts data onto the carrier

amplitude clearly exhibits envelope variations. A candidate in the latter

category is M-ary Quadrature Amplitude Modulation (MQAM)which has been

shown [3] to have greater power efficiency than schemes such as CPFSKor

M-ary Phase Shift Keying (MPSK)which are in the constant envelope category.

However, time-varying envelope signals require a linear RF channel which

proves to be power inefficient in a satellite T_T that must be backed-off to

provide such linearity. In this present _I)MAdownlink the minimization of

signal distortion may require a i0 dB backoff which in our opinion is too

great a price to pay in lost link margin for the increased bandwidth

efficiency. Therefore this first tradeoff concluded that only constant

envelope signals would be acceptable because of the power inefficiencies

caused by the T_T backoff.

Another technique that was considered is to generate a constant

envelope signal that is amplified by the transmit T_rf and then filtered to

shape the spectrum. The modulation scheme shown in Figure i.I-I Was

i

considered relative to the Statement of Work (SOW) requirements. As shown, a

200 Mb/s QPSK constant envelope modulation is employed through the power

amplifier (PA) so that the nonlinear AM/AM and AM/PM characteristics given

in the SOW can be tolerated.
200 MB/S

r

QPSK

Modulator

Constant

Envelope

QPSK

20 GHz

SA(10) J 100 MHz

v I BWH T Filter (W)

k._

v

t

2 Bits/Sec/Hz

Figure 1.1-1 An Alternative Modulator Approach

l.e.,

After the amplifier, the spectrum is of course still that of QPSK,

sin (2 7rf/ fD)

SA(W) = 2 7rf/f B (i)

where, f = frequency removed from the carrier

fB = Bit rate = 200 Mb/s

The first nulls of this spectrum are at + .5 Bit rate, i.e., in the

center of the adjacent channel and consequently the main lobe will cause too

much adjacent channel interference. Thus, additional filtering is required

after the PA.

An approach that is attractive at first glance is to duobinary shape

the spectrum after the amplifier. There are several ways of performing this

spectral shaping. Irregardless of how it is done, the overall combination of

I

transmit and receiver filtering must result in a net filter of:

HdB(W) = cos 27r f I f I < .25f B

fB'

= 0 , elsewhere

(2)

5
One way to perform the filtering is to do the full duobinary shaping at

the transmitter, i.e., squeeze the spectrum of eq. (i) to give HdB(W) in eq.

(2). This requires a transmit waveguide filter after the PA with the

transfer function:

2 7r (f/fH)

HT(W) -sin(27rf/_) cos(2;rf/f B) , I f i < .25f B (3)

= 0 , elsewhere

The transmit filter in eq. (3) causes 3 dB of power loss just due to

spectral truncation of the (sinx)/x spectrum out of the PA. In addition,

there is power loss due to midband insertion loss of the filter. The sum of

the 3 dB spectral loss and the insertion loss is a loss in link margin and

reduces the efficiency of prime power consumption that can be critical in

the satellite environment.

In addition, if the full duobinary shaping is done at the transmitter,

the receive filter theoretically must have an ideal sharp cutoff at + .25 fB

with a flat response across the band. Consequently, the effects, on

performance and on adjacent channel interference rejection, of a more

realistic receiver filter needs to be carefully considered.

Another approach to obtaining the duobinary shaping after the PA is to

equally divide the filtering between the transmitter and the receiver. This

leads to a transmit filter of,

2 7r (f/_)

-sin(27rf/fB) [cos(2;rf/fB)]i/2 , i f ] < .25f B (4)

and a receive filter of:

HR(W) = [cos (2 ;rf/f B) ]1/2 , i f J < .25f B (5)
f

With the transmit filter of eq. (4), 2 dB of spectral truncation loss

occurs, plus the filter midband insertion loss.

If well-known duobinary precoding techniques are used and simple

"slicer" receivers are used to receive the duobinary signal created at the

receiver, 3 dB of theoretical performance loss occurs relative to QPSK

occurs with full duobinary shaping at the transmitter (given one can build a

reasonable approximation to the ideal sharp cutoff filter required at the

receiver without much additional loss). The performance loss for the equal

filter division case with the simple slicer receiver is 2.2 dB theoretical.

Making use of Viterbi algorithm demodulation concepts, it is possible

to recoup most of the performance losses relative to QPSK (3 dB and 2.2 dB

in the full and equal filter division cases, respectively). Such an approach

would involve building two i00 MHz (= symbol rate) 2-state Viterbi

processors (one for each of the quadrature detector outputs).

Table I.i shows the summarizing data concerning the performance of

employing duobinary signaling to meet the _ objectives. From the columns

showing degradation in received signal-to-noise ratio (SNR) requirement

relative to QPSK, the simpler slicer receivers do not provide the needed

perforn_nnce. _is leaves the Viterbi receivers, which obtain the required

performance, but require i00 Mb/s 2-state Viterbi demodulators on each of

the quadrature detector outputs. The i00 Mb/s high rate may be a bit of an

implementation problem, but the 2-state Viterbi demodulator is not

conceptually complex.
Table I.i Duobinary SummaryData

Duobinary

Filter

Division

Full Xmlt

Full Xmit

Equal

Xmlt/RCVR

Equal

Xmit/RCVR

ST

Spectral

Truncation

Loss, dB

3

L I

Filter

Insertion

Loss, dB

1-2

1-2

1-2

1-2

ST+L I

Net Link

Margin

Loss, dB

4-5

4-5

3-4

3-4

RCVR

Viterbi

Slicer

Vlterbi

Slicer

Theory:

QPSK

Degrad.

Loss, dB

-0

-3

-0

-2.2

The desirability of this constant envelope QPSK through the PA followed

by tight filtering reduces to consideration of the importance of these

factors:

I. At best, 3 to 5 dB of link margin will be lost due to the transmit

filters.

2. The modulator required is a 200 Mb/s QPSK modulator.

3. The demodulator is a I00 MHz symbol rate quadrature demodulator

followed by i00 Mb/s 2-state decoders on each rail.

4. Additional filters are required at the downlink modulators.

Other such filtering techniques can be done, but based on link margin

losses, these techniques do not meet the objectives of power efficiency and

thus our efforts are directed to constant envelope modulation waveform

signals.

8
Based on this constant envelope decision, attention was then focused on

those signaling schemes that modulate data unto the phase or frequency of a

carrier. One of the more widely used forms of modulation is Phase Shift

Keying (PSK). It's utility arises in power limited channels where binary PSK

provides good Eb/No performance for a given bit error probability. However

it's capability in bandlimited channels is remarkably poor because the first

sidelobe, which peaks at 1.5 x bit rate, is only 13 dB down from the main

lobe. In order to achieve the spectrum requirement of 20 dB down power

outside of the .5 x bit rate point, an Mary PSKschemewith M > 32 would be

required. Assuming no intersymbol interference, signal power efficiency

would drop some 18 dB from QPSKif M = 64. This power efficiency loss is

deemedtoo severe, and thus eliminates PSK from further consideration.

Attention was then turned toward Frequency Shift Keying (FSK) signaling

schemes.

Conventional FSK signaling (conventional in that the tonal separation

is equal to an integer multiple of the symbol rate) is by itself not a

spectrally efficient modulation scheme. However, two modifications to the

conventional FSKscheme can be madeto minimize this inefficiency. The first

is to reduce the tonal separation, or frequency deviation, thus compressing

the spectrum and necessitating a coherent receiver. Secondly, instead of

permitting phase jumps at the symbol transitions, phase may be forced to be

continuous across the transition boundary. The latter modification produces

what is well known to be continuous phase FSK, or CPFSK.A subset of this

class of signaling schemes is MSK which is merely binary CPFSKwith a

frequency deviation ratio of .5. As seen .in Figure 1.1-2 the only M-ary

CPFSKschemes that have a chance of meeting the out-of-band requirements is

one where M > 16. Both 8-ary CPFSK and 4-ary CPFSK (otherwise known as
-10

__o_oO,_EO .,

15-ARY. {_ = 2

-30

0.5 BR

0 0.2 0.4 0.5

_"-,,.._INARY. 19"" 180 ° (MSK)

i

I

r

0.8 i.0 i.2

RF BW IN BIT RATES

FIGURE 1.1-2 Spectral Characteristic of Uncoded CPESK

lO
!

!

MSK/2) have out-of-band powers greater than the required 20 dB down from the

desired signal power. Excluding intersymbol interference, the power

efficiency loss relative to QPSK performance for 16-ary CPFSK is 13 dB. In

comparison to PSK, CPFSK achieves the spectral requirement without filters

but does so with a smaller power efficiency. Therefore, 16-ary CPFSK was

chosen as the most likely signaling scheme capable of successfully meeting

the QPSK performance when coding is added.

It is unfortunate that when forward error correcting coding is required

in many systems, it is applied only as an afterthought by appending it to an

already defined modulation format. For instance, the application of a rate

1/2 convolutional code, which is quite co_aon, to an 8-ary FSK modulation

format, seems congenial on the surface. However, each FSK symbol contains 3

coded bits thus making soft decision generation somewhat unhandy. On the

other hand if a rate 1/3 code where used, the soft decision generation is

now quite straight-forward, and if desired, more powerful symbol decoding

could be performed in the decoder. This latter case is an example of a

conscious marrying of a coding techniqu e to a modulation format. Applying

such a conscious effort to the bandlimited/power limited channel is an

extremely high priority design focus. In fact we believe it is one of the

most novel approaches toward consciously marrying modulation and coding in

that we do not waste precious bandwidth to squeeze out tenths of dB's in

performance. On the contrary, we use a moderate amount of coding (33% band

spreading) but place it in that part of the modulation waveform where it is

going to yield the greatest coding gain. This novel and Harris-patented

(License rights owned by the Government) approach codes only the LSB's of a

CPFSK symbol since errors are usually made to nearby signals in the signal

space. Any coding to correct extremely low probability noise events (those

]!
that cause errors in distant signals in the signal space) is a waste of

bandwidth. An additional benefit of this coding technique is the hardware

savings it provides by not requiring a decoder sync since symbol timing

coincides with the decoder timing.

The coding technique which we developed on the 1979 RADC-sponsored

Study [5] is almost identical to that investigated by researchers at the

University of Virginia [6,7] in conjunction with M-PSKmodulation on a study

sponsored by NASA/LeRC.Unlike the MPSKschemes, however, our approach using

coded 16-CPFSKmodulation requires no additional spectrum shaping filters to

achieve 2 bits/sec/Hz adjacent channel operation. In addition, the shaped

spectrum signal of our coded 16-CPFSKmodulation is of constant envelope,

and thus avoids all nonlinear amplifier problems.

For the same number of coder states, the coded 16-PSK approach is

theoretically 2 dB more power efficient than our coded 16-CPFSK approach

solely on the basis of received SNR. However (and this is very important)

the 16-PSKschemewill have to use post amplifier filtering to trim the

(sinx)/x spectrum to meet the adjacent channel operability requirements of

the SOW. If pre-amplifier filtering is proposed with the coded 16-PSK

signal, the backoff required to prevent sidelobe restoration after the

nonlinear PA will be excessive from a link power efficiency standpoint. Even

with post amplifier filtering, the 2 dB theoretical advantage of the coded

16-PSKapproach will be offset by the insertion loss of the required filter.

We believe our constant envelope coded 16-CPFSKapproach, in requiring no

filtering, is the better approach from the overall link power efficiency and

equipment simplicity standpoints and thus will be adopted as our baseline.

The final trade-off area to be discussed is the demodulator

implementation. When using CPFSKit is possible to perform data detection

]2
over multiple symbols because of the memoryintroduced into the waveform by

forcing phase continuity during symbol transitions. While this

multiple-symbol detection provides greater power efficiency [8], it carries

along with it the necessity to perform a large number of matched filter

correlations in a Viterbi-like, maximum-likelihood, sequence estimator

algorithm [9]. For 16-ary CPFSKwith a detection over just 2 symbols, 256

(162) individual correlations would need to be performed. This is contrary

to the objective of demodulator simplicity and furthermore it only gains

about 2 dB at an uncoded error rate of 10%. Therefore we have chosen to

perform a simpler multi-symbol observation phase detection. Now, once we

madethis decision we further discovered that we could use a simple, Harris

proven [i0] technique of phase sampling and thus eliminate the need for 16

separate matched filters. A negligible performance difference at low error

rates further enhances this phase sampling technique over the matched filter

approach.

Listed below is a summarization of what these major tradeoffs have

produced:

I. 16-ary CPFSKis the least complex, bandwidth efficient modulation

format capable of meeting the out-of-band power requirement.

2. Multiple symbol detection with a Viterbi-like, maximumlikelihood

sequence estimator is not warranted from a complexity viewpoint

although it does slightly increase power efficiency.

3. Multi-symbol observation detection is performed with a simple,

and Harris proven, phase detector technique.

4. A Harris patented, bandwidth efficient coding technique has been

creatively matched with 16-ary CPFSKto provide coding gain where

it is needed most.

]3
1.2 Rationale for the SchemeSelected

The selection of our approach was driven by key factors from both the

SOWand the evaluation of system requirements for optimizing overall

modulation technique performance. The key considerations in the selection of

the signaling schemeare given below.

i. Constant envelope signaling provides maximumtransmit _T efficiency

2. Any filter at the satellite will dissipate power by spectral

truncation and insertion losses, and will thus reduce link margin

since the T_T is peak limited

3. Coding gain is necessary, but must be applied efficiently

4. Hardware simplicity is critical for cost effective implementations

in the 1990's

Any combination amplitude and phase modulation scheme will require

backoff of the T_T from its saturation point and will decrease the overall

link efficiency. Therefore, the only parameters left for the modulation are

the phase and/or frequency of the signal.

M-ary PSK has been considered by Harris and other researchers [6] for

applications such as this. With proper coding, near-QPSK level performance

can be attained. The difficulty with PSKis that the rapid changes in phase

result in bandspreading of the energy which must then be filtered for

adjacent channel performance. The energy loss of the required filtering

process is directly applied to link margin and must be considered when

evaluating the modulation scheme. To illustrate this consider Figure 1.2-1.

In A the signal is filtered prior to the input to the TWT. However, the

signal now has amplitude variation due to the filter and the TWT must

operate in the linear region (i.e., backoff from saturation) which decreases

the average power and efficiency of the satellite output. In B the input to

]4
theiST is a constant envelope signal; the filtering is accomplished at the

output. The filter truncates the spectrum and dissipates the power from

insertion losses. In either case A or _, the power transmitted from the

satellite is reduced by several dB and the overall system link margin is

decreased.

Amplitude Variation

Due to Filter

M-Ary PSK .._ J

Modulator BPF Output

A. Filtering Prior to T_T

M-ary PSK

Modulator

BPF I T _

Truncation & Insertion

Loss of Filter

B. Filtering After _T

Figure 1.2-1 Transmit Filtering

The bandwidth problem of PSK is solved by utilizing a CPFSK approach.

As shown in Figure 1.1-2, the modulated spectrum is adequate for

transmission with no filter and the only remaining selection is the size of

the transmit alphabet for bandwidth compression. Additionally, a unique

]5
constraint of the phase progression of the signal resulted in a powerful

coding gain for system performance.

Knowledge of the good spectral properties of our proposed CPFSK

signaling is, of course, not unique to Harris. Many efforts have been

directed here and elsewhere at trying to improve the performance obtainable

with CPFSK modulation. These efforts have involved attempts to shape the

phase trajectories and an exploitation of the codir_g-like gains available

with multisymbol observation optimum receivers. Multisymbol observation is

available with CPFSK because of the continuity of RF phase in the

transmitted waveform that makes the present time symbol depend on previously

transmitted symbols. Impressive, tantalizing performances are obtained for

some of the CPFSK schemes. Their only drawback is the complexity of the

optimum Viterbi algorithm demodulators required to get at the performance.

The uniqueness of the Harris demodulation approach resides primarily in

the way we have managed to sidestep the complexity of the optimum

demodulator, yet still retain most of its performance. We have done this by

developing a multisymbol observation phase detection receiver that is

simple, yet obtains performance within 2 dB of the optimum multisymbol

observation Viterbi type of demodulator. Our simple phase detector approach

(see the Harris proprietary addendum) allows relatively narrowband filtering

(1/2 bit rate BW) ahead of the phase detector, and needs no intersymbol

interference corrector to obtain its impressive performance relative to the

complicated optimum receiver. Thus our coherent phase detector technique

exploits the coding-like gains inherently available in the CPFSK signaling

format.

The way in which we apply coding with low (33%) bandspreading, yet

still obtain impressive coding gain is another unique feature of our

]6
approach. We developed this coding strategy on a 1979 study for RADC[5].

Essentially the samecoding approach in connection with M-ary PSKmodulation

is proposed in 1982 [6] and 1984 [ii] papers by researchers at the

University of Virginia. Their work was at least in part sponsored by

NASA/LeRC. We prefer our coded 16-CPFSK approach over a coded 16-PSK

approach for reasons detailed in paragraph i.i.

Conceptually, we believe our approach of overlaying coding on the

spectrally compact CPFSKsignal to improve its performance is a practically

important and enlightened one. Unlike someother ongoing research efforts

that attempt to circumvent the limitations of simple CPFSKthrough the

choice of more complicated phase trajectories (multimod index, cosine

shaping instead of linear shaping of the trajectories, partial response

shaping on the trajectories, etc.), our approach simply lives with the

distance structure inherent in standard CPFSKand then improves it with

coding. From the implementation standpoint, we believe our approach is

superior.

1.3 Detailed Description of the Modulation Scheme Developed

The technique for accomplishing the performance requirements of the SOW

is a 'modulation scheme pioneered by Harris and known as Continuous Phase

Frequency Shift Keying (CPFSK). The scheme is a refinement of the well-known

Frequency Shift Keying (FSK). CPFSK is a modification of FSK which provides

spectral efficiency by reducing the frequency deviation and constraining the

phase to be continuous across symbol transition boundaries. At the beginning

of a symbol, the transmitted frequency is chosen at the modulator to be 1 of

16 possible transmit frequencies (for 16-CPFSK). This resulting frequency is

transmitted for the duration of the symbol and the process is repeated for

]7
each symbol transmitted. Because of the memory induced into the waveform by

forcing the phase continuity, a mapping function that relates the modulator

four bit (i of 16) input to the transmitted phase value at the end of a

symbol time can be generated. By computing a running count on phase, the

modulator can project what frequency must be transmitted to force the output

phase to exactly hit the desired phase node (value) at the end of a symbol

time. This frequency is then sent across the link and a demodulated phase

constellation such as shown in Figure 1.3-1 is generated. This variation on

the transmit frequency selection is transparent to the overall performance

of 16-ary CPFSK but is the key to the application of coding for performance

improv_t.

0101 (_

0111 (_

0110 _)

1 000

1 001

1011 _)

1010_

01

OOQg_0010

(_ 0011

(_ 0001

(_ 0000

_1110

@1111

_)1101

_1100

Figure 1.3-1 Demodulated Phase Constellation

The input data stream is demultiplexed, in the modulator, into three

data streams (see Figure 1.3-2) in which the Least Significant Bit (LSB) is

convolutionally encoded R=I/2, K=7. The corresponding four bit output

18
determines the frequency that will be sent by computing the necessary

frequency deviation to arrive at the desired phase node. From this, it can

be seen that the two Most Significant Bits (MSB's) determine the quadrant of

the transmitted phase (at the end of a symbol) and the LSB's determine the

position within a quadrant. For the bit assignments shown in Figure 1.3-1,

any group of 4 adjacent phases contain all possible combinations for the two

bits from the coder (i.e., LSB's). Further, within the set of any four

adjacent phases, antipodal code branches (e.g., 00 and Ii, or i0 and 01)

produce phases differing by 45 ° and orthogonal branches (e.g., 00 and 01, or

i0 and ii) produce phases differing by at least 22.5 °. These properties are

used in the Harris approach to provide coding gain that results in near QPSK

performance.

200 MB/S_ _----.1

Data In vlDEMUXl--.-- " 1

67 MB/S

67 MB/S

I

/

67 MB/..¢ I R = 1/2

Conv.

Coder

If

f

Rj

f

/

I 11

f

h.

v

16-CPFSK

_. Modulator

v

67MHz

Symbol Rate

P-P

Deviation

=62.SMHz

v

XMTD RF

99.5% BW

=100MHz

v

Figure 1.3-2 CPFSK Modulator

The spectral output power density versus bandwidth is shown in Figure

1.1-2 for 4-ary (also known as MSK/2), 8-ary, and 16-ary CPFSK. From the

SOW, it can be derived that adjacent and co-channel interference

requirements equate to a spectrum shaping requirement that the energy

outside of the 0.5 bit rate bandwidth, be -20 dB relative to the total

]9
signal power. As can be seen in Figure 1.1-2, 16-ary will provide the

spec£ral shaping performance without tran_nit filtering. In addition, the

16-ary exceeds this requirement by a sufficient amount to allow 20-30%

bandspreading to accommodate coding for overall system performance gain.

The combination of information coding in both the transmitted frequency

and the phase state at the end of a symbol time, results in a signal that

makes maximum use of the occupied system bandwidth. This unique spectral

efficiency also supports maximum system power efficiency in two aspects.

First, the resulting signal is constant envelope and thus the transmit _WT

can be saturated for peak performance. Secondly, the transmit spectral

shaping is inherent in the scheme and requires no filter which conserves

power that would be lost in filtered spectrum truncation and insertion

losses. This holds true whether the transmit filters are incorporated before

or after the T_T since peak power available determines the link margin.

If baseband pulse shaping is incorporated into the modulator, further

increases in spectral efficiency may be achieved at the modulator output

without spectral filtering of the IF. In figure 1.3-3 we show the spectra

produced at the modulator output for different choices of the modulator

baseband pulse shaping filter. The curve for square pulses corresponds to

standard 16-CPFSK signalling with 16 equispaced frequencies at a spacing of

1/16 of the symbol rate. The other curves are for various alphas on a square

root of Nyquist filter with a raised cosine frequency characteristic. The

far sidelobes are significantly reduced with the non-square pulse shaping

baseband filters. The adjacent channel is located at 1.5 symbol rates from

center (or .5 bit rate for our 3 information-bit/symbol scheme). We are

contemplating the use of an _ = .25 baseband filter to control adjacent

channel interference.

20
I

16-ARY CONTINUOUS PHASE MODULATION SPECTRA

18

8

-10

_ -4_ .,

_a f II ""

-s8 /..

- I I

-_8 - I /

--./[ °,'

/,°•

A _ PIll 5e2

"

!°0 o

"°., ,

"o.

-2.S -2.B -I .S -! .B -#J.S 8.8 O.S I °8 I .E; Z.B 2.S

SYMBOL RATES FROM CENTER

Figure 1.3-3 16-ary CPFSK Modulation Spectra for Various Baseband Filters

1.4 A Description of the Method and Estimated Speed of Independent Burst

Acquisitions

Here we will provide answers to the TDMA burst acquisition problems.

The problems to be addressed are as follows:

i. How is the coherent phase detector circuitry jammed to the correct

value at the beginning of a burst?

2. What are the effects of frequency offsets on the acquisition

strategy?

3. How is the symbol timing derived for each burst?

4. How is the imsec. TDMAframe timing derived?

21
Figure 1.4-1 illustrates our concept of a single TDMAburst (a TDMA

frame, which lasts 1 msec. in time, may consist of one or more bursts). As

can be seen by Figure 1.4-1 a single TDMA burst consists of three

components; a preamble (32 symbols = 96 bits), a unique word (6 symbols = 18

bits), and data (I 32 symbols). The answers to the above questions all hinge

on the special preamble we are considering to support all the timing

functions.

PREAMBLE UNIQUE WORD DATA

32 Symbols 6 Symbols _ 32 Symbols

96 Bits 18 Bits >_ 96 Bits

Figure 1.4-1 A Single _DMA Burst

The preamble must provide for initial phase acquisition, and initial

symbol timing. In the following paragraphs we will address the methods by

which phase and timing are acquired.

Figure 1.4-2 shows the phase modulation applied during the preamble we

have selected. As shown, the preamble corresponds to an alternating

frequency modulation between ± peak deviation = ± 15/32 symbol rate. The

dotted line shows the rise that will occur for the center frequency input

with no frequency offset. We will simply sum the 32 samples of this phase

error over the preamble and divide by 32 to get the average phase error

relative to the lowest frequency reference.

22
Phase

Relative

To

Lowest

Frequency

o

Op -1615 (2_) x 16 = 30_ radians

0 1 2 3 4 ....

Figure i. 4-2

32

Phase Modulation During Preamble

r

t

T

There remain questions about how well does this "phase jam" strategy

work in the face of noise and initial frequency offset. First, how

accurately can the initial phase be acquired in the face of channel noise?

Since we are averaging 32 samples to arrive at an estimate of initial phase

error, the variance of the phase jitter on the estimate is 1/32 of the

variance on each of the individual phase measurements over the preamble.

Thus the phase jam procedure will have only a small impact on overall

performance, causing about i0 LOgl0 (i + 1/32) = .13 dB degradation in noise

performance. Secondly, what is the impact of initial IF frequency offset on

the phase jam strategy? For a 30 GHz uplink, I0 GHz satellite translation, a

20 GHz downlink, and negligible doppler, assuming 5x 10 -7 L.O. stabilities

everywhere, the initial frequency offset is:

F = (30 + i0 + 20) x 109 x 5 x 10 -7 = 30 kHz.

23
The effect of this 30 kHz offset is to cause the preamble phase given by

Figure 1.4-2 to ramp linearly up (or down, depending on the sign of the

offset) over the 480 nsec. preamble, from zero to:

A 8 = 30 x 103 x 480 x 10-9 = .0144 cycle = 5.2 °

Since the phase error increases linearly from 0 to 5.2 ° , the average of

phase over the preamble is changed by 2.6 °. This means that when peak

frequency offset occurs, our phase jam is 2.6 ° in error. Whether or not this

is of concern depends on which SNR at which we are operating. At 12 dB

Eb/No, the SNR in the half-bit rate IF is 15 dB. The noise caused phase

jitter on our signal at that point is:

82 = ] _ 1 = .0158 rad. 2

s 2(SNR) 2(31.6)

or 8s = 7.2 ° RMS.

Thus, 2.6 ° of error in the phase jam due to frequency offset is not

negligible, but should be tolerable with no more than about .5 dB

degradation before the baseband loop removes it, which for a 1 MHz loop

bandwidth or more, takes less than lusec., or < 64 symbols.

We have already described above a technique for acquiring initial phase

for our loop during the special preamble. However, that technique does not

acquire initial frequency offset, which is approximately 30 kHz. Therefore,

the second order phase lock loop is left with the task of acquiring this

30 kHz frequency offset after the phase is jammed by the procedure described

above. We will make use of Figure 1.4-3 to specify a loop bandwidth, FN,

that will acquire the 30 kHz of frequency offset with little phase pull

during such acquisition.

24
38--

20--

LJ 10

0_._ -

U.I

if)

h_

\

Z

h

-18- I I l I I I I l l I I l I I I I

0.0 0.S I .0 I .g 2.0

FN_*T

Figure 1.4-3 Transient Phase Error for a Frequency Step In Versus FN*T

for a Second Order PLL with Zeta = .707

As shown in Figure 1.4-3, the peak phase error induced by the offset,

FSTEP, in a _ = .707, natural frequency - FN loop is described by:

FN 8 = 26 °

FSTEP e,pk

(6)

From eq. (6), it can be seen that the key to holding peak phase error,

8e,pk, to a small value is to choose FN large relative to FSTEP. If we

choose, during the acquisition of a 30 kHz frequency offset, to hold peak

phase error to 1° (which will have a negligible impact on the performance of

our modem), then FN must be:

= 8 x 26 °

e,pk

30x26

1

kHz = 780 kHz (7)

25
As a baseline, we will assume an FN = 1 MHz. Of course, the wider the

loop bandwidth, the larger the channel noise induced phase jitter. The noise

bandwidth of a second order loop is given by:

w.

BE = 2 ( _+ 4_ ) = z ( .707 + 4(.707) 1 ) =

where, FN = natural frequency of the loop (Hz)

= loop damping factor

The loop signal-to-noise ratio SNR L, is:

SNR L = SNRif B L

where, SNRif = IF signal-to-noise ratio

_if = IF bandwidth

BL = loop equivalent noise bandwidth

In our system, for

_4if = 0.5 x bit rate = i00 MHz & FN = 1 MHz,

Then eq. (3) yeilds

SNR L = 30.0 (SNRif)

3.33 FN

The variance of phase jitter due to channel noise in the loop is,

@L2 = 0.5/ (SNRL) (rad 2)

and on the signal in the IF is,

@2 = 0.5/SNRif (rad 2) if

(8)

(9)

(i0)

(ii)

26
From eqs. (9), (I0), and (ii) one obtains

( _882 )2 _- _/___30.0= .033

if

(12)

Equation (12) shows that for a 1 MHz loop, the reference loop jitter is

negligible relative to the IF signal jitter. Performance loss with the loop

jitter given by eq. (12) would be:

Loss = i0 LOgl0[l + ( 82L )2]

82

if

= i0 Log10(l.033)

Loss = .14 dB

From this analysis, we have concluded that a loop bandwidth of

approximately one (i) MHz should be considered. Since we contemplate a

digital loop filter implementation, loop filter bandwidth changes will be

easy to experiment with.

Now we will describe the method whereby symbol timin 9 is derived for

the independent burst transmissions. The symbol timing function must be

performed by observing the preamble and must provide around 1% of symbol

time setting accuracy at the end of the preamble time.

The frequency modulation applied during the preamble, as shown in

Figure 1.4-4 (a), alternates between + peak deviation and - peak deviation.

The peak deviation is (15/32) SR, where SR is the symbol rate. We propose

here a scheme that observes the frequency detector output during the

preamble time with a correlator (probably a surface acoustic wave device)

with an impulse response equivalent to that shown in Figure 1.4-4 (b). The

frequency response of this correlator is passband centered around half

symbol rate = 33.33 MHz with noise bandwidth of (symbol rate)/32 = 2.08 MHz.

27
I

I

I

/

1234

I

. . 31 32

1234

(a) Frequency Modulation During the Preamble

• . . 31 32

(b) Correlator Impulse Response

Figure 1.4-4 Symbol Timing Waveforms

The noise out of the frequency measuring circuit has a parabolic

spectral density given by:

2

N(f) = (f) (13)

2 (SNRif) _if

The spectral density at the center frequency (half symbol rate) of the

correlator is, therefore:

(SR) 2

N (SR/2) = (14)

8 (SNRif) _if

The noise over the 2.08 MHz noise bandwidth of the correlator is, for all

practical purposes, constant at the density given by eq. (14). Therefore,

the noise power out of the correlator is:

28
(SR) 2 (2.08 MHz)

N =

c 8 (SNRif) HWif

(15)

Since for our system, BWif = i00 MHz, we have from (15):

N = (SR) 2 (2"Q8) =

c 8 (SNRif) (i00) SNRif

(16)

The SR/2 clock signal has peak deviation = (15/32) SR or signal power out of

the correlator when the preamble fills it, of:

Sc = (3_2 SR) 2/2 (17)

From eqs. (16) and (17) we obtain a correlator signal-to-noise ratio (SNRc),

of:

Sc

SNRc = N = .0026 (SNRif) = 42.3(SNRif) (18)

C

The jitter on the SR/2 clock has variance

_2 = 1 = 1, (19)

] 2(SNRc) 84-5(SNRif)

and for Eb/No = 12 dB, SNRif = 15 dB in our half bit rate IF. Since 15 dB =

power ratio of 31.6, eq. (19) yeilds:

82 - 1 = .00037

3 84.5(31.6)

or

O = .019 radians (20)

3

Since pi radians of the SR/2 clock represents one symbol time, T, from eq.

(20) we may obtain the R_ timing jitter from the correlator as

-/ T .019 T = .62%(T)

tj = Ir = Ir

Thus we meet out objective of better than 1% of T capability of jamming

symbol timing phase at the end of the preamble.

29
This symbol timing strategy is not affected by DC offsets out of the

frequency measuring circuit (since the correlator has no DC response). This

procedure is also unaffected by AGC error. Thus the symbol timing is

unaffected by either of the other two burst acquisition problems. Once the

initial symbol timing phase is acquired, we will track it with a narrow band

loop, observing the output of the frequency measuring device during the

duration of the burst.

The following discussion will detail the sequence of events in

acquiring access to the TDMA satellite network.

Our assumption is that the TDMA network is active when a new station

desires entry onto the network. The TDMA channel has a master control

station (MCT) burst interleaved with some number of other bursts from ground

stations which have already gained entry on the network. Since the new

station cannot even request service of the network until it acquires the MCT

burst, a crucial task is to acquire the MCT burst.

As given above, the preamble correlator detects each preamble of a

burst as it arrives. Upon burst detection, the 66.7 MHz symbol timing loop

is jammed to the phase indicated by the next zero crossing after burst

detect from the preamble correlator. After jamming the symbol phase, the

loop develops a tracking signal as detailed in a previous discussion. The

modem timing and control function now distributes symbol clock and timing

signals required to sample the preamble-length delayed signal as well as

direct the digital loop to perform burst acquisition and tracking functions

as described previously. The coherent phase measurements made, within a

burst interval but after the preamble, are delivered to the K=7 Viterbi

decoder which performs the decoding of data as described in our proposal. By

scanning the decoder output bit stream, we can detect the MCT unique word,

3O
thereby providing our modemwith the synchronized TDMAdownlink 1 msec.

frame timing. At this point, after no more than one (i) frame of TDMA

reception, we will know all necessary information to gain access to the TDMA

network.

For a fully operational TDMAsatellite system, we have described the

conceptual capability for our modemto perform all necessary acquisition and

network synchronization functions. We have shown adequate capability to

perform the following functions for independent bursts in the TDMAdownlink:

i. Burst Detection

2. Symbol Timing Acquisition

3. Symbol Timing Tracking

4. Coherent Phase Acquisition

5. Coherent Phase Tracking

6. MCTSynchronization to allow synchronization of our uplink bursts

into the uplink TDMAformat

On the proof-of-concept (POC) modem, all functions except number 6.

will be provided. Indeed, we cannot do 6. since that implies knowledge of

network access protocols which are still under development.

However, we will provide a modem that can interface with equipment

implementing any network access assignment and control protocols. Figure

1.4-5 shows the overall block diagram for our POC modem along with its

inputs and outputs which will interface with the evaluation test beds at

NASA/LeRC.

3]
I

Downllnk ISatelllte Downllnl(

I F ._l TDMA

v[ Burst Coherent

Phase Demod

_CoherenJ.

I PhaseVl

Burst _J

Detect vj

SymboLI

Clock vL

K=7

Viterbl Decoder

Hardware

Upllnk _1,'

Bit Stream_l Satellite Upllnk

Uplink I TDMA

Bit Rate d 16-ary Continuous

Clock _[ Phase Modulator

Burst Upllnk Command T

Downllnk BIL

I Stream

Downllnk

Bit RateCIoc'TK

MasterContr_ol

TermlnalDet'ect

Upllnk

IF

Burst

Figure 1.4-5 Overall Satellite _DMA Modem Block Diagram

The dotted line for the MCT detect pulse, which is necessary in an

operational modem for timing and control circuitry in the modulator to

synchronize uplink bursts into the satellite, will not be provided. Rather,

a_ we understand it, the test bed will perform that function. The test bed

is assumed to provide the signal "Uplink Burst Command" to trigger

transmission of an uplink burst. Other inputs to the uplink modulator from

the test bed include uplink bit stream and uplink bit clock. The upiink IF

signal is output from the modulator to the test bed.

On the demodulator side, downlink IF is provided from the test bed to

t/,e demodulator. Coherent phase measurements along with burst detect and

,_ymool clock signals are provided to our K=7 Viterbi error correction

decoder per our proposal. Outputs from our demodulator to the test bed are

thus; downlink bit stream, downlink bit rate clock, and MCT detect.

32
Therefore, the test bed at NASA/LeRC can use this modem for evaluation

purposes, implementing any desired TDMA network access, assignment, and

control protocols.

2. OONCEPTHAL DESIGN OF THE _ MCKKKATION

In this section of the task one report the conceptual design of the

demodulator hardware is presented along with simulation results. Some of the

detailed hardware configurations axe considered to be Harris proprietary and

therefore, the reader will be referred to the proprietary addendum when

appropriate. In addition to the topics given above, this section of the

report will also discuss issues pertaining to producibility, reliability,

;_intainability, recurring costs, and special test equipment.

2.1 Downlink Modulation System Conceptual Design

Harris originally proposed a coded 16-CPFSK signalling scheme to meet

the requirements for the NASA/_DMA satellite downlink. The coded 16-CPFSK

signal was to be demodulated by a coherent phase measurement receiver using

a phase-locked loop (PLL) IF implementation. During our task one

im!estigations, we have still been considering the conceptually equivalent

modulation and demodulation technique, i.e. a 16-ary continuous phase

frequency shift keying modulator coupled with coherent phase measurement

demodulation. However, our present baseline implementation approach is quite

different. Also, there are some detail differences between our present

approach and the proposed approach; primarily in the area of baseband

waveshaping filters at the modulator and demodulator (see Figure 1.3-3).

These detail differences have some advantage over our proposed approach and

are available only because of our present implementation approach.

33
The most significant difference between our proposed implementation

approach and our current baseline approach, lies in our implementation of

coherent phase detection at the demodulator. Our current baseline uses a

Harris-proprietary technique for coherent phase detection. Reasons for

considering this approach include; (i) hardware simplification, (2) single

rail processing as opposed to in-phase and quadrature (I & Q) dual-rail

processing required in the proposed approach, (3) one high speed (67

Msample/sec.) A/D is required, (4) the coherent phase measurement is

available directly from the single rail with no necessity for conversion

from I and Q rail samples to phase as in our proposed quadrature

demodulator, (5) baseband filter techniques at the demodulator, not

dv._ilable with the proposed approach, are applicable to the current

al_>roach, and (6) requirement for a 3 GHz IF PLL is eliminated by using our .

c_Jr_ ent baseline approach.

We believe that our current baseline approach offers the potential for

significantly reduced hardware complexity relative to our proposed approach.

We also believe that this technology is unique to Harris (We have never seen

Jn the technical literature that our current baseline approach to obtaining

coherent phase measurements is known elsewhere, and thus the need for the

Harris proprietary addendum). By achieving our goals on this contract, this

n_xhm will represent a significant advance in modem technology.

Since our current baseline modem involves a departure from prior

coherent phase measurement receivers, it is necessary to give a clear

c_nce[atual picture of our technique. Figure 2.1-1 illustrates our current

baseline conceptual hardware design. The input to the modulator is a data

slream, a bit rate clock, and a burst command. The output from the

demodulator is a demodulated data stream, a bit rate clock, and imsec.

34
th1_ng marks. Thus, our modemmay be used to implement any desired TDMA

network access, assignment, or control protocols. The mathematical

derivations of how we obtain coherent phase measurements from our current

baseline approach, equivalent to an I and Q demodulator, is given in the

proprietary addendum. Detailed block diagrams of the modem signal

processing functions are also given in the proprietary addendum.

Upllnk Burst Command Channel Noise

Stream t Filter Modulator Filter

_ 16-ary Impulses

Uplink BR Clock

Frequency Measuring ___ Baseband Filter

Device Olgltal] I

Baseband

Vlterbl

Decoder Decoded Bit Stream

t_ BR Clock

1 msec. Ticks

t1_ Uncoded Bit Stream

Figure 2.1-1 Current Baseline Conceptual Modem Hardware Block Diagram

2.2 Theoretical Performance Characteristics and Operating Conditions of the

Downlink Modulation System Design Concept

In this section we present results obtained by computer simulations for

the TDMA modem we have described conceptually in prior sections. These

simulations were undertaken to evaluate the impact of several practical

imperfections on our baseline modem. Some of these practical imperfections

are not easily evaluated analytically, so the simulationresults are

necessary and valuable in assessing whether our unique coherent

phase-measurement implementation technique leads to viable hardware.

35
Someof the effects we have investigated include; (i) the intersymbol

interference caused by the bandlimiting IF filter, (2) effect of the A/D

quantizing error in our baseband signal processing, (3) VCOmodulation

nonlinearity, (4) filter group delay distortion, and (5) the effect on

performance of symbol timing offset.

2.2.1 Bandwidth Efficiency

In Figure 2.2.1-1 we show the spectra produced by our modem for

different choices of the modulator baseband filter. The curve for square

pulse signalling corresponds to standard 16-CPFSK signalling using 16

equispaced frequencies with spacing = 1/16 symbol rate. The other curves are

for various alphas on a square root Nyquist filter with raised cosine

frequency transfer characteristics. The far sidelobes are significantly

reduced with non-square baseband filters. The adjacent channel is located at

1.5 symbol rates from center (or .5 bit rate for our 3 information

bit/symbol scheme). Weare contemplating the use of an alpha = .25 baseband

filter to control adjacent channel interference.

I_.,-/_P 'w COtlT_tlltO'Ig PHA._E HODt;LATZON SP[CTPA

-in ...............

/,

,IV .,

m /./

(J J tO •

............

/ t..

_J/.'

-G_ , , - ........... -

"/."

-7';') "," -" -_ ...........

_ln-- _TTT l"T-,-r I r_, r t T-, T, ,"

--_ C: --7 C_ - t ' ; '" " '" _ n 0 _

c'q,'-nl I'._ rr_ rpofl CENTER

Figure 2.2.1-1

"..\

,.,- ..... ".____

• '_

16-ary Continuous Phase FSK Modulation Spectra

36
Figure 2.2.1-2 shows the IF filter characteristic we are using. This

filter has a -6 dB BW= 1.5 symbol rate = .5 bit rate = I00 MHz. We are

currently investigating an implementation approach that will allow the use

of a SAWdevice for the IF filter. Such SANfilters have desirable low group

delay distortion, coupled with steep skirt selectivity.

FULL RAISED COSINE FILTER RESPONSE

ALPHA= .25,-6DB BW = +.75 SYMBOL RATE

0

-'1

-1

-20

-30

-40

-1.0 -0.5 -11 .5 1 0

SYMBOL RATES FROM CARRIER FREQUENCY

Figure 2.2.1-2 IF Filter Characteristics

2.2.2 Power Efficiency

Any filter at the satellite will dissipate power by spectral truncation

and insertion losses, and will thus reduce link margin since the TWT is peak

limited. Since our nx_dulation scheme is constant envelope, the TWT may be

operated at peak efficiency (saturation). In addition, our modulation

scheme, as previously described, requires no transmit filtering and thus

there are no spectral truncation or insertion losses at the satellite. F o r

the same number of coder states, the coded 16-PSK approach is theoretically

37
2 dB more power efficient than our coded 16-CPFSK approach solely on the

basis of received signal-to-noise ratio. However, the 16-PSK scheme will

have to use post amplifier filtering to trim the (sinx)/x spectrum to meet

adjacent channel operability requirements of the SOW. IF pre-amplifier

filtering is used with the 16-PSK signal, the backoff required to prevent

sidelobe restoration after the nonlinear PA will be excessive. If post

amplifier filtering is used, the 2 dB theoretical advantage of the coded

16-PSK approach is offset by the insertion loss of the required filter.

Therefore, we believe our constant envelope coded 16-CPFSKapproach, in

requiring no filtering makes highly efficient use of overall link power.

2.2.3 Bit Error Rate Performance

In this section of the report, bit error rate versus Eb/No will be

given to illustrate the practical effects of various hardware elements, for

both coded and uncoded operation.

Figure 2.2.3-1 shows a comparison of the uncoded error rate curves of

our proposal and our new approach using the square root of Nyquist baseband

filter and the IF filter given by Figure 2.2.1-2. The proposed scheme used

square pulse 16-CPFSK and experienced large intersymbol interference (ISI)

due to the bandlimiting IF filter. This necessitated, in our proposed

scheme, the use of ISI correction circuitry to handle up to ± 22.5 ° of phase

error introduced by the IF filter. Because of the baseband pulse shaping

filter, ISI is considerably reduced (without requiring ISI correction

circuitry), and the performance curve labeled "New Scheme" in Figure 2.2.3-1

is obtained. From this work, we concluded that the ISI correction circuitry

of our proposal could be eliminated, resulting in simpler hardware.

38
10

t,t

O

,,J

10

10

Figure 2.2.3-1

Uncoded 16-Ary Continuous Phase

IF Fltr. Full RCOS, A=.25, B=.75; BBF=SQRT RCOS, A=.25

-......

.,_ ,_ Proposal

-.'-,

o_

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Eb/No In dB

Performance Curve for the New Scheme Versus the Proposal

Figure 2.2.3-2 shows the result of a Monte-Carlo simulation of the

uncoded error rate performance for a hardware implementation of our modem.

The dotted curve is performance of an optimum Viterbi algorithm demodulator

for 16-CPFSK. The solid curve is the analytical performance prediction for

our modem. The dots are Monte-Carlo simulation points. Through computer

modeling, the entire modulator/demodulator was simulat_. Many sequences of

data were sent for each value of Eb/No. Symbol errors were counted and the

error rate computed by dividing the total errors by the total symbols sent.

Important hardware parameters for the simulation were; (i) 8-bit A/D

quantization assumed, (2) the linearity of the frequency measuring device

was approximately .4%, (3) the phase jam strategy, described in section 1.4,

was modeled, (4) the loops had a damping factor, zeta = .707.

39
<

nO

W

Uncoded 16-Ary Continuous Phase

IF Fltr. Full RCOS, A=.25, B=.75; BBF=SQRT RCOS, A=.25

1

- I I i I l I

p-- •

• Monte-Carlo Simulation

- AdD = 8 Bits

"--. _ - AGC & DCR Loop

BW = 5 x 10 "s SR

"" ..._.

%

10 "'_

-_ !'-..

, Co,,,mom), \,

10

=

_ "...

;..,.

10 t',

4 $ 6 • 8 9 10 11 12 13 14 15 16 17 18 lg 20

Eb/No In dB

Figure 2.2.3-2 Uncoded Performance Derived from a Monte-Carlo Simulation

The results given in Figure 2.2.3-2 were encouraging and indicated that

our new coherent phase measurement implementation could be achieved with

realistic hardware. The close comparison between analytical results and

Monte-Carlo simulation results also validated the analytical prediction.

We next produced the analytical performance prediction for the coded

system using a K=7 rate 1/2 convolutional code in the fashion described in

our proposal. The result is shown in Figure 2.2.3-3, where our proposal

prediction assuming no ISI, our current baseline system with ISI, and QPSK

performances are all plotted for comparison. We note that the prediction for

the current baseline is within 2.7 dB of QPSK at 5 x 10 -7 bit error rate.

But it is approximately 1.4 dB worse than our proposal's prediction assuming

no ISI. The loss is apparently due to the residual ISI. Perhaps some of the

1.4 dB loss relative to the proposal prediction can be recovered by careful

40
equalization of the baseband receiver filter. This remains under

investigation.

Coded Continuous Phase 16-Ary Performance

BBF=SQRT RCOS, Alpha=.25

IF Fltr.=Full RCOS LPBW=.75$R, Alpha=.25

\

I-- _ .

<= _ )\\

= \ ,\

o \ ,

uJ 10-4 _X \ • \

X ., ,\

\ ,

\ ,

\

10

10

2 3 4 $

Figure 2.2.3-3

'_r Current _

edlctlon s/IS IJ

\

\

, '_J

_roposa! Predlcl,0n_

7 8 9 10 11 12 13 14 15 16 17 18

EblNo

Coded Performance Prediction

2.3 "Ility" Data

In this section of the task one report several subjects will be

discussed that have the "ility" suffix such as; producibiiity (including an

estimate of recurring costs), reliability, and maintainability.

2.3.1 Producibility - Special Features for Lowering Costs When Produced in

in Quantity

There are several hardware design features of our modem that can reduce

the cost of producing it when large quantities are purchased. The most

notable features are; the extensive use of digital circuits in the baseband

processing, the use of surface acoustic wave (SAW) technology for filtering

4]
applications, and the use of monolithic microwave integrated circuits (MMIC)

for the IF signal processing.

Digital technology has and still is evolving at an incredible pace.

Because of shrinking geometries, integration at the chip level is increasing

while the gate capacitance is decreasing, leading to lower propagation

delays. Also, the cost of producing complex parts keeps falling due to

greater percentage yeilds over time and a ever increasingly competitive

market. It is for these reasons that we have strived to construct a major

portion of our modem using digital technology. In the POC model we will use

standard ECL parts to implement a majority of the baseband signal processing

functions. However, we envision either gate array and/or custom VLSI

circuits to be used in the production models, both of which have great

potential for low cost when quantity purchases are made. Even VHSIC

technology, which could be used to implement the K=7 Viterbi decoder, will

drop significantly in quantity prices over the next several years as that

technology matures (see section 2.3.2 for detailed cost estimations).

Finally, the use of digital technology in implementing our modem will

eliminate many adjustments that would have to be performed during the

production and test cycles which are labor intensive and costly.

We are considering the use of SAW technology to implement the IF

filter, the preamble correlator, and a delay line. Because SAW devices are

fabricated from a mask (in much the same way as digital devices), the

filters, correlators, and delay lines built using SAW technology are very

repeatable from device to device. That is, the characteristics, of a filter

for example, remain very consistent between various runs of the device. In

addition to repeatability, once the mask for a SAW device has been designed,

42
the fabrication process is very automated (non labor intensive) which leads

to low cost per unit if the NREis spread over a large quantity of units.

Monolithic microwave integrated circuits (MMIC)is a young technology

that is maturing quickly. Currently, companies such as Pacific Monolithics

are offering circuits such as a downconvertor on a chip that has an RF input

range of 3 to 6 GHz and an IF output in the range of 50 to 2000 MHz. Each

chip (part# - PM-CO0601-A)contains numerous components, such as RF and IF

amplifiers, a local oscillator, an LO buffer amplifier, and a

double-balanced mixer. This specific device is used as an example because we

are considering it's use in the POCmodel and because it represents what

type of circuits are available now in quantities for a cost a low as $20 per

unit. Other functions are also available, including A_C amplifiers, limiting

amplifiers, phase shifters, phase modulators, etc., all of which operate in

the GHz regions. Since such powerful devices are currently available, it is

not difficult to predict further integration levels, thus enabling even more

complex MMICsto be fabricated. Weanticipate that by the 1990's, the entire

front-end IF chain of our modemwill consist of one MMIC chip and one SAW

filter on the corner of a PCboard.

43
2.3.2 An Estimate of Recurring Costs

The recurring cost estimate is based on the conceptual design, built in

quantity, in a manufacturing environment. No nonrecurring engineering costs

are included.

Table 2.3.2 shows three costs: first the design using present discrete

components, second the design using gate arrays presently available, and

third the design using 1990's technologies.

Cost data was gathered from vendor quotes, current program costs with

similar complexity designs, and Harris's VHSIC operations. Gate array

performance was established using current issues of VLSI magazine (esp.

December, 1985), and gate array development ongoing at Harris.

Table 2.3.2

Estimationoftherecurringcostofthe TDMA Demodinthe1990's:

GATE ARRAY

FUNCTION PRESENT $ PRESENT

Chassis 1 $ 600 Chassis

Input RF 1 Card $ 2,000 1 Card

Bit Sync 1 Card $ 2,500

Phase 1 Card $ 2,000

Detector

Decoder 1 Card,

7 VHSIC IC's

$30,000

$37,100

1 Saw,

1 VLSI(ECL, ASIC)

1 VLSI (ECL, ASlC)

1 Card, 7 VHSIC IC's

$ 6o0

$ 2,000

$ 5oo

$ 25o

_30,000

$33,350

1990'S

1 Card $ 300

1 MMIC,

2Saw

1 Saw,

1 VHSIC

Part of

Above

1 VHSIC

$750

$65O

_400

$2,100

44
2.3.3 Reliability

The reliability of our modem will be insured by several factors. The

first factor to be considered is the parts that make up the whole, i.e., the

components. To ensure component reliability, our preference for parts

selection will be for those parts that have a proven reliable performance

history, or for those parts similar to parts with a proven reliable history.

In addition our preference will be toward those components that are multiple

sourced. Finally, we will choose components that are capable of satisfactory

performance over time and temperature, and are not stressed by the

application, either thermally, electrically, or otherwise.

The second factor to be considered from a reliability standpoint is at

the chassis level. First, the reliability of the overall box will be insured

by a design that does not allow circuit damage due to improper control

settings. Secondly, a thermal cutoff capability will be designed into the

chassis. Finally, forced air circulation will be used to keep components

well away from degrading or damaging temperature conditions.

2.3.4 Maintainability

The maintainability of our modem will be insured through thoughtful

system level design considerations. Features that have already been

"flagged" as important design considerations for the easy maintenance of our

modem are items such as; status indicators, internal fault indicators, and

easy access test points. In addition, thoughtful chassis layout in

conjunction with connectorized cards will allow easy access to both cards

and modules. Finally, chassis inputs and outputs will be designed for easy

chassis interchange.

45
2.4 Overview of Special Test Equipment

The special test equipment that will be required for testing our modem

is of the type that can be designed and fabricated "in-house". Figure 2.4-1

illustrates the system level concept of a test bed. The test bed consists of

three modulators, a signal-to-noise ratio combiner, and a demodulator. The

three modulators may be configured as co-channel or adjacent channel

modulators which in either case share a common design. They may be operated

in a CW or burst mode, with a fixed burst rate and a variable burst length.

Each modulator will have internal data generators, and the ability to

operate with external clock, data, and uplink burst enable signals.

Modulator

Modulator

Modulator

,J

S + N Combiner

v I

Demodulator

Figure 2.4-1 System Level Block Diagram

Figure 2.4-2 shows a block diagram of the signal to noise combiner. The

signal-to-noise ratio combiner features; an internal noise source, variable

signal attenuators, signal and noise combiner, burst rate and frame clocks.

46
From

MOD

From

MOD

From

MOD

Variable

Attenuator

Variable

Attenuator

Variable

Attenuator

Noise

Source

r[

Combiner

Reference

Generator

To

Demod

To

MODS

FIGURE 2.4-2 Signal to Noise Combiner Block Diagram

3. T_Q]NOIJ3G_ ASS_S_MEb_ AND DF.SI(_ IMPACT

In this section of the task one report we will discuss the impact of

technology on the design of our modem.

3.1 Current Versus Future Technology

Virtually all of the circuitry required to implement our modem is

available now, except for the high rate K=7 Viterbi decoder. The question

is, what form, or what type of technology will be utilized in the

47
construction of these circuits? For example, we propose using an analog VCO

to switch frequencies with no abrupt change in phase at the symbol

boundaries. However, in the future it will be possible (and advantageous as

discussed later in this report) to perform the frequency modulation using a

direct digital synthesis technique (i.e., NCO). In addition, baseband

processing circuits that are now accomplished with SSI and/or MSI ECL

devices may, in the future, be implemented in either VHSIC(.5u CMOS),

VLSI(ECL gate arrays), or digital GaAs circuits with a high degree of

integration at the chip level, enabling many functions to be performed by

one device. The improvements that are realized by the future technology may

be in performance (as in the case of the NCO implementation of the VCO), in

reliability (as in the case of the SSI to VLSI transition), and/or in cost.

To summarize the key technologies used in the modem and their current or

future implementation strategies, respectively, see Table 3. I.

Table 3.1 Current Versus Future Implementation of Key Technology Items

TECHNOLOGY ITEM

Frequency Modulator

Frequency Detector

IF Filter

Baseband Processing

Viterbl Decoder

CURRENT IMPLEMENTATION

Analog VCO

Bulk Analog

SAW

SSI & MSI ECL

Low Rate - SSI/MSI

FUTURE IMPLEMENTATION

Digital NCO

MMIC/SAW

SAW

VHSIC, VLSI

High Rate - VHSIC

48
3.2 Hardware Techniques which Represent an Advancement in the

State-of-the-Art in Modulation Technology

There are various hardware techniques incorporated into our modem which

represent an advancement of the state-of-the-art in modem technology, some

of which are listed in the proprietary adendum. Others include a high speed

Op Amp, high speed A/D converter, high speed D/A converter, IF input filter,

and 1/2 Nyquist lowpass filter. The Op Amp represents advanced technology in

that a true differential amplifier is required that has a very large

bandwidth and a very short settling time. The state-of-the-art in wideband

Op Amps is defined by an amplifier with a -3 dB bandwidth of DC to 200 MHz,

a settling time (to .02%) of roughly i0 nsec., and a slew rate of

7000V/usec. The A/D and D/A convertors represent the state of the art in

conversion technology, again because of the high speed and large bandwidth

requirements of our system. The present state-of-the-art in A/D conversion

is a i00 Msample 6-bit A/D. The present state-of-the-art in D/A conversion

is a I00 MHz 8-bit D/A. The IF filter represents an advance in technology in

that conflicting specifications, such as very steep skirt selectivity

coupled with almost absolute linear phase, must be met in one filter. The

1/2 Nyquist baseband filter advances modulation technology in that it

reduces the sidelobe levels of the non-filtered CPFSK spectrum at the output

of the qWT. For a more thorough description of hardware techniques that

represent an advancement of modulation technology, the reader is referred to

the Harris proprietary adendum.

49
3.3 The Impact of Technology on System Performance

There are a few technology areas that impact the performance of our

modem. That is, as the technology progresses, we will be able to take

advantage of the new technology, not only to decrease the cost of our modem,

but to increase (slightly) it's performance relative to the current (POC)

implementation. Listed in the following paragraph are the technologies that

may affect system performance. Included in this discussion is the specific

a[ea of performance affected as well as the contributor.

The linearity of the frequency detector will impact the BER versus

Eb/No performance of our modem. Our goal for the frequency linearity is 1

percent. As technology progresses, linearities of less than 1% may easily be

realizable. The VCO linearity may also affect the BER performance of our

mr_dem. However, as technology allows an NCO to be implemented at the

frequencies of interest, linearity will be of no concern in that an NCO is

inherently linear. The VCO output power variation with frequency may impact

BER performance. Our goal is to keep the power variation to within .25 dB,

but again, an NCO would alleviate this problem. The ability to correlate

with the preamble and quickly jam the symbol timing along with the RF phase

will impact acquisition. As the ultimate speed of digital technology

increases, the criticality of this timing issue is diminished. The large

number of interconnections required in the baseband processing section with

the use of SSI and MSI technology may impact reliability. However, as the

implementation transitions from SSI/MSI to VHSIC and VLSI, the number of

interconnections between parts as well as the total parts count will

decrease, which will increase the reliability of the modem.

50
3.4 Advantages and Disadvantages of Implementation Technologies

In this section the advantages as well as the disadvantages of the

previously mentioned technology is outlined. These technology items are; the

frequency measurement circuit, the VCO, the NCO,and the baseband signal

processing functions.

The advantage of using a frequency measuring circuit in the

implementation of the demodulator is that it reduces the overall hardware

design complexity of the demodulator. Thus, by reducing circuit complexity,

a cost savings is realized both in the design effort (POC) and in future

production runs (EDMs and beyond). The only disadvantage to the frequency

measuring approach is the possible degradation (slight) in BER performance

due to nonlinearities. Although, there are methods in which to linearize a

frequency measuring device, of which we are currently pursuing to ameliorate

the linearity problem.

The advantage of using a VCO as the continuous phase frequency

modulator is that a VCO is presently available has suitable dynamic

characteristics. The disadvantage of the VCOtechnology is the nonlinearity

of voltage to frequency conversion (goal is < 1%nonlinearity) and the long

term frequency drift of the V_O. An NCO,as previously touted, is inherently

linear and it's frequency stability is as good as it's reference. However,

an NCOis not currently available with an output center frequency capability

of 3.373 GHz, and probably will not be available for some2 to 5 years.

llence, the only disadvantage of the NCOtechnology is the availability of

that technology.

The baseband signal processing functions are implemented using digital

technology and therefore realize all the advantages that are inherent to

threshold logic. These advantages include; stability over time and

5]
temperature, a high degree of integration at the chip level, immunity to

small cross-talk and noise signals, and finally, digital circuits lend

themselves to all kinds of automated processes which reduce production,

test, and maintenance costs. The only disadvantage of using digital circuits

to implement the baseband processing functions of our demodulator are the

high processing speeds at which we must operate (the sample rate = symbol

rate = 67 MHz). This leads to technology such as ECL or GaAs to accf_,plish

the required processing under worst case conditions with margin.

52
TECHNICAL REFERENCES

I , J. D. Oetting, "A Comparison of Modulation Techniques for Digital Radio",

IEEE Transactions on Communications, Vol. COM-27, No. 12, Dec. 1979,

pp. 1752-1762.

, C. R. Ryan, A. R. Hambley, and D. E. Vogt, "760 Mbps Serial MSK Microwave

Modem", IEEE Transactions on Communications, Vol. COM-28, May 1980,

pp. 771-777.

. • Robert C. Davis, "An Experimental 4-ary CPFSK Modem for Line-of-Sight

Microwave Digital Data Transmission," EASCON 1978, pp. 674-682.

. P. R. Hartman, "Digital Radio Technology: Present and Future", IEEE

Communications Magazine, Vol. 19, No. 4, July 1981, pp. 10-14.

, Final Technical Report, RADC-TR-79-56, ',Linear Modulation Techniques for

Digital Microwave," Robert C. Davis, Harris Corporation, Study for Rome

Air Development Center, August 1979.

. S. G. Wilson, H. A. Sleeper, II, P. J. Schottler, M. T. Lyons, "Rate 3/4

Convolutional Coding of 16-PSK: Code Design and Performance Study", IEEE

Tran. of Comm., Vol. COM-32, pp. 1308-1314, Dec. 1984.

, Stephen G. Wilson, Paul J. Schottler, and Harry A. Sleeper, "Rate 3/4 IO-PSK

Phase Codes," ICC 1982, pp. 6 F.1.1-6F.1.5.

. T. A. Schonhoff, "Symbol Error Probabilities for M-ary CPFSK: Coherent

and Non Coherent Detection", IEEE Transactions of Communications, Vol. COM-24,

No. 6, June 1976, pp. 644-652.

, G. David Forney, Jr., "The Viterbi Algorithm" Proceedings of the IEEE,

Vol. 61, No. 3, March 1973, pp. 268-277.

10.

11.

M. G. Palchat, R. C. Davis, and M. B. Luntz, Harris Corporation, "Coherent

Demodulation of Continuous Phase Binary FSK Signals," in Proc. Int. Telemetry

Conf. (Washington, D.C., 1971).

Joe Grabowski and Robert C. Davis, "An Experimental M-QAM Modem Amplifier

Linearization and Baseband Equalization Techniques," National Telesystems

Conference Record, November 1982, Galveston, TX., pp. E3.2.1 - E3.2.6.

53
NAS3-24681

ADVANCED MODULATION TECHNOLOGY DEVELOPMENT

HIGH SPEED A/D CONVERTER

BREADBOARD EVALUATION REPORT

SUBMITTED BY:

JAMES F. ROESCH, JR.

HARRIS GCSD

PREPARED FOR:

NASA LeRC

54
2.3.1 Breadboard Development Definition

2.3 .l(a)

2.3.1(b)

The high speed quantlzer (A/D) was a recommended breadboard item as

presented at NASA LeRC during the Task II review.

Ratlonale supportlng the need for breadboardlng.

J

The high speed 8-blt flash A/D technology is very young. Only three

8-bit, I00 MHz converters are known to exist, with one of the three

not yet a reality. Utilizing such new technology in such a critical

function in our system, it was deemed necessary to evaluate and verify

the performance of the technology relative to vendor specifications.

In so doing, valuable information as to the proper utilization of the

technology could be inferred for use in the detail design phase of the

POC model.

2.3.1(c) A description of the objectives and approaches for breadboardlng.

The objectives of the A/D breadboard phase are quite straightforward.

They are:

(1) To verify accurate 8-blt resolution (1/2 LSB llnearlty)

digitization of frequencies between DC to 50 MHz, at a sampling

rate of 72.73 MHz.

(2) To verify the input bandwidth of the device.

(3) To experiment with the clocking scheme of the Siemens SDA-8010 A/D

and verify accurate sampling with STRI = CLK and STR2 = CLK.

The approach taken to verify the above objectives is also quite

straightforward. All necessary hardware will be built and tests

conducted, as given in Section 2.3.2, to verify the major objectives

outlined above.

Tests will also be performed as necessary to verify minor objectives

pursuant to the major objectives.

A block diagram of the test bed including the SDA-8010 A/D breadboard

is given in Figure 2.3.1.

2665V/A/D Converter 55
! GOULD BIOMATION

HIGH SPEED

K105-D LOGIC ANALYZER

OSCILLOSCOPE

SYNTHESIZED SIGNAL

GENERATOR .1 - 100 MHz

SYNTHESIZED SIGNAL

GENERATOR 72.73 MHz

i SOA-8O,O_oBREADBOARD

] SDA-80,0i ' !

i___L_t ......

' f

I

SlNEWAVE TO Q

ECL CLOCK CONVERTER _"

LATCH _ AD-9700

O O __ 8-BIT

1,1"r o,_

'1

I

I

I

J

Figure 2.3.1. SDA-8010 A/D Test Bed

A/O,OIOTX

56
2.3.1(d) Functlonal Requirements of the SDA-8010 A/D Breadboard.

The functional requirements of the SDA-8010 A/D breadboard as

pertalnlng to the performance of the A/D itself may be found in Sect/on

2.3.1(c). Other, more general functional requirements, pertain to

interface and testability requirements. These requirements include

separate inputs for the analog voltage input, the two clock inputs of

the A/D (Strobe i and Strobe 2), and the system clock input that clocks

the data latch and the D/A converter. Each of these inputs are

connected via SMA connectors, and have the appropriate device pins

terminated in the characteristic impedance of the stripline (50 ohms).

A 50 ohm terminated analog output voltage is supplied via an SMA

connector, while a digital representation of the input waveform is

available dlrectly at the output pins (Q or Q) of the data latch.

2.3.1(e) Material Requirements.

SDA-8010 A/D Breadboard Parts List

Part Number

SDA-8010

AD9700BD

FI00151

0P07A

LM313

VK-200

M39018/01-0653M

CDR04BXI04AKSM

CDR04BXB92AKSM

CMR03CI00DOCM

IN4149

RNC55H2400FM

RNC55HI002FM

Qty Description

I B-Bit i00 MHz A/D

i 8-Bit 125 M/_z D/A

2 Hex D Flip Flop

5 SMA Connector

2 0p Amp

2 Bandgap Voltage Ref.

ii Low Freq. RF Choke

8 4.7 F Elec. Cap

25 0.1 F Chip Cap

10 3900 pF Chip Cap

2 10 pF Capacitor

3 Diode

3 240 Ohm Res.

2 10K Ohm Res.

Vendor

Siemens

Analog Devices

Fairchild

PMI

National Semi

2665V/A/D Converter 57
SDA-8010A/D Breadboard Parts List (Continued)

Part Number Qty

RNC55H4020FM 1

RNC55HI000FM 8

RNC55H49R9FM 13

M39015/I-004WM 2

M39015/1-003WM 2

RNC55HI800FM 2

Description

402 Ohm Res.

100 Ohm Res.

49.9 Ohm Res.

IK Ohm Pot.

500 Ohm Pot.

180 Ohm Res.

Vendor

2.3.2 Breadboard Test Plan and Test Procedures

2.3.2.1(a) Test Type.

Clock timing adjustment.

2.3.2.1(b) Objective of the-Test.

The objective of the clock timing adjustment test is to find which

pulse timing relationship for Strobe 1 and Strobe 2, hereafter referred

to as STRI and STR2, yields the best dynamic performance of the A/D.

The goal will be to establish a simple relationship between STRI and

STR2 of CLK and CLK. To provide a background on the strobe timing

relationships of the Siemens SDA-8010 A/D, an excerpt from the SDA-8010

Technical Description will be given below.

2.3.2.1(c) Range of Test Parameters.

The range of test parameters associated with the clock timing

adjustment are units of time measured in nanoseconds. There is

probably an infinite number of ways that the clock signals STRI, STR2,

and CLKL could be adjusted both in duty cycle and in relative delay

between rising edges; however, only a few should be and will be

considered. These are the pulse diagram of Figure 9, and that of

setting STRI = CLK and STR2 = CLKL = CLK.

2665V/A/D Converter 58
2.3 Clock circuitry

SDA 8010 is driven by two ECL clock signals Str 1

and Str 2 (figure 9). The internal CLK1 and _-LK 1

signals driving the first comparator stage are

derived from Str 1. The pulse width of Sir 1 affec;ts

the conversion characteristics. A duty cycle of 1:1

is recommended under normal 100-MHz operating

conditions; for particulars refer to chapter 4.

The second signal Str 2 delivering CLK2 and

is responsible for regeneration of the digital signals

in the second comparator latches and influences

the pulse shape of the output signals. The internal

signals are latched during hold time tH _ and tH 2

respectively. Thus the positive transition of Str 1

causes sampling of the analog signal after an

aperture delay of approx. 3 ns. The output-signal

transitions are determined by the rising edge of Sir

2+The signal transition time to. o marks the time

interval between the positive transition of Str 2 and

the beginning of the data valid range tv. Q of the

output signal. The data valid range in turn is

related to the pulse width tH2"

The duty cycle of Str 1 is limited by two effects If

the strobe time ts, 1 (see figure 9) is too small, the

fir.,t comparator stage cannot settle to the new

analog voltage in time and conversion errors

increase. The upper limit of ts, _ is dictated by the

smallest hold time required to pass information to

the second comparator latch. The setting of ts, _ is

not particularly critical, the limits being shown in

table 1.

Table 1 Range of clock settings for operation over

the whole temperature range. Characterization

measurements were performed with typical

settings.

I min type) ! max

ts, 1 3.5 5 6.5 ns

tst, _ i 4.02) 3.5 4.5 ns

tsetu_,st, 2 0 -1.5 -2.5 ns

tHo,d.Sir 2 l 1 3 ns

,) Recommended for normal operation at room temperature

2)At room temperature the minimum strobe width is 3 ns

Fig. 9: Pulse diagram

S(onn+n_ poinl

i+

In the digital section, accurate clock timing

er,sures easy handling of the 100-MHz output data

st-earn. Figure 13 gives recommended settings of

the converter cloc ks together with the resulting

output signals at jJnction temperatures of 30, 90

arid 125°C. Additi()nally the latch clock CLK L for

tte external output register is shown. Valid data

a:e assumed if the conversion of a 30-MHz/2-Vpp

signal yields an SNR of greater than 40 dB at a

C )nversion rate of 100 MHz. To achieve proper

¢ peration over the whole temperature range,

latching of data into the output register must

occur between 10.5 ns and 13 ns after the rising

edge of Str 2. This can be achieved using

ECL 100 K latches (e.g. 100150). If a larger range of

valid data is required, temperature dependence

has to be given to the latch clock CLKL

corresponding to the temperature dependence of

the signal transition time t_.o shown in figure 10.

ORi_i._AL PAGE _5

OF POOR QUALITY

2665V/A/D Converter 59
®

+V

V

Figure 2.3.2.1. Clock Generator Block Diagram

2.3.2.1(d) Test Procedure

STR 1

STR 1 ,,,._

STR 2

STR 2

CLK L

re,=

CLK L

To find the optimum clocking scheme for the SDA-8010, a flexible clock

generator circuit must be provided. A detailed block diagram of the

circuit used to generate and adjust the clocks is given in Figure

2.3.2.1.

As given by Figure 2.3.2.1, the 100K ECL clock signals are derived from

a single slnewave source by three separate comparator circuits. Each

comparator has its own threshold reference so that the duty cycle of

each clock may be independently adjusted. Also, a delay (trombone)

llne is added in the signal path leading to the CLKL comparator so that

its rising edge may be adjusted relative to STRI and STR2. Delays 2

2665V/A/D Converter 60
and 3 depicted in Figure 2.3.2.1 are implemented by adjusting the

length of coaxial cables, and function to adjust the rising edge of

STR2 relative to Strobe I.

The testing procedure will be to adjust the clocking signals STRI, STR2

and CLKL for various timing relationships, and simply observe the

dynamic behavior of the A/D via a high speed logic analyzer. Timing

relationships will be searched until good dynamic A/D outputs result

such as; no missing or erroneous codes, and low waveform distortion

(relates to good dynamic linearity).

2.3.2.2(a) Test Type.

Static Nonlinearity

2.3.2.2(b) Objectives of the Test.

The objective of the static nonlinearity test Is to verify the vendor

specification of +I/2 LSB linearlty error.

2.3.2.2(c) Range of Test Parameters.

Wlth the positive and negative voltage references set at a magnitude of

0.75 VDC, the LSB weighting of,

+Vref + l-Vrefl = 5.86 mV/LSB

256

results.

Thus, the expected range of data points (in volts) between bit

transitions is;

LSB welghtlng + 1/2 LSB

= 5.86 mV +2.93 mV or

2.93 mV < expected data _ 8.79 mV

2665V/A/D Converter 61
2.3.2.2(d) Test Procedure.

The static linearlty of the SDA-8010 will be measured by first

accurately setting the positive and negative voltage references of the

A/D to +0.75 and -0.75 DC respectively, to establish an LSB weighting

In mV/LSB. Then a DC voltage will be applied to the analog voltage

input of the A/D, taking note of the voltage value for which a stable

numerical output results. Thls process will be laboriously repeated

for the numerical outputs of zero to 255. The data taken can then be

analyzed to verify the 1/2 LSB nonlinearity (or llnearity error)

specification given by the vendor.

2.3.2.3(a) Test Type.

Amplitude response of SDA-8010.

2.3.2.3(b) Objectives of the Test.

The objective of the amplitude response test of the SDA-8010 is verify

the input bandwidth of the device.

2.3.2.3(c) Range of Test Parameters.

The output (numbers) of the A/D should fall off no more than

approximately 0.2 dB over the input frequency range of DC to 45 MHz,

for proper operation In our system. The baseband square root of

Nyquist filter is down roughly 6 dB at 36.4 MHz, and falls off very

rapidly beyond that frequency. The A/D frequency response remaining

flat to 45 MHz ensures that the cascaded response of the baseband

filter with the A/D (filter) Is essentially that of the baseband filter.

2.3.2.3(d) Test Procedure.

The amplitude response of the SDA-8010 will be measured by three

separate techniques.

2665V/A/D Converter 52
2.3.2.3.1 The first technique will be that of keeping the voltage constant at the

input to the device over the measured range In frequency. The response

will be measured by measuring the numerical positive and negative peaks

with a logic analyzer. These peaks will be recorded for several

frequencies so that the frequency response of the SDA-8010 can be

determined. A block diagram of the test setup is given below.

50

50Q COAX

___._Vo VARIES >

?

SDA-8010

1'

D OUT

TO LOGIq

ANALYZE

CLOCK = 72.73 MHz

Figure 2.3.2.3.1. Amplitude Response (50 ohm System)

Test Setup Block Diagram

In this first test, VAI N is held constant, and therefore any

filtering act/on at the input to the A/D is not accounted for in the

digital measurements.

2.3.2.3.2 The second technique, will be that of holding the source power constant

over the.entire frequency spectrum of interest. In this test VAI N

will vary somewhat due to filtering at the Input of the A/D. This

filtering action is mainly due to an internal capacitance and an

external resistance setting up an RC time constant. Therefore, a

minimum loss network will be added at the input of the A/D so that the

2665V/A/D Converter 63
A/D "sees" a lower source impedance of 25 ohms while the signal source

"sees" a characteristic im)edance of 50 ohms. A block diagram of the

test setup is given by Fig_Jre 2.3.2.3.2.

 )Vo

5O

I

50 _) 30AX 10

CONST

300

VAIN

50

---I

I

._L__

"--T"--"

I

I

SDA-8010

T

CLOCK = 72.73 MHz

>

D OUT

TO LOGIC

ANALYZE

Figure 2.3.2.3.2. Amplitude Response Test Setup Block Diagram

The frequency response will be measured at the A/D output by measuring

the numerical positive and negative peaks (of the sinewave) with a

logic analyzer. These peak values will be recorded for several

different input frequencies so that the amplitude response at the

output can be determined.

2.3.2.3.3 The third amplitude response measurement technique involves the use of

a low output impedance amplifier at the input of the A/D. A block

diagram of the test setup is given by Figure 2.3.2.3.3.

2665V/A/D Converter 64
5O

Vo = CONST

50 Q COAX

5O

5O

1500

25

5O

COMLINEAR

CLC220

VAIN

CLOCK = 72.73 MHz

D OUT

TO LOG

ANALYZ

Figure 2.3.2.3.3. Amplitude Response Test Setup Using a Buffer Amplifier

The measurement of amplitude response will be measured directly at the

A/D output as previously detailed in Sections 2.3.2.3.1 and 2.3.2.3.2.

2.3.3 Breadboard Design

See Schematic Diagram of the SDA-8010 Breadboard.

2.3.4 Breadboard FabrLcatlon

See color photographs of the SDA-8010 Breadboard

2665V/A/D Converter 65
2.3.5 Breadboard Testing

2.3.5.1 Clock Timing Adjustment

Dynamic Response of the A/D was insensitive to the duty cycle of STRI.

Very good dynamic behavior resulted when the simple CLK, CLK scheme was

applied to the A/D, and therefore no further testing was performed in

thl8 area. Remember, the goal was to achieve good dynamic behavior

using STRI = CLK, STR2 = _, as stated in Section 2.3.2.1(b).

A pulse diagram of the clocking scheme used to clock the SDA-8010 and

the 100151 fllp-flops following the AID is given in Figure 2.3.5.1.

The output of the SDA-8010 A/D for 1.4 volt peak-peak sinewave inputs

of 1 MHz, 36 MHz, and 70 MHz were recorded by photographing the KI05

logic analyzer display. The clocking scheme used to produce all

photographs was that given by Figure 2.3.5.1, with a clock frequency of

72.73 MHz.

2665V/A/D Converter 66
SCANNING

6.87 nSEC

STR 1

sTR 2

/

/

r

\

X

'I I

I

I

I

I

I

I I

I I

I I

I 1

7'

I

I I

13.75 nSEC

/

13.25 SEC _

.5 nSEC

\

/

I

I

I

I

Ik_l

iv!

!

!

I

=CLK

=CLK

/

= CLK

(DELAYED)

DO-7

/

DATA VALID /.'

/'- ,,

F_gure 2.3.5. l(a). Timing of Clocking Scheme Used With SDA-8OIO A/D.

Clock Frequency is 72.73 MHz

A.,DI0107X

67
Figure 2.3.5.1(b). SDA-8010 Output for an Almost Full Scale 1 MHz

Slnewave Input; STR1 = CL---K,STR2 = CLK, Clock Freq. = 72.73 MHz

ORIGINAL PAGE IS

OF POOR QUALITY

Figure 2.3.5.1(c). Horizontal Expansion of Figure 2.3.5.1(b)

to Show More Detail

2665V/A/D Converter 68
ORIGINAL PAGE IS

OF POOR QUALITY

Figure 2.3.5.1(d). SDA-8010 Output for an Almost Full Scale 36 MHz

Slnewave Input. STRI = CLK, STRI - CL----K,Clock Frequency = 72.73 MHz

Note the 365 kHz beatnote frequency produced by sampling a 36 MHz

slnewave wlth a 72.73 HHz clock. Sampling a 36 MHz tone wlth a 72.73

HHz clock, maximally stresses the A/D because each adjacent sample has

opposite polarity, and therefore each successive sample has an HSB

transition. Note that there are no missing codes and the dynamic

llnearlty seems to be "good."

2665VIAID Converter 69
Figure 2.3.5.1(e). SDA-8010 Output for an Almost Full Scale 70 MHz

Sinewave Input. STRI = CLK, STR2 = CLK, Clock Frequency = 72.73 MHz

The slnewave of Figure 2.3.5.1(e) is slightly distorted. The

distortion, however, is a result of the source, not the conversion

process. The frequency of the displayed sinewave is the difference

between the sample frequency (72.73 MHz) and the input frequency 70

MHz) which is 2.73 MHz.

2.3.5.2 Static Nonlinearity

The static llnearity error was measured as described by Section

2.3.2.2(d). The measured data is given on the following pages.

ORIG|_._L F/J.GE _3

OF POOR QUALITY

2665V/A/D Converter 70
Static Llnearlty (+Vref = .750V, -Vref = -.750V)

Code

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

0OOO1O0O

00001001

00001010

00001011

00001100

00001101

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

00010110

00010111

00011000

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

00100001

Code Voltage Voltage

-.750 00100010 -.548

-.744 00100011 -.542

-.737 00100100 -.537

-.731 00100101 -.532

-.725 00100110 -.525

-.720 00100111 -.520

-.713 00101000 -.513

-.708 00101001 -.507

-.702 00101010 -.501

-.696 00101011 -.495

-.690 00101100 -.489

-.685 00101101 -.483

-.679 00101110 -.478

-.673 00101111 -.472

-.667 00110000 -.467

-.661 00110001 -.460

-.655 00110010 -.455

-.650 00110011 -.449

-.645 00110100 -.443

-.638 00110101 -.436

-.631 00110110 -.430

-.625 00110111 -.425

-.619 00111000 -.419

-.614 00111001 -.413

-.608 00111010 -.407

-.603 00111011 -.401

-.596 00111100 -.395

-.591 00111101 -.389

-.584 00111110 -.383

-.579 00111111 -.377

-.572 01000000 -.370

-.567 01000001 -.365

-.560 01000010 -.360

-.554 01000011 -.355

2665V/A/D Converter 7]
Static Llnearlty (+Vref = .750V, -Vref = -.750V) (Continued)

Code Voltage Code

01000100 -.350 01100110

01000101 -.344 01100111

01000110 -.338 01101000

01000111 -.333 01101001

01001000 -.326 01101010

01001001 -.321 01101011

01001010 -.314 01101100

01001011 -.309 01101101

01001100 -.302 01101110

01001101 -.297 01101111

01001110 -.292 01110000

01001111 -.285 01110001

01010000 -.279 01110010

01010001 -.274 01110011

01010010 -.268 01110100

01010011 -.263 01110101

01010100 -.256 01110110

01010101 -.251 01110111

01010110 -.245 01111000

01010111 -.239 01111001

01011000 -.234 01111010

01011001 -.228 01111011

01011010 -.222 01111100

01011011 -.217 01111101

01011100 -.209 01111110

01011101 -.204 01111111

01011110 -.198 10000000

01011111 -.192 10000001

01100000 -.187 10000010

01100001 -.182 10000011

01100010 -.175 10000100

01100011 -.169 10000101

01100100 -.164 10000110

01100101 -.158 10000111

Voltage

-.152

-.145

-.139

-.134

-.129

-.124

-.117

-.112

-.107

-.101

-.095

-.088

-.083

-.077

-.072

-.065

-.060

-.054

-.048

-.043

-.037

-.030

-.025

-.020

-.014

-.007

-.001

+.005

+.009

+.015

+.021

+.027

+.033

+.039

2665V/A/D Converter 72
Static L1nearity (+Vref = .750V, -Vref = -.750V) (Continued)

Code Voltage Code

i0001000 +.044 I0101011

I0001001 +.050 I0101100

i0001010 +.056 iOlOllOl

i0001011 +.063 lOlOlllO

i0001100 +.068 i0101111

10001101 +.075 10110000

10001110 +.080 10110001

10001111 +.085 10110010

10010000 +.091 10110011

10010001 +.097 10110100

10010010 +.103 10110101

10010100 +.114 10110110

10010101 +.120 10110111

10010110 +.126 10111000

10010111 +.131 10111001

10011000 +.136 10111010

10011001 +.143 10111011

10011010 +.150 10111100

10011011 +.155 10111101

10011100 +.161 101111_0

10011101 +.166 10111111

10011110 +.172 11000000

i0011111 +.179 1100000%

10100000 +.184 11000010

10100001 +.190 11000011

10100010 +.196 11000100

10100011 +.201 11000101

i0100100 +.207 ii000110

I0100101 +.213 ii000111

i0100110 +.219 11001000

i0100111 +.225 ii001001

10101000 +.231 11001010

10101001 +.237 11001011

10101010 +.243 11001100

Voltage

+.249

+.255

+.261

+.267

+.273

+.279

+.285

+.291

+.295

+.302

+.308

+.314

+.321

+.327

+.332

+.337

+.343

+.350

+.355

+.361

+.367

+.374

+.382

+.390

+.394

+.399

+.405

+.412

+.4i7

+.424

+.429

+.434

+.441

+.448

2665V/A/D Converter 73
Static Llnearlty (+Vref = .750V, -Vref = -.750V) (Continued)

Code Voltage

ii001101 +.453

11001110 +.459

UO01111 +.464

Ii010000 +.470

ii010001 +.477

ii010010 +.483

ii010011 +.488

Ii010100 +.493

II010101 +.500

llOlOllO +.505

ii010111 +.512

Ii011000 +.519

II011001 +.524

11011010 +.530

llOllOll +.535

ii011100 +.542

ii011101 +.547

11011110 +.554

11011111 +.559

11100000 +.565

11100001 +.570

11100010 +.576

11100011 +.583

11100100 +.588

11100101 +.594

11100110 +.601

11100111 +.607

11101000 +.612

11101001 +.619

11101010 +.625

11101011 +.632

11101100 +.637

11101101 +.642

11101110 +.647

Code

Ii01111

11110000

iiii0001

11110010

iiii0011

11110100

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

iiiiiiii

Voltage

+.653

+.659

+.666

+.672

+.677

+.683

+.690

+.696

+.701

+.708

+.713

+.720

+.725

+.731

+.737

+.742

+.750

2665V/A/D Converter 74
A graph of the measured data is given In Figure 2.3.5.2(a).

CODE

Figure 2.3.5.2(a). Voltage to Code Transfer Function of the SDA-8010

A graph of the differential llnearlty error is given in Figure

2.3.5.2(b). Differential llnearlty error of less than +_1/2 LSB,

ensures no missing codes.

: ! J : ":i

. / o &..

. r.... t

._J

3-, -" C. .., _,--_._'_*:-_'_i,'" ,--J_ _ u _.,._.-:ir'_ I_[tllr, ' : i_r-_fl;_-,L, ' '" i'-'-_; _ _Ii"' tl_'_:fl.l" ' '' "_" _i_I,. '_'_ f!l}_*,.,_ .....

_'t Il' I I r " I ! ! _ "" +' .., "_..... _, _ '.Jfti'_Ii,,i!'/i "L_,!i,", ` il_!':!:_i i: '_;}.":_,i'il(.:i i!J_!'

fl: - _ _..

'_ ._.

-,-_

': _ _,:: K

_j

..,

i : ; i II

10_. 15_.

"l

::1

:::

-.¢

, i , I

2",". 25;_.

Figure 2.3.5.2(b). Differential Linearlty Error Plot for the SDA-8010

2,)65V/A/D Converter 75 O_'_i_i_6.!_,.. _._1i x

OF POOR QUALITY
In addition to the static llnearlty error tests performedj a crude

dynamic llnearlty test was also performed. A (72.73 MHz) -I x 256

second long ramp was applied to the analog input of the SDA-8010. This

ramp was not exactly linear and is shown in the photograph of Figure

2.3.5.2(c). The output response of the SDA-8010 to the ramp was then

converted back to an analog voltage (Figure 2.3.5.2(d)). The output of

the D/A was then subtracted from the input of the SDA-8010 to yield the

photograph of Figure 2.3.5.2(e). The photograph of Figure 2.3.5.2(e)

shows a straight llne w_ich indicates good dynamic llnearity.

O_'°'-" -poOR QU glint7

Figure 2.3.5.2(c).

2565V/A/D Converter

Ramp input to the SDA-8010 of Length 3.52 usec

76
OE. POOR QUALITY

Figure 2.3.5.2(d). Ramp Output of the AD9700 D/A Converter

Figure 2.3.5.2(e). Difference Between the Ramp Input to the SDA-8010, and

the Ramp Output of the AD9700 D/A, Which Represents the Cumulative

Linearlty Error of Both Devices

2665V/A/D Converter 77
2.3.5.3 Amplitude Response of the SDA-8010

2.3.5.3.1 The amplitude response of the SDA-8010 was measured as given by the

test procedure in Section 2.3.2.3.1 of this report.

SDA-8010 Amplitude Response, VAI N = Const.

Binary Numbers Out

Input Frequency Positive Peak Negative Peak dB, 1 MHz*

500 kHz iiii0011 00001000 -0.18

1 MHz iiii0101 00000101 0.0

5 MHz Iiii0100 00001000 -0.15

i0 MHz iiii0111 00001001 -0.07

20 MHz iiii0110 00000100 +0.07

30 MHz iiii0110 00000100 +0.07

40 M_z Iiii0111 00000011 +0.14

50 MHz Iiii0110 00000101 +0.04

60 MHz iiii0101 00000110 -0.04

70 MHz iiii0100 00001000 -0.15

* dB, 1 MHz = .20 log/Positive - Negative Peak @ X MHz) _Positive Negative Peak _ i MHz

2.3.5.3.2 The amplitude response of the SDA-8010 was measured as outlined by the

test procedure in Section 2.3.2.3.2.

SDA-8010 Amplitude Response, V° - Const., R s

= 25 ohms

Binary Numbers Out

Input Frequency

I MHz

5 MHz

I0 MHz

20 MHz

30 MHz

40 MHz

45 MHz

50 MNz

60 MHz

70 MHz

* dB, i MHz =

Positive Peak Negative Peak dB, I MHz*

ii010000 00101011 0.0

Ii010001 00101100 0.0

ii010010 00101110 -0.05

ii010001 00101110 -0.ii

ii010000 00101110 -0.16

ii010000 00101110 -0.16

Ii001111 00101111 -0.27

Ii001110 00110000 -0.38

11001010 00110100 -0.83

ii000011 00111011 -1.68

20 log(Posltlve - Negative Peak @ X MHz_

tPositive Negative Peak @ I MHz /

2665V/A/D Converter 78
2.3.5.3.3 The amplitude response of the SDA-8010 was measured as outlined be the

test procedure in Section 2.3.2.3.3.

SDA-8010 Amplltude Response, V = Const.

o

Buffer Amp Used, R s " 25 ohms

Binary Numbers Out

Input Frequency Positive Peak Negative Peak dB, 1 MBz*

500 kHz iii01001 00010111 +0.04

1 MHz iii01000 00010111 0.0

5 MHz iii01001 00011000 0.0

i0 MHz iii01001 00011010 -0.08

20 MHz iii01000 00011011 -0.16

30 MHz iii00111 00011010 -0.16

40 MBz iii01000 00010111 0.0

45 MHz iii01001 00010111 +0.4

50 MHz Iii01010 00010101 +0.16

60 MHz iii01011 00010100 +0.25

70 MHz iii01010 00010110 +0.12

2.3.6 Test Evaluation

2.3.6(a) Results of the Evaluation.

Three test have been performed; the clock timing adjustment test, the

llnearlty test, and the amplitude response test. The evaluation of the

test data for these three tests follows.

The test data given in Section 2.3.5.1 indicates clearly, that a

straightforward CLK, CLK clocking scheme may be used at the 72.73 MHz

clock rate, even though vendor technical information indicates this

clocking scheme Is not optimal. This scheme will simplify the

generation of timing by eliminating the need for voltage references

(with their associated drifts) necessary in the comperator c_rcuitry to

generate other than CLK, CLK 50% duty cycle clocks.

2665V/A/D Converter 79
The test data given in Section 2.3.5.2 indicates that linearity errors

are less than +112 LSB, and therefore, the device may be operated at

the desired clock frequency with no missing codes at the output:

The test data given in Section 2.3.5.3 indicates that the amplitude

response of the SDA-8010 is relatively flat, especially if the voltage

right at the analog input can be held constant. An external source

resistance with an internal (nonlinear) capacitance forms an RC time

constant which will cause rolloff at the analog input. If, however,

the source resistance is minimlzedthe effect of the RC time constant

can be "pushed" out to frequencies beyond the bandwidth of interest.

In other words, the -3 dB bandwidth of the RC filter can be made high

enough in frequency that the amplitude rolloff over the bandwidth of

interest (DC to 45 MHz in our design) is on the order of a few tenths

of a dB.

2.3.6(b) Revisions Necessary or Recommended, from Breadboard Evaluation.

The revisions to the SDA-8010 evaluation breadboard based on test

results are as follows.

Since the CLK, CLK clocking scheme will be used for the STRI, STR2

.

clock signals of the SDA-8010, it is recommended that a dlfferentlal

line receiver be used on the quantizlng card to receive the clock

signal. This provides common mode rejection between cards.

In addition, it is recommended that the circuit given by Figure

2.3.2.3.3 be used to "drive" the SDA-8010, in that it gives the best

amplitude response. A lower gain buffer device designed specifically

for driving Flash A/D converters (the Comllnear CLC231) is under

consideration for replacing the CLC220, so that amplitude peaking (see

Section 2.3.5.3.3) may be reduced to less than tenths of a dB.

2665V/A/D Converter 80
NAS3-24681

ADVANCED MODULATION TECHNOLOGY DEVELOPMENT

TASK V REVIEW

JANUARY 28, 1987

HARRIS CORPORATION, GCSD

P.O. BOX 91000

MELBOURNE, FL. 32902

PRESENTED BY:

RICHARD D. CROWLEY

ROBERT C. DAVIS

JAMES A. GANN

PREPARED FOR:

NASA LEWIS RESEARCH CENTER

CLEVELAND, OH. 44135

87
ADVANCED MODULATION TECHNOLOGY DEVELOPMENT

TASK V REVIEW

AGENDA

9:00-9:10

9:10-9-45

9:45-10:30

10:30-10:45

10:45-12:00

12:00-1:00

1:00-1:45

1:45-2:00

Introduction

System Overview

Modulator Design

Baseband

RF

Break

Demodulator Design

RF

Coherent Demodulator

(Phase Detector)

Bit Synchronizer

Baseband

Lunch

Signal Combiner

Digital

RF

Mechanical

Rich Crowley

Bob Davis

Rich Crowley

Jim Gann

Jim Gann

Jim Gann

Jim Gann

Rich Crowley

Rich Crowley

Rich Crowley

Rich Crowley

82
NASA/TDMA'.

SYSTEM OVERVIEW

NASA Lewis Research Center

Cleveland, OH

January 28, 1987

Presented l_y:

Bob Davis

Harris Corporation

Advanced Technology Department

83
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Vicwgraph 6

This vicwgraph shows the 16 symbol ending phases from the 16-ary'CPFSK modulator along

with the mapping of codcd 4-bit groups onto them. These assignments were choscn for good

code propcrtics. You will note that any group of 4 succesive phases contain all rate 112 code

branches (the 2 LSB's--sec prcvious vicwgraph). This forms the basis for our decoding strategy.

The strategy, briefly, is to retain for consideration by the decoder only the four phase nodes

nearest to the received phase. The Viterbi decoder then decidcs which of the four retained

phases is most likcly to havc becn transmitted. The 2 MSB's associatcd with the dccodcrs dccision arc output as 2 of thc dccodcd bits. The third bit decision is that information bit dccision

madc by the dccoder. Thcsc three bits make the total in/or._la:,t,r_ _:_. s_zcam output.

94
HARRIS

Government Communication

LU SystemsDivision

Modem Engineering Sectio

II I J I II I I I I

PHASE PLOT

0101

0100

0010

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1000

22.5

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0000

1001 110

1011 1111

1010

1100

1101

95
Vicwgraph 7

This viewgraph shows the performance predicted for the coded 16- CPFSK signal. Also shown

for comparison is the performance for QPSK.

g6
CODED_l_rl'Iff_LIS PHAEIG--ARYPERFORH/d,'CIZ

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177
DI-VELOPMENT OF A CODED 16-ARY CPFSK COHERENT DEMODULATOR

KEN CLARKE, Government Communications Systems Division, Harris Corporation, United States;

ROBERT DAVIS, Advanced Technology Department, Harris Corporation, United States;

JIM ROESCH, Government Communications Systems Division, Harris Corporation, United States.

I tARRIS CORPORATION

P.O. Box 37

Mail Stop 3A-1912

Melbourne, Florida 32901

United States

ABSTRACT

Theory and hardware are described for a proof-of-concept 16-ary Continuous Phase Frequency Shift Keying (16-CPFSK) digital modem. The 16 frequencies are spaced every 1/16th baud rate for 2 bits/sec/Hz operation. Overall rate 3A

convolutional coding is incorporated. The demodulator differs significantly from

typical quadrature phase detector approaches in that phase is coherently measured

by processing the baseband output of a frequency discriminator. Baud rate phase

,_amplcs from the baseband processor are decoded to yield the original data

_trcam. The method of encoding onto-the 16-ary phase nodes, together with convolutional coding gain, results in near QPSK performance. The modulated signal

is of constant envelope; thus the power amplifier can be saturated for peak performance. The spectrum is inherently bandlimited and requires no RF filter.

MODEM OVERVIEW

We discuss a bandwidth efficient constant envelope modem: 16-ary Continuous Phase Frequency

Shift Keying (16-CPFSK). Error-correction coding is applied to reduce the performance disadvantage

relative to AM .schemes. The modem is designed for 200 mb/s TDMA application with 100 mHz

adjacent channel spacing.

Theoretical Considerations

Two novel theoretical techniques are used in this 16-CPFSK modem: I) coherent phase mcasurcmcnts obtained by processing an FM discriminator baseband output; II) Modulation via a closedI(xop linearized VCO. Refer to Figure 1 in the following discussion.

Obtaining coherent phase from a discriminator, A discriminator outputs ¢'(t), where ¢(t) is the

signal's phase modulation. Integration of t_'(t ) recovers the desired signal, _t ). Implementation of the

intcgration has several practical problems: 1) Integrator output can grow without bound; 2) Initial

pha_, ¢(0), must be determined; 3) AGC is needed on the baseband signal. Regarding problem 1),

fortunately, we need only know phase Mod-2_. Thus the growth problem is avoided by integrating

Mod-27t. How can such an integrator be implemented? It is essential only that we obtain tb(nT),

phase at baud time intervals. An integrator yielding _(nT) can be implemented as a T-interval

hltcgrate-and-Dump (I&D) sampled by an A/D which feeds a digital accumulator that rolls over

Mod.2rc. The I&D is actually a lowpass Half-Nyquist filter in this modem, but the conceptual picture

remains useful.

Problem 2)--acquiring initial unknown phase, tl)(0), is handled by first observing for each baud

lime, the phase error to the closest one of the 16-CPFSK phase nodes (Mod-2n) equally spaced in the

accumulator. This phase error is filtered by a lowpass loop filter whose output is subtracted from the

178
ORIGINAL PAGE IS

OF POOR QUALITY

accumulator inpuL The initial phase error, _0), appears as a DC component of the error and is eliminated by the baseband loop. Frequency offset ( DC offset from the discriminator ) also is eliminated

by this baseband loop, the equations for which are identical to those for a PLL.

DATA

- FR_Q,__£.f t'--:J-I I I

-° "'1

"

a) MODULATOR

i, BP ' Y "-r" lal I I" I,d 2.1 =oo

t)) DEMODULATOR

Fig. 1. Basic modem block diagram

Problem 3), AGC, is bandied as shown in Figure 1. The accumulator phase error is correlated

with input samples, and baseband gain is adjusted to zero the correlation.

Linearized VCO modulator. Figure 1 shows the closed-ioop-linearized VCO modulator. The

I_a_cband filter output is applied through a feedback summer to the VCO. F(s) is a wideband loop

iiller The output of the VCO is immediately converted back to baseband by the discriminator (DISC)

and subtracted from the baseband input modulating signal to generate a correction signal in the closed

1_i., The VCO is thus modulated with small error between the baseband modulating signal and the

,)ut_ut of the DISC. If the modulator DISC is identical to the demod DISC, this modulator linearizes

!lie baseband signal path through the modem's VCO/DISC combination.

Brief Description of Modem Operation.

As shown in Figure I, incoming data is split into 3 parallel bit streams. The 2 MSBs are passed

ul,altered to modulator MSB positions. The LSB bit stream is coded by a rate tA, K=7 convolutional

cncoder. The 2 resulting coded branch bits go to the 2 LSB positions of the modulator. The 4 bits

produced by this encoding process specify one of 16 symbol-ending phases (Mod-2n) from the 16-

CPFSK modulator. Haif-Nyquist filtering is employed at the VCO baseband on 16-ary impulses to

produce the IF signal at the modulator. At the demod the IF signal is filtered and passed to the DISC.

The DISC baseband signal is Half-Nyquist filtered and sampled at symbol rate by an 8-bit A/D. The

I lalf-Nyquist filter completes shaping begun at the VCO, producing an overall Nyquist response to

!6 ary impulses. The A/D samples feed the accumulator, whose output is _nT). These phase samples

fccd a Viterbi decoder for demodulation of the original 3 data streams.

Figure 2 shows the 16-CPFSK phase nodes, along with the mapping of coded 4-bit groups onto

d_cm. Any set of 4 adjacent phases contains "all 4 rate tA code branches and has good distance structure. This fact forms the basis for our decoding strategy, to wit: retain only the 4 phase nodes nearest

the received coherent phase measurement; then let the Viterbi decoder determine which of these 4

phases is most likely to have been transmitted. The 2 modulator MSBs associated with the decoder's

decision are output as 2 of the decoded bits. The third bit decision is the data bit decision made by

the decoder. These 3 bits form the total output data bit stream.

179
Figure 3 shows performance predicted for the coded 16-CPFSK modem.

I.

0101 X

0111 X

0110 X

1000 X

1001 X

1011 X

1010 X

0100

X tO'i"

_l OI ''4 •

!

ill "4 .

ii "1 ....

100 ,-- ,.--

X 0010

X 0011

X 0001

X 0000

X 1110

X 1111

X 1101

Fig. 2. 16-CPFSK phase nodes.

\

! Illl III 14.1 I1.1

m_ll II

Fig. 3. Modem performance.

DIGITAL BASEBAND PROCESSING

We now discuss the Coherent Baseband Phase Detector (CBPD) hardware. Figure 4 depicts the

f,_uJ major functional portions of the CBPD circuitry: 1) Baseband Preprocessor, 2) Phase

Accumulator/De Restore Loop, 3) AGC Loop, and 4) Timing and Control.

,_3C Ltx_

TIC Ga_ T&C

MSB

PM_ W t OC R_mme

I

U"c_'_ "1

Fig. 4. Coherent Baseband Phase Detector.

I._;L'_Cband Preprocessor

The filtered (Raised Cosine, 25% excess bandwidth) output of the frequency discriminator is

_mpleJ at symbol rate by an 8-bit A/D converter. The samples are sequentially stored in 4 registers

tt) allow detection of an "all f0's" portion of the TDMA preamble. If detected, the remaining registers in the phase detector circuitry operate normally; otherwise, these registers are asynchronously held

Iou, The output of the fourth register, along with a ]6-bit attenuation factor, K, are input to a 16 x 16

EeL multiplier, which provides AGC on any gain variation at the output of the limiter/discriminator

!_ () 2:_% max.). At the output of the multiplier, a binary number is added to the 12-bit two's complement product such that when an f0 is received, zero is output to the phase accumulator circuit.

F_.h;l_eAccumulator/De Restore Loop

180

ORIGINAL P._C_ ._S

OF POOR QUALrPt'
OR]G:_ALPAOEIS

OF POORQUALITY

An error term, proportional to DC offset in the discriminator output (which results from frequency offset in the IF), is subtracted from the 12-bit number output from the baseband preprocessor.

"rhc "De restored" value is then accumulated by a 12-bit accumulator, completing the implementation

,,I an integrator. The output of the 12-bit accumulator represents 360 ° of coherent phase (Mod-2n).

The DC restore loop is constructed in the following fashion. During the data portion of a burst

(folh)wing the preamble and unique word), the transmiued phase constellation is restricted to that of

4-ary signalling (90 ° spacing) on every fourth transmitted symbol (called a "tracking" symbol). During the tracking symbols, the 10 LSBs, of the accumulator output, directly represent the error in hittin_.) a phase node (error-to-node). Thus, a modulo 90 ° (+45 °) phase detector characteristic is displayed

by the 10 LSBs of accumulator output during the tracking symbol. To control DC offsets out of the

discriminator, the error-to-node is multiplied by a gain factor, KL, and subtracted from the input to

the coherent phase accumulator. This processing is equivalent to a lst-order PLL correction. For a 1st

order control loop with open loop gain, K, the loop noise equivalentbandwidth is given by: Bt. = K/4

(G,u'dner, 1979). During the data portion of a burst, with KL = 1/4, and corrections being applied to

the loop on every fourth symbol, BL = Rs/64 MHz, where Rs = the symbol rate.

Phase acquisition for independent bursts is accomplished during the all-f0's portion of the

preamble. Initially, the phase accumulator is zeroed. After the all-f0's portion of the preamble has

been detected by the Baseband Preprocessor, the DC restore loop is allowed to update during every

_ymbol interval (providing maximum loop gain, and thus wide loop bandwidth). This processing

acquires _(0) and initial DC offset at the discriminator output. Since the loop corrects on every symIx_l, the loop gain is four times that of the "tracking" loop gain, and thus, BL = Rs/16 MHz. Tran.

sport delay in the digital control loop is minimized to maintain stable closed loop response for wide

loop bandwidths.

AGC Loo.12

An error term, proportional to gain missetting, is derived by correlating a delayed version of the

discriminator sign output with the error-to-node signal. The gain error is filtered by a digital accumulator, and a detector bias (1.0) is added at the accumulator output. The resulting AGC correction factor, KA, is 1 + 0.0625. The input to the CBPD circuit is scaled by KA using a 16x16 EeL multiplier.

Thus, fine decision-directed AGe is provided, which prevents "walkoff" of the coherent phase accumulator.

The loop bandwidth of the AGe loop is given by; BL = KI4, where K = Open Loop Gain.

During the all-f0's portion of the preamble, the AGe loop updates on every symbol and the open

r_)op gain is Rs/16. Like the DC Restore loop, the AGe loop updates on every fourth symbol during

tracking, so that the open loop gain is 1⁄4 that of acquisition. Thus, BL = Rs/64 during acquisition and

BL ---Rs/256 during tracking.

!ii!j!ing and Control

The major portion of the baseband timing control circuit is the Unique Word (UW) detector.

Fhc UW consists of six unique symbols immediately following the preamble. The UW is detected

when the 6 symbols fill the Lrw detector correlator cells, allowing one symbol error. The UW, when

tlctccted, establishes a second level time tick for burst processing (first level is symbol synchronization) The UW detector establishes the gating clock used to update the control loops on every fourth

:_ymbol during the data portion of a bursL

BASEBAND ENCODER/MODULATOR

In the baseband encoder, the data stream (at 200 Mbps) is partitioned into 3-bit symbols. The

two MSBs are used directly, and the LSB is rate _h, K=7 convolutionally encoded to produce a 4-bit

symbol. This overall rate 3A code, combined with the CPFSK characteristic, promotes good bandwidth

efficiency.

With 3-bit symbols, the symbol rate is reduced to 1/3 the 200 Mbps data bit rate, allowing use

of off-the-shelf EeL and eliminating need for custom ICs or GaAs technology.

181
Figure 5 shows a block diagram of the encoder/modulator. The input data buffer translates the

2(X) Mbps .serial data stream into a parallel I l-bit word, allowing the input data RAM to operate at

1/I lib of the input bit rate. The ECL RAM input buffer is configured as a FIFO. After buffering, the

data l_ read out of the FIFO and partitioned into three, 3-bit groups, and one 2-bit group. Each 3-bit

group is operated on as previously described (2 MSBs unaltered; LSB R=_A encoded) to produce 4-bit

coded symbols. The remaining 2 bits are treated as MSBs and two zero bits are appended to form the

fourth 4-bit symbol. This is done as previously described to aid the demodulator in maintaining carrier

II K'k

INPUT DATA

MUX

&

PREAMBLE J

DIFFERENTIAL

PHASE

MAPPING

4

MODULATOR

Fig. 5. Encoder block diagram.

Preamble/Unique Word

Prior to sending data, a TDMA preamble is sent. The preamble is a 32,symbol pattern alternating between the two peak frequencies of the 16-CPFSK signal, followed by 32 symbols of lowest frequency, which allows symbol synchronization and coherent phase acquisition.

A 6-symbol unique word to flag start-of-data follows the preamble. Encoded data symbols

immediately follow the unique word. The preamble, unique word, and encoded data are all selected

via the mux function shown in Figure 5.

Sy.!bolMa____j_qg

With CPFSK, transmitted frequency symbols convey "differential" phase information rather than

ab._olute phase. For example, if the previous encoded 4-bit symbol produced a phase value of _s and

the next 4-bit symbol represented phase Or0, then the modulated frequency sent out for the current

_ymlxd time is that needed to swing phase from _5 to _=o. The mapping function shown in Figure 5

provides this operation. Two registers address the mapping PROM. One contains the previous 4-bit

,'rwoded symbol and the other contains the current 4-bit symbol. This provides the mapping PROM

v,ith sufficient information to determine the required frequency to transmit such that the received

phase point will be that specified by the current 4-bit symbol.

['ncodcr Termination Sequence

At the end of the input buffered data, six zeroes are appended to the data stream sent to the

_o, volutionai encoder. This forces the encoder to start and end in state 000000 each TDMA burst.

At the receiver, the Viterbi decoder function exploits this a priori knowledge by forcing the decoder

to N'_,in in state 0000(30 on every burst.

BASEBAND DEMODULATOR

]82

OF POOR QUALITy,
OR|GlObAL PAGE IS

OF POOR QUALITY

Major baseband demodulator functions are highlighted in Figure 6 The 7-bit phase mcasurelncnt:_ as received from the CBPD, are rate buffered and sent to the mapping function, which determ,r_c_ the 4 signal phase points closest to each demodulated value. This homes in on a quadrant of

:_(Ijaccnt phase tx)ints retained as likely decision candidates.

" _ INPUT

DEMO(DUI_ATOR

Fig.6. Decoder blockdiagram.

The phase distances of these 4 candidate nodes from a given demodulated phase point serve as

hraJ,_l_ metrics to the Viterbi decoder for the four (00, 01, 10, 11) LSB R=1⁄2 code-branch bit pairs.

l'he dccoder uses these metrics direcdy to determine which of the four candidates was most likely

traJ_smitted.

As noted already, ANY four consecutive nodes in the signal constellation always contain the

values 00, 01, 10, an 11 for the encoded LSB portion; and the two unencoded MSBs simply "tag

along" with the respective encoded LSB values. These MSB tag-along bits are sent to a FIFO buffer

who.;;e length equals the throughput delay of the Viterbi decoder.

Viterbi Decoder

The four candidate branch metrics described above are fed directly into a R=_A, K=7 Viterbi

d_',:¢w:;lcrto recover the coded third of the total data bit stream. The decoder output data is then recn,:cxlcd to produce an error-corrected 2-bit symbol pair (code branch). This pair selects the

corresponding tag-along MSB bit pair from the tag-along FIFO. These tag-along MSB bits are

re_'roupcd with the corresponding output data bit from the Viterbi decoder to form the recovered 3-bit

data group.

Final Processing

The recovered 3-bit data groups are collected. On every fourth group, only two tag-along bits

:ue recovered (because the LSBs were forced to 00 back at the encoder to support phase tracking). In

_vldition, the (XXXXX)coder termination sequence is removed from the recovered data bit sequence.

The recovered data bits are then rate buffered in another FIFO whose output is then parallel-to-

,:cri:d converted. This reconstructs the original data stream at the original high speed data bit rate (200

Mbp._).

Par',dlclism in the design of the encoder/modulator and decoder/demodulator allows thc use of

lower speed, lower cost technology for most internal processing operations. High data rate parts are

limited to the encoder/modulator input and to the decoder/demodulator output.

REFERENCES

Gardner, F.M. 1979. Phaselock Techniques. John Wiley & Sans, New York, New York.

183
TASK VII REPORT

Harris Corporation GCSD

P.O. BOX 91000

Melbourne, FL 32902

prepared for

NASA Lewis Research Center

Contract number NAS3-24681

184
SECTION

TABLE OF CONTENTS

PAGE

1.0

1.1

1.2

1.3

2.0

2.1

2.2

2.3

3.0

3.1

3.2

INTRODUCTION ........................................................................................... 186

Reason for Test ........................................................................................ " ]86

Description of Unit Under Test (UUT) ............................................. 186

Applicable Documents ........................................................................... ] 86

PROOF-OF-CONCEPT MODEL TEST RESULTS ................................... 187

System Noise ............................................................................................. 187

Nonlir,,ear Distortion ............................................................................... ] 9]

Inter Symbol Interference ................................................................... 19]

PROOF<:)F-CONCEPT MODEL TEST ANALYSES,

ASSESSMENT, AND RECOMMENDATIONS ........................................... ] 93

Assessment of Technology Readiness to Proceed with

Engineering Model Development ........................................................ 193

Design Modification Recommendations for Engineering

Model Development .................................................................................. 194

Frequency Measuring Circuits ............................................................ 195

Baseband Circuits .............................................................. ...................... ] 95

APPENDIX A - POC Model Test Plan, Procedure,

and Test Data Sheets ............................................................................. ] 98

APPENDIX B - Gate Array Industry Survey .................................... 269

185
1.0 INTRODUCTION

This report is prepared by Harris Government Communications

Systems Division for NASA Lewis Research Center under contract

NAS3-24681. This report is written in response to SOW paragraph 2.7,

Task VII Proof-of-Concept (POC) Testing and Analyses. The purpose of

this document is to present the results of the tests conducted in

accordance with the POC Model Test Plan and Procedure developed in

response to SOW subtask 2.5.3 and which covers in detail all of the

categories of the top level test plan generated under subtask 2.4.4.

1.1 Reason for Test

The purpose of the POC Model Test is to verify the ability of the

POC model to meet the performance requirements of SOW sections 3.1 and

3.2, and to provide a quantitative measure of the required electrical and

performance parameters. Additionally, the purpose of the POC Model Test

is to produce recommendations for the development of an engineering

model demodulator using further advanced implementation technology,

based on analyses of test results.

1.2 Descriotion of Unit Under Test I[UUT)

The UUT is the POC model demodulator which is comprised of

the Demodulator chassis and the Demodulator Power Supply chassis. The

Demodulator chassis contains the RF and digital circuits that transform

the 3.373 GHz 16-ary CPFSK RF waveform to digital burst data. The

Demodulator Power Supply chassis houses the DC power supplies that

provide power to the Demodulator chassis. The chassis are standard Zero

enclosures.

1.3 Applicable Documents

• Contract NAS3-24681 Statement of Work (SOW)

• POC Model Performance Specification, Rev. A, November 1986

• POC Model Test Plan and Procedure

The POC Model Test Plan and Procedure document is attached as

Appendix A to this report. Section 2.0 contains the P©C Model Test Plan,

Section 3.0 contains the POC Model Test Procedure, and Section 4.0

contains the POC Model Test Data Sheets.

]86
2.0 PROOF-OF-CONCEPT MODEL TEST RESULTS

Regrettably, contract funds were exhausted before the POC

Model Test could be performed. Certain technical problems with the POC

model hardware prevented the desired BER performance from being

achieved. As a result, no meaningful data could be derived by performing

the formal POC model test procedure. We believe that conceptually the

modulation approach we selected is sound and that the problems with the

POC model hardware implementation can be resolved. The following

paragraphs serve to document the known problems and explain their effect

on system performance.

2.1 System Noise

A noise floor exists within the POC Model Demodulator and

Special Test Equipment (STE) that establishes an error floor which

prevents the system from operating error free. One of the functions of the

Signal Combiner Chassis is to allow noise to be summed with the desired

signal for the purpose of measuring BER performance versus Eb/N 0. Even

when no noise from the internal noise source is summed with the desired

signal, a significant amount of unexpected noise can be measured at the

demodulator. The exact origin of the unwanted noise is unknown but

switching power supply pick up, amplifier noise figures, and coupling from

the internal noise source are all suspected to be potential contributors.

The purpose of this discussion is to document the amount of noise present

and project its effect on system BER performance.

Figure 2.1.1 shows a spectrum analyzer plot at the

discriminator output of the demodulator. The single carrier shown at

36.36 MHz was produced by alternately transmitting f0 f15 tones. These

tones represent the maximum FSK tone spacing available in our modulation

scheme and are spaced 15/16*symbol rate, or 68.18 MHz apart. Since

these tones alternate at a period equal to 2 symbols, their fundamental

frequency is 1/(2*symbol period), or 36.36 MHz. They are shown as a

reference point since the number of LSBs for the maximum f0 f15 peak to

peak frequency deviation is known to be 120 LSBs. Since this f0 f15

signalling is sinusoidal, the RMS value of the signal in LSBs can be

computed by the following:

!20 LSB_ p-p = 42.43 LSBs

2q2

187
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Figure 2.1.1 Spectrum Analyzer Plot at Demod Discriminator

188
The noise floor in figure 2.1.1 is at -60 dBm and was measured within a

resolution bandwidth of 100 kHz. If we assume the noise power is flat out

to 40 MHz (36.36 MHz is the ideal Nyquist baseband filter corner

frequency), the noise power in a 40 MHz bandwidth is:

-60 dBm + 101og(40MHz/100kHz)

-60 dBm + 26 dB = -34 dBm

The signal to noise ratio at the discriminator output is then:

S/N = -2 dBm - (-34 dBm) = 32 dB

Given that we know the RMS value of the signal at -2 dBm corresponds to

42.43 LSBs (RMS), we can compute the RMS value of the noise in the

system from the following:

S/N = 101og(42.43/n) 2 -- 32 dB

Solving for n"

(42.43/n) 2 = 1585

n 2 = 42.432/1585

n = 1.06 LSBs (RMS)

From figure 2.1.2 we know the noise variance at the output of

the tracking loop due to the A/D converter quantizing noise. At the 1 MHz

loop natural frequency the RMS jitter is 0.6 LSBs. At the input to the loop,

i.e. the A/D converter output, the quantizing noise is uniformally

distributed over + 0.5 LSB. The RMS value of the quantizing noise in a

quantizing interval of width q is q/_/12, or 0.29 LSBs. Thus the ratio of

the RMS noise at the output of the loop to the RMS noise at the input to the

loop is (0.6)/(0.29). Since we computed the amount of RMS noise at the

discriminator output to be equal to 1.06 LSBs, the amount of noise at the

output of the loop is 1.06"(0.6)/(0.29) = 2.2 LSBs (RMS).

Figure 2.1.2 shows the amount of RMS noise at the output of the

loop due only to additive white gaussian noise at an IF signal to noise ratio

of 17 dB. This noise is represented by the horizontal line labeled

sigmadisc and is equal to 1.75 LSBs of RMS jitter. An IF signal to noise

ratio of 17 dB corresponds to an Eb/N 0 of 14 dB and is computed from the

following equation"

189
r./3

_Q

t-"-

t"--

p,-

II

<

N

O

O

,..j

<

r_

N

E

C

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Z

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Figure 2.1.2 Loop Jitter VS Natural Frequency at 17 dB IF SNR

]90
Eb/N 0 -- (S/N)(BW/BR)

Eb/N 0 = 17 dB + 10log(100 MHz/200 MHz)

Eb/N 0 = 17dB-3dB= 14dB

From this we know that 1.75 LSBs of RMS jitter at the output of the loop

corresponds to an Eb/N 0 of 14 dB. Earlier we calculated the amount of

noise at the output of the loop from the spectrum analyzer plot of the

discriminator output to be 2.2 LSBs of RMS jitter. This means that the

Eb/N 0 at IF that would correspond to the amount of noise we observe in

our system with a.signal only input is poorer than 14 dB and can be

calculated from the following:

Eb/N01@ 2.2 LSBs = Eb/N01@ 1.75 LSBs + 101og(1.75/2.2) 2

Eb/N01@ 2.2 LSBs = 14 db - 2 dB = 12 dB

From figure 2.1.3, an Eb/N 0 = 12 dB corresponds to a predicted error rate

of approximately 2"10 -5 . This means that unless the amount of unwanted

noise is reduced, an error rate of no better than 2"10 -5 is possible.

2.2 Nonlinear Distortion

The nonlinearities from VCO baseband input to discriminator

baseband output needs to be 1% or less. For a cubic nonlinearity, this

translates to a requirement that third order intermod distortion, as

measure by a two tone test, be at least 45 dB down relative to the desired

tones. This requirement has been difficult to achieve and maintain. We

currently believe that the hardware meets this requirement, however past

problems with error rate performance have often been traced to this

difficult requirement. The D/A converter in the modulator was changed

from a Brooktree to a Honeywell unit specifically to improve the system

end to end linearity. A substantial improvement in error rate performance

was obtained by making this transition.

2.3 Inter Symbol Interference

Inter Symbol Interference (ISI) has presented problems since

the _/Nyquist filters are specified in the frequency domain yet the

performance requirements exist in the time domain. The conversion from

time domain to frequency domain was made to allow the filter vendors to

work within a medium they are familiar with. We have had to make manual

adjustments to the tunable slug coils within the filters, once they were

191
MODEM ERROR RATE PERFORMANCE

The figure shows the Bit Error Rate Performance predicted for the Harris TDMA Modem

compared to QPSK performance.

P[EFU_CE aF 16-¢PFS[

E

R

R

0

R

R

A

T

E

6,I

0,8J

0.0001

1E-_

1E-0_

1E-07

\

\

\

\

\

CIPS'_

\

_ MC,DE]Vl

\

\

\

=REDICTION

1E-08

2 3 _ 5 6 7 8 9 10 11 12 13 14 15 18

EB/I_Oin dB

1'7 18

Figure 2.1.3 16-CPFSK BER Performance

192
installed in the system, in order to optimize BER performance.

3.0 PROOF-OF-CONCEPT MODEL TEST ANALYSESI ASSESSMENT, AND

RECOMMENDATIONS

We believe that conceptually the modulation approach we

selected is sound and that the problems with the POC model hardware

implementation can be resolved. There are many inherently desirable

aspects of our design that lend themselves to the long term goal of a low

cost, highly reliable, TDMA earth station modem for commercial

applications. The following sections address the benefits of the existing

POC model hardware technology and potential improvements for future

engineering model and production units.

3.1 Assessment of Technology Readiness to Proceed with

Engineering Model Develo.oment

There are various hardware techniques incorporated into our

modem which represent an advancement of the state-of-the-art in modem

technology. Examples are: a high speed Op Amp, high speed A/D converter,

high speed D/A converter, SAW IF filter, and 1/2 Nyquist baseband Iowpass

filters. The Op Amp represents advanced technology in that a true

differential amplifier is required that has a very large bandwidth and a

very short settling time. The A/D and D/A converters represent the state

of the art in conversion technology, again because of the high speed, large

bandwidth, and low distortion requirements of our system. The IF filter

represents an advance in technology in that conflicting specifications,

such as steep skirt selectivity coupled with almost linear phase, must be

met in one filter. The 1/2 Nyquist baseband filter advances modulation

technology in that it reduces the sidelobe levels of the non-filtered CPFSK

spectrum at the output of the TWT, while minimizing Inter Symbol

Interference (ISI) at the demodulator.

Much of the existing technology utilized in the POC Model

hardware lends itself to lower recurring cost in production quantities.

Examples are: the extensive use of digital circuits in the baseband

processing, the use of surface acoustic wave (SAW) technology for the IF

filter, and the use of monolithic microwave integrated circuits (MMIC) for

the IF signal processing.

Digital technology has and still is evolving at an incredible

pace. Because of shrinking geometries, integration at the chip level is

increasing while the gate capacitance is decreasing, leading to lower

propagation delays. Also, the cost of producing complex parts keeps

193
falling due to greater percentage yields over time and an ever increasingly

competitive market. For these reasons, we have strived to construct a

major portion of our modem using digital technology. IN the POC model we

used standard ECL parts to implement a majority of the baseband signal

processing functions. We envision the use of ECL gate array circuits in the

engineering and production models, which have great potential for low

cost when quantity purchases are made. Finally, the use of digital

technology in our modem eliminates many adjustments that would have to

be performed during the production and test cycles which are labor

intensive and costly.

The IF filter is implemented using SAW technology. Because

SAW devices are fabricated from a mask (in much the same way as digital

devices), filters built using SAW technology are very repeatable from

device to device. That is, the characteristics of a filter remain very

consistent between various production runs. In addition to repeatability,

once the mask for a SAW device has been designed, the fabrication

process is automated (non labor intensive) which leads to low cost per

unit if the NRE is spread over a large quantity of units. This NRE

investment for the IF filter has already been made during the POC model

development.

Monolithic microwave integrated circuits (MMIC) is a young

technology that is maturing quickly. Many types of circuits are available

now in quantities for costs as low as $20 per unit. Available functions

include! AGC amplifiers, limiting amplifiers, phase shifters, phase

.modulators, etc., all of which operate in the GHz region. Since such

powerful devices are currently available, it is not difficult to predict

further integration levels, thus enabling even more complex MMICs to be

fabricated. We anticipate that by the 1990's, the entire front-end chain of

our modem might consist of one MMIC chip and one SAW filter on the

corner of a printed circuit card.

3.2 Design Modification Recommendations for Engineering

Model Developmenl;

We are currently using an analog VCO to switch frequencies

with no abrupt change in phase at the symbol boundaries. In the future it

will be possible and advantageous to perform the frequency modulation

using a direct digital synthesis technique via a Numerically Controlled

Oscillator (NCO). In addition, baseband processing circuits that are now

accomlished with SSI and/or MSI ECL devices can be implemented in ECL

gate arrays with a high degree of integration at the chip level, enabling

many functions to be performed by one device. The improvements that are

194
realized by the future technologies may be in performance (as is the case

of the NCO implementation of the VCO), in reliability (as is the case of the

SSI to VLSI transition), and/or cost. The key technologies used in the

modem and their current or future implementation strategies are

summarized in Table 3.2.

Table 3.2 Current VS Future Implementation of Key Technology Items

TECHNOLOGY ITEM

Frequency Modulator

Frequency Detector

IF Filter

Baseband Processing

Viterbi Decoder

CURRENT IMPLEMENTATION

_nak_g VCO

Bulk Analog

SAW

SSI & MSI ECL

Low Rate - SSI/MSI

FUTURE IMPLEMENTATION

Digital NCO

MMIC/SAW

SAW

ECL Gate Array

High Rate - VHSIC

3.2.1 Freauency Measuring Circuits

The advantage of using a frequency measuring circuit in the

implementation of the demodulator is that it reduces the overall hardware

design complexity of the demodulator. Thus, by reducing circuit

complexity, a cost savings is realized both in the POC model design effort

and in future production quantities. The only disadvantage to the

frequency measuring approach is the tight linearity requirements,

necessary to achieve near QPSK BER performance.

The linearity of the frequency detector and VCO impacts the

BER versus Eb/N 0 performance of our modem. Our design_ goal for the

frequency linearity was 1% which was difficult to achieve using existing

technology. As technology progresses, linearities of less than 1% will be

more easily realizable. As technology allows an NCO to be implemented at

the frequencies of interest, linearity will be of no concern in that an NCO

is inherently linear. The VCO output power variation with frequency also

impacts BER performance. Our design goal for this parameter was 0.25 dB,

but again, an NCO would alleviate this problem.

The reason a VCO was used as the continuous phase frequency

modulator is that VCOs were available that had suitable dynamic

characteristics. The disadvantage of the VCO technology is the

nonlinearity of the voltage to frequency conversion and the long term

frequency drift of the VCO. An NCO, as previously touted, is inherently

linear and its frequency stability is as good as its reference.

195
3.2.2 Baseband Circuits

The baseband signal processing functions are implemented

using digital technology and therefore realize all the advantages that are

inherent to threshold logic. These advantages include: stability over time

and temperature, a high degree of integration at the chip level, immunity

to small cross-talk and noise signals, and finally, digital circuits lend

themselves to all kind of automated processes which reduce production,

test, and maintenance costs. The only disadvantage of using digital

circuits to implement the baseband processing functions of our

demodulator are the large number of interconnections required in the

baseband processing section with the use of SSI and MSI technology. This

design is inherently less reliable than an implementation with fewer LSI

components. As the implementation transitions from SSI/MSI to gate

arrays, the number of interconnections between parts as well as the total

parts count will decrease, which will increase the reliability of the

modem. The high processing speeds at which we must operate (the sample

rate = the symbol rate = 72.73 MHz) led to ECL technology to accomplish

the required processing under worst case conditions with margin. ECL

gate arrays have lagged .behind CMOS and bipolar technologies but are now

emerging in the marketplace with impressive equivalent gate counts and

speeds. A recently completed vendor survey is included in Appendix B

which highlights the capabilities of several vendors to manufacture

devices that lend themselves to this modulation technology.

We estimate that the bulk of the baseband processing circuitry

in the POC model demodulator could be replaced by five ECL gate array

devices. Each large wire wrap card could be relaced with one gate array

device. Figure 3.2.2 shows the 4 printed circuit card Viterbi decoder

implementation currently used in the POC model demodulator (on the right)

next to its functional LSI equivalent-(on the left). Although the LSI

version was developed for another application, this photograph is a

dramatic example of the reduction possibilities inherent in this design

implementation.

196
Figure 3.2.2 Four Card Viterbi Decoder and LSI Equivalent 

ORIGINAL PAGE 

8LACK AND WHITE PHOTOGRAPH 

197 
APPENDIX A

POC MODEL TEST PLAN

POC MODEL TEST PROCEDURE

POC MODEL TEST DATA SHEETS

POC MODEL TEST PLAN AND PROCEDURE

FOR THE

NASA AMTD POC MODEL DEMODULATOR

PART OF TASK V SOW REQUIREMENT

prepared for

NASA Lewis Research Center

Contract number NAS3-24681

198
SECTION

TABLE OF CONTENTS

PAGE

1.0

1.1

1.2

1.3

1.4

1.5

2.0

2.1

2.2

2.3

3.0

3.1

3.2

3.3

4.0

4.1

4.2

4.3

INTRODUCTION ........................................................................................... 200

Scope ............................................................................................................. 200

Description of Unit Under Test (UUT) ............................................. 200

Applicable Documents ........................................................................... 200

Test Equipment Required ...................................................................... 200

Failure Recovery ...................................................................................... 20]

POC MODEL TEST PLAN ........................................................................... 202

Signal Combiner Chassis Test Plan ................................................. 202

Modulator Test Plan ................................................................................ 208

POC Model Demodulator Test Plan .................................................... 21 ]

POC MODEL TEST PROCEDURE .............................................................. 217

Signal Combiner Chassis Acceptance Test Procedure ............ 218

Modulator Acceptance Test Procedure ........................................... 231

POC Model Demodulator Test Procedure ........................................ 235

POC MODEL TEST DATA SHEETS_ ......................................................... 243

Signal Combiner Chassis Acceptance Test Data Sheets ........ 244

Modulator Acceptance Test Data Sl_eets ....................................... 253

POC Model Demodulator Test Data Sheets .................................... 257

199
1.0 INTRODUCTION _

1.1

This document establishes the test requirements and describes

the Proof-of-Concept (POC) Model Test Procedure used to test the POC

Model demodulator developed for NASA Lewis Research Center on the

Harris Study entitled Advanced Modulation Technology Development for

Earth Station Demodulator Appfications.

1.2 De$criptien of Unit Under Test (UUT)

The UUT is the POC model demodulator which is comprised of

the Demodulator chassis and the Demodulator Power Supply chassis. The

Demodulator chassis contains the RF and digital circuits that transform

the 3.373 GHz 16-ary CPFSK RF waveform to digital burst data. The

Demodulator Power Supply chassis houses the DC power supplies that

provide power to the Demodulator chassis. The chassis are standard Zero

enclosures.

1.3 ADDlicable Documents

• POC Model Top Level Test Plan

• Contract NAS3-24681 Statement of Work (SOW)

• POC Model Performance Specification, Rev. A, November 1986

1.4 Test Eaui.Dment ReQuired

1.4.1 SPeCial Test Equipment (STE)

The following Special Test Equipment has been developed on

this contract for the purpose of providing the necessary and sufficient

test and simulation capability for verification of POC model demodulator

performance. This equipment was designed for operation in a laboratory

environment. This POC model test procedure contains the Acceptance Test

Procedures (ATPs) for the STE which are required to validate their

performance prior to initiating the POC model test on the demodulator.

Equivalent equipment may be used.

20O
Name

Continuous Phase Frequency Shift Keying Modulator No. 1

Continuous Phase Frequency Shift Keying Modulator No. 2

Signal Combiner Chassis

1.4.2 Commerc;ially Available Standard Test Eauioment

Name M_,nufacturer Model

1.4.3

Data Generator

Error Detector

Data Error Analyzer

Synthesized Signal Generator

Synthesized Signal Generator

Synthesized Signal Generator

Spectrum Analyzer

Oscilloscope

Cables

Hewlett Packard 3760A

Hewlett Packard 3761A

Hewlett Packard 1645A

Hewlett Packard 8660C

Hewlett Packard 8662A

Hewlett Packard 8672A

Hewlett Packard 8566

Tektronix 485

Test cables include those required to connect the UUT to the

STE plus additional support cables for interconnections between the

commercially available standard test equipment and the STE. An

interconnect diagram which shows the cables required for testing is

shown in figure 1.4.3.

1.5 Failure Recovery

In all cases, it is important for the test operator to record the

observed anomaly and all events and conditions pertinent to the failure.

It is extremely important that the test operator carefully

document the existing conditions, the state of the STE, and UUT BEFORE

taking steps to determine the cause of the test failure.

If the cause of the failure of a given test or subtest is not

immediately obvious, the test operator will repeat the test or subtest to

determine if a recurring fault is present. If such a recurring fault is

present, the test operator will initiate procedures to isolate the cause of

the fault, especially to distinguish between faults attributed to the UUT

versus other causes. If the UUT passes the retest, the test operator may

(with concurrance from QC) elect to continue the test.

20]
When recurring test failures are observed, the test will be

halted, the UUT repaired (or adjusted), and the test will be restarted. At

the time the test is restarted, the test operator, with the concurrence of

the cognizant QC representative, will determine which of the tests or

subtests previously completed must be scrapped and reaccomplished with

the repaired UUT. This determination will be made based on the nature of

the fault and the circuitry repaired or adjusted in the UUT.

In all cases where the UUT is repaired or readjusted, the

activities will be documented per applicable QC standard procedures.

2.0 POC MODEL TEST PLAN

The purpose of the POC Model Test is to characterize the

performance of the POC model demodulator with respect to design

requirements outlined in the contractual SOW and various design goals

established during the early phases of the program and defined in the POC

Model Performance Specification, Rev. A, November 1986. Table 2.0 is a

test requirements matrix which lists the various requirements and

provides a cross reference from the SOW to other documents. The purpose

of the POC Model Test is to validate those requirements listed in table 2.0

which are verifiable by testing. Analysis is provided for those

requirements which are not practical to test.

The test plan is organized in the same order that testing will

occur. First an acceptance test is performed on the Signal Combiner

Chassis and the CPFSK Modulators. The STE must pass acceptance test

criteria in order to provide the proper test environment for formal P©C

model demodulator testing.

2.1 Signal Combiner Chassis Test Plan

The Signal Combiner Chassis receives continuous low rate data

from an external data generator, buffers it, and outputs a burst of data at

the required 200 Mbps data rate for as many as three CPFSK demodulators.

Along with the 200 Mbps bursted data, it provides a 200 MHz clock and a

burst command which goes high while data is valid. It provides a test

profile switch which is used to select test options for combinations of the

modulator outputs. It also contains an internal noise source which is

summed with the modulator outputs to produce the composite IF test

signal for the demodulator. It receives demodulated 200 Mbps bursted

data from the demodulator, buffers it, and outputs continuous low rate

202
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203
data to an external bit error rate counter.

2.1.1 200 Mobs Data WraD Around Test

Much of the Signal Combiner circuitry can be verified by this

straightforward test. Normally the 200 Mbps data produced by the Signal

Combiner is routed to the Modulator, modulated onto the 3.373 GHz IF

carrier, routed to the POC Model Demodulator, CPFSK demodulated, and

routed back to the Signal Combiner. This normal configuration is shown in

figure 2.1.1. This is the standard test configuration for BER testing.

Each of the three modulator data outputs can be individually

connected directly to the receive data inputs. The data compared at the

bit error rate counter to the PN sequence generated by the data generator

will be verified to contain no errors. This one test verifies much of the

buffering and data handling operations performed internally by the Signal

Combiner. Figure 2.1.1 also shows this test configuration which wraps the

modulator data, clock, and, burst command outputs back into the receive

data, receive clock, and unique word detect inputs.

I Data Bit Error Data Bit Error Generator Rate Counter Generator Rate Counter

Low Rate Data LOw Rate Data

_r _r

Signal Signal

Combiner Combiner

I

200 Mbps Data

'qr

CPFSK

Modulator

3.373 GHz IF I

POC Model

Demodulator

200 Mbps Data

NORMAL CONFIGURATION DATA WRAP AROUND TEST

Figure 2.1.1 200 Mbps Data Wrap Around Test Configuraton

During the 200 Mbps Data Wrap Around Test, the ACQ FAILURE

lamp will be observed to remain extinguished. The acquisition failure

circuits that drive this lamp look for a unique word detect (UWDET) pulse

back from the demodulator fQr every burst command (BURST) generated by

204
the Signal Combiner. If it misses one, the ACQ FAILURE lamp is

illuminated. In the test configuration shown if Figure 2.1.1, these signals

are directly connected to prevent the acquisition failure circuits from

illuminating the lamp. This function will be tested by disconnecting the

wrap around cable while still in the wrap around test configuration.

Illumination of the lamp will be verified. The cable will then be

reconnected and the action of pressing the START button will be observed

to extinguish the lamp.

2.1.2 Signal Combiner Data Length Test

The Signal Combiner provides a selection of three different

length data messages per burst: 170 bits, 3,734 bits, and 11,258 bits.

Each of the modulator data outputs will be verified to produce the three

message lengths by measuring the time interval of the burst command

signal and observing the data and clock signals for each modulator output.

The burst duty cyle will also be measured to verify compliance with SOW

requirement 3.2.2(i) for a 1 burst per msec minimum burst duty cycle.

2.1.3 Test Profile Switch Function Test

The Test Profile Switch has two positions and controls how

many bursts per frame are used and whether the incoming PN data is

separated into unique data streams or all PN bits sent to all modulators.

When the Test Profile Switch is in the 1 position, the desired signal at the

demodulator has one burst per frame. Interfering baseband data messages

are produced in this mode with overlapping burst commands for co-channel

and adjacent channel testing. When the Test Profile Switch is in the MULT

position, the demodulator sees the desired signal as two staggered bursts

per frame.

2.1.3.1 Overlappinq Burst Command Test

The purpose of the Co-channel Interferer Test is to measure the

BER performance degradation with an interferer which occupies the same

time slot and frequency band but is 20 dB below the desired signal.

Therefore the burst commands produced by the Signal Combiner should

overlap as shown in figure 2.1.3. The burst command signals from each of

the modulator data outputs will be simultaneously compared to verify the

overlap.

2O5
CH 1

CH2

I I i

4 symbol times

L__

0.3 I

all PN sequences the same

TEST PROFILE SWITCH, POSITION 1

10 nsec min

k. J

Y

different PN sequences

TEST PROFILE SWITCH, POSITION MULT

Figure 2.1.3 Burst Commands VS Test Profile Switch Position

The purpose of the Adjacent Channel Interferer Test is to

measure the BER performance degradation with an interferer which

occupies the same time slot and an adjacent band one half bit rate away in

frequency. This is done with the interferer power equal to the desired

signal power. In the Adjacent Channel Interferer Test, the burst

commands produced by the Signal Combiner should have the same

relationship as in the Co-channel Interferer Test. In both cases the PN

sequences are the same for each of the modulator data outputs, but offset

in time by four symbol periods, or 13.75 nsec. This data relationship will

also be visually verified.

2.1.3.2 Staggered Bursl; Command Test

In the Independent User Test, consecutive messages per TDM

frame are transmitted from independent sources, separated by a minimum

guard time of 10 nsec. The Independent User Test demonstrates the ability

of the demodulator to fully acquire consecutive independent users in one

TDM frame. It is also indicates the sensitivity of the demodulator bit

synchronizer to asynchronous symbol clock relationships. In the Staggered

Burst Command Test, the burst commands produced by the Signal Combiner

should be separated by a minimum guard time of 10 nsec as shown in

figure 2.1.3. Different PN sequences for each message should also be

produced. The Signal Combiner generates the different PN sequences by

doubling the data generator data rate and demultiplexing the incoming PN

sequence into unique sequences for each modulator. The burst command

signals from each of the modulator data outputs will be simultaneously

compared to verify the staggered relationship. The guard time between

206
successive bursts will be measured to verify compliance with the 10 nsec

minimum guard time requirement of SOW 3.2.2(h). The data outputs will

also be compared to verify that the .messages are not the same.

2.1.4 RF Output Test

The Signal Combiner contains an internal noise source which is

summed with the modulator outputs to produce the composite IF test

signal for the demodulator. The maximum noise spectral density at IF will

be measured and the noise output flatness will be determined. The gain

through each of the modulator channels will also be measured for a 3.373

GHz CW input at -30 dBm.

2.1.4.1 Noise Spectral Density Determination

The objective of this test is to assess the noise spectral

density, No, about the 3.373 GHz IF, at the output of the Signal Combiner.

This test is performed with the noise source on at its highest power level

and all modulators off. The first measurement is in the form of an

observation. The signal combiner output will be observed on an

oscilloscope. The oscilloscope should reveal a bandlimited waveform with

no DC component and no noticeable clipping of the waveform. Noise

flatness will be determined by observing the Signal Combiner output on a

spectrum analyzer at a low video bandwidth. The noise power should be

flat within + 1 dB over a 400 MHz bandwidth centered at 3.373 GHz. N o , or

the noise spectral density measured about the IF will be determined by

utilizing a feature of the spectrum analyzer which allows the rms noise

level to be read out normalized to a 1 Hz noise power bandwidth. The

spectrum analyzer accurately correctes the noise level measurement

readout for its log amplifier and detector response and normalizes the

value to a 1 Hz bandwidth. The measurement is made by centering the

spectrum analyzer marker at the average noise power level within the 400

MHz bandwidth and invoking the noise level measurement feature.

2.1.4.2 RF Output Power

With the noise source disconnected, a CW 3.373 GHz signal from

an external frequency synthesizer will be connected to each of the

modulator IF inputs and the power level at the summed output measured.

With a -30 dBm power level at each of the modulator inputs, the output

power level at the SUMOUT connector should be 0 dBm.

207
2.2 Modulator Test Plan

A fully functional Signal Combiner Chassis, which has passed

its ATP, is required to perform the ATP on the Modulator. Several SOW

design requirements are verified indirectly by observing that the

waveforms produced by the STE are within specified limits.

2.2.1 Bas0band Data Test

The Modulator receives 200 Mbps bursted serial NRZ data from

the Signal Combiner Chassis and demultiplexes it into three parallel bit

streams. Every third bit in is rate one half convolutionally encoded,

resulting in a 4 parallel bit symbol. Normally every three serial data bits

in are used to produce a 4 parallel bit symbol. Every fourth symbol,

however, is used for tracking and is derived by taking two data bits in and

assigning them as the MSB and NSB of the symbol as usual. The difference

is that the third data. bit in is not clocked into the encoder, which is

frozen. Instead, two zeros are appended as LSBs to the MSB and NSB to

form the tracking symbol. Therefore, for three consecutive trios of

incoming bits a symbol is formed. Every fourth symbol is formed from two

incoming bits. The ratio of incoming bits to symbols is therefore 11/4.

This relationship holds true for all of the data bits except for the last 16

bits in the message.

Eight consecutive zeros are clocked into the encoder for the

last eight symbols in the message in order to flush the encoder or force it

to terminate in an all zeros state. Two incoming serial data bits are

assigned as the MSB and NSB of the symbol as usual. Instead of clocking

the third data bit in the sequence into the encoder, a zero is substituted

for it and clocked in instead. This process continues for the last 16 bits

in, or the last eight symbols out. The ratio of incoming bits to symbols for

the last 8 symbols is therefore 16/8 or 2/1.

The Modulator also generates and affixes the preamble and

unique word symbols in front of the data message.

2.2.1.1 Minimum Length Message Test

The Modulator provides a data length message selector which

has to match the data length selected at the Signal Combiner for one of

three different length data messages per burst. The minimum length

message is 170 bits long or (170-16)'4/11 + 16"1/2 (Termination

Sequence) = 64 symbols. The requirement that the data portion of the

minimum length message in a burst be equal in length to the preamble

208
portion of the burst will be verified by observing the output of an

amplifier past the D/A converter and Nyquist filter, but before the VCO.

The preamble, which consists of a 32 symbol long alternating fo' f15

pattern followed by 32 consecutive fo symbols, can be clearly observed,

followed by the 6 symbol long unique word. The termination sequence is

derived from the last 16 message bits in and is therefore part of the data

message. The relationships of the preamble, unique word, and data

message are depicted in Figure 2.2.1. The number of preamble symbols

will be counted and compared to the data message symbols. This test, in

conjunction with the POC demodulator test verifies SOW requirement

3.2.2(I).

!-" 1.8425 usec

i TM

Short

Message -- i_i_i _i!i_TM •  ̧ ̧_ ̧ ̧_ ilii

Long

Message

°

Preamble

57.2825 usec

i_ i

_ _Unique Word Data Message

Figure 2.2.1 Burst Structure at Modulator D/A Output

2.2.1.2 Modulator Data Length Test

There are three possible message lengths which are selectable

by the burst data length switch on the front panel: 170 bits, 3,734 bits,

and 11,258 bits. Although this test was previously performed on the

Signal Combiner, it is necessary to reverify the data lengths and burst

duty cycle. The Modulator reclocks the incoming bit stream with an

asynchronous symbol clock and creates a symbol stream complete with

preamble and unique word. The burst duty cycle will also be measured to

verify compliance with SOW requirement 3.2.2(i) for a 1 burst per msec

209
minimum burst duty cycle.

2.2.1.3 Uniaue Word Length Test

Using the same test configuration, the requirement that the

unique word length be less than 20 bit times will also be verified. With

random data furnished from the data generator, the unique word is easily

distinguished from the preamble and the data message by observing

multiple bursts of data. The number of unique word symbols will be

counted, which is by design, six. Since 6s*11b/4s = 16.5 bits, it is

obvious that SOW requirement 3.2.2(e) is met.

2.2.1.4 Uniaue Word Pattern Test

The format of the unique word generated by the Modulator must

match one of four possible addresses which the P©C Model Demodulator is

designed to recognize. Both modulators must also have the same unique

word in order to perform the successive bursts per frame test. The fixed

unique word pattern generated by the modulator will be verified to be f8 f8

fo f8 fo f8"

2.2.3 Modulated SDectra Test

In this test, the spectra of the modulator output will be

observed, recorded, and compared to the predicted spectra. The objective

of this test is to verify that the modulator output spectral characteristics

are such that SOW requirement 3.2.2(a)for a minimum bandwidth

efficiency of 2 b/s/Hz is met.

The output of the Modulator will be observed on a spectrum

analyzer and plotted on a sheet of paper. A mask printed on a transparent

overlay will be placed over the plotter output and compared against the

Modulator output spectra. The modulated spectra will be verified to fall

within the mask limits, as shown in Figure 2.2.3. If the entire burst were

comprised of random data, the resulting spectra would fall totally within

the mask. Since each burst contains a non-random preamble containing an

alternating fo f15 pattern, associated spectral components occur every

36.36 MHz (the fundamental frequency of the fof15 pattern), or 1/2 symbol

rate away from the center frequency. Due to the dominance of the fo tone

in the preamble, its associated spectral component is also visible in the

modulator output spectra. It is located 34.09 MHz or 1/2"15/16 symbol

rate to the right of the 3.373 GHz center frequency. Due to the non-random

nature of the preamble it is permissible for the preamble spectral

210
components to break the mask limits, as illustrated in Figure 2.2.3.

fo at 34.09 MHz from center

liillllllllltttllllll

preamble harmonics at n'36.36 MHz

Outer Mask

lJlllllnllllllnll

Modulato_

RFOUT

Inner

IIIIIIiiinlnlll

Figure 2.2.3 16-ary CPFSK Modulator Output Spectra

2.3 POC Model Demodulator Test Plan

This section describes the plan for testing the POC Model

Demodulator. The results of this testing will be published and analyzed in

the Task VII POC Model Test Report. The POC Model Test configuration is

shown in Figure 2.3.

2.3.1 Eb/No Calibration

This section describes the calibration of Eb/N o and as such is

not, by strict definition, a test. The maximum noise spectral density of

the Signal Combiner was determined and recorded as part of its ATP. The

Modulator has been designed such that when no baseband data is supplied

to the input, a single tone (carrier) output will result, if it is active. The

carrier power will be measured using a spectrum analyzer at the Output of

the Signal Combiner, with the noise source off and only one modulator

active. Using an external attenuator, the carrier power will be adjusted to

the nominal value of 0 dBm. Once the nominal carrier power has been set

to 0 dBm, the noise power will be attenuated to achieve a given Eb/N o.

From equation (2), the N o required for a given Eb/N o may be determined.

Equation (3} gives the amount of noise attenuation necessary to achieve

the Eb/N o, given the maximum noise spectral density previously recorded.

211
N o, dBm/Hz = C, dBm - Eb/N o, dB - 1010g(Rb) (2)

11.258 MHz

3.734 MHz

170 KHz

i Sig PN Gen CIk I

_ 10MHzRef I 200SigGenMHZ_

_r

l

Generator* °ata

I Err°r Detector*

wPN CLK IN

PN IN

200 MHz

REFIN

PN OUT

PN CLK OUT

IF IN

200 MHz

CLK DATA BURST

CLOCK DATA BURST I

I

C_,OIVBMAND

MODULATOR I

RF OUT I

5 MHz

REF IN

NOISE OUT

SIGNAL COMBINER

RX RX

DATA CLK

NOISE IN

SUM Ot

UWDET I

I DATA CLK DATA I

OUT OUT VALID

POC MODEL

DEMODULATOR

EXT LO DWN LINK IN

t

G.zl Sig Gen J

E

t 3.37373 GHz

I 5 MHz I

Rubidium Std

Distribution Amp I

* The Data Generator and Error Detector are replaced by the Data Error Analyzer

when the Short Burst length, i.e., 170 KHz PN clock is selected.

Figure 2.3 POC Model Test Configuration

Noise attenuation = N o, maximum - N o, desired (3)

In our system the data rate, R b is 200 Mbps. For example, to achieve an

Eb/N o of 12 dB, with a carrier power of 0 dBm, a noise spectral density of

2]2
N o = 0 - 12 - 101og(200"106) = -95 dBm/Hz is necessary. Thus, if the

maximum noise spectral density is -78 dBm/Hz, the noise source should be

attenuated by:

Noise attenuation = -78 - (-95) = 17 dB

2.3.2 .Connectivity Test

In this test the demodulator is tested in the absence of

external noise. This characterizes the performance of the demodulator and

verifies the integrity of the test setup. This test is performed with the IF

power set and held at a nominal level and with only one modulator active.

The long message (12,408 bits) will be selected. The error rate achieved

in this configuration will be recorded.

2.3.3 Valid Data Test

SOW subparagraph 3.2.1(e) requires the POC Model Demodulator

to produce a real time indication of start of valid data. In this test the

DATA VALID output is connected to one channel of a dual channel

oscilloscope and the timing compared against DATA OUT and CLK OUT. The

data bits and clocks are then verified to fall within the DATA VALID pulse.

The test configuration is the same as used in the Connectivity Test and the

long message (12,408 bits) will be selected. The duration of DATA VALID,

DATA OUT, and CLK OUT will be recorded.

2.3.4 Acauisition Test

During POC Model Demodulator testing the ACQ FAILURE lamp on

the Signal Combiner will be monitored. Any acquisition failures that occur

during POC model testing will be recorded along with the relevant test

equipment settings such as carrier power level and noise attenuation.

Since it is statistically unlikely that meaningful acquistion performance

data can be obtained during testing, the following acquistion failure rate

analysis is provided.

2.3.5 .A.cq .uisition Analysis

SOW subparagraph 3.2.2(d) requires a probability of acquistion

failure of less than 10 8.

2.3.6 BER Baseline Test

In this test the demodulator is tested in the presence of

213
external noise. The relationship of carrier power to noise attenuation will

be varied to produce a set of data points for Eb/N o versus error rate. The

resulting information will be plotted on a BER curve which shows the

relationship of the measured data to the theoretical QPSK performance

curve. Figure 2.3.5 shows an error rate curve for theoretical QPSK versus

the predicted performance curve for our system which was published in

the Task I Report. The performance requirements from SOW subparagraph

3.2.2(b) and POC Model Performance Specification, Rev. A, paragraph

2.1.1(f) are such that the Pe should be less than 5"10 -7 at an Eb/N o of 13.5

dB. This test will be performed with only one modulator active and the

long message (12,408 bits) selected. The error rate achieved in this

configuration will be recorded.

2.3.7 IF Power Level Variation Test

This test is similar to the BER Baseline Test except that

demodulator BER performance is measured at both higher and lower than

nominal IF power levels. This test statically exercises the IF limiting

stage, which is required by SOW subparaph 3.2.2(c) to operate over a 10 dB

dynamic range, or .-I:.5 dB from nominal. The actual operational effects of

dynamic range on BER performance will be determined by varying the total

IF power and plotting demodulator BER performance at an error rate of

5"1 0 -7 . This test will be performed with only one modulator active and

the long message (12,408 bits) selected.

2.3.8 POC Model Demodulator Data Length Test

In this test, the length of the data message is varied to assess

the demodulator's sensitivity to message length. Demodulator BER

performance at an error rate of 5"10 -7 is measured as a function of data

message length while holding Eb/N o constant. This test will determine the

extent to which the demodulator has fully acquired initial phase and AGC

setting by the end of the preamble. SOW subparagraph 3.2.2(d) requires a

maximum time to acquire synchronization of less than 100 information bit

times, or 36.36 symbol times. Harris requested and received permission

to increase the maximum time to acquire synchronization from 36.36

symbol times to 64 symbol times (880 nsec). This change is reflected in

the POC Model Performance Specification, Rev. A, paragraph 2.1.1(h). In

our design the first 32 alternating fo' f15 symbols of the preamble are

used to achieve symbol synchronization and burst detect. This information

is used to train the bit sync over the last 32 symbols. The last 32 all fo

symbols are used for carrier acquisition during which time the DC restore

and AGC loops track out any offsets so that the phase accumulator ends up

2]4
MODEM ERROR RATE PERFORMANCE

The figure shows the Bit Error Rate Performance predicted for the Harris TDMA Modem

compared to QPSK performance.

PERFOIW_CE OF I$-CFFSI

0.1

\

tE-B6

IE-87

IE-08

2 3 4 5 6 7 8 0 tB II

DEll! JRE DICTION

\

\

12 13 14 15 IS 17 t8

EBINOin dB

2]5
with the correct value for fo, prior to the start of unique word. If the

maximum time to acquire synchronization requirement is not met, the

demodulator will make errors early in the message and the error rate will

go up as message length is decreased. If the error rate performance stays

constant for all three possible message lengths, then the maximum time to

acquire synchronization requirement has been met.

2.3.9 Indeoendent User Test

In this test, two consecutive bursts separated by a minimum

guard time of 10 nsec are transmitted per TDM frame. This test verifies

compliance with the requirement to demodulate successive bursts per

frame from independent users (SOW subparagraph 3.2.1(d)). It will also

indicate any demodulator sensitivity to bit sync acquisition, since the

modulators each have independent, asynchronous symbol clocks. IF power

is allowed to vary up to +5 dB from nominal between independent sources.

The medium length message (4,070 bits) is selected and the IF output

frequency is set to 3.373 GHz for both modulators.

2.3.10 Co-channel Interference Test

The purpose of the Co-channel Interference Test is to measure

the BER performance degradation with an interferer which occupies the

same time slot and frequency band but is 20 dB below the desired signal.

In the Co-channel Interference Test, the burst commands overlap as shown

in Figure 2.1.3. In both cases the PN sequences are the same for each of

the modulator data outputs, but offset in time by four symbol periods, or

13.75 nsec. This test verifies compliance with sow requirement 3.2.2(g).

The long message length (12,408 bits) is selected and the IF output

frequency is set to 3.373 GHz for both modulators. The desired signal

power level will be set to nominal and the interfering signal power level

will be adjusted to achieve an error rate of 5"10 -7 . The power level of

each modulator output will be recorded.

2.3.11 Adjacent Channel Interference Test;

The purpose of the Adjacent Channel Interferer Test is to

measure the BER performance degradation with an interferer which

occupies the same time slot and an adjacent band one half bit rate away in

frequency. This is done with the interferer power equal to the desired

signal power. In the Adjacent Channel Interference Test, the burst

commands overlap as shown in Figure 2.1.3. In both cases the PN

sequences are the same for each of the modulator data outputs, but offset

in time by four symbol periods, or 13.75 nsec. The IF output frequency of

216
the modulator which produces the desired signal is set to 3.373 GHz and

the interfering modulator is set 100 MHz away. This test verifies

compliance with SOW requirement 3.2.2(f). IF power is set to the nominal

levelfor each modulator and the long message length (12,408 bits) is used.

The desired signal Eb/N o required to achieve an error rate of 5"10 -7 will

be recorded.

3.0 POC MODEL TEST PROCEDURE

The POC Model Test Procedure provides an Acceptance Test

Procedure (ATP) for each of the STE chassis and provides a POC Model

Demodulator Test Procedure for executing the POC Model Test at the

conclusion of Task VII. The purpose of these test procedures is to verify

those requirements described in the POC Model Test Plan, Section 2.0,

which are verifiable by testing. Analysis is provided in section 2.0 for

those requirements which are not practical, to test.

2]7
3.1 Signal Combiner Chassis Acceptance Test Procedure

Setup the test configuration for the Signal Combiner ATP as

shown if Figure 3.1.

11.258 MHz

3.734 MHz

170 KHz

PN CIk

Sig Gen

Data

Generator*

Error

Detector*

10 MHz Ref

Ii Sig Gen I_ F_'_

PN CLK IN IN

PN OUT CLK OUT

IF IN

200 MHz

CLK

..._j_ 5 MHz I

200 MHz 5 MHz

REF IN REF IN

NOISE OUT

SIGNAL COMBINER NOISE IN

SUM OUT

RX RX

DATA BURST DATA CLK UWDET

I ' t ''

5 MHz

Rubidium Std

Distribution

Amp

* The Data Generator and Error Detector are replaced by the Data Error Analyzer

when the Short Burst length, i.e., 170 KHz PN clock is selected.

Figure 3.1 Signal Combiner ATP Test Configuration

(a) Power the Equipment on with the cables disconnected.

Allow 30 minutes for the signal generators to stabilize.

(b) Set the HP 8662A frequency to 200 MHz and the output

level to 0.0 dBM.

(c) Set up the HP 3760A Data Generator and HP 3761A Error

Detector as defined in Table 3.1.

(d) Set the HP 8660A frequency to 11.258 MHz and the output

level to 0.9 V (+12.1 dBm, 50_2).

(e) Connect the cables between equipment as shown.

218
Table 3.1 Error Detector and Data Generator Initial Settings

Error Detector

CLOCK INPUT FIELD:

LEVEL = 0

TRIGGER MODE = +AUTO

RATE = 1.5 - 50 MBITS

DATA INPUT FIELD:

PHASE = 0

POLARITY = DATA

PRBS LENGTH 2N - 1 BITS = 8

DISPLAY FIELD:

DISPLAY HOLD = MIN

MODE = BER

SYNC = AUTO

INTERVAL 10 n CLOCK PERIODS = n - 5

GATE = REP

Data Generator

CLOCK FIELD:

TRIGGER MODE -- AUTO

RATE MBITS -- EXT

DATA DELAY ns = 0

CLOCK OUPUT FIELD:

AMPLITUDE = 3.2 V

VERNIER = MAX

CLOCK/CLOCKN = CLOCKN

DC OFFSET = +

0 TO 3V VERNIER = STRAIGHT UP

DATA FIELD:

ADD ERROR

PRBS LENGTH 2N - 1 BITS

WORD = 1010010100

DATA OUTPUT FIELD:

DC OFFSET = +

0 TO 3 V VERNIER = 1:30

RZ/NRZ = NRZ

AMPLITUDE = 3.2 V

VERNIER = MAX

DATA/DATAN = DATA

2]9
3.1.1

(f) Connect the CHANNEL 1 200 MHZ CLK, DATA, and BURST

outputs to the RX CLK, RX DATA, and UWDET inputs as shown.

(g) Place the DATA LENGTH switcll on the Signal Combiner

front panel inthe L position.

(h) Place the TEST PROFILE switch on the Signal Combiner

front panel in the 1 position.

(i) Record the following information in the Signal Combiner

Chassis Acceptance Test Procedure Data Sheets, section 4.1:

• All test equipment serial numbers and cal due dates

• Test operator and QC initials certifying correct setup

200 Mbos Data Wrao Around Test

(a) Press the RESET button on the front of the Signal Combiner.

(b) Verify that the ACQ FAILURE lamp is extinguished, The

lamp should remain extinguished at all times while the wrap

around cables are connected.

(c) Record the error rate displayed on the Error Detector. The

error rate display should read 1.9 * 10-6.

(d) Disconnect the cable between the CHANNEL 1 BURST output

and the UWDET input.

(e) Verify that the ACQ FAILURE lamp is illuminated.

(f) Reconnect the cable between the CHANNEL 1 BURST output

and the UWDET input.

(g) Press the RESET button on the front of the Signal Combiner.

(h) Verify that the ACQ FAILURE lamp is extinguished.

(i) Disconnect the three cables from the CHANNEL 1 outputs

and reconnect them to the CHANNEL 2 outputs.

(j) Press the RESET button on the front of the Signal Combiner.

(k) Verify that the ACQ FAILURE lamp is extinguished. The

lamp should remain extinguished at all times while the wrap

around cables are connected.

(I) Record the error rate displayed on the Data Error Analyzer.

The error rate display should read 1.9 * 10-6.

(m) Disconnect the cable between the CHANNEL 2 BURST output

and the UWDET input.

(n) Verify that the ACQ FAILURE lamp is illuminated.

(o) Reconnect the cable between the CHANNEL 2 BURST output

and the UWDET input.

(p). Press the RESET button on the front of the Signal Combiner.

(q) Verify that the ACQ FAILURE lamp is extinguished.

(r) Disconnect the three cables from the CHANNEL 2 outputs

and reconnect them to the CHANNEL 3 outputs.

220
(s) Press the RESET button on the front of the Signal Combiner.

(t) Verify that the ACQ FAILURE lamp is extinguished. The

lamp should remain extinguished at all times while the wrap

around cables are connected.

(u) Record the error rate displayed on the Data Error Analyzer.

The error rate display should read 1.9 * 10-6.

(v) Disconnect the cable between the CHANNEL 3 BURST output

and the UWDET input.

(w) Verify that the ACQ FAILURE lamp is illuminated.

(x) Reconnect the cable between the CHANNEL 3 BURST output

and the UWDET input.

(y) Press the RESET button on the front of the Signal Combiner.

(z) Verify that the ACQ FAILURE lamp is extinguished.

3.1.2 Signal Combiner Data Length Test

(aa) Connect the CHANNEL 1 BURST output to CH 1 of the

oscilloscope and trigger on the rising edge of the CH 1 input.

Adjust the TIME/DIV to 10 usec/div. Adjust CH 1 VOLTS/DIM

to 0.5 volts/div.

(ab) The time interval between the rising and falling edges of

the BURST pulse should be approximately 5.6 divisions, or 56.29

+ 5 usec in duration. Record the time interval on the data

sheet.

(ac) Connect the CHANNEL 1 200 MHZ CLK to CH 2 of the

oscilloscope and adjust CH 2 VOLTS/DIV to 0.5 volts/div.

(ad) The time duration of the 200 MHZ CLK should be

approximately 5.6 divisions, or 56.29 + 5 usec in duration.

Record the time interval on the data sheet.

(ae) Connect the CHANNEL 1 200 MHZ DATA to CH 2 of the

oscilloscope.

(af) The time duration of the 200 MHZ DATA should be

approximately 5.6 divisions, or 56.29 + 5 usec in duration.

Record the time interval on the data sheet.

(ag) Connect the CHANNEL 2 BURST output to CH 1 of the

oscilloscope.

(ah) The time interval between the rising and falling edges of

the BURST pulse should be approximately 5.6 divisions, or 56.29

+ 5 usec in duration. Record the time interval on the data

sheet.

(ai) Connect the CHANNEL 2 200 MHZ CLK to CH 2 of the

oscilloscope.

22]
11.258 MHz

3.734 MHz

170 KHz

PN CIk 1_

Sig Gen J""

Data

Generator*

Error

Detector*

10 MHz Ref I

PN CLK IN

PN IN

200 MHz

Sig Gen

200 MHz.

REF IN

5 MHz

REFIN

NOISE OUT

PN OUT

PN CLK OUT

IF IN

200 MHz

CLK DATA

SIGNAL COMBINER NOISE IN

RX

BURST DATA

SUM OUT

RX

CLK UWDE-I"

I Twinaxial to Coaxial connector converter I Ext Power / Supply (-5V]

Connect as described in test procedure

I Oscilloscope

(Test Configuration for Data Length Test and Burst Command Tests)

I 5 MHz I

Rubidium Std

Distribution Amp I

* The Data Generator and Error Detector are replaced by the Data Error Analyzer

when the Short Burst length, i.e., 170 KHz PN clock is selected.

Figure 3.1.2 Test Configuration for Data Length and Burst

Command Tests

(aj) The time duration of the 200 MHZ CLK should be

approximately 5.6 divisions, or 56.29 + 5 usec in duration.

Record the time interval on the data sheet.

(ak) Connect the CHANNEL 2 200 MHZ DATA to CH 2 of the

•oscilloscope.

222
(al) The time duration of the 200 MHZ DATA should be

approximately 5.6 divisions, or 56.29 + 5 usec in duration.

Record the time interval on the data sheet.

(am) Connect the CHANNEL 3 BURST output to CH 1 of the

oscilloscope.

(an) The time interval between the rising and falling edges of

the BURST pulse should be approximately 5.6 divisions, or 56.29

+ 5 usec in duration. Record the time interval on the data

sheet.

(ao) Connect the CHANNEL 3 200 MHZ CLK to CH 2 of the

oscilloscope.

(ap) The time duration of the 200 MHZ CLK should be

approximately 5.6 divisions, or 56.29 + 5 usec in duration.

Record the time interval on the data sheet.

(aq) Connect the CHANNEL 3 200 MHZ DATA to CH 2 of the

oscilloscope.

(ar) The time duration of the 200 MHZ DATA should be

approximately 5.6 divisions, or 56.29 + 5 usec in duration.

Record the time interval on the data sheet.

(as) Set the HP 8660A frequency to 3.734 MHz and place the

DATA LENGTH switch on the Signal Combiner front panel in the

M position.

(at) Connect the CHANNEL 1 BURST output to CH 1 of the

oscilloscope and adjust the TIME/DIV to 2 usec/div.

(au) The time interval between the rising and falling edges of

the BURST pulse should be approximately 9.3 divisions, or 18.67

+ 1 usec in duration. Record the time interval on the data

sheet.

(av) Connect the CHANNEL 1 200 MHZ CLK to CH 2 of the

oscilloscope.

(aw) The time duration of the 200 MHZ CLK should be

approximately 9.3 divisions, or 18.67 +_1 usec in duration.

Record the time interval on the data sheet.

(ax) Connect the CHANNEL 1 200 MHZ DATA to CH 2 of the

oscilloscope.

(ay) The time duration of the 200 MHZ DATA should be

approximately 9.3 divisions, or 18.67 _+_1 usec in duration.

Record the time interval on the data sheet.

(az) Connect the CHANNEL 2 BURST output to CH 1 of the

oscilloscope.

(ba) The time interval between the rising and falling edges of

the BURST pulse should be approximately 9.3 divisions, or 18.67

+ 1 usec in duration. Record the time interval on the data

sheet.

223
(bb) Connect the CHANNEL 2 200 MHZ CLK to CH 2 of the

oscilloscope.

(bc) The time duration of the 200 MHZ CLK should be

approximately 9.3 divisions, or 18.67 + 1 usec in duration.

Record the time interval on the data sheet.

(bd) Connect the CHANNEL 2 200 MHZ DATA to CH 2 of the

oscilloscope.

(be) The time duration of the 200 MHZ DATA should be

approximately 9.3 divisions, or 18.67 ± 1 usec in duration.

Record the time interval on the data sheet.

(bf) Connect the CHANNEL 3 BURST output to CH 1 of the

oscilloscope.

(bg) The time interval between the rising and falling edges of

the BURST pulse should be approximately 9.3 divisions, or 18.67

± 1 usec in duration. Record the time interval on thedata

sheet.

(bh) Connect the CHANNEL 3 200 MHZ CLK to CH 2 of the

oscilloscope.

(bi) The time duration of the 200 MHZ CLK should be

approximately 9.3 divisions, or 18.67 + 1 usec in duration.

Record the time interval on the data sheet.

(bj) Connect the CHANNEL 3 200 MHZ DATA to CH 2 of the

oscilloscope.

(bk) The time duration of the 200 MHZ DATA should be

approximately 9.3 divisions, or 18.67 4- 1 usec in duration.

Record the time interval on the data sheet.

(bl) Replace the HP 3760A and HP 3761A Data Generator and

Error Detector with the HP 1645A Data Error Analyzer and set

it for external clock.

(bm) Set the HP 8660A frequency to 170 KHz and place the

DATA LENGTH switch on the Signal Combiner front panel in the

S position.

(bn) Connect the CHANNEL 1 BURST output to CH 1 of the

oscilloscope and adjust the TIME/DIV to 0.1 usec/div.

(bo) The time interval between the rising and falling edges of

the BURST pulse should be approximately 8.5 divisions, or 0.85

+ 0.05 usec in duration. Record the time interval on the data

sheet.

(bp) Connect the CHANNEL 1 200 MHZ CLK to CH 2 of the

oscilloscope.

(bq) The time duration of the 200 MHZ CLK should be

approximately 8.5 divisions, or 0.85 + 0.05 usec in duration.

Record the time interval on the data sheet.

(br) Connect the CHANNEL 1 200 MHZ DATA to CH 2 of the

224
oscilloscope.

(bs) The time duration of the 200 MHZ DATA should be

approximately 8.5 divisions, or 0.85 + 0.05 usec in duration.

Record the time interval on the data sheet.

(bt) Connect the CHANNEL 2 BURST output to CH 1 of the

oscilloscope.

(bu) The time interval between the rising and falling edges of

the BURST pulse should be approximately 8.5 divisions, or 0.85

+ 0.05 usec in duration. Record the time interval on the data

sheet.

(bv) Connect the CHANNEL 2 200 MHZ CLK to CH 2 of the

oscilloscope.

(bw) The time duration of the 200 MHZ CLK should be

approximately 8.5 divisions, or 0.85 + 0.05 usec in duration.

Record the time interval on the data sheet.

(bx) Connect the CHANNEL 2 200 MHZ DATA to CH 2 of the

oscilloscope.

(by) The time duration of the 200 MHZ DATA should be

approximately 8.5 divisions, or 0.85 .+_0.05 usec in duration.

Record the time interval on the data sheet.

(bz) Connect the CHANNEL 3 BURST output to CH 1 of the

,)scilloscope.

(ca) The time interval between the rising and falling edges of

the BURST pulse should be approximately 8.5 divisions, or 0.85

+ 0.05 usec in duration. Record the time interval on the data

sheet.

(cb) Connect the CHANNEL 3 200 MHZ CLK to CH 2 of the

oscilloscope.

(cc) The time duration of the 200 MHZ CLK should be

approximately 8.5 divisions, or 0.85 4- 0.05 usec in duration.

Record the time interval on the data sheet.

(cd) Connect the CHANNEL 3 200 MHZ DATA to CH 2 of the

oscilloscope.

(ce) The time duration of the 200 MHZ DATA should be

approximately 8.5 divisions, or 0.85 + 0.05 usec in duration.

Record the time interval on the data sheet.

(cf) Connect the CHANNEL 1 BURST output to CH 1 of the

oscilloscope and adjust the TIME/DIV to 0.2 msec/div.

(cg) The time interval between the rising edges of consecutive

BURST pulses should be approximately 5 divisions, or 1 + 0.04

msec in duration. Record the time interval on the data sheet.

(ch) Connect the CHANNEL 2 BURST output to CH 1 of the

oscilloscope.

(ci) T.he time interval between the rising edges of consecutive

225
3.1.3.1

BURST pulses should be approximately 5 divisions, or 1 ± 0.04

msec in duration. Record the time interval on the data sheet.

(cj) Connect the CHANNEL 3 BURST output to CH 1 of the

oscilloscope.

(ck) The time ihterval between the rising edges of consecutive

BURST pulses should be approximately 5 divisions, or I + 0.04

msec in duration. Record the time interval on the data sheet.

Overlapoing Burst Command Test

(a) Connect the CHANNEL 1 BURST output to CH 1 of the

oscilloscope and adjust the TIME/DIV to 0.1 usec/div.

(b) Connect the CHANNEL 2 BURST output to CH 2 of the

oscilloscope.

(c) The two burst pulses should predominately overlap, with

the rising edge of the CHANNEL 1 BURST leading the rising edge

of the CHANNEL 2 BURST. Verify this overlapping relationship.

(d) The time interval between the rising edges of each of the

BURST pulses should be approximately 0.55 divisions, or 0.055

+ 0.05 usec in duration. Record the time interval on the data

sheet.

(e) The time interval between the falling edges of each of the

BURST pulses should be approximately 0.55 divisions, or 0.055

+ 0.05 usec in duration. Record the time interval on the data

sheet.

(f) Connect the CHANNEL 2 BURST output to CH 1 of the

oscilloscope and adjust the TIME/DIV to 0.1 usec/div.

(g) Connect the CHANNEL 3 BURST output to CH 2 of the

oscilloscope.

(h) The two burst pulses should predominately overlap, with

the rising edge of the CHANNEL 2 BURST leading the rising edge

of the CHANNEL 3 BURST. Verify this overlapping relationship.

(i) The time interval between the rising edges of each of the

BURST pulses should be approximately 0.55 divisions, or 0.055

+ 0.05 usec in duration. Record the time interval on the data

sheet.

(j) The time interval between the falling edges of each of the

BURST pulses should be approximately 0.55 divisions, or 0.055

+ 0.05 usec in duration. Record the time interval on the data

sheet.

(k) Connect the CHANNEL 2 BURST output to the external

trigger input of the oscilloscope and set it to trigger on the

rising edge.

(I) Connect the CHANNEL 2 200 MHZ DATA output to CH 1 of the

226
3.1.3.2

3 1.4.1

oscilloscope.

(m) Connect the CHANNEL 3 200 MHZ DATA output to CH 2 of

the oscilloscope.

(n) The PN sequences for each channel should be the same,

except time delayed. Verify that the sequences are the same.

Staggered Burst Command Test

(a) Set the HP 8662A frequency to 340 KHz and place the TEST

PROFILE switch on the Signal Combiner front panel in the MULT

position. Press Reset.

(b) Connect the CHANNEL 1 BURST output to CH 1 of the

oscilloscope and adjust the TIME/DIV to 0.2 usec/div.

(c) Connect the CHANNEL 2 BURST output to CH 2 of the

oscilloscope.

(d) The two burst pulses should be staggered and separated by

a minimum guard time of 10 nsec. Verify this staggered

relationship.

(e) Change the oscilloscope.to trigger on the falling edge of

CH 1 and adjust the TIME/DIV to 5 nsec/div.

(t) The time interval between the falling edge of CH 1 and the

,tsing edge of CH 2 should be greater than 2 divisions, or 10

nsec in duration. Record the time interval on the data sheet.

(g) Connect the CHANNEL 1 BURST output to the external

trigger input of the oscilloscope and set it to trigger on the

rising edge. Adjust the TIME/DIV to 0.2 usec/div.

(h) Connect the CHANNEL 1 200 MHZ DATA output to CH 1 of the

oscilloscope.

(i) Connect the CHANNEL 2 200 MHZ DATA output to CH 2 of the

oscilloscope.

(j) The PN sequences for each channel should be different.

Verify that the sequences are not the same.

Noise S.oectral Density_ Determination

(a) Connect the Signal Combiner NOISE OUT to NOISE IN.

(b) Connect the Signal Combiner SUM OUT to CH 1 of the

oscilloscope. DC couple the input.

(c) The bandlimited noise output should have no DC component.

Increase the CH 1 VOLTS/DIV for maximum gain. Verify that

the output has no DC component.

(d) Observe the peak noise amplitude. Verify that there is no

noticeable clipping of the waveform.

227
11.258 MHz

3.734 MHz

170 KHz

PNCIk L _ 1OMHzRef

Sig Gen Ii Generator* Da*a

Detector* Error _

PN CLK IN

PN IN

PN OUT

PN CLK OUT

IF IN

200 MHz

(_LK DATA

200 Sig Gen MHz I

200 MHz

REF IN

[-_ "_5 MHz

I'

5 MHz

REF IN

NOISE OUT

SIGNAL COMBINER

RX RX

BURST , DATA CLK

NOISE IN

SUM OU_

UWDET I

I Oscilloscope I

Connect as described in test procedure

I Spectrum Analyzer I

5 MHz

Rubidium Sld

* The Data Generator and Error Detector are replaced by the Data Error Analyzer

when the Short Burst length, i.e., 170 KHz PN clock is selected.

Figure 3.1.4.1 NoiseSpectral Density Determination Setup

(e) Connect the Signal Combiner SUM OUT to the HP 8566

Spectrum Analyzer.

(f) Set the spectrum analyzer video bandwidth to 300 Hz and

the center frequency to 3.373 GHz.

(g) The noise power should be flat within + 1 dB over a 400

MHz bandwidth centered at 3.373 GHz. Record the noise power

flatness in ribs.

(h) Place the spectrum analyzer marker at a point within the

400 MHz bandwidth which is centered in amplitude with

respect to the peak excursions measured in step (g).

228
(i) Press SHIFT, M, NORMAL to invoke the noise level

measurement normalized to a 1 Hz bandwidth.

(j) Record the value for NOdisplayed in dBm/Hz.

2.1.4.2 RF Out out Power

11.258 MHz

3.734 MHz

170 KHz

PN CIk

Sig Gen

r

Data Generator*

Error

Detector*

10 MHz Ref

PN CLK IN

PN IN

PN OUT

PN CLK OUT

IF IN

200 MHz

CLK DATA

200 MHz

Sig Gen

200 MHz

REF IN

FT--L

5 MHz

REF IN

SIGNAL COMBINER

RX RX

BURST DATA CLK

5 MHz

NOISE OUT

NOISE IN

SUM OUT --

UWDET

I Rubidium 5 MHz Std I

I Distribution Amp

3.373 GHz

Sig Gen

't

I Spectrum Analyzer

* The Data Generator and Error Detector are replaced by the Data Error Analyzer

when the Short Burst length, i.e., 170 KHz PN clock is selected.

Figure 3.1.4.2 RF Output Power Test Configuration

(a) Disconnect the Signal Combiner NOISE OUT from NOISE IN.

(b) Connect a -30 dBm, 3.373 GHz signal from the HP 8672A

Signal Generator to the Signal Combiner CHANNEL 1 IF IN input.

(c) Connect the spectrum analyzer to the Signal Combiner

SUM OUT output.

(d) The output power level at the SUM OUT connector should be

approximately 0 dBm. Record the output power level.

(e) Connect the -30 dBm, 3.373 GHz signal from the HP 8672A

229
Signal Generator to the Signal Combiner CHANNEL 2 IF IN input.

(f) The output power level at the SUM OUT connector should be

approximately 0 dBm. Record the output power level.

(g) Connect the -30 dBm, 3.373 GHz signal from the HP 8672A

Signal Generator to the Signal Combiner CHANNEL 3 IF IN input.

(h) The output power level at the SUM OUT connector should be

approximately 0 dBm. Record the output power level.

230
3.2 Modulator Acceptance Test Procedure

Setup the test configuration for the Modulator ATP as shown in

Figure 3.2.

11.258 MHz

3.734 MHz

170 KHz

l Sig PN Gen CIk I_'"

¶ r

l Generator* °ata

Detector*

10 MHz Ref

PN CLK IN

200 MHz I

Sig Gen

PN IN

PN OUT

PN CLK OUT

200 MHz 5 MHz

REF IN REF IN

NOISE OUT

SIGNAL COMBINER NOISE IN

IF IN SUM OU'[

200 MHz RX RX

CLK DATA BURST DATA CLK UWDET

I 5 MHz I

Rubidium Std

CLOCK DATA BURST I

COMMAND I

MODULATOR I

TP 1 RFOUT I

[Oscill°scope I"_" I I J Spectrum Analyzer

Distribution

Amp

•_ Plotter J

* The Data Generator and Error Detector are replaced by the Data Error Analyzer

when the Short Burst length, i.e., 170 KHz PN clock is selected.

Figure 3.2 Modulator ATP Test Configuration

(a) Power the Equipment on with the cables disconnected.

Allow 30 minutes for the signal generators to stabilize.

231
3.2.1

(b) Set the HP 8662A frequency to 200 MHz and the output

level to 0.0 dBM.

(c) Set the HP 1645A Data Analyzer for external clock.

(d) Set the HP 8660A frequency to 170 KHz and the output

level to 0.9 V (+12.1 dBm, 50.Q).

(e) Connect the cables between equipment as shown.

(f) Connect the CHANNEL 1 200 MHZ CLK, DATA, and BURST

outputs to the Modulator CLOCK, DATA, and BURST COMMAND

inputs as shown.

(g) Place the DATA LENGTH switch on the Signal Combiner

front panel in the S position.

(h) Place the TEST PROFILE switch on the Signal Combiner

front panel in the 1 position.

(i) Place the BURST LENGTH switch on the Modulator front

panel in the SHORT position.

(j) Remove the top cover of the Modulator and

disconnect the coaxial cable between the wideband amplifier

output and the input to the VCO. Connect a test cable from the

wideband amplifier output to the oscilloscope CH 1 input.

(i) Record the following information in the Modulator

Acceptance Test Procedure Data Sheets, section 4.2:

• All test equipment serial numbers and cal due dates

• Test operator and QC initials certifying correct setup

Baseband Data Test

(a) Adjust CH 1 VOLTS/DIV to 0.5 volts/div and the TIME/DIV

to 0.2 msec/div.

(b) The burst of baseband data should repeat every 1 msec or

once every 5 divisions, or 1000 + 40 usec in duration. Record

the time interval of the burst duty cycle on the data sheet.

(c) Adjust the TIME/DIV to 0.2 usec/div.

(d) Measure the time interval of the preamble which consists

of 32 alternating fo' f15 symbols followed by 32 fo symbols.

This time interval should be approximately 4.4 divisions, or

880 nsec in duration. Verify this approximate time interval.

(e) The next six symbols following the preamble are the unique

word. From the end of the unique word, measure the remaining

time interval of the burst. This message portion of the burst is

obvious due to its "noisey" appearance caused by the

nonrepetitive PN sequence. This time interval should be

approximately 4.4 divisions, or 880 nsec in duration. Verify

this approximate time interval.

232
(f) Change the position of switch number $2 on the Signal

Combiner dip switch to change from the random external PN

pattern to an internal fixed data pattern.

(g) Pull the DLY'D SWEEP knob and adjust the TIME DELAY of the

oscilloscope to 10 nsec.

(h) Expand the time base and use the delay time position

vernier to scan through the burst from beginning to end and

count the number of preamble symbols. The number of preamble

symbols should be 64. A symbol is 13.75 nsec in duration.

Record the number of preamble symbols.

(i) The next 6 symbols are the unique word. The unique word

pattern is f8 f8 fo f8 fo f8 An f8 is approximately halfway in

amplitude between the maximum voltage excursion and the

minimum voltage excursion. An fo corresponds to the minimum

voltage excursion. The unique word pattern is shown in Figure

3.2.1. Count the number of unique word symbols and record the

pattern on the data sheet.

f f f

8 8

f f f

o 8 o 8

Figure 3.2.1 Unique Word Pattern at input to VCO

(j) Count the remaining number of symbols in the burst,

follwing the six unique word symbols. Record the remaining

number of symbols in the burst which should be 64.

(k) Take the oscilloscope out of the DELAYED SWEEP mode and

adjust the TIME/DIV to 2 usec/div.

(I) The burst length should be approximately 1 division, or 2

usec (1.8425 usec to be exact) in duration. Verify this

approximate time interval.

(m) Replace the HP 1645A Data Error Analyzer with the HP

3760A and HP 3761A Data Generator and Error Detector as

shown in Figure 3.1.

(n) Set the HP 8660A frequency to 3.734 MHz and place the

BURST LENGTH switch on the Modulator front panel in the

MEDIUM position.

233
3.2.3

(o) Place the DATA LENGTH switch on the Signal Combiner

front panel in the M position and press the front panel RESET

switch.

(p) The burst length should be approximately 10 divisions, or

20 usec (19.6625 usec to be exact) in duration. Verify this

approximate time interval.

(q) Set the HP 8660A frequency to 11.258 MHz and place the

BURST LENGTH switch on the Modulator front panel in the LONG

position.

(r) Place the DATA LENGTH switch on the Signal Combiner

front panel in the L position and press the front panel RESET

switch.

(s) Adjust the oscilloscope TIME/DIV to 10 usec/div.

(t) The burst length should be approximately 6 divisions, or

usec (57.2825 usec to be exact) in duration. Verify this

approximate time interval.

Modulated S0ectra Test

(a) Connect the Spectrum Analyzer to the Modulator RF OUT

connector, as shown in Figure 3.2.

(b) Adjust the Spectrum Analyzer for a frequency SPAN of 364

MHz and a CENTER frequency of 3.373 GHz.

(c) Set the RES BW to 300 kHz and the VBW to 1MHz.

f0 at 34.09 MHz from center

6O

harmonics at n'36.36 MHz

Outer Mask

Illllllllllllllll|

ModulatoM

RFOUT

Inner Mas

IIIIIIIIIIIIIIlU

Figure 3.2.3 Modulated Spectra Waveform within Mask Limits

234
3.3

as shown in

(d) Select LOG 10 dB/div and adjust the REFERENCE LINE and

LEVEL until the center of the modulated spectra is on the first

horizontal line down from the top of the display.

(e) The resulting waveform should fit within the mask

provided, as illustrated in figure 3.2.3.

(f) Plot the output of the Spectrum Analyzer display and

overlay the mask provided. Verify that the Modulator output

falls within the mask limits.

POC Model Demodulator Test Procedure

Set up the test configuration for the POC Model Test Procedure

Figure 3.3.

(a) Power the Equipment on with the cables disconnected.

Allow 30 minutes for the signal generators to stabilize.

(b) Set the HP 8662A frequency to 200 MHz and the output

level to 0.0 dBM.

(c) Set the HP 1645A Data Analyzer for external clock.

(d) Set the HP 8660A frequency to 11.258 MHz and the output

level to 0.9 V RMS (+12.1 dBm, 50_).

(e) Connect the cables between equipment as shown.

(f) Connect the Demodulator DATA OUT, CLK OUT, and DATA

VALID outputs to the Signal Combiner RX DATA, RX CLK, and

UWDET as shown.

(g) Place the DATA LENGTH switch on the Signal Combiner

front panel in the L position.

(h) Place the TEST PROFILE switch on the Signal Combiner

front panel in the 1 position.

(i) Place the BURST LENGTH switch on the Modulator front

panel in the LONG position.

(j) Place the BURST LENGTH switch on the Demodulator front

panel in the LONG position.

(k) Place the UNIQUE WORD switch on the Demodulator in the

110101 position.

(I) Set the Signal Combiner internal dip switches $1 and $2 to

the open position to select an external random PN pattern as a

data source. Set $4 to the closed position for coded testing.

Set $8 to the closed position to select rising edge clock

alignment.

(m) Record the following information in the POC Model

Demodulator Test Procedure Data Sheets, section 4.3:

• All test equipment serial numbers and cal due dates

235
• Test operator and QC initials certifying correct setup

11 258 MHz

3.734 MHz

170 KHz

PN CIk

Sig Gen

Data

i _3ef;erator*

i D_;tector* Erro r

w

10 MHz Ref

PN CLK IN

!PN IN

I 200 Sig Gen MHz _,

'"

200 MHz 5 MHz

REF IN REF IN

PN OUT

PN CLK OUT

IF IN

SIGNAL COMBINER

200 MHz RX RX

CLK DATA BURST DATA CLK

5 MHz

I 5 MHz I

Rubidium Std

Distribution

Amp

t t t

CLCCK DATA BURST DATA CLK DATA I

r

COMMAND OUT OUT VALID

POC MODEL

MODULATOR DEMODULATOR

EXT LO

t

2.87373 GHz 1

Sig Gen J

RFOUT

SUM O_

UWDET I

DWN LINK IN I

3.37373 GHz

• The Data Generator and Error Detector are replaced by the Data Error Analyzer

when the Short Burst length, i.e., 170 KHz PN clock is selected.

Figure 3.3 POC Model Test Configuration

3.3.1 Eb/No .Calibration

(a) Disconnect the CLOCK, DATA, and BURST COMMAND inputs

to the Modulator.

(b) Disconnect the NOISE OUT from the NOISE IN on the Signal

Combiner.

236
(c) Connect the SUM OUT to the spectrum analyzer and record

the measured carrier power in dBs.

(d) Add attenuation between the Modulator RF OUT connector

and the Signal Combiner IF IN connector until the displayed

carrier power level reads 0 dBm. Record the attenuation in dBs.

(e) Add 5 dB of attenuation at the output of the SUM OUT

connector to drop the signal level to the -5 dBm nominal

operating value for the Demodulator. Record the attenuation in

dBs. This attenuation will be used in subsequent tests.

(f) Add an additional 5 dB of attenuation at the output of the

SUM OUT connector to drop the signal level to the -10 dBm

lower level operating value for the Demodulator. Record the

attenuation in dBs. This attenuation will be used in subsequent

tests.

3.3.2

3.3.3

Connectivity Test

(a) Reconnect the CLOCK, DATA, and BURST COMMAND inputs

to the Modulator. ..

(b) Add the 5 dB of attenuation measured in 3.3.1 (e) to the

output of the SUM OUT connector. This drops the signal level to

the -5 dBm nominal operating value for the Demodulator.

(c) Connect the output of the external attenuator at the SUM

OUT output to the Demodulator DWN LINK IN as shown in Figure

3.3 and press the front panel RESET button.

(d) Record the error rate achieved in this test configuration.

Valid Data Test

(a) Connect the Demodulator DATA VALID output to CH 1 of the

oscilloscope and trigger on the rising edge of the CH 1 input.

Adjust the TIME/DIV to 10 usec/div. Adjust CH 1 VOLTS/DIV

to 0.5 volts/div.

(b) The time interval between the rising and falling edges of

the DATA VALID pulse should be approximately 5.6 divisions, or

56.29 + 5 usec in duration. Record the time interval on the data

sheet.

(c) Connect the Demodulator CLK OUT to CH 2 of the

oscilloscope and adjust CH 2 VOLTS/DIV to 0.5 volts/div.

(d) The time duration of CLK OUT should be approximately 5.6

divisions, or 56.29 _+5 usec in duration. Record the time

interval on the data sheet.

(e) Connect the Demodulator DATA OUT to CH 2 of the

oscilloscope.

237
3.3.6

3.3.7

(f) The time duration of DATA OUT should be approximately 5.6

divisions, or 56.29 + 5 usec in duration. Record the time

interval on the datasheet.

B ER. B_seline Test

(a) Reconnect the Demodulator DATA OUT, CLK OUT, and DATA

VALID outputs to the Signal Combiner as shown in Figure 3.3.

(b) Record the value of N Oin dBm/Hz which was determined

during the ATP performed on the Signal Combiner in test

3.1.4.1, step (k).

(c) Add 83 dB to the value recorded in step (b) and record this

new value. For example, if the value recorded in step (b) was

-78 dBm/Hz, then 83 + (-78) = 5.

(d) In order to determine the amount of attenuation needed

between the NOISE OUT and NOISE IN connectors, add the value

recorded in (c) to the desired Eb/N 0. Using the same example,

if an Eb/N o of 12 dB is desired, 12 + 5 -- 17 dB of attenuation.

(e) By changing the amount of attenuation between the NOISE

OUT and NOISE IN connectors, record the number of errors on

the Error Detector display for each Eb/N O setting. The

recommended range of data points would be for values of Eb/N o

between +8 and +14 dB.

(f) Plot the number of errors versus Eb/N Oon the BER curve

graph paper provided in the data sheets.

IF Power Level Variation Test

(a) Remove the external attenuator at the output of the Signal

Combiner SUM OUT connector and connect the SUM OUT

connector directly to the Demodulator DWN LINK IN connector.

(b) By changing the amount of attenuation between the NOISE

OUT and NOISE IN connectors, record the number of errors on

the Error Detector display for each Eb/N Osetting. The

recommended range of data points would be for values of Eb/N o

between +8 and +14 dB. The attenuationvalue for each Eb/N O

setting is determined in the same manner as described in

3.3.6(d).

(c) Plot the number of errors versus Eb/N Oon the BER curve

graph paper provided in the data sheets for the case of 0 dBm

input signal power.

(d) Add the 10 dB of attenuation measured in 3.3.1(f) to the

238
3.3.8

output of the SUM OUT connector. This drops the signal level to

the -10 dBm lower operating value for the Demodulator.

Connect the output of the attenuator to the Demodulator DWN

LINK IN connector.

(e) By changing the amount of attenuation between the NOISE

OUT and NOISE IN connectors, record the number of errors on

the Error Detector display for each Eb/N Osetting. The

recommended range of data points would be for values of Eb/N o

between +8 and +14 dB. The attenuation value for each Eb/N O

setting is determined in the same manner as described in

3.3.6(d).

(f) Plot the number of errors versus Eb/N Oon the BER curve

graph paper provided in the data sheets for the case of -10 dBm

input signal power.

POC Model Demodulator Data Lenqth Test

(a) Add the 5 dB of attenuation measured in 3.3.1(e) to the

output of the SUM OUT connector. This returns the signal level

to the -5 dBm nominal operating value for the Demodulator.

(b) Connect the output of the attenuator to the Demodulator

DWN LINK IN connector as shown in Figure 3.3 and press the

front panel RESET button.

(c) Refer to the test results of 3.3.6. Restablish the amount of

attenuation between the NOISE OUT and NOISE IN connectors

which resulted in a bit error rate closest to 5"10 -7. Record

the number of errors on the Error Detector display and the value

for Eb/N 0.

(d) Set the HP 8660A frequency to 3.734 MHz.

(e) Place the DATA LENGTH switch on the Signal Combiner

front panel in the M position.

(f) Place the BURST LENGTH switch on the Modulator front

panel in the MEDIUM position.

(g) Place the BURST LENGTH switch on the Demodulator front

panel in the MEDIUM position.

(h) Press the Signal Combiner front pane! RESET button.

(i) Record the number of errors on the Error Detector display.

(j) Replace the HP 3760A and HP 3761A Data Generator and

Error Detector with the HP 1645A Data Error Analyzer and set

it for external clock.

(k) Set the HP 8660A frequency to 170 KHz.

(I) Place the DATA LENGTH switch on the Signal Combiner

front panel in the S position.

239
3.3.9

(m) Place the BURST LENGTH switch on the Modulator front

panel in the SHORT position.

(n) Place the BURST LENGTH switch on the Demodulator front

panel in the SHORT position.

(o) Press the Signal Combiner front panel RESET button.

(p) Record the number of errors on the Error Detector display.

Indepen_lent User Test

(a) Connect the second Modulator RF OUT to the Signal

Combiner CHANNEL 2 IF IN and disconnect the first Modulator RF

OUT from the Signal Combiner CHANNEL 1 IF IN.

(b) Disconnect the NOISE OUT test cable.

(c) Connect the SUM OUT to the spectrum analyzer and record

the measured carrier power in dBm.

(d) Add attenuation between the second Modulator RF OUT

connector and the Signal Combiner IF IN connector until the

displayed power level reads 0 dBm. Record the attenuation in

dBs.

(e) Reconnect the SUM OUT through the 5 dB attenuator to the

Demodulator DWN LINK IN.

(f) Reconnect the NOISE OUT test cable.

(g) Reconnect the first Modulator RF OUT to the Signal

Combiner CHANNEL 1 IF IN.

(h) Connect the Signal Combiner CHANNEL 2 baseband outputs

to the CLOCK, DATA, and BURST COMMAND inputs of the second

Modulator.

(i) Replace the HP 1645A Data Error Analyzer with the HP

3760A Data Generator and HP 3761A Error Detector.

(j) Set the HP 8660A frequency to 7.468 MHz.

(k) Place the DATA LENGTH switch on the Signal Combiner

front panel in the M position.

(I) Place the BURST LENGTH switch on the Modulator front

panel in the MEDIUM position.

(m) Place the BURST LENGTH switch on the Demodulator front

panel in the MEDIUM position.

(n) Place the TEST PROFILE switch on the Signal Combiner

front panel in the MULT position and press the RESET button.

(o) Using the same attenuation between the NOISE OUT and

NOISE IN connectors as used in 3.3.8, record the number of

errors on the Error Detector display.

240
3.3.10 Co-channel Interference Test

3.3.11

(a) Disconnect the first Modulator RF OUT from the Signal

Combiner CHANNEL 1 IF IN and disconnect the Signal Combiner

CHANNEL 2 baseband outputs from the CLOCK, DATA, and BURST

COMMAND inputs of the second Modulator.

(b) Disconnect the NOISE OUT test cable.

(c) Connect the SUM OUT to the spectrum analyzer and record

the measured carrier power in dBm.

(d) Add attenuation between the second Modulator RF OUT

connector and the Signal Combiner IF IN connector until the

displayed power level reads -20 dBm. Record the attenuation in

dBs.

(e) Reconnect the SUM OUT through the 5 dB attenuator to the

Demodulator DWN LINK IN.

(f) Reconnect the Signal Combiner CHANNEL 2 baseband outputs

to the CLOCK, DATA, and BURST COMMAND inputs of the second

Modulator.

(g) Reconnect the first Modulator RF OUT to the Signal

Combiner CHANNEL 1 IF IN.

(h) Reconnect the NOISE OUT test cable.

(i) Set the HP 8660A frequency to 11.258 MHz.

(j) Place the DATA LENGTH switch on the Signal Combiner

front panel in the L position.

(k) Place the BURST LENGTH switch on the Modulator front

panel in the LONG position.

(I) Place the BURST LENGTH switch on the Demodulator front

panel in the LONG position.

(m) Place the TEST PROFILE switch on the Signal Combiner

front panel in the 1 position and press the RESET button.

(n) Using the same attenuation between the NOISE OUT and

NOISE IN connectors as used in 3.3.8, record the number of

errors on the Error Detector display.

Adjacent Channel Interference Test

(a) Disconnect the first Modulator RF OUT from the Signal

Combiner CHANNEL 1 IF IN and disconnect the Signal Combiner

CHANNEL 2 baseband outputs from the CLOCK, DATA, and BURST

COMMAND inputs of the second Modulator.

(b) Connect the SUM OUT to the Spectrum Analyzer and adjust

the center frequency of the Modulator output until the carrier

frequency is 100 MHz away from the nominal 3.373 GHz.

(c) Disconnect the NOISE OUT test cable.

24]
(d) Connect the SUM OUT to the spectrum analyzer and record

the measured carrier power in dBm.

(e) Add attenuation between the second Modulator RF OUT

connector and the Signal Combiner IF IN connector until the

displayed power level reads 0 dBm. Record the attenuation in

dBs.

(f) Reconnect the SUM OUT through the 5 dB attenuator to the

Demodulator DWN LINK IN.

(g) Reconnect the Signal Combiner CHANNEL 2 baseband outputs

to the CLOCK, DATA, and BURST COMMAND inputs of the second

Modulator.

(h) Reconnect the first Modulator RF OUT to the Signal

Combiner CHANNEL 1 IF IN.

(i) Reconnect the NOISE OUT test cable.

(j) Press the RESET button on the Signal Combiner front panel.

(k) Using the same attenuation between the NOISE OUT and

NOISE IN connectors as used in 3.3.8, record the number of

errors on the Error Detector display.

242
4.0 POC MODEL TEST DATA SHEETS

Section 4.0 contains the test data sheets for the STE ATPs and

the POC Model Test of the Demodulator.

243
4.1 Signal Combiner 0hassis Acceptance Test Data Sheets

The test operator and QC representative shall record the test

data, including any pertinent comments, on the following Signal Combiner

Chassis ATP data sheets.

INITIAL STARTUP DATA:

Date

Test Operator (print):

QC Representative (print):

CUSTOMER WITNESS:

Organization:

I.JU! Ser;al Number:

244
TEST EQUIPMENT SERIAL NUMBERS:

EQUIPMENT MODEL

Data Generator HP 3760A

Error Detector HP 3761A

Data Error Analyzer

Signal Generator

Signal Generator

Spectrum Analyzer

High Speed Oscilloscope

HP 1645A

HP 8660A

HP 8662A

HP 8566B

Tek 485

HARRIS ID NO CAL DUE DATE

The remaining pages provide data sheets to be used for

recording the data from the tests. Make additional copies of these data

sheets as necessary for repeated tests.

245
4.1.1 200 Mbps Data Wrap Around Test Data Sheet

DATA

(b) ACQ FAILURE lamp off

(c) error rate display reads 1.9"10 -6

(e) ACQ FAILURE lamp on

(h) ACQ FAILURE lamp off

(k) ACQ FAILURE lamp off

(I) error rate display reads 1.9"10 -6

(n) ACQ FAILURE lamp on

(q) ACQ FAILURE lamp off

(t) ACQ FAILURE lamp off

(u) error rate display reads 1.9"10 -6

(w) ACQ FAILURE lamp on

(z) ACQ FAILURE lamp off

PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

246
4.1.2

(ab)

(ad)

(af)

(ah)

Signal Combiner Data Lenqth Test Data Sheets

DATA

CHANNEL 1 long BURST duration

CHANNEL 1 200 MHz CLK duration

CHANNEL 1 DATA duration

CHANNEL 2 long BURST duration

(aj) CHANNEL 2 200 MHz CLK duration

(al) CHANNEL 2 DATA duration

(an) CHANNEL 3 long BURST duration

(ap) CHANNEL 3 200 MHz CLK duration

(ar) CHANNEL 3 DATA duration

(au) CHANNEL 1 medium BURST duration

(aw) CHANNEL 1 200 MHz CLK duration

(ay) CHANNEL 1 DATA duration

(ha) CHANNEL 2 medium BURST duration

(bc) CHANNEL 2 200 MHz CLK duration

(be) CHANNEL 2 DATA duration

(bg) CHANNEL 3 medium BURST duration

(bi) CHANNEL 3 200 MHz CLK duration

(bk)

(bo)

(bq)

CHANNEL 3 DATA duration

CHANNEL 1 short BURST duration

CHANNEL 1 200 MHz CLK duration

247

PASS/FAIL
(bs)

(bu)

(bw)

(by)

(ca)

(cc)

(ce)

(cg)

(ci)

(ck)

CHANNEL 1 DATA duration

CHANNEL 2 short BURST duration

CHANNEL 2 200 MHz CLK duration

CHANNEL 2 DATA duration

CHANNEL 3 short BURST duration

CHANNEL 3 200 MHz CLK duration

CHANNEL 3 DATA duration

CHANNEL 1 BURST duty cycle

CHANNEL 2 BURST duty cycle

CHANNEL 3 BURST duty cycle

Test Operator Date

QC Representative Date

Reason for Test

248
4.1.3.1 OverlaDoina Burst Command Test Data Sheet

DATA

(c) CHANNEL 1 and 2 burst pulses overlap

(d) interval between rising edges

(e) interval between falling edges

(h) CHANNEL 2 and 3 burst pulses overlap

(i) interval between rising edges

(j) interval between falling edges

(n) PN sequences are the same

PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

249
4.1.3.2 Staggered Burst Command Test Data Sheet

DATA

(d) CHANNEL 1 and 2 burst pulses staggered

(f) interval between burst pulses

(j) PN sequences are not the same

PASS/FAll.,

Test Operator Date

QC Representative Date

Reason for Test

250
4.1.4.1 Noise Soectral Density Determination Data Sheet

DATA

no DC component in noise at SUM OUT

no noticeable noise waveform clipping

noise power flatness < + 1 dB

in dBm/Hz

(c)

(d)

(g)

(j) max Signal Combiner NO

PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

25]
4.1.4.2 RF Outout Power Test Data Sheet

(d) output power at SUM OUT for CHANNEL 1

(f) output power at SUM OUT for CHANNEL 2

(h) output power at SUM OUT for CHANNEL 3

DATA PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

252
4.2 Modulator A¢¢eDtance Test Data Sheets

The test operator and QC representative shall record the test

data, including any pertinent comments, on the following Modulator ATP

data sheets.

INITIAL STARTUP DATA:

Date:

Test Operator (print):

QC.,Representative (print):

CUSIOMER WITNESS:

N_-:I_,q.o:

Organization:

[IL_" _::,erial Number:

253
TEST EQUIPMENT SERIAL NUMBERS:

EQUIPMENT

Data Generator

Error Detector

Data Error Analyzer

Signal Generator

Signal Generator

Spectrum Analyzer

High Speed Oscilloscope

MODEL

HP 3760A

HP 3761A

HP 1645A

HP 8660A

HP 8662A

HP 8566B

Tek 485

HARRIS ID NO CAL DUE DATE

The remaining pages provide data sheets to be used for

recording the data from the tests. Make additional copies of these data

sheets as necessary for repeated tests.

254
4.2.1 Baseband Data Test Data Sheet

(b) burst duty cycle

(d) preamble duration verified

(e) message duration verified

(h) number of symbols in preamble = 64

(i) number of symbols in unique word = 6

unique word pattern

(j) number of sy.mbols in message = 64

(I) short burst length duration verified

(p) medium burst length duration verified

(t) long burst length duration verified

DATA PASS/FAIL,

Test Operator Date

QC Representative Date

Reason for Test

255
4.2.3 M0_lulated Spectra Test Data Sheet

(f) modulated spectra within mask

DATA PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

256
4.3 POC Model Demodulator Te_t Data Sheets

The test operator and QC representative shall record the test

data, including any pertinent comments, on the following POC Model

Demodulator Test data sheets.

INITIAL STARTUP DATA:

Date:

Test Operator (print):

QC Representative (print):

CUSTOMER WITNESS:

Name:

Organization:

UUT Serial Number:

257
TEST EQUIPMENT SERIAL NUMBERS:

Data Generator

Error Detector

Data Error Analyzer

Signal Generator

Signal Generator

Signal Generator

Spectrum Analyzer

High Speed Oscilloscope

MODEL

HP 3760A

HP 3761A

HP 1645A

HP 8660A

HP 8662A

HP 8672A

HP 8566B

Tek 485

HARRIS ID NO CAL DUE DATE

The remaining pages provide data sheets to be used for

recording the data from the tests. Make additional copies of these data

sheets as necessary for repeated tests.

258
4.3.1 Eb/No Calibration Date Sheet

(c) SUM OUT power with no attenuation

(d) atten required for SUM OUT = 0dBm

(e) atten required at SUM OUT for -5dBm

(f) atten required at SUM OUT for -10dBm

DATA PASS/FAIL,

Test Operator Date

QC Representative Date

Reason for Test

259
4.3.2 Connectivity Test Data Sheet

(d) error rate for signal only

DATA PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

260
4.3.3 Valid Data Test Data Sheet

(b) DATA VALID duration

(d) CLK OUT duration

(F) DATA OUT duration

DATA PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

261
4.3.6 I_ER Baseline Test Data Sheet

DATA PASS/FAIL

(b) maximum N o from 4.1.4.1, step (k)

(c) (b) + 83

(e) Eb/N O

versus BER

Test Operator Date

QC Representative Date

Reason for Test

262
4.3.7 IF Power Level Variation Test Data Sheet

DATA

(b) E b/N o versus BER

for +5 dBm

(e) Eb/N O versus BER

for -5 dBm

263
Test Operator Date

QC Representative Date

Reason for Test

264
4.3.8 POC Model Demodulator Data Length Test Data Sheet

DATA

(c) Eb/N O versus BER

long burst

(i) medium burst BER

(p) short burst BER

PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

265
4.3.9 Independent User Test Data Sheet

(c) 2nd Modulator power out at SUM OUT, dBm

(d) second Modulator attenuation

(o) staggered burst BER

DATA PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

266
4.3.10 C0-ohennel Interference Test Data S.heet

DATA

(c) 2nd Modulator power out at SUM OUT, dBm

(d) 2nd Modulator attenuation for -20 dBm

(n) BER with co-channel interferer

PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

267
4.3.11

(d)

(e)

(k)

Adjaoent 0hannel Interference Test Data Sheet

DATA

2nd Modulator power out at SUM OUT, dBm

2nd Modulator attenuation for 0 dBm

BER with adjacent channel interferer

PASS/FAIL

Test Operator Date

QC Representative Date

Reason for Test

268
APPENDIX B

GATE ARRAY INDUSTRY SURVEY

In order to properly evaluate the present gate array capability available in the

industry, the circuits shown in Figures B-1 and B-2 were supplied to vendors to

evaluate. Vendors were requested to calculate propagation delay, maximum

thoughput rate, power dissipation, NRE costs and gate count. A variety of vendors in

the CMOS, ECL and Bipolar technologies were contacted. Direct comparisons were

difficult for gate count because each technology defines cell or gate in a different

manner. Perhaps a better metric would be the size of the die (information that was not

supplied to all vendors). Vendors were requested to quote maximum thoughput rate,

or propagation delay for functional block in the diagram. This was to enable

identification of the time critical circuits from each vendor and enable a functional

comparison between the technologies and associated vendors. The list of vendors

and their technologies are shown in Table B-I. Figure B-3 illustrates the various

processing speed quotes from responsive vendors. Each speed value is identified

with technology and power required to implement that speed.

_t_"l'3E M CLOCK

iECL)

°&TA

BUFFER

14984-3g (X_

Figure B-1. Correlatation Circuit

269
ORIGINAL P._.GE IS

OF POOR QUALITY

¢ I

Figure B-2. Demux Circ :.-..: --"L_.J-_..',

GATE ARRAY VENDOR TECHNOLOGY

VTC Incorporated Bipolar ASIC. CMOS ASIC

Computer Circuits Laboralories. Inc. CCL Technology on Bipolar Process

Integrated CMOS Systems. Inc. CMOS 1 and 1.5 Micron Process

VLSI Technology. Inc. CMOS 1 and !.5 Micron Process

LSI Logic Corporation CMOS 1 and 1.5 Micron Process

Seattle Silicon CMOS Process

GE.RC_lntersil (Harris) CMOS 1.2 Micron Process

Sor, y Corporation of America ECL Gale Arrays

Applied Micro Circuits Corporation ECL Gale Arrays

Fujitsu Limited ECL Gale Arrays

ECL Gale Arrays Plessey Semiconductor

Table B-1. Gate Array Vendors Contacted for Information and Test Evaluation

Vendor reactionvaried from completely compliant responses to nonresponsive. Some

vendors would give generic reaction about their standard gate arrays but would not

evaluate the correlator or Mux/Demux circuit for our proposal. In general, the

advertised speeds of their processes greatly exceeded the speed at which data could

be run into and out of the device or through a macro function such as those defined in

the correlator circuit. With such a variety of responses, we felt that the best

presentation for each vendor would be to summarize the responses, we felt that the

best presentation for each vendor would be to summarize the responses from them

and include that data in this appendix.

270
CORRELATOR

CJRCUff

PROCESSING

SPEED (MHz)

1so! -

110

130

120

110

100

90

BO

70 _

5W

5Q _

40

C

"tO -- M

0

20 -- S

70

0

ICS. _NC.

NI$

H

4.7W

m

B

I

P

O

L

A

R

1SW

m

E

L

1KW

m

m

E

C

L

4500 -

4000 --

3500 --

m

3000 --

2500 I

2000 --

1500 -- 7W m m

D

i 1000 -- D

M E

-- U M

NIS X U

H m '

S00 -- 6W 11W

) 0

I..,51LOGIC CCL AMCC PLESSEY AMCC FUJITSU

Figure B-3. Power Versus Implementation versus Vendor

_W

' i i

O

M E

U M

X U

X

SONY

VTC INCORPORATED

Vendor was not responsive to the industry survey. Data included is from phone

convcersation.

Bipolar an CMOS Gate Arrays

Bipolar Process

Part Number VL2000

Low Power 1000 gate gate array

Normal Power 4000 gate gate array

High density 2 micron process

Clock speeds: 500 MHz

Cell library available: digital

Part Number VL3000

30,000 gates

High density 2 micron process

Clock speeds: 1 GHz

Cell library available: linear, digital and memory

Contact: Jay Waldero CMOS

Gary Heye BIPOLAR

27t
INTERGRATED CMOS SYSTEMS, INC.

Quote received on the correlator circuit.

CMOS Gate Arrays

8 x8 multiplier

Overall speed limiter was the 8 x 8 multiplier: 40 MHz

50 MHz

1.5 micron orocess

a. Max clock speed 40 MHz

b. Max correlation circuits in array 4

c. I/O pins 153

d. Package requirement 256 PGA

e. Power consumption 2.5 W

1.5 micron

1.0 micron

1.0 micron orocess

a. Max clock speed

b. Max correlation circuits array

c. I/O pins

d. Package requirement

e. Power consumption

50 MHz

8

285

340 pin surface mount

4.5W

NRE: 27,000 gates

25,000 gates

Moderate NRE

High NRE

5 weeks delivery

7 weeks delivery

** The circuit evaluation did not include an accumulator.

Contact: Richard Gluck

Bruce Kligensmith

(1.5 micron)

(1.0 micron)

272
VLSI TECHNOLOGY, INC.

Quote received on the correlator cicuit.

CMOS Gate Arrays

Register/adder/register:

Register/adder/mux/register:

RegisterRAMregister"

Register/multiplier/register:

14.6 ns

20.5 ns

12 ns

25.8 ns

68.5 MHz

48.7 MHz

83.3 MHz

38.7 MHz

I/O pins: 52

Package: 64 pin PGA

1.5 micron process

Die size: 140 mils

Equivalent gates: 278

No power quoted

No NRE quoted

No delivery quoted

Contact: Sunil Wadwani

273
SONY SEMICONDUCTOR

Quote received on the mux/demux circuit.

ECL Gate Arrays

2000 gate gate array

I/O pins: 100

Power: 6 watts

Propagation delay: 220 ps

Package: 32 pin PGA

200 gate gate array

I/O pins: 25

Power: 1.7 watts

Propagation delay: 150 ps

Package: 32 pin metal flat pack

NRE: Very low NRE

One 1:8 8 bit demux/IC

One 1.64 8 bit demux/four IC's

Contact: Masa Mizuno

274
APPLIED MICRO CIRCUITS CORPORATION

Fully compliant quote, i.e., quote for both correlator and mux/demux cicuit with all

questions ansewered.

ECL/TTL Logic Arrays

Correlation Circuit:

Q35090T 130 MHz: 89% util;

QM1600T 123 MHz: 89% util;

2 micron oxide isolated bipolar process

NRE; Low

Speed limit: accumulator path 123 MHz

Power: Q3500T: 8.2 Watts

QM1600T: 7.8 Watts

Demultiplexer Circuit:

Q5000T

8 bit 1:16 demux

2 micron oxide isolated bipolar process

NRE: Low

Power: 11 Watts

Mulitplexer Circuit:

Q5000T

8 bit 16:1 mux

2 micon oxide isolated bipolar process

NRE: Low

Power 5.8 Watts

149 pin PGA;

149 pin PGA;

296 cells

207 cells

350 MHz 60%util; 226 pin PGA; 353 cells

350MHz; 33% util; 226 pin PGA; 379 cells

Recommendation: Use new products currently being proven.

Q20000 series

8000 gates

16000

Contact: Keith Nootbar

Richard Negin

NRE Low January 89

NRE Low June 89

275
LSI LOGIC CORPORATION

Quote received for correlator circuit.

CMOS Gate Array

0.7 micron orocess

LCA 100135

LCA 100182

LCA 100235

60K gates

80K gates

100K gates

NRE: Very high

Includes: 15 prototypes

application engineer time

user's class

design capture center time

simulation

20 MHz test

verification package

Speed limit: 24 MHz due to multiplier cicuit

Power dissipation: no information supplied

Number of gates in design: verbal quote that design would fit in packages

outlined above.

Contact: Bill King

Dan Deitz

Bill Casanova

Special note: LSI has a design center on the Harris facility with full time

application engineers at the facility to help facilitate the design capture phase of

the process.

276
FUJITSU LIMITED

Nonresponsive to vendor request.

Information supplied below is from vendor supplied data sheet.

ECL Gate Arrays

ET3000. 3072 gates

ET4500 4480 gates

Propagation Delay: 0.7 ns for I/O buffer

Power dissipation: 7 Watts

Package: 149 pin PGA

NRE: no information supplied

Logic Library: includes mux/demux, but no hihg level macros.

PLESSY SEMICONDUCTOR

Quote received on the correlation circuit.

ECL Gate Array

Pq,qs available:

16000 gates

8000 gates

2000 gates

Contact: Mike Fisher

277
COMPUTER CIRCUITS LABORATORIES, INC.

Vebal quote received on the correlation circuit.

CCL technology on Bipolar process

Prop

Function Delay_ Power

8 bit latch 0.9 ns 77 mW

5 bit mux 0.9 ns 32 mW

8 bit adder 3.2 ns 182 mW

8 x 8 multiplier 5.0 ns 1500 mW

32 x 8 SRAM 5.0 ns 800mW

Speed limited to 150 MHz by multiplier

1.5 micron bipolar process

Core power: -2.0 V

I/O power: -4.5 V

Memory power: -4.5 V

68 pins

4.7 watts maximum

0-70 temperature range

4 fin heat sink

Contact: Dennis Prestholt

SEATTLE SILICON

Vendor was not responsive to industry survey, but supplied the following

information about the company:

CMOS ASIC design

Company sells technology tools to develop ASIC's

Wafers are bought from foundries: GE (Harris); VTC; AMI

Tools include: auto route and place software

design verification

Processes include 2.5, 1.5, 1.25, and 1.00 micron

Contact: John Schroeter

278
N,dtona_ Aeronautics rind Report Documentation Page

Space, Admtn_slrat_on

t. ReportNo. 2. GovernmentAccessionNo. 3. Recipient'sCatalogNo.

NASA CR-185126

4. Title and Subtitle

Advanced Modulation Technology Development for

Earth Station Demodulator Applications

7. Author(s)

R.C. Davis, J.V. Wernlund, J.A. Gann, J.F. Rocsch,

T. Wright, and R.D. Crowley 10.

9.

12.

Performing Organization Name and Address

Harris Corporation GCSD

P.O. Box 91000

Melbourne, Florida 32902

SponsoringAgency Name and Address

National Aeronautics and Space Administration

Lewis Research Center

Cleveland, Ohio 44135-3191

5. ReportDate

July 1989

6. PerformingOrganizationCode

8. PerformingOrganization ReportNo.

None

Work Unit No.

650-60-21

11. Contractor GrantNo.

NAS3-2468 l

13. Type of Reportand PeriodCovered

Contractor Report

Final

14. SponsoringAgencyCode

15. SupplementaryNotes

Project Manager, William D. Ivancic, Space Electronics Division, NASA Lewis Research Center.

16 Abstract

This report is the resuit of work performed under contract for NASA Lewis Research Center under the Advanced

Modulation Technology Development program. The purpose of this contract was to develop a high rate (200 Mbps),

bandwidth efficient, modulation format using low cost hardware, in 1990's technology. The modulation format

chosen is 16-ary CPFSK. The implementation of the modulation format uses a unique combination of a limiter/

discriminator followed by an accumulator to determine transmitted phase. An important feature of the modulation

scheme is the way coding is applied to efficiently gain back the performance lost by the close spacing of the phase

points.

17. Key Words(Suggestedby Author(s))

16 CPFSK

Modulation

Coding

18. DistributionStatement

Unclassified- Unlimited

Subject Category 17

19. SecurityClassif.(of this report) I 20. SecurityClassif.(of thispage) 21. No of pages

Unclassified J Unclassified 283

NASAFORM1626OCT86 *For sale by the National Technical Information Service, Springfield, Virginia 22161

22. Price*AI3

4