# Patent

## Title
Switching-mode power supplies capable of operating at valley switching, and relevant control methods

## Abstract

Control methods and related power controllers diminish audible noise in a power supply capable of performing valley switching. The power supply has an inductive device and a power switch. When the power switch is OFF, a winding voltage of the inductive device oscillates to provide an oscillation signal with at least one signal valley. An occurrence number of the signal valley is detected, and is compared with a lock number. When the occurrence number and the lock number fit a predetermined condition, the power switch is turned ON to start a cycle time at a start moment. Whether the start moment falls within an expectation window is checked. The lock number is changed if the start moment falls outside of the expectation window.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to and the benefit of Taiwan Application Series Number 105102001 filed on Jan. 22, 2016, which is incorporated by reference in its entirety.
BACKGROUND
The present disclosure relates generally to switching-mode power supplies, and more particularly to switching-mode power supplies capable of performing valley switching.
A switching-mode power supply normally uses s power switch to control the current through an inductive device, such as an inductor or a transformer. In comparison with other types of power supplies, switching-mode power supplies generally benefit from compact product sizes and efficient power conversions, and are adopted by most of power supply manufactures.
Among a variety of switching-mode power supplies, some can operate in a quasi-resonance (QR) mode and are named as QR-mode power supplies. A QR-mode power supply could perform zero-voltage switching, meaning a power switch is turned ON substantially at the moment when a voltage across the power switch is zero or minimum, so switching loss of the power switch could be minimized in theory. A QR-mode power supply generally enjoys excellent power conversion especially when the load it drives is heavy.
FIG. 1 shows a QR-mode power supply 10 in the art, where a transformer is an inductive device with a primary winding PRM, a secondary winding SEC and an auxiliary winding AUX, inductively coupled to one another. The QR-mode power supply 10 converts the input voltage VIN into an output voltage VOUT and an output current IOUT to power a load 24. A QR power controller 26 provides at a node GATE pulse-width modulation (PWM) signal VGATE to periodically turn ON and OFF a power switch 34. Via voltage-dividing resistors 28 and 30, the QR power controller 26 detects winding voltage VAUX across the auxiliary winding AUX. FIG. 2 shows waveforms of PWM signal VGATE, winding voltage VAUX, valley signal SQRD and blanking signal SBLANK. In FIG. 2, between two rising edges of the PWM signal VGATE is one cycle time TCYC consisting of one ON time TON and one OFF time TOFF, where an ON time TON is a period of time when the power switch 34 is turned ON, and an OFF time TOFF, in the opposite, is a period of time when the power switch 34 is turned OFF. As shown by the rear half of an OFF time TOFF in FIG. 2, because of the completion of demagnetization, the winding voltage VAUX starts oscillating to generate two signal valleys VL1 and VL2. The QR power controller 26 provides a valley signal SQRD which pulses each time when a signal valley is detected. The QR power controller 26 concludes the cycle time TCYC based upon the occurrence of the signal valley VL2, and this kind of switching ON a power switch in response to the occurrence of a signal valley is commonly called as valley switching.
At a compensation node COMP of the QR-mode power supply 10 is a compensation voltage VCOMP controlled by an operational amplifier 20 comparing the output voltage VOUT with a target voltage VTAR. The compensation voltage VCOMP substantially determines the durations of the ON time TON and a blanking time TBLANK, and the power controller 26 allows the cycle time TCYC to end after the blanking time TBLANK. The blanking time TBLANK can avoid the QR-mode power supply 10 from suffering low power conversion because of a too-high switching frequency fCYC (=1/TCYC). As demonstrated in FIG. 2, the blanking time TBLANK continues and does not end when the signal valley VL1 appears, so the power switch 34 is still turned OFF. Nevertheless, the signal valley VL2 appears when the blanking time TBLANK has concluded, and it makes the power switch 34 turned ON to start a next cycle time. A signal valley selected to perform valley switching is called a selected valley hereinafter, and in FIG. 2 it is the signal valley VL2.
The QR-mode power supply 10 in the art could generate uncomfortable audible noise, however. For a constant load 24, the compensation voltage VCOMP could vibrate, making the selected valley jump to and fro between two adjacent signal valleys, and resulting in an instable operation and noise in the transformer. Since a power supply operating with noise is hardly accepted in the market, the noise caused by the valley jump should be diminished or eliminated.



BRIEF DESCRIPTION OF THE DRAWINGS
Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted.
The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows a QR-mode power supply in the art;
FIG. 2 shows waveforms of PWM signal VGATE, winding voltage VAUX, valley signal SQRD and blanking signal SBLANK;
FIG. 3 demonstrates a switching-mode power supply according to embodiments of the invention;
FIG. 4 demonstrates the power controller in FIG. 3;
FIG. 5 demonstrates the valley selector in FIG. 4;
FIG. 6 illustrates timing diagrams explaining how a start moment tCYC-STRT is determined;
FIG. 7A illustrates a scenario when the start moment tCYC-STRT is behind the expectation window TGOOD;
FIG. 7B illustrates a scenario when the start moment tCYC-STRT is within the expectation window TGOOD;
FIG. 7C illustrates a scenario when the start moment tCYC-STRT is ahead of the expectation window TGOOD; and
FIG. 8 shows another power controller according to embodiments of the invention.



DETAILED DESCRIPTION
FIG. 3 demonstrates a switching-mode power supply 60, where a power controller 66 could be an integrated circuit packaged with power pins VCC and GND, current-sense pin CS, compensation pin COMP, driving pin GATE, and feedback pin FB. Each pin could be deemed as a node in view of circuit diagram, and therefore all the pins of the power controller 66 are renamed as nodes in the following description. However, a node is not necessary to be a pin in this specification.
Once the power switch 34 is turned OFF and the transformer with the primary winding PRM, the secondary winding SEC and the auxiliary winding AUX completes demagnetization, the winding voltage VAUX starts oscillation and generates at least one signal valley. According to one embodiment of the invention, the power controller 66 provides a lock number, and detects the occurrence number of the signal valley via the feedback node FB, where the occurrence number of the signal valley refers to how many times the signal valley appears. After the occurrence number and the lock number fit a predetermined condition, the power controller 66 can select a signal valley for valley switching, so the power switch is turned ON to end a cycle time and start a following cycle time at a start moment. This predetermined condition could be, for example, the occurrence number is not less than the lock number according to one embodiment of the invention.
The start moment is checked whether it is within an expectation window. If the start moment falls within the expectation window, the present switching frequency seems appropriate and the lock number remains unchanged. If the start moment occurs ahead of the expectation window, meaning the following cycle time starts even though the expectation window has not started yet, the lock number increases, expecting to lengthen the duration of the next cycle time. So a start moment of a subsequent cycle time could be delayed to fall within the expectation window. In the other hand, if the start moment falls behind the expectation window, meaning the following cycle time does not start even though the expectation window has come to an end, the lock number decreases, expecting to shorten the duration of the next cycle time. A start moment of a subsequent cycle time could become earlier to fall within the expectation window.
FIG. 4 demonstrates the power controller 66 in FIG. 3, including a compensation-voltage generator 84, a valley detector 80, a valley selector 82 and a logic gate 86.
The compensation-voltage generator 84 includes a sample-and-hold (S/H) circuit 94 and an operational amplifier 95. During an OFF time TOFF, the S/H circuit 94 samples the feedback voltage VFB at the feedback node FB to hold a voltage sample VSAMP, which the operational amplifier 95 compares with a reference voltage VREF to drive the compensation node COMP, at which the compensation voltage VCOM is generated. If the sampling is timely, the voltage sample VSAMP could be a representative of the output voltage VOUT, so the compensation voltage VCOM is generated by detecting the output voltage VOUT through the auxiliary winding AUX. The output voltage VOUT is sensed indirectly by the circuits in the primary side, and this kind of output voltage control is commonly called as primary side control (PSC). In another embodiment of the invention, a power supply controls a compensation voltage VCOMP in response to an output voltage VOUT by way of secondary side control (SSC) , which uses circuits in the secondary side to detect the output voltage VOUT, and feeds the detection result to the primary side through an isolation device, an photo coupler for example, to affect the compensation voltage VCOMP, so the power switch 34 and the power converted are controlled.
A buffer 97, a unit amplifier for example, forwards compensation voltage VCOMP to valley selector 82 and a resistor RO1. The resistors RO1 and RO2 connected in series provide to the comparator 88 a voltage level in proportion to the compensation voltage VCOMP 
When the power switch 34 is turned ON, the current sense voltage VCS at the current-sense pin CS ramps up over time in a substantially linear manner. Once the current sense voltage VCS exceeds the voltage level provided from the resistors RO1 and RO2, the comparator 88 resets the SR register 90, which in response turns the power switch 34 OFF via a driver 92 and the driving node GATE. The input and the output of the driver 92 are PWM signals SSW and VGATE, respectively. In view of their logic values, the PWM signals SSW and VGATE are substantially the same, even though they might have different voltage levels.
The valley detector 80, the valley selector 82 and the logic gate 86 in combination are coupled to the feedback node FB, for setting the SR register 90. When the SR register is set, it is the start moment tCYC-STRT of a next cycle time because the power switch 34 is turned ON, and it is also the end moment TCYC-END of the present cycle time because the present cycle concludes.
The valley detector 80 compares the feedback voltage VFB at the feedback node FB with a reference voltage, which is about 0V for example. The valley detector 80 detects whether the winding voltage VAUX becomes below 0V, an indication a signal valley is happening, and the valley detector 80 in response provides a corresponding pulse as the valley signal SQRD.
As will be detailed later, the valley selector 82 counts how many times pulses of the valley signal SQRD show up, to provide an occurrence number NVLY. For example, if the occurrence number NVLY is currently 3, the 3rd pulse of the valley signal SQRD has started and the 4th pulse has not. Once the occurrence number NVLY and a lock number NVLY_LCK from the valley selector 82 fit a predetermined condition, the valley selector 82 asserts a pass signal SGO. For example, this condition could be the occurrence number NVLY is not less than the lock number NVLY_LCK When the pass signal SGO is asserted, anyone pulse of the valley signal SQRD can go through the logic gate 86 to set the SR register 90, which in response makes driver 92 turn ON the power switch 34, performing valley switching. Accordingly, the moment when the power switch 34 is turned ON is referred to as a start moment tCYC-STRT, at which the present cycle time ends and a next cycle time starts.
Theoretically, if the lock number NVLY_LCK is X, the selected valley for performing valley switching should be the Xth signal valley, meaning the start moment tCYC-STRT should be somewhere within the duration when the Xth signal valley appears.
FIG. 5 demonstrates the valley selector 82 in FIG. 4, including a counter 120, a window generator 124, an up/down counter 128, and a digital comparator 122. Please refer to FIGS. 5 and 6, where FIG. 6 illustrates timing diagrams explaining how a start moment tCYC-STRT is determined. According to one embodiment of the invention, the lock number NVLY_LCK from the up/down counter 128 has up and bottom limits as 7 and 0 respectively, meaning the up/down counter 128 could count up to not more than 7 and down to not less than 0. It is supposed in FIG. 6 that the lock number NVLY_LCK is 4 when the present cycle time TCYC shown in FIG. 6 starts. During an ON time TON, the counter 120 is reset to have the occurrence number NVLY 0. An OFF time TOFF starts as the ON time TON ends. The winding voltage VAUX is clamped to be about a constant at the beginning of the OFF time when the transform demagnetizes. As aforementioned, the winding voltage VAUX starts oscillating after the completion of demagnetization. Every time when the winding voltage VAUX falls below 0V, the valley signal SQRD in response provides a rising edge, which makes the counter 120 count up and the occurrence number NVLY increased by 1. The occurrence number NVLY, therefore, represents how many signal valleys the winding voltage VAUX has shown in this present cycle time TCYC. The digital comparator 122 compares the lock number NVLY_LCK with the occurrence number NVLY,and asserts the pass signal SGO when these two numbers are equal. As demonstrated in FIG. 6, the pass signal SGO is de-asserted as being logic “0” when the occurrence number NVLY is 0, 1, 2 or 3, but becomes asserted after the occurrence number NVLY is switched to be 4, equal to the lock number NVLY_LCK No pulse of the valley signal SQRD can reach the SR register 90 in FIG. 4 when the pass signal SGO is de-asserted and so the logic gate blocks the valley signal SQRD. When the pass signal SGO is asserted, a pulse of the valley signal SQRD propagates a period of delay time to set the SR register 90 in FIG. 4, and, at the start moment tCYC-STRT, the present cycle time ends and a next cycle time starts.
The window generator 124 determines the beginning and the duration of an expectation window TGOOD. The up/down counter 128 checks whether the start moment tCYC-STRT falls within the expectation window TGOOD, and, in response, determines the lock number NVLY_LCK 
FIG. 7A illustrates a scenario when the start moment tCYC-STRT is behind the expectation window TGOOD. It is supposed in FIG. 7A that the lock number NVLY_LCH is an integer XN in the beginning of the present switching cycle TCYC.
Refer to both FIGS. 5 and 7A. The window generator 124 has a lead time generator 140 and a delay generator 142. Based on the compensation voltage VCOMP, the lead time generator 140 provides a preparation signal SMAX-f, which indicates an end moment tPRE-END of a preparation time TPRE. When an ON time TON starts the preparation signal SMAX-f is set to be “1” in logic, and at the end moment tPRE-END when the preparation time TPRE ends it becomes “0” in logic. The preparation time TPRE in FIG. 7A starts when the ON time TON starts, but this invention is not limited to. Embodiments of the invention could have the preparation time TPRE start when the ON time TON ends, for example. The delay generator 142 provides a delay signal SMAX-fD, a step signal as shown in FIG. 7A, after a predetermined duration following the end moment tPRE-END, and this predetermined duration is the expectation window TGOOD. The delay signal SMAX-fD is reset to be “0” when the ON time TON starts. As shown in FIG. 7A, the expectation window TGOOD follows right after the preparation time TPRE, and ends when the delay signal SMAX-fD changes from “0” into “1”. As demonstrated in FIG. 7A, an OFF time TOFF could be divided into three portions: a lead time TLEAD, the expectation window TGOOD, and a lag time TLAG, where the lead time TLEAD is ahead of the expectation window TGOOD and the lag time TLAG behind.
Shown in FIG. 5, the preparation signal SMAX-f is forwarded to an UP terminal of the up/down counter 128, and the delay signal SMAX-fD to a DOWN terminal of the up/down counter 128. At the start moment tCYC-STRT when the PWM signal SSW has a rising edge, the up/down counter 128 determines whether the lock number NVLY_LCK is changed based upon the logic levels of the preparation signal SMAX-f and the delay signal SMAX-fD. For example, if the preparation signal SMAX-f is “1”, the lock number NVLY_LCK is increased by 1. If the delay signal SMAX-fD is “1”, it is reduced by 1. If both the preparation signal SMAX-f and the delay signal SMAX-fD are “0”, the lock number NVLY_LCK remains unchanged.
Based on the aforementioned analyses, the lock number NVLY_LCK determines the selected valley within which the start moment tCYC-STRT appears, and the selected valley could be in the 1st signal valley, the 2nd signal valley, or a further subsequent one. In FIG. 7A, the start moment tCYC-STRT happens while the preparation signal SMAX-f is “0” and the delay signal SMAX-fD are “1”. It is determined that the start moment tCYC-STRT happens in the lag time TLAG behind the expectation window TGOOD. So the lock number NVLY_LCK is decreased by 1, changing from XN into XN−1. As the lock number NVLY_LCK decreases, the next cycle time is expected to end earlier, and a subsequent start moment tCYC-STRT could approach or fall within the expectation window TGOOD.
FIG. 7B illustrates a scenario when the start moment tCYC-STRT is within the expectation window TGOOD. Analogously, the lock number NVLY_LCK in FIG. 7B is supposed to be an integer XN in the beginning. The similarity of FIG. 7B to FIG. 7A is self-explanatory based upon the aforementioned teaching, and is not redundantly detailed.
In FIG. 7B, the start moment tCYC-STRT happens when the preparation signal SMAX-f and the delay signal SMAX-fD are both “0”. It implies the start moment tCYC-STRT happens while the expectation window TGOOD has not ended yet. Therefore, the start moment tCYC-STRT is within the expectation window TGOOD, and the lock number NVLY_LCK remains as XN for the next switching cycle.
FIG. 7C illustrates a scenario when the start moment tCYC-STRT is ahead of the expectation window TGOOD Analogously, the lock number NVLY_LCK in FIG. 7C is supposed to be an integer XN in the beginning. The similarity of FIG. 7C to FIGS. 7A and 7B is self-explanatory based upon the aforementioned teaching, and is not redundantly detailed.
In FIG. 7C, the start moment tCYC-STRT happens when the preparation signal SMAX-f is “1” and the delay signal SMAX-fD is “0”. It implies the start moment tCYC-STRT happens while the expectation window TGOOD has not started. Therefore, the start moment tCYC-STRT is within the lead time TLEAD ahead of the expectation window TGOOD. So the lock number NVLY_LCK is increased by 1, changing from XN into XN+1. As the lock number NVLY_LCK increases, the next cycle time is expected to end later, and a subsequent start moment tCYC-STRT could approach or fall within the expectation window TGOOD.
In embodiments of the invention, the compensation voltage VCOMP determines the duration of the preparation time TPRE but the expectation window TGOOD is a constant in length. For example, when the compensation voltage VCOMP increases because of an increment to the load 24, the preparation time TPRE becomes shorter and the length of the expectation window TGOOD remains the same. In other words, the preparation time TPRE is determined in response to the compensation voltage VCOMP, and the duration of the expectation window TGOOD is independent from the compensation voltage VCOMP. The compensation voltage VCOMP determines the beginning of the expectation window TGOOD, but not the duration of the expectation window TGOOD.
In some embodiments of the invention, the compensation voltage VCOMP determines both the durations of the preparation time TPRE and the expectation window TGOOD. For example, when the compensation voltage VCOMP increases, the preparation time TPRE becomes shorter and the expectation window TGOOD becomes wider.
If the lock number NVLY_LCK is 0, the bottom limit, the power controller 66 in FIG. 4 will always select the 1st signal valley to perform valley switching. This invention is not limited to however. FIG. 8 shows another power controller 66a, capable of replacing the controller 66 according to embodiments of the invention.
The similarity of the power controller 66a in FIG. 8 to the power controller 66 in FIG. 4 is self-explanatory based upon the aforementioned teaching, and is not redundantly detailed. In comparison with the power controller 66, the power controller 66a additionally has an OR gate 103 and a CCM controller 101. The CCM controller 101 has inputs for the delay signal SMAX-fD and the lock number NVLY_LCK, and an output to the OR gate 103. Every time when an ON time TON starts, the output of the CCM controller 101 is reset to be “0” in logic.
When the lock number NVLY_LCK is not 0, the CCM controller 101 is configured to have its output “0” in logic all the time, and the power controller 66a operates exactly the same as the power controller 66 in FIG. 4 does.
When the lock number NVLY_LCK is 0, the CCM controller 101 passes the delay signal SMAX-fD, which could go through the OR gate 103 to set the SR register 90 and turn the power switch 34 ON. If the 1st pulse of the valley signal SQRD happens earlier than the rising edge of the delay signal SMAX-fD does, the power controller 66a will select the 1st signal valley to perform valley switching, just like the power controller 66 does. If in the opposite the rising edge of the delay signal SMAX-fD happens earlier than the 1st pulse of the valley signal SQRD does, the power controller 66a will turn the power switch 34 ON right after the expectation window TGOOD ends at the rising edge of the delay signal SMAX-fD, possibly making a corresponding power supply operate in a continuous conduction mode (CCM) mode instead of a QR mode.
Based on the aforementioned analyses, if the load 24 in FIG. 3 is stable, the power controller 66 could make the switching-mode power supply 60 operate in a QR mode, the selected valley determined by the lock number NVLY_LCK, and the start moment tCYC-STRT fall within the expectation window TGOOD. The selected valley won't change if the lock number NVLY_LCK remains the same, so the troublesome audible noise might not happen. Change to the load 24 could affect the output voltage VOUT and the compensation voltage VCOMP, and in response, the expectation window TGOOD shifts and varies. The power controller 66 will modify the lock number NVLY_LCK if the start moment tCYC-STRT falls outside the expectation window TGOOD.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

## Claims

1. A control method for use of a power supply with an inductive device and a power switch, wherein when the power switch is OFF a winding voltage of the inductive device oscillates to provide an oscillation signal with at least one signal valley, the control method comprising:
providing a lock number;
detecting an occurrence number of the signal valley;
comparing the lock number with the occurrence number;
when the occurrence number and the lock number fit a predetermined condition, turning the power switch ON to start a cycle time at a start moment;
providing an expectation window;
checking if the start moment falls within the expectation window; and
changing the lock number if the start moment falls outside of the expectation window.

2. The control method as claimed in claim 1, wherein keeping the lock number unchanged if the start moment falls within the expectation window.

3. The control method as claimed in claim 1, wherein the step of providing the expectation window comprises:
providing a preparation time;
wherein the expectation window follows next to the preparation time.

4. The control method as claimed in claim 1, further comprising:
turning ON the power switch right after the expectation window ends if the lock number is a predetermined minimum.

5. The control method as claimed in claim 4, wherein the power supply operates in a continuous conduction mode.

6. The control method as claimed in claim 1, further comprising:
decreasing the lock number if the start moment occurs ahead of the expectation window; and
increasing the lock number if the start moment occurs behind the expectation window.

7. The control method as claimed in claim 1, comprising:
providing the expectation window in response to a compensation voltage; and
generating the compensation voltage in response to an output voltage of the power supply.

8. The control method as claimed in claim 7, wherein the duration of the expectation window is independent from the compensation voltage.

9. A power controller suitable for use in a power supply with an inductive device and a power switch, wherein when the power switch is OFF the inductive device is capable of providing an oscillation signal with at least one signal valley, the power controller comprising:
a valley detector coupled to the inductive device, for detecting the signal valley to provide a valley signal; and
a valley selector receiving the valley signal, for counting an occurrence number of the signal valley, comparing the occurrence number with a lock number, and when the occurrence number and the lock number fit a predetermined condition, providing a pass signal that allows the valley signal to make the power switch turned ON so a cycle time starts at a start moment;
wherein the valley selector checks if the start moment falls within an expectation window, and changes the lock number if the start moment falls outside of the expectation window.

10. The power controller as claimed in claim 9, further comprising a logic gate coupled to receive the pass signal and the valley signal, wherein when the occurrence number and the lock number fit the predetermined condition the valley signal passes through the logic gate to make the power switch turned ON.

11. The power controller as claimed in claim 9, wherein the valley selector comprises a lead time generator that provides a preparation time followed by the expectation window.

12. The power controller as claimed in claim 11, wherein the valley selector further comprises a delay generator generating a step signal to conclude the expectation window.

13. The power controller as claimed in claim 12, wherein the valley selector comprises an up/down counter coupled to the delay generator and the lead time generator, for providing the lock number.

14. The power controller as claimed in claim 9, wherein the valley selector comprises an up/down counter that counts up to increase the lock number when the start moment occurs behind the expectation window and counts down to decrease the lock number when the start moment occurs ahead of the expectation window.

15. The power controller as claimed in claim 9, wherein when the lock number is a predetermined minimum the power controller is capable of operating the power supply in a continuous conduction mode.

16. The power controller as claimed in claim 9, wherein the expectation window has a beginning determined by a compensation voltage in response to an output voltage of the power supply.

17. The power controller as claimed in claim 16, wherein the expectation window has a duration independent from the compensation voltage.

18. The power controller as claimed in claim 16, wherein the compensation voltage is generated by detecting the output voltage through the inductive device.