# Patent

## Title
Method and apparatus for phase current estimation in semi-resonant voltage converters

## Abstract

A resonant or semi-resonant voltage converter includes a synchronous rectification (SR) switch through which a current having a half-cycle sinusoidal-like shape is conducted when the SR switch is active. The current through the SR switch is modelled, and estimates of the SR switch current are generated by a digital estimator based on the model. The SR switch current estimates are updated at a fairly fast rate, as may be needed by a controller of the voltage converter. Analog converters are run at a slower rate, and generate error signals that are fed back into the digital estimator in order to improve future SR switch current estimates. Because the analog converters run at a fairly slow rate, power usage is minimal. However, the SR switch current estimates are updated at a rate that is fast enough to provide adequate control for the voltage converter.

## Background
TECHNICAL FIELD
The present application relates to semi-resonant and resonant voltage converters and, in particular, relates to techniques for estimating the current flowing through each phase of such converters.
BACKGROUND
Resonant and semi-resonant DC-DC voltage converters, including isolated and non-isolated topologies, are used in a variety of applications including telecommunications, consumer electronics, computer power supplies, etc. The usage of such converters is gaining popularity because of their zero-voltage and/or zero-current switching characteristics, and their ability to utilize parasitic electrical properties inherent in an electronic circuit. Such converters provide advantages including lower cost and higher efficiency as compared to other types of converters.
The output current of many resonant and semi-resonant voltage converters takes the shape of the upper half cycle of a sinusoid, wherein this shape occurs during each switching cycle of such voltage converters. These converters are often controlled using a variable switching frequency in order to meet their associated load requirements, which may vary over time. Multiple phases of such converters may be connected in parallel in order to increase the available load current and in order to reduce ripple at the output of such converters.
A high-performance voltage converter needs current information for each of its phases in order to provide high-quality power to its load. Such phase current information is critical in providing key features such as phase fault detection, peak current protection, phase balancing, accurate load line estimation, power saving modes, over-current protection, and improved transient response. Conventional switching power converters, including resonant converters, include current sensing/sampling networks for obtaining phase current information. However, conventional current sampling networks consume significant power and require a relatively large die area.
For example, one conventional approach for sampling phase current information makes use of flash analog-to-digital converters (ADCs). While such ADCs provide can provide fast conversion and high precision, they are relatively expensive, have high leakage current even when they are not actively converting, use high power while they are converting, and require significant die area on a controller chip or elsewhere within a voltage converter. Another conventional approach for obtaining phase current information makes use of tracking ADCs. However, tracking ADCs are susceptible to noise, require relatively high power, consume significant die area, and have poor tracking capability and performance at high currents.
Accordingly, there is a need for improved phase current estimation techniques that may be used by resonant or semi-resonant voltage converters, wherein the estimation techniques consume low power and die area, while providing accurate and fast phase current tracking.
SUMMARY
According to an embodiment of a switching voltage converter, the converter makes use of a variable switching frequency and includes a first phase, a control circuit, and a current estimator. The first phase comprises a synchronous rectification (SR) switch through which an SR current having a half-cycle sinusoidal-like shape is conducted when the SR switch is active. The current estimator includes both a digital estimation circuit and an analog conversion circuit. The digital estimation circuit generates a first estimate of the SR current using a model of current through the SR switch and an error signal. The digital estimation circuit runs at a first frequency, and updates its first estimate of SR current at the first frequency. The analog conversion circuit generates the error signal based upon an actual measured SR current and the first estimate of SR current generated by the digital estimation circuit. The analog conversion circuit updates the error signal and provides conversions at a second frequency, which is generally lower than the first frequency which is used by the digital estimation circuit. The control circuit is operable to control cycle-by-cycle switching of the SR switch by providing a pulse width modulation (PWM) control signal to the SR switch, wherein the frequency and/or the duty cycle of the PWM control signal is based upon the first estimate of the SR current.
According to an embodiment of a method, a method for current estimation in a variable-frequency voltage converter is provided. The voltage converter includes a synchronous rectification (SR) switch through which an SR current having a half-cycle sinusoidal-like shape is conducted when the SR switch is active. The method would typically be implemented within the voltage converter, or a controller within it. For each switching cycle of the voltage converter, the SR switch is enabled such that it conducts the SR current for an SR conducting period, wherein the SR conducting period is a portion of a switching period for a current switching cycle. A modelled SR current is generated based upon a model of the SR current during the SR conducting period, and is updated at a first frequency. A first SR current estimate is generated using the modelled SR current and a digital error signal. The first SR current estimate is converted into an analog SR current estimate, wherein the analog SR current estimate is updated at a second frequency. An analog SR current error is generated by taking the difference between the analog SR current estimate and a measured SR current estimate. This analog SR current estimate is then converted into a digital error signal that is also updated at the second frequency. The first SR current estimates are thus updated at a first frequency, and the analog-to-digital and digital-to-analog conversions are performed at a second frequency, wherein the second frequency is typically much lower than the first frequency. The method is normally repeated for each switching cycle of the voltage converter.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.



BRIEF DESCRIPTION OF THE FIGURES
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description that follows.
FIG. 1 illustrates a block diagram of an embodiment of a multi-phase voltage converter including a control circuit, wherein the control circuit includes a phase current estimator.
FIG. 2 illustrates a circuit diagram of an embodiment for one phase of a voltage converter such as that illustrated in FIG. 1, and may be considered itself as a single-phase voltage converter.
FIG. 3 illustrates voltage and current waveforms as might be generated in one phase of a semi-resonant voltage converter such as that shown in FIG. 2.
FIG. 4 illustrates a waveform corresponding to the current flowing through a synchronous rectification (SR) switch within a semi-resonant voltage converter such as the SR switch shown in FIG. 2.
FIG. 5 illustrates an embodiment of a phase current estimator, such as that illustrated in FIG. 1.
FIG. 6 illustrates an embodiment of a phase current estimator, such as that of FIG. 5, but with additional detail.
FIG. 7 illustrates an embodiment of a slope estimator, such as that shown in the phase current estimator of FIG. 6.
FIG. 8 illustrates a flow diagram corresponding to a method for estimating current flowing through an SR switch within a semi-resonant voltage converter, such as that shown in FIG. 2.



DETAILED DESCRIPTION
The embodiments described herein provide techniques for estimating the current within a phase of a resonant or semi-resonant voltage converter that uses variable-frequency switching. The estimated current is updated fairly frequently, but the analog components that are used for estimating the current are run at a relatively low frequency. The techniques make use of a model for the current, and then use that model and the actual measured current to create an error signal. The error signal is fed back into the model in order to update and improve the estimated current. Because the analog components that provide the error signal are run at a fairly low frequency, the current consumption and die area of the analog components can be kept fairly low. However, these techniques provide accurate current tracking with fairly frequent current estimate updates, as are needed by the controller of a variable-frequency switching voltage converter.
Various embodiments of voltage converter circuits and methods within voltage converters will be provided in the following detailed description and the associated figures. The described embodiments provide particular examples for purposes of explanation, and are not meant to be limiting. Features and aspects from the example embodiments may be combined or re-arranged, except where the context does not allow this.
FIG. 1 illustrates an embodiment of a voltage converter 100 that is configured to input power from a power source VIN, output power for driving a load 120, and that includes a phase current estimator 118. The voltage converter 100 supplies a current IOUT to the load 120 and to a capacitor C0 that serves to filter an output voltage VOUT. The voltage converter of FIG. 1 includes multiple phases 130, 180, 190. Phase 1 (130), which is taken as representative of the multiple phases, is illustrated in block diagram form with the understanding that the other phases would be similarly configured. While FIG. 1 illustrates a multi-phase voltage converter, most of the techniques presented herein are also applicable to a single-phase voltage converter.
As illustrated, phase 1 (130) includes a passive circuit 134 that couples a power stage 132 to the voltage converter output VOUT. The power stage 132 inputs switch control signals HS1 and LS1 for controlling switches therein. The switches within the power stage 132 typically require drivers (not shown for ease of illustration). The passive circuit 134 is coupled to a synchronous rectification (SR) switch stage 138, which serves to switchably couple the passive circuit 134 to ground. The SR switch stage 138 includes an SR switch (not shown), which also typically requires a driver (also not shown).
A control circuit 110 controls the switches of the power stage 132 and the SR switch stage 138 for each of the phases 130, 180, 190 of the voltage converter 100. A frequency and duty cycle generator 112 determines a switching frequency and duty cycle for the voltage converter 100 based upon the load requirements as sensed from the output voltage VOUT, and provides these parameters to a pulse-width modulation (PWM) generator 116. The PWM generator 116, in turn, generates switch control signals (e.g., HS1, LS1, SR1) for each of the phases of the voltage converter 100. The switching frequency of the voltage converter 100 is variable and changes as the load requirements change.
A phase current estimator 118 generates an estimate of current for each phase of the voltage converter 100. This estimate is based, in part, on a sensed (measured) current from each phase I1SENSE, I2SENSE, INSENSE. The phase current estimates generated by the phase current estimator 118 are provided to other circuits within the control circuit 110. Examples of circuits that may use the phase current estimates include a phase balancer 114 (for multi-phase voltage converters), a fault detector 113, and the frequency and duty cycle generator 112.
The control circuit 110 and its constituent parts may be implemented using a combination of analog hardware components (such as transistors, amplifiers, diodes, and resistors), and processor circuitry that includes primarily digital components. The processor circuitry may include one or more of a digital signal processor (DSP), a general-purpose processor, and an application-specific integrated circuit (ASIC). The control circuit 110 may also include memory, e.g., non-volatile memory such as flash, that includes instructions or data for use by the processor circuitry. The control circuit 110 inputs several sensor signals (e.g., VOUT, I1SENSE, I2SENSE, INSENSE) to estimate the power requirements for the load 120 and to otherwise aid in the generation of the switch control signals.
Techniques for determining the switching frequency and duty cycles based upon the load requirements of a voltage converter are, generally, well-known in the art. Likewise, techniques for fault detection and phase balancing are well-known. Such conventional techniques will not be further elaborated upon herein, in order to avoid obfuscating the unique aspects of the invention. Instead, the following description will focus on detailed techniques related to phase current estimation and, more particularly, phase current estimation within resonant and semi-resonant voltage converters. Before delving into these phase current estimation techniques, the voltage converter circuits to which they apply will first be described in order to better understand the waveforms of the phase currents that are being estimated.
FIG. 2 illustrates a circuit diagram 200 which shows phase 1 (130) of the voltage converter 100 illustrated in FIG. 1 in greater detail. In order to simplify the following description, only the single-phase voltage converter 200, as shown in FIG. 2, will be described henceforth. It is to be understood that the phase current estimation techniques are readily extended to a multi-phase voltage converter, such as that illustrated in FIG. 1. In order to support a multi-phase voltage converter, the phase current estimator 218 may be replicated for each of the phases in order to create a multi-phase current estimator 118, or may otherwise be extended, e.g., via time-slicing, to support multiple phases.
An input voltage VIN is provided to a power stage 232 at a high-side switch QHS is that is coupled to a low-side switch QLS at a switching node VSW. The low-side switch QLS is, in turn, connected to ground. Each of these switches QHS, QLS is controlled by a respective driver 232a, 232b as shown. The switching node VSW of the power stage 232 is coupled to a passive circuit 234, which provides an output current IPH_OUT and voltage VOUT to a load 120. The passive circuit 234 includes a resonant tank comprised of a capacitor CRES and an inductor LRES. The inductor LRES may merely be leakage inductance (e.g., the inherent parasitic inductance of the circuit wiring), or it may be an actual inductor component together with some leakage inductance.
The inductor LRES is coupled to a transformer/tapped inductor 236 having N1 primary-side windings 236a and N2 secondary-side windings 236b. The ratio N2/N1 determines the output/input voltage ratio of the transformer/tapped inductor 236 when it is conducting current. (Conversely, the ratio N1/N2 determines the output/input current ratio of the transformer/tapped inductor 236.) Because of the high peak current provided at the output of the transformer/tapped inductor 236 and in order to reduce the AC resistance, the transformer/tapped inductor 236 is often designed to have a single secondary-side winding 236b. Defining the total number of primary and secondary-side windings as n, the turns ratio is thus (n−1) to 1. Henceforth, the convention of n total windings and 1 secondary-side winding 236b will be used, but it should be understood that the equations and formulas that follow may instead be derived using N1 primary-side windings 236a and N2 secondary-side windings 236b. 
For the illustrated circuit 130, a magnetizing inductor LM is connected across the transformer/tapped inductor 236. An SR switch stage 238 is connected to the transformer/tapped inductor 236 and serves to couple its center tap to ground when the SR switch stage 238 is conducting. The SR switch stage 238 includes an SR switch QSR, and, typically, a driver 238a which is coupled to a control terminal (e.g., a gate) of the SR switch QSR.
The high-side, low-side, and SR switches QHS, QLS, QSR are shown in FIG. 2 as enhancement-mode metal-oxide semiconductor field-effect transistors (MOSFETs), but other switch devices may be used. For example, junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), or other types of power transistors may be preferred in some applications. The switches of the power stage 232 and of the SR switch stage 238 (e.g., QHS, QLS, QSR) may be integrated on the same semiconductor die, may each be provided on separate dies, or may otherwise be spread across a plurality of semiconductor dies. The drivers for the switches may be integrated on the same semiconductor die(s) as their corresponding switches, or may be provided on separate dies.
The control circuit 110 generates PWM signals HS, LS, and SR which are coupled to the drivers 232a, 232b, 238a that control the switches QHS, QLS, QSR. The control circuit 110 determines the frequency and duty cycles of the PWM signals HS, LS, SR so as to meet the power requirements of the load 120. In a semi-resonant voltage converter, such as that illustrated in FIG. 2, the high-side and low-side switches QHS, QLS of the power stage 232 are controlled such that these switches QHS, QLS do not conduct at the same time. A typical switching cycle of the voltage converter 200 begins with a “dead time” during which none of the switches QHS, QLS QSR are conducting. This is followed by a “TON” period during which the high-side switch QHS is conducting, but the low-side switch QLS and the SR switch QSR are not conducting. A “TOFF” period follows this, during which the high-side switch QHS is not conducting, but the low-side switch QLS and the SR switch QSR are conducting. Note that the terms “TON” and “TOFF,” as conventionally used in the context of resonant converters, refer, respectively, to the conducting and non-conducting periods of a high-side switch such as QHS. Hereinafter, the term “TSR_ON” will often be used instead of “TOFF,” as TSR_ON more clearly describes this period in the context of the current estimation techniques described below.
The phase current estimator 218 is illustrated as being a part of the control circuit 110, but it should be understood that, in some embodiments, the phase current estimator 218 may be implemented separately from the control circuit 110. The phase current estimator 218 is provided with a measured current from the phase circuit 130. As illustrated in FIG. 2, the current ISR through the SR switch QSR is measured (sensed). Other phase currents, such as IPH_OUT, could instead be measured (sensed), but the following explanation presumes that the current ISR is measured, and that the phase current estimator 218 is estimating the current ISR through the SR switch QSR.
FIG. 3 illustrates waveforms 300 for the output current IPH_OUT from the phase circuit 130, the voltage at the switch node VSW, and the resonant and magnetizing currents IRES, IM of the voltage converter 200 during a switch cycle. At the start of a dead time period DT0, the phase output current IPH_OUT and the magnetizing current IM are at a minimum value −IMIN. None of the power switches QHS, QLS, QSR are conducting during the dead time DT0, i.e., the control circuit 110 generates PWM signals HS=0, LS=0, SR=0. The current −IMIN charges the output capacitance of the low-side switch QLS and causes the switch node voltage VSW to rise to a level near VIN during the dead time DT0. At the end of the dead time DT0, the high-side power switch QHS is turned on, whereas the low-side switch QLS and the SR switch QSR remain off, e.g., by setting HS=1, LS=0, and SR=0 at the end of DT0. This state is maintained for an interval of time denoted “TON.” During TON, the switch node voltage VSW is tied to VIN through the high-side power switch QHS, and the phase output current IPH_OUT and the magnetizing current IM of the voltage converter phase 130 rise in a linear manner until the magnetizing current IM reaches a maximum value IMAX. The magnetizing current IM associated with the LC tank formed by the resonance capacitor CRES, the inductor LRES and the magnetizing inductor LM accounts for the rise in the phase output current IPH_OUT during TON. (With the SR switch QSR disabled, substantially no current flows through the primary-side windings 236a and the secondary-side winding(s) 236b of the transformer/tapped inductor 236 meaning that magnetizing current IM≈IRES.)
During the next interval of the switching cycle, denoted as “TOFF” or “TSR_ON,” the high-side switch QHS is turned off, while the low-side switch QLS and the SR switch QSR are turned on, e.g., by setting HS=0, LS=1, and SR=1. The switch node voltage VSW drops to and remains at zero during the TOFF (TSR_ON) interval, because the switch node VSW is coupled to ground though the low-side switch QLS. Also during the TOFF (TSR_ON) interval, a resonance is formed between the resonance capacitor CRES and inductor LRES, and results in a resonant current IRES. A portion of this current, i.e., IPRIM=IM−IRES, flows through into the primary-side winding 236a of the transformer/tapped inductor 236, and leads to a current ISEC=(N1/N2)*(IM−IRES)=(n−1)*(IM−IRES) flowing through the secondary-side winding 236b of the transformer/tapped inductor 236. The output current IPH_OUT of the phase 130 is, thus, the current IM flowing through the magnetizing inductor LM plus the current ISEC flowing through the secondary-side winding 236b, i.e., IPH_OUT=IM+(n−1)*(IM−IRES). As illustrated in FIG. 3, this current IPH_OUT initially rises during TOFF (TSR_ON), subsequently falls, and takes on the shape of the upper half cycle of a sinusoid.
The currents described above may be well-approximated using piecewise first and second order polynomials. In some embodiments, more accurate approximations may be made with higher-order polynomials, but at the expense of increased complexity, which requires more die area and higher power consumption for the phase current estimator 218. Because the additional accuracy is relatively insignificant, such higher-order polynomial approximations are not preferred, and the following examples are described using polynomials of order two or less.
As illustrated in FIG. 3, the magnetizing current IM may be approximated using:




  
    
      
        
          I
          M
        
        ≈
        
          {
          
            
              
                
                  -
                  
                    I
                    MIN
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  DT
                  ⁢
                  
                    
                  
                  ⁢
                  0
                
              
            
            
              
                
                  
                    
                      m
                      1
                    
                    ⁢
                    t
                  
                  -
                  
                    I
                    MIN
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    ON
                  
                
              
            
            
              
                
                  
                    
                      -
                      
                        m
                        2
                      
                    
                    ⁢
                    t
                  
                  +
                  
                    I
                    MAX
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    OFF
                  
                
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




The resonant current IRES is the same as the magnetizing current IM while the SR switch QSR is not conducting (i.e., during DT0 and TON), but, as illustrated in FIG. 3, has a different value during TOFF (TSR_ON), as approximated with:





  
    
      
        
          I
          RES
        
        ≈
        
          {
          
            
              
                
                  -
                  
                    I
                    MIN
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  DT
                  ⁢
                  
                    
                  
                  ⁢
                  0
                
              
            
            
              
                
                  
                    
                      m
                      1
                    
                    ⁢
                    t
                  
                  -
                  
                    I
                    MIN
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    ON
                  
                
              
            
            
              
                
                  
                    α
                    ⁢
                    
                      
                    
                    ⁢
                    
                      t
                      2
                    
                  
                  +
                  
                    β
                    ⁢
                    
                      
                    
                    ⁢
                    t
                  
                  +
                  
                    I
                    MAX
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    OFF
                  
                
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




As explained above, the output phase current may then be given by:





  
    
      
        
          I
          
            PH
            ⁢
            _
            ⁢
            OUT
          
        
        =
        
          {
          
            
              
                
                  
                    I
                    M
                  
                  =
                  
                    -
                    
                      I
                      MIN
                    
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  DT
                  ⁢
                  
                    
                  
                  ⁢
                  0
                
              
            
            
              
                
                  I
                  M
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    ON
                  
                
              
            
            
              
                
                  
                    I
                    M
                  
                  +
                  
                    
                      (
                      
                        n
                        -
                        1
                      
                      )
                    
                    ⁢
                    
                      (
                      
                        
                          I
                          M
                        
                        -
                        
                          I
                          RES
                        
                      
                      )
                    
                  
                
              
              
                
                  during
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    OFF
                  
                
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




No current flows through the SR switch QSR while it is disabled, i.e., during DT0 and TON. The current ISR through the SR switch QSR when it is enabled, i.e., during TOFF (TSR_ON) is given by:





  
    
      
        
          I
          SR
        
        =
        
          
            n
            ⁡
            
              (
              
                
                  I
                  M
                
                -
                
                  I
                  RES
                
              
              )
            
          
          ≈
          
            {
            
              
                
                  0
                
                
                  
                    during
                    ⁢
                    
                      
                    
                    ⁢
                    DT
                    ⁢
                    
                      
                    
                    ⁢
                    0
                  
                
              
              
                
                  0
                
                
                  
                    during
                    ⁢
                    
                      
                    
                    ⁢
                    
                      T
                      ON
                    
                  
                
              
              
                
                  
                    n
                    ⁡
                    
                      (
                      
                        
                          
                            -
                            
                              m
                              2
                            
                          
                          ⁢
                          t
                        
                        -
                        
                          α
                          ⁢
                          
                            
                          
                          ⁢
                          
                            t
                            2
                          
                        
                        -
                        
                          β
                          ⁢
                          
                            
                          
                          ⁢
                          t
                        
                      
                      )
                    
                  
                
                
                  
                    during
                    ⁢
                    
                      
                    
                    ⁢
                    
                      
                        T
                        OFF
                      
                      ⁡
                      
                        (
                        
                          T
                          
                            SR
                            ⁢
                            _
                            ⁢
                            ON
                          
                        
                        )
                      
                    
                  
                
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




FIG. 4 illustrates a waveform 400 corresponding to the SR switch current ISR. Note that this waveform takes on the shape of the upper half cycle of a sinusoid, and that it may be well approximated by a second-order polynomial such as that given in equation (4).
A current IRES flows (oscillates) through the resonant inductor LRES due to the switching of the high and low-side power switches QHS, QLS, buts the average current <IRES> is zero. The average output current <IPH_OUT> for the phase, also denoted as IO, is, thus, the same as the average current <ISR> through the SR switch QSR. During steady-state operation, this leads to the following equations for the average currents in the voltage converter 200:

<IRES>=0  (5)

IO=<IPH_OUT>=<ISR>=<n(IM−IRES)>=<nIm>  (6)





  
    
      
        
          〈
          
            I
            M
          
          〉
        
        =
        
          
            I
            O
          
          n
        
      
    
    
      
        (
        7
        )
      
    
  




Setting the average magnetizing current <IM> over an entire cycle period (i.e., DT0, TON, and TOFF) to





  
    I
    O
  
  n




in equation (1) and solving for IMIN yields:





  
    
      
        
          I
          MIN
        
        =
        
          
            -
            
              (
              
                
                  I
                  O
                
                n
              
              )
            
          
          +
          
            
              
                m
                1
              
              ⁢
              
                T
                ON
              
            
            2
          
        
      
    
    
      
        (
        8
        )
      
    
  




Substituting the approximation for IMIN given by equation (8) into the approximations for IRES given by equation (2) yields the following approximations for the coefficients α and β:

β=−αTOFF−m2  (9)





  
    
      
        α
        =
        
          
            6
            ⁢
            
              
            
            ⁢
            
              I
              O
            
            ⁢
            
              T
              SW
            
          
          
            nT
            OFF
            3
          
        
      
    
    
      
        (
        10
        )
      
    
  




Substituting the approximation for β given in equation (9) into the equation for the SR switch current ISR given in equation (4) yields the following simplified approximation for ISR:

ISR≅nα(TOFF−t)t during TOFF(TSR_ON)  (12)

The maximum SR switch current ISR,max occurs at the mid-point of each TOFF (TSR_ON) period, i.e., at t=(TSR_ON/2) from the beginning of such a period. This can be seen by taking the derivative with respect to time of the current ISR, as given in equation (12), setting this derivative





  
    d
    ⁡
    
      (
      
        I
        SR
      
      )
    
  
  dt




to zero, and solving for time t. This is also readily apparent from the waveform 400 of the current ISR as illustrated in FIG. 4. At time t=(TSR_ON/2), the SR switch current is given by:





  
    
      
        
          I
          SR
        
        ,
        
          max
          =
          
            n
            ⁢
            
              
            
            ⁢
            
              α
              ⁡
              
                (
                
                  
                    T
                    SR_ON
                    2
                  
                  4
                
                )
              
            
          
        
      
    
    
      
        (
        13
        )
      
    
  








  
    
      
        
          I
          SR
        
        ,
        
          max
          =
          
            
              n
              ⁡
              
                (
                
                  
                    6
                    ⁢
                    
                      
                    
                    ⁢
                    
                      I
                      O
                    
                    ⁢
                    
                      T
                      SW
                    
                  
                  
                    nT
                    
                      SR
                      ⁢
                      _
                      ⁢
                      ON
                    
                    3
                  
                
                )
              
            
            ⁢
            
              (
              
                
                  T
                  SR_ON
                  2
                
                4
              
              )
            
          
        
      
    
    
      
        (
        14
        )
      
    
  








  
    
      
        
          I
          SR
        
        ,
        
          max
          =
          
            (
            
              
                1.5
                ⁢
                
                  I
                  O
                
                ⁢
                
                  T
                  SW
                
              
              
                T
                
                  SR
                  ⁢
                  _
                  ⁢
                  ON
                
              
            
            )
          
        
      
    
    
      
        (
        15
        )
      
    
  




Using equation (13), note that a may be solved as a function of the maximum SR switch current:





  
    
      
        α
        =
        
          (
          
            
              
                4
                ⁢
                
                  
                
                ⁢
                
                  I
                  SR
                
              
              ,
              max
            
            
              nT
              SR_ON
              2
            
          
          )
        
      
    
    
      
        (
        16
        )
      
    
  




The above equations provide several approximations that may be used when modelling the SR switch current ISR using a 2nd order polynomial. Attention is now turned to describing a detailed implementation of the phase current estimator 218 based upon the models and approximations given in equations (1) to (16).
FIG. 5 illustrates, at a high-level, an embodiment of the phase current estimator 218 of FIG. 2. This estimator 218 is partitioned into an analog conversion circuit 540 and a digital estimation circuit 550. The analog conversion circuit 540 includes an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). (For ease of illustration, the ADC and DAC are not shown in FIG. 5.) While these components generally require high power, the ADC and DAC of the analog conversion circuit 540 consume relatively low power because they are running at a slow clock frequency f2. The digital estimation circuit 550 uses a higher clocking frequency f1, but it also consumes relatively low power because it only contains digital circuitry. The digital estimation circuit generates an estimate of the phase current IPH_EST which is updated at the higher clocking frequency f1. The estimated phase current IPH_EST is provided to external circuits, such as circuits within the control circuit 110 of the voltage converter 100 illustrated in FIG. 1, whereas a downsampled version of this current, denoted IPH_EST_F2, is fed back to the analog conversion circuit 540.
The analog conversion circuit 540 is provided with a measured (sensed) phase current IPH_SENSE, which it combines with the downsampled current estimate IPH_EST_F2 to arrive at a digital error signal error_d. The digital error signal error_d is updated at the slower clock frequency f2, and is provided to the digital estimation circuit 550 so that it may update (improve) its phase current estimation IPH_EST.
As previously mentioned, the phase current IPH_SENSE could be measured (and estimated) based on several different currents within a phase of a voltage converter, but the phase current must correspond to the output current, such as IPH_OUT shown in FIG. 2, for most uses that are required by the control circuit 110 of the voltage converter 100. The output phase current IPH_OUT, as illustrated in FIG. 2, could be directly measured and estimated by the phase current estimator 218. However, this is not preferred as the approximations for this current IPH_OUT, e.g., as given in equation (3), are somewhat complicated due to the three (3) piecewise waveforms that must be approximated. Instead, and as described in the following embodiment, measuring and estimating the current ISR through the SR switch QSR is preferred, as the only (non-zero) waveforms that must be approximated are during the TOFF (TSR_ON) time period. This current ISR provides the necessary input required for controlling a voltage converter such as the voltage converter 200 of FIG. 2, and this current ISR may be estimated reasonably efficiently using approximations such as those given by equation (4).
The current ISR may be measured by using the effective on-state resistance (Rdson) of the SR switch QSR and the voltage across the SR switch QSR, or by using a current mirror. The current measurement, for ISR or otherwise, may also be accomplished by using other standard means such as measuring the voltage across a sensing resistor, or by using direct current sensing (DCR) techniques.
FIG. 6 illustrates an embodiment of the phase current estimator 218 in greater detail. As in FIG. 5, the phase current estimator 218 is partitioned into an analog conversion circuit 540 and a digital conversion circuit 550. The digital conversion circuit 550 is principally comprised of a slope estimator 670, a slope adjuster 660, and a slope integrator 680.
The slope estimator 670 generates estimates mEST of the slope for the phase current ISR. These slope estimates mEST are updated at a rate of f1. The slope estimator 670 only provides slope estimates mEST while current ISR is flowing through the SR switch QSR. This is indicated in FIG. 6 by an enable signal ENSR_ON, which may correspond, e.g., to the PWM signal “SR” of the voltage converter 200 in FIG. 2. In addition to the slope estimates mEST, the slope estimator 670 may also provide a relatively infrequent estimate, denoted by IO_EST, of the current ISR, that is only updated once per switch cycle (TSW) of the voltage converter 200. As also shown in FIG. 6, the slope estimator 670 inputs an integrated error signal KINT*(err_int), which may be used to update and improve the slope estimate mEST as well as the switch cycle period TSW and the SR conducting period TSR_ON, which are also used in the generation of the slope estimate mEST. Further details regarding the slope estimator 670 are provided below in conjunction with the description of FIG. 7.
The slope estimate mEST is modified by a digital summing circuit 682 to yield an improved slope estimate mEST_IMP, which is input to a slope integrator 680. The slope integrator 680 integrates the improved slope estimate mEST_IMP to generate the phase current estimate IPH_OUT. The slope integrator 680 operates on digital samples mEST_IMP, which are provided/updated at a rate given by the frequency f1. A discrete/digital integration, as performed by the slope integrator 680, is the same as an accumulation of the samples mEST_IMP over time. Because the input samples mEST_IMP to the slope integrator 680 are updated at the frequency f1, the output current estimate IPH_OUT will also be updated at the frequency f1. The slope integrator 680 may be cleared/reset at the end of an SR switch period TSR_ON, as the phase current estimate IPH_EST is typically expected to be zero when the SR switch QSR is not conducting and any residual accumulation at the end of an SR switch period TSR_ON should not be carried forward to the beginning of the next SR switch period TSR_ON.
The analog conversion circuit 540 includes a digital-to-analog converter (DAC) 642 and an analog-to-digital converter (ADC) 644, both of which provide conversions at a frequency of f2. Before it can be used by the DAC 642, the phase current estimate IPH_EST must be downsampled from the frequency f1 of the digital estimation circuit 550 to the frequency f2 of the analog conversion circuit 540. This is performed by a downsampler 684 which is shown within the digital estimation circuit 550, but which could also be located elsewhere, including within the analog conversion circuit 540. The downsampled phase current estimate, denoted as IPH_EST_F2, is converted into an analog signal IPH_EST_F2_ANALOG by the DAC 642. An analog measured (sensed) phase current IPH_SENSE is input to an analog summation circuit 646, which subtracts the analog phase current estimate signal IPH_EST_F2_ANALOG from the sensed current IPH_SENSE to yield an analog error signal IERR_ANALOG. The analog error signal IERR_ANALOG is digitized by the ADC 644 to generate a digital error signal error_d, which is provided back to the digital estimation circuit 550. Because the ADC 644 is providing conversions at the frequency f2, the digital error signal error_d is updated at a rate corresponding to the frequency f2.
The digital error signal error_d is provided to a slope adjuster 660, which provides modified versions of this error signal to the slope estimator 670 and to the digital summing circuit 682. An error integrator 664 inputs the digital error signal error_d and integrates (accumulates) it in order to generate an integrated error err_int. The integrated error err_int is then scaled by a gain block 666 and provided to the slope estimator 670, which uses the integrated error KINT*err_int to update/improve its slope estimation, as will be explained more fully in the description of FIG. 7. The error integrator 664 will typically be reset by a signal RSTERR_INT at the beginning of each conducting period TSR_ON for the SR switch QSR, so as to clear out any noise that has erroneously accumulated during the off period of the SR switch QSR or any integrated error left over from a prior switching cycle. The error integrator 664 may be reset to zero or to a non-zero initial value such as some portion of the final value left in the integrator at the end of the prior SR conducting period TSR_ON, e.g., it could be set to 25% or 50% of its prior final value. The reset signal RSTERR_INT typically corresponds to, and may be the same as, the PWM signal “SR” shown in FIG. 2.
In addition to updating the slope estimator 670, the outputs of the slope adjuster 660 are provided to the digital summation circuit 682 in order to provide a more direct error correction. The integrated error err_int is scaled by KINT and added to the slope estimate mEST to improve this estimate. The integration of the error signal error_d serves to filter (smooth) the signal and prevent any large changes due to noise or other systematic anomalies which should not be tracked. However, this smoothing comes at the expense of slower tracking of the estimated phase current IPH_EST to the actual sensed current IPH_SENSE. Another version of the digital error signal error_d is not integrated, but is merely scaled by KP within a gain block 662 to yield a proportional error term that can more quickly correct/improve the slope estimate mEST. The improved slope estimate output by the digital summation circuit 682 is thus given by mEST_IMP=mEST+KP*error_d+KINT*err_int. The gain terms KP and KINT determine the speed and noise suppression of the tracking loop. A relatively high value of KP leads to faster tracking, but introduces the possibility of undesirably tracking noise. Conversely, a relatively high value for KINT should suppress noise or other transients, but at the expense of slower tracking of the phase current IPH_SENSE. Note that the slope estimate mEST provided by the slope estimator 670 is updated at the (fast) f1 frequency, whereas the other terms contributing to mEST_IMP are only updated at the (slow) f2 frequency.
FIG. 7 illustrates the slope estimator 670 in further detail. The slope estimator 670 is based upon a model of the current ISR through the SR switch QSR as given by equation (12), which is replicated below (with the notation TSR_ON used rather than TOFF) along with its time derivative:

ISR=nα(TSR_ON−t)t, for 0<t<TSR_ON  (17)





  
    
      
        
          
            
              
                
                  
                    d
                    ⁢
                    
                      
                    
                    ⁢
                    
                      I
                      SR
                    
                  
                  dt
                
                =
                
                  n
                  ⁢
                  
                    
                  
                  ⁢
                  
                    α
                    ⁡
                    
                      (
                      
                        
                          T
                          SR_ON
                        
                        -
                        
                          2
                          ⁢
                          t
                        
                      
                      )
                    
                  
                
              
              ,
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              t
              <
              
                T
                SR_ON
              
            
          
        
      
    
    
      
        (
        18
        )
      
    
  




The slope of the SR switch current ISR may be determined from its time derivative and, thus, equation (18) may be used to estimate the current slope mEST during the on period TSR_ON of the SR switch QSR. For simplification in the low-level implementation, the term (TSR_ON−2t) will be converted into an alternate form. For the time range given by 0<t<TSR_ON, the term tshift=(TSR_ON−2t) varies from +TSR_ON to −TSR_ON. Substituting tshift for (TSR_ON−2t) in equation (18) thus leads to:





  
    
      
        
          
            
              
                
                  
                    d
                    ⁢
                    
                      
                    
                    ⁢
                    
                      I
                      SR
                    
                  
                  dt
                
                =
                
                  n
                  ⁢
                  
                    
                  
                  ⁢
                  
                    α
                    ⁡
                    
                      (
                      
                        t
                        shift
                      
                      )
                    
                  
                
              
              ,
            
          
          
            
              
                for
                ⁢
                
                  
                
                +
                
                  T
                  SR_ON
                
              
              <
              
                t
                shift
              
              <
              
                -
                
                  T
                  SR_ON
                
              
            
          
        
      
    
    
      
        (
        19
        )
      
    
  




The slope estimator 670 only produces slope estimates mEST at discrete points in time given by





  
    k
    =
    
      
      
        
          t
          shift
        
        
          T
          CLK
        
      
      
    
  
  ,




where TCLK is related to the sample frequency f1 as TCLK=1/f1. This leads to the digital (discrete) form of equation (19) given by:

mEST(k)=nα(k*TCLK), for k=+NSR_ON to −NSR_ON,  (20)

where NSR_ON=TSR_ON/TCLK, and k is an integer.
Substituting the approximation for a that was derived in equation (16) yields:




  
    
      
        
          
            
              m
              EST
            
            ⁡
            
              (
              k
              )
            
          
          =
          
            
              
                n
                ⁡
                
                  (
                  
                    
                      
                        4
                        ⁢
                        
                          
                        
                        ⁢
                        
                          I
                          SR
                        
                      
                      ,
                      max
                    
                    
                      nT
                      SR_ON
                      2
                    
                  
                  )
                
              
              ⁢
              
                (
                
                  k
                  *
                  
                    T
                    CLK
                  
                
                )
              
            
            =
            
              
                k
                ⁡
                
                  (
                  
                    
                      4
                      ⁢
                      
                        
                      
                      ⁢
                      
                        T
                        CLK
                      
                    
                    
                      T
                      SR_ON
                      2
                    
                  
                  )
                
              
              ⁢
              
                I
                SR
              
            
          
        
        ,
        
          max
          =
          
            k
            ⁢
            
              
            
            ⁢
            γ
          
        
        ,
      
    
    
      
        (
        21
        )
      
    
  




where




  
    
      
        
          γ
          =
          
            
              (
              
                
                  4
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    CLK
                  
                
                
                  T
                  SR_ON
                  2
                
              
              )
            
            ⁢
            
              I
              SR
            
          
        
        ,
        max
        ,
      
    
    
      
        (
        22
        )
      
    
  




and k varies from +NSR_ON to −NSR_ON.
The slope estimator 670 includes a down counter 771 which generates the count k during the conducting period TSR_ON of the SR switch QSR. The down counter 771 is reset to an initial value at the beginning of each SR conducting period TSR_ON, as may be indicated by the rising edge of the PWM signal “SR” that is generated by the control circuit 110 shown in FIG. 2 and as may be provided by a reset signal RSTcount. The initial value is set to NSR_ON=∥TSR_ON/TCLK)∥, where TSR_ON corresponds to the conducting period TSR_ON of the SR switch QSR for the current switch cycle, and may be provided by the control circuit 110. The count k is decremented at a frequency given by f1, i.e., k is reduced by one after each clock period TCLK.
The count k generated by the down converter 771 is provided to a gain block 772 wherein the count k is multiplied by a slope gain γ to produce the slope estimate mEST. As shown in equation (22) above, the slope gain γ is initialized to a value based upon TSR_ON and ISR,max, each of which are, at least typically, updated once per switch cycle. As will be explained later, the slope gain γ may be updated within a switch cycle to improve the slope estimate mEST.
Note that several alternatives to the above-described circuit based upon the down counter 771 are possible, and may be preferred in some embodiments. For example, a standard (up) counter may be used, in which case equation (18) may be used more directly. The initial value for such an up counter would be different (e.g., zero), a subtraction such as in equation (18) would need to be performed, and a different gain term may need to be derived.
The maximum current ISR,max through the SR switch QSR occurs midway through the conducting period, i.e., at TSR_ON/2. The maximum current ISR,max is stored by a latch 776, which updates this current ISR,max by capturing the phase current estimate IPH_EST at TSR_ON/2. The count value k, which is generated by the down counter 771, is used for determining when to latch the current estimate IPH_EST. For the count sequence shown in FIG. 7 and described above, the phase current estimate IPH_EST would be latched at k=0 to capture the maximum current ISR,max.
In addition to its usage in determining the slope gain γ, as described above, the maximum current ISR,max is also used to generate an estimate IO_EST of the average output current, i.e., the current IO shown in equation (6). This average output current estimate IO_EST may be used by the control circuit 110 for purposes that only require infrequent estimates of the phase current ISR, and for which the half-sinusoidally shaped SR current estimate IPH_EST is inappropriate. As with the maximum current ISR,max, the average output current estimate IO_EST is only updated once per switching cycle. The average output current estimate IO_EST is generated by the gain block 777 by multiplying the latched maximum current ISR,max, by a gain term λ. The gain term λ may be derived from equation (15) as follows:




  
    
      
        
          
            I
            O
          
          =
          
            
              (
              
                
                  
                    I
                    SR
                  
                  ,
                  
                    max
                    ⁢
                    
                      
                    
                    ⁢
                    
                      T
                      SR_ON
                    
                  
                
                
                  1.5
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    SW
                  
                
              
              )
            
            =
            
              λ
              ⁢
              
                
              
              ⁢
              
                I
                SR
              
            
          
        
        ,
        max
        ,
      
    
    
      
        (
        23
        )
      
    
  








  
    
      
        λ
        =
        
          
            (
            
              
                T
                SR_ON
              
              
                1.5
                ⁢
                
                  
                
                ⁢
                
                  T
                  SW
                
              
            
            )
          
          .
        
      
    
    
      
        (
        24
        )
      
    
  




As described previously, the initial slope gain γ is based upon TSR_ON and ISR,max, each of which are only updated once per switching cycle. In order to better track the phase current within a conducting period TSR_ON of the SR switch QSR, the initial slope gain γ is modified by taking into account an error signal that is input to the slope estimator 670. Preferably, the scaled and integrated error signal KINT*(err_int) generated by the slope adjuster 660 is input to a loop-up table 775, which generates a correction scaling for the slope gain γ. This correction scaling is then provided to a multiplier 774, which feeds the slope gain γ to the slope gain block 772.
For the case where the slope estimate mEST is perfect and the phase current estimate IPH_EST is perfectly tracking the measured phase current IPH_SENSE, there is no error and the scaled and integrated error signal KINT*(err_int) provided to the look up table 775 would be zero. The look up table 775 would provide a value of 1.0 to the multiplier 774, such that the multiplier output would provide a slope gain γ equivalent to the initial value of the slope gain γ as given by equation (22). If the scaled and integrated error signal KINT*(err_int) is sufficiently positive, indicating that the measured phase current IPH_SENSE is greater than the phase current estimate IPH_EST, then the estimated slope mEST is too small. For this case, the look up table 775 would provide a correction scaling greater than 1.0 that would be used by the multiplier 774 to increase the slope gain γ. This, in turn, would lead to an increased estimated slope mEST, an increased phase current estimate IPH_EST, and reduced error signals error_d, err_int. Conversely, if the scaled and integrated error signal KINT*(err_int) is sufficiently negative, this indicates that the measured phase current IPH_SENSE is smaller than the phase current estimate IPH_EST. For this case, the look up table 775 would provide a scaling less than 1.0 that would subsequently reduce the estimated slope mEST and lead to a more accurate phase current estimate IPH_EST.
The correction provided by the look up table 775 could be performed in alternate ways, e.g., the correction could be provided by a function that depends upon an integrated error or some other variation of the error. The look up table 775 could use hard-coded values that are put in place when the slope estimator 670 is produced, could include values that are adaptively updated during normal operation, or could be loaded with values produced during a calibration phase of the slope estimator 670.
As described above, the slope estimator 670 uses the switch cycle period TSW and the SR conducting period TSR_ON in its generation of the slope estimate mEST, e.g., to determine the count initialization NSR_ON, the slope gain γ, and the gain term λ. These periods TSW, TSR_ON may be provided directly from some other portion of the control circuit 110, e.g., the frequency and duty cycle generator 112, or they may be determined by the phase current estimator 218 based upon other input signals (not shown in FIG. 6 or 7 for ease of illustration). For example, one or more of the PWM signals HS, SR shown in FIG. 2 could be used by the phase current estimator 218 to determine the periods TSW, TSR_ON. Whether the periods TSW, TSR_ON are provided to or determined by the phase current estimator 218, there is typically a lag of one switch cycle in updating these periods TSW, TSR_ON. In other words, the values used by the phase current estimator 218 for the periods TSW, TSR_ON for a given switching cycle are typically based upon the periods TSW, TSR_ON generated by the PWM generator 116 in the previous switching cycle.
FIG. 8 illustrates an embodiment of a method 800 for estimating phase current in a resonant voltage converter such as those shown in FIGS. 1 and 2. The method 800 of FIG. 8 may be implemented within the control circuit 110 of the voltage converter 100 or 200.
The method begins with the enabling 810 of an SR switch within a voltage converter, such that the SR switch conducts current. The SR switch is left enabled for a time period TSR_ON. A counter and clock may be used to count down the time period TSR_ON. A model of current ISR through the SR switch is generated and updated 822. This updating is performed at a fast frequency of f1. Next, an SR current estimate IPH_EST is generated 824 using the model and an error signal. The estimated SR current estimate IPH_EST is converted 832 into an analog estimate IPH_EST_F2_ANALOG at a slow frequency f2. The measured SR switch current ISENSE is input 834. The analog estimate IPH_EST_F2_ANALOG is combined with the measured SR switch current ISENSE, e.g., by subtracting, to generate 836 an analog current error. This analog current error is then converted 838 (digitized) to form the error signal that was used in the generation 824 of the SR current estimate IPH_EST. Once the above sequence is complete, a check 840 is made to determine if the SR conducting period TSR_ON has ended. This may be done, for example, by comparing a counter that was reset when the SR switch was enabled 810 against a threshold corresponding to the SR conducting period TSR_ON. If the SR conducting period TSR_ON is not over, then operation continues with the generation and update 822 of the SR current model. If the SR conducting period TSR_ON is completed, then the loop is exited and the SR switch is be disabled 850.
Note that the steps within the dotted box 820 are performed at the (fast) frequency f1, whereas the steps within dotted box 830 are performed at the slower frequency f2. Accordingly, the steps 820 may be performed multiple times, and the current estimate IPH_EST updated multiple times, for each iteration of the steps in box 830.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

## Claims

1. A voltage converter that uses a variable switching frequency, the voltage converter comprising:
a first phase that comprises a synchronous rectification (SR) switch through which an SR current having a half-cycle sinusoidal-like shape is conducted when the SR switch is active;
a PWM generator operable to control cycle-by-cycle switching of the SR switch by providing a pulse width modulation (PWM) control signal to the SR switch, the frequency of the PWM control signal being based upon a first estimate of the SR current; and
a current estimator comprising:
a digital estimation circuit configured to generate the first estimate of the SR current using a model of current through the SR switch and an error signal, and configured to update the first estimate of the SR current at a first frequency; and
an analog conversion circuit configured to input a measured current corresponding to the SR current, to provide conversions at a second frequency, and to generate the error signal.

2. The voltage converter of claim 1, wherein the first phase further comprises:
a power stage including a high-side switch and a low-side switch coupled to the high-side switch at a switching node of the power stage; and
a passive circuit including a transformer/tapped-inductor, the passive circuit coupling the switching node to an output node of the voltage converter, and that is coupled to ground through the SR switch when the SR switch is conducting,
wherein the PWM generator is further operable to control cycle-by-cycle switching of the high-side switch and the low-side switch by providing PWM control signals to each of the high-side and low-side switches.

3. The voltage converter of claim 1, further comprising additional phases, each of which comprises an additional SR switch through which an additional SR current having a half-cycle sinusoidal-like shape is conducted when the additional SR switch is active.

4. The voltage converter of claim 1, wherein the first frequency is greater than the second frequency.

5. The voltage converter of claim 1, wherein the digital estimation circuit is configured to model the SR current based upon a polynomial of order two or higher.

6. The voltage converter of claim 5, wherein the polynomial is a second-order polynomial given by:


ISR_EST=nα(TSR_ON−t)t 

wherein n is related to the turns ratio of a transformer/tapped-inductor to which the SR switch is coupled,
TSR_ON is a period of time within a cycle of the voltage converter during which the SR switch is conducting,
t is a time from the beginning of the period during which the SR switch is conducting, and
α is based upon a switch period TSW of the cycle of the voltage converter, and the period of time TSR_ON that the SR switch is conducting.

7. The voltage converter of claim 1, wherein the analog conversion circuit comprises:
a digital-to-analog converter configured to input the first estimate of the SR current and to convert this first estimate into an analog SR current estimate at a rate corresponding to the second frequency;
a current summation circuit configured to generate an analog error by summing the analog SR current estimate and the measured current; and
an analog-to-digital converter configured to convert the analog error into the error signal at a rate corresponding to the second frequency.

8. The voltage converter of claim 1, wherein the digital estimation circuit further comprises:
a slope estimator configured to generate a first estimate of the slope of the SR current, the estimated slope being updated at the first frequency.

9. The voltage converter of claim 1, wherein the digital estimation circuit further comprises:
an error integrator configured to integrate and scale the error signal to produce an integrated error, wherein the integrated error is updated at a rate corresponding to the second frequency.

10. The voltage converter of claim 9, wherein the digital estimation circuit further comprises:
a digital summation circuit configured to generate an improved slope estimate by summing the integrated error, the error signal or a scaled version of the error signal, and a first estimate of the slope of the SR current; and
a slope integrator configured to integrate the improved slope estimate.

11. The voltage converter of claim 9, further comprising:
a slope estimator configured to generate a first estimate of the slope of the SR current based upon the integrated error and a look-up table.

12. The voltage converter of claim 9, wherein the digital estimation circuit is further configured to generate a second SR current estimate based upon the first SR current estimate, by latching the first SR current estimate at a time given by t=TSR_ON/2, wherein the time t starts at zero when the SR switch is turned on during a switching cycle, and TSR_ON is a period of time during which the SR switch is conducting before it is turned off during the switching cycle, the second SR current estimate being updated once in each switching cycle.

13. A method for current estimation in a variable-frequency voltage converter, the variable-frequency voltage converter including a synchronous rectification (SR) switch through which an SR current having a half-cycle sinusoidal-like shape is conducted when the SR switch is active, the method comprising, for each switching cycle of the variable-frequency voltage converter:
enabling the SR switch such that it conducts the SR current for an SR conducting period, the SR conducting period being a portion of a switching period for a current switching cycle;
generating a modelled SR current, the modelled SR current being based upon a model of the SR current during the SR conducting period and being updated at a first frequency;
generating a first SR current estimate using the modelled SR current and an error signal;
converting the first SR current estimate to an analog SR current estimate such that the analog SR current estimate is updated at a second frequency;
inputting a measured SR current and generating an analog SR current error by generating a difference between the measured SR current and the analog SR current estimate; and
converting the analog SR current error into the error signal, such that the error signal is updated at the second frequency.

14. The method of claim 13, wherein the first frequency is greater than the second frequency.

15. The method of claim 13, wherein the model of the SR current is based upon a polynomial of order two or higher.

16. The method of claim 13, wherein the polynomial is a second-order polynomial given by:


ISR_EST=nα(TSR_ON−t)t 

wherein n is related to the turns ratio of a transformer/tapped-inductor to which the SR switch is coupled,
TSR_ON is the SR conducting period,
t is a time from the beginning of the SR conducting period for the current switching cycle, and
α is based upon the switching period TSW for the current switching cycle and the SR conducting period TSR_ON.

17. The method of claim 13, further comprising:
generating an estimate of a slope of the SR current, the slope estimate being updated at the first frequency.

18. The method of claim 13, further comprising:
generating an integrated error by integrating and scaling the error signal, such that the integrated error is updated at a rate corresponding to the second frequency, and
wherein the generation of the first SR current estimate is further based upon the integrated error.

19. The method of claim 18, further comprising:
generating an estimate of a slope of the SR current;
summing the integrated error, the error signal or a scaled version of the error signal, and the estimate of the slope of the SR current to generate an improved slope estimate;
integrating the improved slope estimate to generate an integrated slope; and
updating the estimate of the slope of the SR current based upon the integrated slope.

20. The method of claim 18, further comprising:
generating an estimate of a slope of the SR current based upon the integrated error and a look-up table.

21. The method of claim 13, further comprising:
generating a second SR current estimate based upon the first SR current estimate, by latching the first SR current estimate at a time given by t=TSR_ON/2, TSR_ON being the SR conducting period for a given switching cycle, the time t starting at zero at the beginning of the SR conducting period, the second SR current estimate being updated once in each switching cycle.