# Patent

## Title
Power factor correction device and correcting method thereof

## Abstract

A power factor correction device comprises a power stage circuit converting input alternating current voltage into input current according to a pulse width modulation signal and outputs the input current to a load generating output voltage on the load, and sampling the input current outputting a correcting current; a current compensating circuit receiving and comparing the correcting current with a reference current signal generating a compensating current signal; a voltage compensating circuit receiving and comparing the output voltage with a reference voltage generating a compensating voltage signal; a multiplication amplifier receiving the compensating current signal and the compensating voltage signal generating an updated reference current signal by multiplying the compensating current signal with the compensating voltage signal; and a pulse width modulation converter receiving the compensating current signal and the compensating voltage signal generating the pulse width modulation signal to synchronize phase of alternating current voltage and input current.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation application of a pending US patent application entitled “POWER FACTOR CORRECTION DEVICE AND CORRECTING METHOD THEREOF” application Ser. No. 13/408,077, filing date: Feb. 29, 2012, inventor Chung-Ping Ku. The above contents are incorporated herein by reference for any and all purposes.


FIELD OF THE INVENTION
The invention relates to power factor correction (PFC) devices, in particular to a power factor correction device for PFC Boost converters.
BACKGROUND OF THE INVENTION
Nowadays, high-quality power supplies with increasing energy efficiency are in high demand. Power factor correction technique plays an important role in improving the electric power supply efficiency of electric appliances, which are usually inductive loads that cause the current and voltage out of phase leading to low energy efficiency. A power factor corrector synchronizes the phases of the input voltage and the input current of an electric appliance, namely, the load of the electric appliance is adapted similar to a resistance-type load, thus harmonic distortion of the input current is effectively reduced resulting in high power factor of power supply.
A common power factor correction device requires a pulse width modulation (PWM) signal generator to provide a pulse width modulation (PWM) signal and a sample of an input voltage as a reference signal for correcting the current. In the conventional technologies, for example, the pulse width modulation signal generator disclosed by U.S. Pat. No. 5,886,586 does not require the input voltage sample but uses an integrator to perform one-cycle (i.e., feed-forward) control method to decide charge-discharge time and electric potential of an integrated capacitor. Other US patents, such as U.S. Pat. Nos. 7,068,016 and 5,804,950, also disclose similar technologies. However, the above patents using the integrator or the integrated capacitor in or out of a circuit, as such the response speed of the internal circuit is greatly reduced during the operation. In addition, the circuit is internally provided with a switch for discharging the integrated capacitor; therefore, power consumption is increased and the circuit space is enlarged.
Hence, the invention provides a power factor correction device and a correcting method thereof to solve the above problems.
SUMMARY OF THE INVENTION
The present invention provides a power factor correction device and a correcting method. The current compensating circuit and the voltage compensating circuit are connected to a multiplier to multiply the compensating voltage signal by the compensating current signal to generate an updated reference current signal. The updated reference current signal is provided to the current compensating circuit to perform power factor correction. The device and method of the present invention can avoid the use of the integrated capacitor, therefore the response speed of the internal circuit is greatly increased during operation, thus power factor correcting efficiency is improved.
To achieve the above purpose, the present invention provides a power factor correction device, which comprises a power stage circuit. The power stage circuit, which is connected to a load, receives an input alternating current (AC) voltage and a pulse width modulation signal. The input alternating current voltage is converted into an input current in accordance with the pulse width modulation signal via the inductor, the power diode and the power transistor, which are driven by the pulse width modulation signal. The input current is output to the load, which produces an output voltage on the load. The power stage circuit samples the input current through the sample resistor as a correcting current. The power stage circuit is connected to the current compensating circuit that receives error between the correcting current and the reference current signal, thus a compensating current signal is generated through the current error amplifier and the current compensator. The power stage circuit is also connected to the voltage compensating circuit and the error between the output voltage and a reference voltage is received by the voltage divider, thus, a compensating voltage signal is generated by the voltage error amplifier and the voltage compensator. The outputs of the current compensating circuit and the voltage compensating circuit are connected with a multiplication amplifier that receives the compensating current signal and the compensating voltage signal, thus an updated reference current signal is generated after multiplying the compensating current signal by the compensating voltage signal. The current compensating circuit and the voltage compensating circuit are connected to a pulse width modulation converter that receives the compensating current signal and the compensating voltage signal to generate the updated pulse width modulation signal and to obtain the same phases of the alternating current voltage and the input current.
The present invention also provides a power factor correcting method. First the correcting current and output voltage is compared to a reference current signal and a reference voltage respectively generating a compensating current signal and a compensating voltage signal through the current compensating circuit and the voltage compensating circuit, as such an updated pulse width modulation signal is generated and same phases of the alternating voltage and the input current are obtained. An updated reference current signal is obtained by multiplying the compensating current signal with the compensating voltage signal through the multiplication amplifier. Finally, the updated pulse width modulation signal is generated from the compensating current signal and the compensating voltage signal and the same phases of the alternating current voltage and the input current are achieved.



BRIEF DESCRIPTION OF THE DRAWINGS
As shown in attached drawing, the embodiment of the invention is more sufficiently described. However, the attached drawing is only used for explanation and illustration rather than limitation to the scope of the invention.
FIG. 1 is a circuit schematic diagram of the power correction device of the present invention.
FIG. 2 is a block diagram for the transfer function of the power correction device of the present invention.
FIG. 3 is a flow diagram of the correcting method of the present invention.
FIG. 4 is a waveform diagram of all received and generated signals in power correction device of the present invention.
FIG. 5 is an amplified waveform diagram of the reference current signal, the compensating current signal and the compensating voltage signal of FIG. 4.
FIG. 6 is a waveform diagram of the ramp signal, the compensating current signal and the pulse width modulation signal.
FIG. 7 is a waveform diagram of the 220V alternating current voltage and its input current achieved by the power correction device of the present invention.
FIG. 8 is a waveform diagram of the 110V alternating current voltage and its input current achieved by power correction device of the present invention.



DETAILED DESCRIPTION OF THE EMBODIMENTS
As shown in FIG. 1, the power factor correction device of the invention includes a power stage circuit 12 connected to a load 10. The power stage circuit 12 receives an alternating-current (AC) voltage VAC and a pulse width modulation signal VPWM, then, the alternating-current (AC) voltage VAC is converted into an input current IAC in accordance with the pulse width modulation signal VPWM. The input current IAC is fed to the load 10 to generate an output voltage Vo on the load 10. The input current IAC is also sampled as a correcting current Isen. The power stage circuit 12 is connected to a current compensating circuit 14 and a voltage compensating circuit 16. The current compensating circuit 14 receives and compares the correcting current Isen with a reference current signal Iref to generate a compensating current signal IEA. The voltage compensating circuit 16 receives and compares the output voltage Vo with a reference voltage Vref to generate a compensating voltage signal VEA. Both of the current compensating circuit 14 and the voltage compensating circuit 16 are connected to a multiplication amplified 8 and a pulse width modulation converter 20. The multiplication amplifier 18 receives and multiplies the compensating current signal IEA with the compensating voltage signal VEA to generate an updated reference current signal Iref. The pulse width modulation converter 20 receives the compensating current signal IEA and the compensating voltage signal VEA to generate an updated pulse width modulation signal VPWM, thus same phases of the alternating current voltage VAC and the input current IAC is obtained.
The power stage circuit 12 includes a sample resistor 22 and an alternating-current/direct-current (AC/DC) converter 24. The AC/DC converter 24 includes an inductor 241, a power transistor 243, and a power diode 245. The sample resistor 22 is connected to the current compensating circuit 14. The AC/DC converter 24 is connected to the load 10, the sample resistor 22, the current compensating circuit 14 and the voltage compensating circuit 16. The AC/DC converter 24 receives AC voltage VAC and pulse width modulation signal VPWM, then the AC voltage VAC is converted into input current IAC in accordance with the pulse width modulation signal VPWM by inductor 241, power transistor 243, and power diode 245, thus the input current IAC is fed to the load to generate the output voltage Vo. Furthermore, the input current IAC is sampled by the sample resistor 22 to generate the correcting current Isen.
The current compensating circuit 14 includes a current error amplifier 26 and a current compensator 28. The current error amplifier 26 connected to the sample resistor 22 of the power stage circuit 12 receives and compares the correcting current Isen and a reference current signal Iref, thus generating a comparing current. The current compensator 28 connected to the current error amplifier 26 receives and compensates the comparing current to generate the compensating current signal IEA. The voltage compensating circuit 16 comprises a voltage divider 30 that is connected to the AC/DC converter 24 of the power stage circuit 12, receives and divides the output voltage Vo to generate a feedback voltage VFB. The voltage divider 30 is connected to a voltage error amplifier 32 that receives and compares the feedback voltage VFB with a reference voltage Vref to generate a comparing voltage. The voltage error amplifier 32 is connected to a voltage compensator 34 that receives and compensates the comparing voltage thus generates a compensating voltage signal VEA.
The multiplication amplifier 18 includes a multiplier 36 and a current gain regulator 38. The multiplier 36 is connected to the current compensator 28 of the current compensating circuit 14 and the voltage compensator 34 of the voltage compensating circuit 16 and receives the compensating current signal IEA and the compensating voltage signal VEA to generate a compensating feedback current by multiplying the compensating current signal IEA by the compensating voltage signal VEA. The multiplier 36 is also connected to the current gain regulator 38 that receives the compensating feedback current and generates an updated reference current signal Iref by multiplying the compensating feedback current by a current gain Km.
The pulse width modulation converter 20 includes a ramp generator 40 that is connected to the voltage error amplifier 32 of voltage compensating circuit 16 and receives the compensating voltage signal VEA to generate a ramp signal VRAMP. Ramp generator 40 and current error amplifier 26 of the current compensating circuit 14 are connected to a conversion comparator 42 that receives and compares ramp signal VRAMP with compensating current signal IEA to generate an updated pulse width modulation signal VPWM that is fed into the AC/DC converter 24 of the power stage circuit 12. When the voltage value of the ramp signal VRAMP is higher than the corresponding voltage value of the compensating current signal IEA, the updated pulse width modulation signal VRAMP is a high level voltage. Otherwise, when the voltage value of the ramp signal VRAMP is lower than the corresponding voltage value of the compensating current signal IEA the updated pulse width modulation signal VPWM is a low level voltage.
In order to obtain same phases of the input alternating current voltage and the input current, the sample resistance, the pulse width modulation signal VPWM, the input current IAC, the alternating current voltage VAC, the output voltage Vo and the ramp signal VRAMP have to be satisfied the following conditions:

RS·iin(θ)=dOFF(θ)·TS.W.·SV  (1)

dOFF(θ)=Vin_pk·sin(θ)/Vo=1−d(θ)  (2)

iin(θ)=Vin_pk·sin(θ)/Rin(ac)  (3)

where:

    
    
        iin(θ) is the input current IAC,
        Vin _pk·sin(θ) is the alternating current voltage VAC,
        SV is slope of the ramp signal VRAMP,
        Rin(ac) is equivalent input alternating current resistance,
        TS.W. and d(θ) are cycle and duty cycle of the pulse width modulation signal VPWM respectively.

Formulas (4) and (5) can be obtained from formulas (1), (2) and (3) as follows:

    
    






  
    
      
        
          
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From formula (5), Rin(ac) is a constant, therefore, the phases of the alternating current voltage and the input current are the same.

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Where:

Kmulti is multiplication gain of the multiplier 36,
gmv is the gain of the voltage error amplifier 32,
Cs is a capacitance value of the interior capacitor of the ramp generator 40,
IEAmax is the largest current value of the compensating current signal IEA, and
VACmin is the smallest value of the alternating current voltage.
An updated reference current signal Iref is obtained by multiplying the compensating current signal IEA by the compensating voltage signal VEA, as follows:




  
    
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Where:

KV is a voltage division proportion of the voltage divider 30, and
Zcomp is impedance of the current compensator 28.
In this invention, a sample of the input voltage is not required and the compensating current signal IEA and the compensating voltage signal VEA are used to acquire an updated reference current signal Iref to achieve the correction of the power factor. The method of the invention can avoid the use of an integrated capacitor, as such the response speed of the internal circuit is greatly increased during operation to improve the power correction efficiency.
FIG. 2 and FIG. 3 describe a correcting method of the invention. As shown in FIG. 2, Gv(s) is a transfer function of the voltage compensator 34, Gi(s) is the transfer function of the current compensator 28, Gid(s) is the transfer function of the AC/DC converter 24, and KPWM is the transfer function of the pulse width modulation converter 20. As shown in step S10, the AC/DC converter 24 of the power level circuit 12 receives the input alternating current voltage VAC and the pulse width modulation signal VPWM, then converts the alternating current voltage VAC into the input current IAC in accordance with the pulse width modulation signal VPWM. As shown in step S12, the input current IAC is converted into the output voltage Vo by the AC/DC converter 24 of the power stage circuit 12, and the input current IAC is also sampled via the sample resistor 22 as a correcting current Isen. As shown in step S14, the current compensating circuit 14 receives the correcting current Isen that is compared to a reference current signal Iref via the current compensating circuit 14 to generate the compensating current signal IEA. Specifically, the current error amplifier 26 receives and compares the correcting current Isen with the reference current signal Iref thus generates a comparing current. Then, the current compensator 28 receives and compensates the comparing current thus generates the compensating current signal IEA.
The voltage compensating circuit 16 receives the output voltage Vo that is compared with a reference voltage Vref via the voltage compensating circuit 16 to generate the compensating voltage signal VEA. Specifically, the voltage divider 30 receives the output voltage Vo to generate one feedback voltage. Then, the voltage error amplifier 32 receives and compares the feedback voltage with a reference voltage Vref to generate the comparing voltage. Finally, the voltage compensator 34 receives and compensates the comparing voltage thus generates the compensating voltage signal VEA.
An updated reference current signal Iref is obtained by multiplying the compensating current signal IEA by the compensating voltage signal VEA by the multiplication amplifier 18. Specifically, the multiplier 36 receives the compensating current signal IEA and the compensating voltage signal VEA to generate the compensating feedback current by multiplying the compensating current signal IEA by the compensating voltage signal VEA, then the current gain regulator 38 receives the compensating feedback current that is multiplied by the current gain Km to generate the reference current signal Iref.
Finally, as shown in step S16, the pulse width modulation converter 20 receives the compensating current signal IEA and the compensating voltage signal VEA to generate the updated pulse width modulation signal VPWM that is transmitted into the power stage circuit 12. Specifically, the ramp generator 40 receives the compensating voltage signal VEA to generate ramp signal VRAMP, then, conversion comparator 42 receives and compares the ramp signal VRAMP and compensating current signal IEA thus generates the updated pulse width modulation signal VPWM that is fed to the power stage circuit 12, thus returning back to step S10. The whole process of steps S10 to S16 is repeated to achieve the phase synchronization for the alternating current voltage and the input current.
FIG. 4 shows the waveforms of the reference current signal Iref, compensating voltage signal VEA, feedback voltage VFB, alternating current voltage VAC, compensating current signal IEA and ramp signal VRAMP. FIG. 5 shows corresponding reference current signal Iref, compensating current signal IEA and compensating voltage signal VEA of FIG. 4 after amplifying.
In conversion process of the conversion comparator 42, when the voltage value of the ramp signal VRAMP is higher than the corresponding voltage value of the compensating current signal IEA, the updated pulse width modulation signal VPWM is a high level voltage. Otherwise, when the voltage value of the ramp signal VRAMP is lower than the corresponding voltage value of the compensating current signal IEA, the updated pulse width modulation signal VPWM is a low level voltage, as shown in FIG. 6.
FIG. 7 shows the waveforms of 220V alternating current voltage VAC and its input current IAC and FIG. 8 shows the waveforms of 110V alternating current voltage VAC and its input current IAC, which are achieved by the correction device of the present invention. As shown in these figures, the phases of the alternating current voltage VAC and its input current are the same, as such the purpose of power factor correction is achieved.
The present invention uses only one multiplication amplifier to receive compensating current signal and compensating voltage signal to generate the updated reference current signal that is provided to the current compensating circuit for correcting the power factor of the input signal.
The above is only one better embodiment of the invention, which is not used for limiting the scope of implementation of the invention. Therefore, equivalent changes and decorations caused by the shapes, configurations, characteristics and spirits in the scope of application for patent in the invention are all contained in the scope of the application for patent in the invention.

## Claims

1. A power factor correction device comprising:
a current compensating circuit comprising a current error amplifier, wherein the current error amplifier receives and compares a correcting current with a reference current signal, thereby generating a compensating current signal;
a voltage compensating circuit receiving and comparing a first output voltage with a reference voltage, thereby generating a compensating voltage signal;
a multiplication amplifier connected to the current compensating circuit and the voltage compensating circuit, the multiplication amplifier receiving the compensating current signal and the compensating voltage signal, thereby generating an updated reference current signal provided to the current compensating circuit.

2. The power factor correction device of claim 1, wherein the multiplication amplifier generates the updated reference current signal by multiplying the compensating current signal with the compensating voltage signal.

3. The power factor correction device of claim 1, further comprising a power stage circuit connecting to a load receiving an alternating current voltage and a control signal, wherein the power stage circuit converts the alternating current voltage into an input current in accordance with the control signal and outputs the input current to the load to generate a second output voltage on the load, and wherein the power stage circuit samples the input current to output the correcting current to the current error amplifier connected to the power stage circuit.

4. The power factor correction device of claim 3, wherein the power stage circuit further comprises a sample resistor connected to the current compensating circuit, and an AC/DC converter connected to the current compensating circuit, the load, the sample resistor, and the voltage compensating circuit, wherein the AC/DC converter receives the alternating current voltage and the control signal, wherein the AC/DC converter converts the alternating current voltage into the input current in accordance with the control signal and feeds the input current to the load to generate the second output voltage; and wherein the sample resistor samples the input current for the AC/DC converter to output the correcting current.

5. The power factor correction device of claim 3, wherein the current compensating circuit further comprises a current compensator connected to the current error amplifier, wherein the current error amplifier receives and compares the correcting current with the reference current signal to generate a comparing current, and wherein the current compensator receives the comparing current to generate the compensating current signal.

6. The power factor correction device of claim 3, wherein the voltage compensating circuit further comprises a voltage divider connected to the power stage circuit, a voltage error amplifier connected to the voltage divider and a voltage compensator connected to the voltage error amplifier, wherein the voltage divider receives the second output voltage and generates a feedback voltage, wherein the voltage error amplifier receives and compares the feedback voltage with another reference voltage to generate a comparing voltage; and wherein the voltage compensator receives the comparing voltage to generate another compensating voltage signal.

7. The power factor correction device of claim 1, wherein the multiplication amplifier further comprises a multiplier connected to the current compensating circuit and the voltage compensating circuit and a current gain regulator connected to the multiplier, wherein the multiplier receives and multiples the compensating current signal and the compensating voltage signal to generate a compensating feedback current; and wherein the current gain regulator receives and multiples the compensating feedback current with a current gain to generate the reference current signal.

8. The power factor correction device of claim 1, further comprising a converter connected to the current compensating circuit and the voltage compensating circuit, the converter receiving the compensating current signal and the compensating voltage signal to generate a control signal to synchronize a phase of an alternating current voltage and an input current.

9. The power factor correction device of claim 8, wherein the converter further comprises a ramp generator connected to the voltage compensating circuit and a conversion comparator connected to the ramp generator and the current compensating circuit, wherein the ramp generator receives the compensating voltage signal to generate a ramp signal; and wherein the conversion comparator receives and compares the ramp signal and the compensating current signal to output the control signal to a power stage circuit.

10. The power factor correction device of claim 9, wherein whenever a voltage value of the ramp signal is higher than a corresponding voltage value of the compensating current signal, the control signal is a high level voltage, and whenever the voltage value of the ramp signal is lower than the corresponding voltage value of the compensating current signal, the control signal is a low level voltage.

11. A power factor correcting method comprising the following steps:
receiving an alternating current voltage and a control signal so as to convert the alternating current voltage into an input current according to the control signal;
converting the input current into an output voltage and sampling the input current to output a correcting current;
comparing the correcting current with a reference current signal to generate a compensating current signal,
comparing the output voltage with a reference voltage to generate a compensating voltage signal;
multiplying the compensating current signal by the compensating voltage signal to generate an updated reference current signal; and
receiving the compensating current signal and the compensating voltage signal to generate an updated control signal.

12. The power factor correcting method of claim 11, wherein the step of comparing the correcting current with the reference current signal to generate the compensating current signal further comprises the following sub-steps: receiving the correcting current and the reference current signal, outputting a comparing current after comparing the correcting current with the reference current signal; and receiving the comparing current to generate the compensating current signal after performing current compensation.

13. The power factor correcting method of claim 11, wherein the step of comparing the output voltage with the reference voltage to generate the compensating voltage signal further comprises the following sub-steps: receiving the output voltage for voltage division to generate a feedback voltage; receiving the feedback voltage and the reference voltage, outputting a comparing voltage after comparing the feedback voltage with the reference voltage; and receiving the comparing voltage to generate the compensating voltage signal after performing voltage compensation.

14. The power factor correcting method of claim 11, wherein the step of multiplying the compensating current signal by the compensating voltage signal to generate the updated reference current signal further comprises the following sub-steps:
receiving the compensating current signal and the compensating voltage signal to generate a compensating feedback current after multiplying the compensating current signal by the compensating voltage signal; and receiving the compensating feedback current and multiplying with a current gain to generate the reference current signal.

15. The power factor correcting method of claim 11, wherein the step of receiving the compensating current signal and the compensating voltage signal to generate the control signal further comprises the following sub-steps: receiving the compensating voltage signal to generate a ramp signal; and receiving the ramp signal and the compensating current signal to output the updated control signal after comparing the ramp signal with the compensating current signal.

16. The power factor correcting method of claim 15, wherein whenever a voltage value of the ramp signal is higher than a corresponding voltage value of the compensating current signal, the updated control signal is a high level voltage; and whenever the voltage value of the ramp signal is lower than the corresponding voltage value of the compensating current signal, the updated control signal is a low level voltage.

17. The power factor correcting method of claim 15, wherein a sample resistor samples the input current to provide the correcting current.

18. The power factor correcting method of claim 17, wherein the control signal comprises a pulse width modulation signal.

19. A power factor correcting method comprising the following steps:
receiving an alternating current voltage and a control signal, so as to convert the alternating current voltage into an input current according to the control signal, wherein the control signal comprising a pulse width modulation signal;
converting the input current into an output voltage, and sampling the input current to output a correcting current, wherein a sample resistor samples the input current to provide the correcting current;
comparing the correcting current with a reference current signal to generate a compensating current signal,
comparing the output voltage with a reference voltage to generate a compensating voltage signal;
multiplying the compensating current signal by the compensating voltage signal to generate an updated reference current signal; and
receiving the compensating current signal and the compensating voltage signal to generate an updated control signal, wherein the step of receiving the compensating current signal and the compensating voltage signal to generate the updated control signal further comprises the following steps:
receiving the compensating voltage signal to generate a ramp signal; and
receiving the ramp signal and the compensating current signal to output the updated control signal after comparing the ramp signal with the compensating current signal;

wherein the sample resistor, the pulse width modulation signal, the input current, the alternating current voltage, the output voltage and the ramp signal satisfy the following conditions:


RS·iin(θ)=dOFF(θ)·TSW·SV 



dOFF(θ)=Vin_pk·sin(θ)/Vo=1−d(θ); and



iin(θ)=Vin_pk·sin(θ)/Rin(ac),


wherein Rs is a resistance value of the sample resistor, iin(θ) is the input current, Vin_pk sin(θ) is the alternating current voltage, Vo is the output voltage, Sv is a slope of the ramp signal, Rin(ac) is an equivalent input alternating current resistance, Tsw and d(θ) are cycle and duty cycle of the pulse width modulation signal VPWM respectively.