# Patent

## Title
Power converter with reverse recovery avoidance

## Abstract

A power converter includes a reverse-recovery avoidance scheme. The power converter may include deliver current from a direct current (DC) power source to an alternating current (AC) load. A first switch and second switch of the power converter may be operated to supply the AC load with positive current respective to the AC load from the DC power source. A third and fourth switch of the power converter may be operated to supply the AC load with negative current respective to the AC load from the DC power source. A first diode may be electrically coupled in series with the second switch and second diode may be electrically coupled in parallel with the first diode and the second switch. The second diode may conduct the positive current when the first switch is off and the second switch is on. A third diode may be electrically coupled in series with the fourth switch and a fourth diode may be electrically coupled in parallel with the third diode and the fourth switch. The fourth diode may conduct the negative current when the third switch is off and the fourth switch is on.

## Background
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to power converters, and more specifically to avoiding reverse recovery conditions during power converter operation.
2. Related Art
Typical power converters implement one or more switches to selectively apply a voltage source to an output load. Various power converter configurations may be used such as a half-bridge configuration. Transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) may be used as the switches in the half-bridge arrangements. During operation, internal diodes of some transistors may store electrical charge due to conduction properties of the internal diodes. Electrical current spikes through the transistors may occur due to the stored electrical charge. These electrical current spikes may contribute to a significant amount of power loss through dissipation in the transistors.
SUMMARY
According to one aspect of the disclosure, a power converter may include at least four switches to deliver power from a direct current (DC) power source to an alternating current (AC) load. A first and second switch may be electrically coupled to deliver DC current from a DC power source to an AC load. The first and second switch may deliver current to the AC load positive in polarity with respect to the AC load when the first and second switches are in respective on states. A third and fourth switch may be electrically coupled between the DC source and the AC load to deliver current to the AC load negative in polarity with respect to the load when the third and fourth switches are in respective on states. To avoid reverse recovery conditions during switching, a first diode may block reverse-recovery-causing current from flowing through the fourth switch and a second diode may provide a current path for the reverse-recovery-causing current. The first and second diodes may be used in such a manner when the current is positive with respect to the AC load and the first switch is turned off. Similarly, a third diode may block reverse-recovery-causing current from flowing through the second switch and a fourth diode may provide a current path for the reverse-recovery-causing current. The third and fourth diodes may be used in such a manner when the current is negative with respect to the AC load and the third switch is turned off. In one example, the second and fourth diodes may be Schottky diodes or ultrafast diodes.
A controller may be configured to generate switching signals for each of the switches. The switching frequency of the first switch and third switch may be based on the desired AC load current and on the desired polarity of the output current and an error signal between output current of the power converter and desired AC load current. The switching frequency of the second switch and the fourth switch may be based on the desired polarity of the output current.



BRIEF DESCRIPTION OF THE DRAWINGS
The disclosure may be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like referenced numerals designate corresponding parts throughout the different views.
FIG. 1 is a circuit diagram of an example power converter having an energy recovery circuit.
FIG. 2 is a circuit diagram of a portion of an example controller for the power converter of FIG. 1.
FIG. 3 is a circuit diagram of another portion of the example controller of FIG. 2.
FIG. 4 is a plot of an error signal versus time during operation of the example power converter of FIG. 1.
FIG. 5 is a plot of a ramp signal versus time during operation of the example power converter of FIG. 1.
FIG. 6 is a plot of an output current versus time during operation of the example power converter of FIG. 1.
FIG. 7 is filtered a plot of the output current of FIG. 6 filtered versus time.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a circuit diagram of an example power converter 100. In FIG. 1, the power converter 100 may be configured to convert direct current (DC) power to alternating current (AC) power, and thus, the power converter 100 may be referred to as a DC-AC converter or power inverter. In FIG. 1, the power converter 100 may transfer DC power from a DC voltage source Vbus, convert the DC power to AC power, and deliver the AC power to an output load 102. In one example, the output load 102 may be an AC power grid, such as that used in electric utilities. In one example, the voltage source Vbus may be generated based on a renewable energy source such as solar power, for example. The power converter 100 may be used to convert DC power produced by a DC power source such as a solar power module, including one or more of photovoltaic cells, to AC power and deliver the AC power to the output load 102. In FIG. 1, the output load 102 may be an AC power grid, such as that connected to a residential home, for example. An AC power grid may be represented by an AC voltage source Vline and an inductive element Lline. In other examples, the AC power grid may be represented by other elements such as resistive or capacitive elements, or some combination.
The power converter 100 may deliver an output current io. At least a portion of the output current io may be received by the output load 102. The output current io is based on source current is provided by the voltage source Vbus. Because the voltage source Vbus provides a DC current, the power converter 100 may invert the DC current (source current is) with respect to the output load at desired times, in order to provide an appropriate AC current to the output load 102. In one example, the power converter 100 may be configured in an “H-bridge” arrangement to convert the DC power from the voltage source Vbus to the output load 102. In FIG. 1, the power converter 100 may include switches SW1 through SW4. In FIG. 1, each switch SW1 through SW4 may be a transistor such as a metal-oxide semiconductor field effect transistor (“MOSFET”). A gate (G), drain (D), and source (S) of each switch SW1 through SW4 is shown in FIG. 1. The term MOSFET may refer to other field effect transistors such as those having a gate material other than metal, such as polysilicon (polycrystalline silicon) or other suitable gate material. The term MOSFET may also include insulated-gate field-effect transistors (IGFETs), as well. Other suitable switch types may be used for SW1 through SW4 for appropriate applications.
The power converter 100 may also include a filter 104 that includes a first filter element LOC1 and a second filter element LOC2. In other examples, more filter elements may be implemented. In FIG. 1, the filter elements LOC1 and LOC2 may each be embodied as inductive elements such as one or more inductors. In other examples, other filtering mechanisms may be implemented. The first filter element LOC1 may be electrically coupled between the output load 102 and the switch SW1. The second filter element LOC2 may be electrically coupled between the output load 102 and the switch SW4. A third filter element CT may be electrically coupled between the filter elements LOC1 and LOC2 and in parallel to the output load 102. The third filter element CT may be a capacitive element, such as one or more capacitors. The filter elements LOC1, LOC2, and CT may be used to filter output ripple associate with the output load 102. In alternative examples, a single filter element may be used, such as one or more inductors electrically coupled in series with the output load 102. The power converter 100 may also include a sense resistor Rsns electrically coupled between the filter element LOC2 and the filter element CT. As later described in detail, the sense resistor Rsns may be used to generate a sense voltage Vio—sns used for control of the switches SW1 through SW4. The sense resistor Rsns and third filter element CT may be electrically coupled to a common ground COM. In alternative examples, other circuit elements and/or circuits may be used to sense the output current io.
The power converter 100 may also include a series diode D1 electrically coupled between the output load 102 and the switch SW3. In FIG. 1, the series diode D1 includes a cathode electrically coupled to the drain of the switch SW3 and an anode electrically coupled to the filter element LOC1. Similarly, the power converter 100 may include a second series diode D2 electrically coupled between the output load and the switch SW4. In FIG. 1, the cathode of the series diode D2 is electrically coupled to a drain of the switch SW4 and the anode of the series diode D2 is electrically coupled to the filter element LOC2. The power converter 100 may also include recovery diodes RD1 and RD2. As later described in detail, the recovery diodes RD1 and RD2 may contribute to reducing, removing, and/or avoiding conditions associated with causing reverse recovery current within the power converter 100. The recovery diode RD1 may be electrically coupled in parallel to the series diode D1 and the switch SW3. The recovery diode RD2 may be electrically coupled in parallel to the second series diode D2 and the switch SW4. In FIG. 1, the cathodes of the recovery diodes RD1 and RD2 may be electrically coupled to the anodes of the series diodes D1 and D2, respectively. The anodes of the recovery diodes RD1 and RD2 may be electrically coupled to the sources of the switches SW3 and SW4, respectively.
In FIG. 1, each switch SW1 through SW4 may have an “on” state and “off” state. When embodied as FETs, the on and off state of each switch SW1 and SW4 may be based on voltage applied to the gates (G) of each switch SW1 through SW4 through gate signals GS1 through GS4, respectively. In alternative examples, the gates signals GS1 through GS4 may be used to control a variety of suitable switch types. In one example, the gate signals GS1 through GS4 may be generated by controller 106 having a processor 108 in communication with a memory 110. The memory 110 may include one or more memories and may be computer-readable storage media or memories, such as a cache, buffer, RAM, removable media, hard drive or other computer readable storage media. Computer readable storage media may include various types of volatile and nonvolatile storage media. Various processing techniques may be implemented by the processor 108 such as multiprocessing, multitasking, parallel processing and the like, for example. The processor 108 may include one or more processors.
The memory 110 may store software modules executable by the processor 108 to cause the controller 106 to generate the gate signals GS1 through GS4 according to a desired switching strategy. The term “module” may be defined to include a plurality of executable modules. As described herein, the modules are defined to include software, hardware or some combination thereof executable by the processor 108. Software may include instructions stored in the memory 110, or other memory device, that are executable by the processor 108 or other processor. Hardware may include various devices, components, circuits, gates, circuit boards, and the like that are executable, directed, and/or controlled for performance by the processor 108. In other examples, the controller 106 may include analog components, digital components, or both, such as that described with regard to FIGS. 2 and 3.
In order to convert the DC power from the voltage source Vbus to AC power, the switches SW1 through SW4 may be operated to provide the appropriate power type and amount. Since the average DC source current is is positive with respect to the voltage source Vbus, the source current is may be appropriately routed using switches SW1 through SW4 to provide an AC current relative to the output source 102. For example, a positive current relative to the output load 102 flows into the positive terminal (+) of the AC voltage source Vline. To supply the output load 102 with a positive polarity current relative to the output load 102, switches SW1 and SW4 may be actively switched and switches SW2 and SW3 are turned off (open) to allow the source current is to initially flow through switch SW1 and through the first filter element LOC1. Some of the output current io may flow through the third filter element CT, providing a line current iline supplied to the output load 102 to be the difference between the output current io and a filter current iT. The line current iline flows through the output 102. On the return path, the output current io(iline+iT) flows through the sense resistor R and the second filter element LOC2. The output current io then flows through the series diode D2 and the switch SW4 prior to returning to the voltage source Vbus.
When negative polarity of the output current io is desired, the switches SW1 and SW4 may be switched to the respective off states (open) and switches SW2 and SW3 may be switched to the respective on states. This allows the source current is to substantially be the output current io as it flows through the switch SW2 and through the second filter element LOC2 and the sense resistor Rsns, prior to splitting between iT and the line current iline. The source current is, as the output current io, then flows through the first filter element LOC1, the series diode D1 and the switch SW3 prior to returning the voltage source Vbus.
In operation, when providing an output current io having a positive polarity, the switches SW1 and SW4 may be switched on. However, to control the amount of power provided to the output load 102, pulse-width-modulation (PWM) control may be used to control the switch SW1. The switch SW4 may be switched on during an entire cycle of desired positive polarity output current io. In one example, the switch SW4 may be switched to an on state when the output current io is desired to have a positive polarity, and thus may have a switching frequency in accordance with a fundamental frequency of the desired AC output current io, such as 60 Hz as found in most United States power grids. In a similar manner, when the output current io is desired to have a negative polarity relative to the output load 102, the switch SW3 may be switched at the desired fundamental frequency of the desired output current and the switch SW2 may be switched using PWM to provide the desired amount of power to output load. The PWM switching strategy may be performed at a relatively much higher switching frequency such as 20-100 kHz. The switch SW1 may have a variable duty cycle to control the amount of power provided to the output load 102. Due to the inductive nature of the output load 102, current continues to flow through the power converter 100 to the output load 102 even when the switch SW1 is turned off for a relatively short time. Thus, the output current io flowing through the power converter 100 may require a conductive path when the switch SW1 is off.
The converter arrangement of FIG. 1 without the series diodes D1 and D2 and the recovery diodes RD1 and RD2 being present, in operation, may result in destructive conditions such as shoot-through current due to reverse recovery conditions. For example, such a configuration, while positive polarity current is being supplied to the output load 102, switch SW1 may be switched on and off switched using PWM or any other switching strategy. During switching, when the switch SW1 is turned off, current flowing to the output load 102 requires a path but is unable to flow through SW1 while turned off.
As shown in FIG. 1, each switch SW1 through SW4 may include an internal body diode BD1 through BD4, respectively, such as those found in MOSFETs. Each body diode BD1 through BD4 may conduct current even when the respective switch SW1 through SW4 is turned off. Thus, in a traditional H-bridge arrangement, as switch SW1 is turned off while positive polarity current is being supplied to the output load 102, the body diode BD3 will conduct the output current io until SW1 is turned on. However, as the body diode BD3 conducts the output current io, the body diode BD3 stores charge. As a consequence, when the switch SW1 is turned on again the charge stored in the body diode BD3 will be discharged resulting in a spike in current flowing through the switch SW1 and the body diode BD3 causing a significant and undesired expenditure of power in SW1 with each turn on during such operation. Similarly, body diode BD4 may conduct current when negative polarity current is being delivered to the output load 102 and switch SW2 is turned off causing reverse recovery current to occur when the switch SW2 is turned on again.
In FIG. 1, the power converter 100 is configured to reduce reverse recovery current. During operation, when switches SW1 and SW4 are cooperatively operating to provide positive polarity current, the source current is, which is also substantially the output current io at this time, flows through both switches SW1 and SW4. When SW1 is turned off while positive polarity current is being delivered to the output load 102, the flow of the output current io requires a path. In FIG. 1, the output current io is blocked from flowing through the body diode BD3 by the series diode D1 forcing the current to flow through the reverse recovery diode RD1, indicated as io—SW1—off. Similarly, when switches SW2 and SW3 are cooperatively operating to provide negative polarity current, SW2 may experience off states during PWM control. The output current io will flow through the recovery diode RD2 (indicated as io—SW2—off) due to series diode D2 blocking the output current io from flowing through the body diode BD4.
In one example, the recovery diodes RD1 and RD2 may be high voltage diodes since they must block the full DC voltage from Vbus. In one example, the recovery diodes RD1 and RD2 may be SiC Schottky diodes. Schottky diodes typically do not display reverse recovery characteristics, and thus store little to no charge when conducting. As a result, in FIG. 1, when SW1 is turned off, positive polarity current flows through the recovery diode RD1 and when switch SW1 is turned back on, there is little to no charge stored in the recovery diode RD1 to cause significant reverse recovery current. Similarly, the recovery diode RD2 alleviates reverse recovery conditions when switch SW2 is turned on and off while negative polarity current is being delivered to the output load 102. In other examples, diodes having substantially no reverse recovery characteristics, such as accumulating nominal charge during current conduction, may be used as the recovery diodes RD1 and RD2.
FIGS. 2 and 3 show an example control circuit configured to generate the gate signals GS1 through GS4. FIGS. 2 and 3 show the control circuit 200 as including hardware components. However, in other examples, the control circuit 200 may be embodied as software or a combination of software and hardware modules. FIG. 2 shows a circuit schematic of a portion of the control circuit 200 configured to rectify and amplify the sense voltage Vio—sns. In FIG. 2, the sense voltage vio—sns may be provided to a resistive element Rrec1 electrically coupled to the non-inverting input of operational amplifier (op-amp) Q1. The inverting input of the op-amp Q1 may be electrically coupled to the output of the op-amp Q1. The output of the op-amp Q1 may be electrically coupled to a non-inverting input of op-amp Q2. An inverting input of the op-amp Q2 may be electrically coupled between the resistive element Rrec2 and a resistive element Rrec3. In one example, the resistive elements Rrec1, Rrec2, and Rrec3 may have approximately the same resistance.
The output of op-amp Q2 is electrically coupled to the resistive element Rrec3 and a non-inverting input of an op-amp Q3. An inverting input of the op-amp Q3 is electrically coupled to a resistive element R1, a resistive element RF, and a capacitive element CF. The resistive element R1 may also be coupled to ground. The output of the op-amp Q3 may be electrically coupled to the resistive element RF and the capacitive element CF. The output of the op-amp Q3 may provide a sense current isns indicative of the instantaneous value of output current io. Each of the op-amps Q1, Q2, and Q3 may be connected to a common voltage source Vs or different voltage sources configured to provide an adequate voltage for appropriate operation.
FIG. 3 is a circuit schematic of another portion of the control circuit 200 used to generate gate signals GS1 through GS4. The driver circuit includes a comparison op-amp Q4. The comparison op-amp Q4 includes an inverting input electrically coupled between resistive elements Ri and Rf. The resistive element Ri is configured to receive the sense current isns and provide a voltage to the non-inverting input of the comparison op-amp Q4 indicative of the sense current isns. The resistive element Rf is electrically coupled to a capacitive element Cf, which is also electrically coupled to an output of the comparison op-amp Q4. A commanded current signal icmd is provided to an absolute value module (“abs”) 300 to provide the absolute value of the commanded current signal icmd to a non-inverting input of the comparison op-amp Q4. The commanded current icmd may be a command signal generated from a controller, such as the controller 106 and indicative of the current desired to be provided to the output load 102. The comparison op-amp Q4 may also be connected to the common voltage source Vs or be connected to another appropriate voltage source for operation.
The comparison op-amp Q4 performs a comparison of the sense current isns and the absolute value of the commanded current signal icmd to generate an error signal “d” representing the duty cycle ratio command used to generate PWM control signals. The error signal d may be supplied to a non-inverting input of a control signal comparator Q5. A ramp signal r may be generated based on a clock signal CLK received by a resistive element Rramp electrically coupled to a capacitive element Cramp and an inverting input of the control signal comparator Q5. The frequency of the clock signal CLK may be based on a desired switching frequency of the switches SW1 and SW2, such as about 50 kHz. Other clock signal CLK frequencies may be used such as frequencies with the range of 20 kHz-100 kHz for example.
An output signal PWM of the control signal comparator Q5 may signal when the switches SW1 and SW2 should be switched. Thus, the on times for the switches SW1 and SW2 is based on the duty cycle of the output signal PWM. For example, the output signal PWM may provide a non-zero voltage when the error signal d is greater than the ramp signal r and may provide an approximately zero voltage when the error signal d is less than the ramp signal r. However, in order to use the switches SW1 and SW2 to provide positive polarity and negative polarity current to the output load 102, the switch SW1 may be turned on when the current supplied to the output load 102 is desired to be of positive polarity. Similarly, the switch SW2 may be turned on when the current supplied to the output load 102 is desired to be of negative polarity. Thus, the control circuit 200 includes a polarity comparator Q6 configured to receive the commanded current signal icmd at its non-inverting input and have its inverting input grounded. As a result, a polarity output signal p of the polarity comparator Q6 indicates the desired polarity of the output current. For example, when the commanded current signal icmd is greater than zero, the output signal p of the polarity op-amp is a non-zero voltage. When the commanded current signal icmd is less than or equal to zero, the output signal p is approximately zero volts.
As described, the outputs of comparators Q5 and Q6 may be a non-zero voltage or approximately zero volts, depending on the respective input signals allowing the outputs of comparators Q5 and Q6 to act as logic signals to be implemented in controlling gate signals GS1 through GS4. In FIG. 3, the output signals PWM and p may be provided to an “AND” gate 302. The output of the AND gate 302 may be the gate signal GS1. The gate signal GS1 provides a gate voltage to the switch SW1 when both output signals PWM and p are “high” logic signals indicating that, based on the duty cycle, the voltage source Vbus should be applied to the output load 102 and the desired current is positive in polarity. The output p of the comparator Q6 is the gate signal for switch SW4, which should be turned on when the desired current is greater than zero. The output signal p is inverted by an inverter 304 to generate the gate signal GS3. The gate signal GS3 should turn on the switch SW3 when the desired current is zero or less, and thus, is the inverse of the gate signal GS4. The last gate signal, GS2, should turn on the switch SW2 when the duty cycle indicates the voltage source Vbus should be applied to the output load 102 and the desired current is negative in polarity. To accomplish this, the gate signal GS2 may be an output of an AND gate 306 having the output signal PWM and the inverted output signal p, the gate signal GS3, as inputs.
FIGS. 4-7 show voltages and currents associated with operation of the power converter 100 based on the component values in Table 1. In other examples, other component configurations and components sizes could be used to provide similar functionality.


















TABLE 1







LOC1
3
mH
Vs
3.3
V
RF
48.7
kΩ
Rramp
10
kΩ


LOC2
3
mH
Rrec1
1
kΩ
CF
33
pF
Cramp
1
nF


CT
330
nF
Rrec2
1
kΩ
Ri
54.9
kΩ
Switching
20
kHz


Lline
1.25
mH
Rrec23
1
kΩ
Rf
30.1
kΩ
Frequency




Rsns
0.02
Ω
R1
1
kΩ
Cf
1
nF









FIG. 4 is a plot of an example error signal d versus time. FIG. 5 is a plot of an example ramp signal r versus time. FIG. 6 is a plot of the output current io versus time. FIG. 7 is a plot of an example output load current iline versus time.
While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the invention. The various embodiments described herein include a variety of electrical elements and combinations of electrical elements, such as inductors, capacitors, voltage sources, switches, resistors, diodes, and power converters electrically coupled in various manners. The described example configurations of electrical elements and devices are examples that may be embodied through equivalent configurations having additional or fewer of the described elements, circuits, and devices, and alternative elements, alternative circuits, and/or alternative devices while remaining within the scope of invention. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents.

## Claims

1. A power converter configured to transfer power between a direct current (DC) voltage source and an alternating current (AC) load, the power converter comprising:
a plurality of switches electrically configured to be electrically coupled between the voltage source and the load;
a first series diode electrically coupled between the load and a first switch of the plurality of switches;
a second series diode electrically coupled between the load and a second switch of the plurality of switches;
a first recovery diode electrically coupled in parallel to the first series diode, the first switch, and a body diode of the first switch; and
a second recovery diode electrically coupled in parallel to the second series diode, the second switch, and a body diode of the second switch,
wherein the first recovery diode or the second recovery diode conducts a common current flowing between the DC voltage source and the AC load when one of the plurality of switches is in an off state.

2. The power converter of claim 1, wherein the first switch and a third switch of the plurality of switches are each configured to conduct the common current flowing between the DC voltage source and the AC load when the first switch and the third switch are each in a respective on state, wherein the common current is positive in polarity with respect to the AC load.

3. The power converter of claim 2, wherein the first series diode is configured to conduct the common current flowing between the voltage source and the load when the first switch and the third switch are in the respective on state.

4. The power converter of claim 2, wherein the second recovery diode is configured to conduct the common current when the third switch is in a respective off state.

5. The power converter of claim 4, wherein the second switch and a fourth switch of the plurality of switches are each configured to conduct the common current flowing between the DC voltage source and the AC load when the second switch and the fourth switch are each in a respective on state, wherein the common current is negative in polarity with respect to the load.

6. The power converter of claim 5, wherein the second series diode is configured to conduct the common current when the second switch and the fourth switch are in the respective on state.

7. The power converter of claim 5, wherein the first recovery diode is configured to conduct the common current when the fourth switch is in a respective off state.

8. The power converter of claim 1, wherein a first switch and a second switch of the plurality of switches are each configured to conduct a common current flowing between the DC voltage source and the AC load when the first switch and the third switch are each switched to an on state, wherein the first switch is configured to be switched at a first switching frequency and the second switch is configured to be switched at a second switching frequency different from the first switching frequency.

9. The power converter of claim 8, wherein the first frequency is greater than the second frequency.

10. The power converter of claim 9, wherein the second switching frequency is a desired frequency of current being supplied from the DC voltage source and the AC load.

11. The power converter of claim 1, wherein at least one of the first recovery and second recovery diodes is a Schottky diode and wherein the voltage source is a renewable energy source.

12. The power converter of claim 1, wherein at least one of the first recovery and second recovery diodes is a diode having substantially no reverse recovery characteristics.

13. A power delivery system comprising:
a plurality of switches configured to supply power from a direct current (DC) power source to an alternating current (AC) load, wherein the plurality of switches comprises:
a first switch and a second switch each configured to direct a current from the DC power source to the AC load, wherein the current is positive in polarity with respect to the AC load, and wherein the first switch is configured to be switched at a first frequency and the second switch is configured to be switched at a second frequency different than the first frequency; and
a third switch and a fourth switch each configured to direct the current from the DC power source to the AC load, wherein the current is negative in polarity with respect to the AC load, and wherein the third switch is configured to be switched at the first frequency and the fourth switch is configured to be switched at the second frequency;

a first series diode and second series diode, wherein the first series diode is electrically coupled in series with the second switch and the second series diode is electrically coupled in series with the fourth switch; and
a first recovery diode and a second recovery diode, wherein the first recovery diode is electrically coupled in parallel with the first series diode and the second switch having a body diode and the second recovery diode is electrically coupled in parallel with the second series diode and the fourth switch having a body diode, and
wherein the first recovery diode or the second recovery diode is positioned and connected to conduct the current when one of the plurality of switches is in an off state.

14. The power delivery system of claim 13 further comprising a controller, wherein the controller is configured to generate a plurality of respective control signals, wherein each of the plurality of control signals is configured to control a respective one of the plurality of switches between a respective on and off state.

15. The power delivery system of claim 14, wherein a first one and a second one of the plurality of control signals is based on an error signal indicative of a comparison between the current and a desired current and also is based on a polarity signal indicative of a desired polarity of the current, and wherein a third one and a fourth one of the plurality of control signals are based on the polarity signal.

16. The power delivery system of claim 13, wherein the first recovery diode is configured to conduct the current flowing through the AC load when the first switch is in a respective off state and the current is positive in polarity with respect to the AC load.

17. The power delivery system of claim 13, wherein the second recovery diode is configured to conduct the current flowing through the AC load when the third switch is in a respective off state and the current is negative in polarity with respect to the AC load.

18. The power delivery system of claim 13, wherein at least one of the first recovery diode and the second recovery diode is a Schottky diode and wherein the direct current power source is a renewable energy source.

19. The power delivery system of claim 13, wherein at least one of the first recovery diode and the recovery diode is a diode having substantially no reverse recovery characteristics.

20. A power converter comprising:
switching means for delivering positive and negative current from a power source to an AC load; and
a processor configured to control the switching means; and
means for avoiding reversing recovery in the switching means coupled in parallel with at least one switch within the switching means, wherein the means for avoiding reversing recovery conducts the current from the power source to the AC load if a switch of the switching means is in an off state.

21. The power converter of claim 1, wherein the first recovery diode conducts the common current when the first series diode blocks current flow to the body diode of the first switch.

22. The power converter of claim 1, wherein the second recovery diode conducts the common current when the second series diode blocks current flow to the body diode of the second switch.

23. The power converter of claim 1, further comprising a filter element electrically coupled to at least one of the first series diode and the second series diode.

24. The power delivery system of claim 13, wherein the first recovery diode is configured to conduct the current when the first series diode blocks current flow to the body diode of the second switch.

25. The power delivery system of claim 13, wherein the second recovery diode conducts the current when the second series diode blocks current flow to the body diode of the fourth switch.

26. The power delivery system of claim 13, wherein the first switch and the second switch are configured to receive a respective control signal at each switch to control whether the current flows through the first series diode or the first recovery diode.

27. The power delivery system of claim 13, wherein the third switch and the fourth switch are configured to receive a respective control signal at each switch to control whether the current flows through the second series diode or the second recovery diode.

28. The power converter of claim 20, wherein the processor is configured to generate gate signals to control the switching means and enable the means for avoiding reversing recovery in the switching means.