# Patent

## Title
DC-to-AC power converting device

## Abstract

A power converting device is adapted for converting a DC voltage input from an external power source into an AC voltage output. The power converting device includes: a transformer having first and second windings each having opposite first and second ends; a clamp unit coupled to the external power source, and including a first switch coupled between a reference node and the second end of the first winding, and a series connection of a clamp capacitor and a second switch coupled across the first winding; and an inverting unit coupled to the first end of the second winding, and operable so as to output the AC voltage output based on an induced voltage across the second winding.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a power converting device, more particularly to a DC-to-AC power converting device.
2. Description of the Related Art
FIG. 1 illustrates a conventional solar power converting system that includes a solar cell array 1 for converting solar energy into electrical energy, a power conditioner 2 for receiving the electrical energy from the solar cell array 1 and for outputting an AC voltage output to a load or a power network, and a rechargeable battery 6. The power conditioner 2 includes a charge/discharge controller 21 coupled to the solar cell array 1 and the rechargeable battery 6, a DC-to-DC converter 22 coupled to the charge/discharge controller 21, and a DC-to-AC inverter 23.
FIG. 2 illustrates a conventional boost device that can be applied to the aforesaid DC-to-DC converter 22 of FIG. 1. The conventional boost device includes an inductor 11, a switch 12, a diode 13, and a capacitor 14. The inductor 11 has a first end coupled to an external power source 10, and a second end. The switch 12, such as a semiconductor power switch, has a first terminal coupled to a common node between the second end of the inductor 11 and an anode of the diode 13, a second terminal coupled to ground, and a control terminal for receiving an external control signal such that the switch 12 is operable between an ON-state and an OFF-state in response to the external control signal. The capacitor 14 is coupled between a cathode of the diode 13 and ground.
When the switch 12 is operated in the ON-state, a current (iL) from the external power source 10 flows through the inductor 11 to store electric power. When the switch 12 is operated in the OFF-state, the capacitor 14 is charged with a current from the inductor 11 through the diode 13 such that the conventional boost device outputs an output voltage, i.e., a voltage across the capacitor 14, to a load.
The following are some of the drawbacks of the conventional boost device:
1. When the switch 12 is in the OFF-state, a voltage across the switch 12 is substantially equal to the output voltage. Therefore, if the switch 12 is implemented as a MOSFET device, a relatively large conducting impedance is exhibited by the MOSFET device, thereby resulting in a relatively large conduction loss.
2. When the switch 12 is switched from the OFF-state to the ON-state, a reverse bias surge current is generated to flow through the switch 12 that causes serious switching loss, thereby reducing power transformation efficiency.
FIG. 3 illustrates another conventional boost device that can be applied to the aforesaid DC-to-DC converter 22 of FIG. 1. The conventional boost device includes a coupling inductor 15, a switch 16, a diode 17, and an output capacitor 18. The coupling inductor 15 has first and second windings 151, 152, each of which has a polarity end and a non-polarity end. The polarity end of the first winding 151 is coupled to an external power source 10. The switch 16 has a first terminal coupled to a common node between the non-polarity end of the first winding 151 and the polarity end of the second winding 152, a second terminal coupled to ground, and a control terminal for receiving an external control signal such that the switch 16 is operable between an ON-state and an OFF-state in response to the external control signal. The diode 17 has an anode coupled to the non-polarity end of the second winding 152, and a cathode. The capacitor 18 is coupled between the cathode of the diode 17 and ground.
When the switch 16 is operated in the ON-state, a current from the external power source 10 flows through the first winding 151 such that the first winding 151 is excited to store electric power. When the switch 16 is operated in the OFF-state, energy stored in the coupling inductor 15 charges the output capacitor 18 through the second winding 152 and the diode 17 such that the conventional boost device outputs an output voltage, i.e., a voltage across the output capacitor 18, to a load.
When the switch 16 is switched from the ON-state to the OFF-state, a voltage is generated as a result of a leakage inductance of the coupling inductor 15 and can cause damage to the switch 16. As such, an additional snubber circuit is required to absorb energy attributed to the leakage inductance.
Since the operation of the conventional boost device is described in detail in the aforesaid patent, further discussion of the same is omitted herein for the sake of brevity.
However, such a conventional boost device cannot provide electrical isolation. Thus, for an outdoor power supplying appliance including the conventional boost device, lightning strike may result in damage to the conventional boost device.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a boost device that can attain high power transformation efficiency and that can provide electrical isolation.
According to the present invention, there is provided a power converting device for converting a DC voltage input from an external power source into an AC voltage output. The power converting device comprises:
a transformer having first and second windings each having opposite first and second ends, the first end of the first winding being adapted to be coupled to the external power source;
a clamp unit coupled to the transformer and adapted to be coupled to the external power source, the clamp unit including

    
    
        a first switch coupled between a reference node and the second end of the first winding of the transformer, and operable between an ON-state and an OFF-state, and
        a series connection of a clamp capacitor and a second switch coupled across the first winding of the transformer, the second switch being operable between an ON-state and an OFF-state; and
    
    


an inverting unit coupled to the first end of the second winding of the transformer, and operable so as to output the AC voltage output based on an induced voltage across the second winding of the transformer.



BRIEF DESCRIPTION OF THE DRAWINGS
Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment with reference to the accompanying drawings, of which:
FIG. 1 is a schematic circuit block diagram illustrating a conventional solar power converting system;
FIG. 2 is a schematic electrical circuit diagram illustrating a conventional boost device;
FIG. 3 is a schematic electrical circuit diagram illustrating another conventional boost device;
FIG. 4 is a schematic electrical circuit diagram illustrating the preferred embodiment of a power converting device according to the present invention;
FIGS. 5a and 5b illustrate waveforms of external control signals (vgS1, vgS2) for first and second switches of a clamp unit of the preferred embodiment, respectively;
FIG. 5c illustrates waveforms of currents (iLP, iLS) flowing respectively through first and second windings of a transformer of the preferred embodiment;
FIG. 5d illustrates a waveform of an exciting current (iLM) of the transformer of the preferred embodiment;
FIG. 5e illustrates waveforms of a current (iS1) flowing through the first switch, and a voltage (vS1) across the first switch;
FIG. 5f illustrates waveforms of a current (iS2) flowing through the second switch, and a voltage (vS2) across the second switch;
FIG. 5g illustrates waveforms of a current (i1) flowing through a diode of a first switch unit of the preferred embodiment, and a voltage (vD1) across the diode of the first switch unit;
FIG. 5h illustrates waveforms of a current (iDW) flowing through a first diode of a boost unit of the preferred embodiment, and a voltage (vDW) across the first diode;
FIG. 5i illustrates waveforms of a current (iDY) flowing through a second diode of the boost unit of the preferred embodiment, and a voltage (vDY) across the second diode;
FIG. 6 is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a first mode;
FIG. 7 is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a second mode;
FIG. 8 is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a third mode;
FIG. 9 is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a fourth mode;
FIG. 10 is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a fifth mode;
FIG. 11 is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a sixth mode;
FIG. 12 is a schematic equivalent electrical circuit diagram illustrating the preferred embodiment when operated in a seventh mode;
FIGS. 13a and 13b illustrate respectively waveforms of the current (iLP) flowing through the first winding (LP) and a control signal (vgS1) for the first switch when in a step-down operation; and
FIG. 14 is a plot illustrating experimental results of power transformation efficiency of the preferred embodiment for a DC voltage input of 18 Volts.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 4, the preferred embodiment of a power converting device according to the present invention is shown to be adapted for converting a DC voltage input (VIN) from an external power source into an AC voltage output, such as a sinusoidal signal. The power converting device includes a transformer (Tr), a clamp unit 3, an inverting unit 5, and a boost unit 4.
The transformer (Tr) includes first and second windings (LP, LS) wound around an iron core. A winding ratio of the first and second windings (LP, LS) is equal to 1:N. Each of the first and second windings (LP, LS) has a polarity end serving as a first end, and a non-polarity end serving as a second end. The polarity end of the first winding (LP) is adapted to be coupled to the external power source for receiving the input voltage (VIN). It is noted that the transformer (Tr) can accommodate high leakage inductance component. The first and second windings (LP, LS) can be separately wound in a known manner, which is much easier compared to a conventional sandwich winding manner.
The clamp unit 3 is coupled to the transformer (Tr) and is adapted to be coupled to the external power source. The clamp unit 3 includes a first switch (S1), and a series connection of a clamp capacitor (CX) and a second switch (S2). The first switch (S1) is coupled between a reference node, such as ground, and the non-polarity end of the first winding (LP) of the transformer (Tr). The first switch (S1) has a control end for receiving an external control signal (vgS1), and is operable to switch between an ON-state and an OFF-state in response to the external control signal (vgS1). The series connection of the clamp capacitor (CX) and the second switch (S2) is adapted to be coupled to the external power source, and is coupled in parallel to the first winding (LP) of the transformer (Tr). The second switch (S2) has a control end for receiving an external control signal (vgS2), and is operable to switch between an ON-state and an OFF-state in response to the external control signal (vgS2).
It is noted that, based on the external control signals (vgS1, vgS2) shown in FIGS. 5a and 5b, the first and second switches (S1, S2) are operated alternately in the ON-state, and duration of the ON-state of one of the first and second switches (S1, S2) does not overlap duration of the ON-state of the other one of the first and second switches (S1, S2). In this embodiment, the first and second switches (S1, S2) are switched at a frequency of 100 KHz.
The inverting unit 5 is coupled to the polarity end of the second winding (LS) of the transformer (Tr), and is operable so as to output the AC voltage output (vO) based on an induced voltage across the second winding (LS) of the transformer (Tr). The inverting unit 5 includes a full-bridge circuit and an output capacitor (CO).
The full-bridge circuit has a configuration similar to that disclosed in U.S. patent application Ser. No. 12/470,246. The full-bridge circuit includes a first series connection of first and second switch units 51, 52, and a second connection of third and fourth switch units 53, 54. The first and second series connections are coupled in parallel between the polarity end of the second winding (LS) of the transformer (Tr) and the reference node. Each of the first, second, third and fourth switch units 51, 52, 53, 54 includes a diode (D1, D2, D3, D4) and a switch (T1, T2, T3, T4) coupled in series to each other. The switch (T1, T2, T3, T4) of each of the first, second, third and fourth switch units 51, 52, 53, 54 is operable between an ON-state and an OFF-state. In this embodiment, the first switch unit 51 is coupled to the third switch unit 53, and the second switch unit 52 is coupled to the fourth switch unit 54. The diode (D1, D3) of each of the first and third switch units 51, 53 has an anode coupled to the polarity end of the second winding (LS) of the transformer (Tr), and a cathode coupled to the switch (T1, T3) thereof. The diode (D2) of the second switch unit 52 has an anode coupled to the switch (T1) of the first switch unit 51, and a cathode coupled to the switch (T2). The diode (D4) of the fourth switch unit 54 has an anode coupled to the switch (T3) of the third switch unit 53, and a cathode coupled to the switch (T4). The switches (T1, T4) of the first and fourth switch units 51, 54 are simultaneously in the ON-state, and the switches (T2, T3) of the second and third switch units 52, 53 are simultaneously in the ON-state. When the switch (T1) of the first switch unit 51 is in the ON-state, the switch (T2) of the second switch unit 52 is in the OFF-state. It is noted that the diodes (D1, D2/D3, D4) are used to prevent short circuit. In this embodiment, the switches (T1, T2, T3, T4) are switched at a frequency of 60 Hz.
The output capacitor (CO) is coupled between a first common node (n1) between the first and second switch units 51, 52, and a second common node (n2) between the third and fourth switch units 53, 54. The AC voltage output (vO) is a voltage across the output capacitor (CO). The output capacitor (CO) is capable of being charged through the full-bridge circuit with an induced voltage across the second winding (LS) of the transformer (Tr). When the switches (T1, T4) of the first and fourth switch units 51, 54 are in the ON-state, the output capacitor (CO) is charged so that the AC voltage output (vO) is a positive half of a sinusoidal signal. When the switches (T2, T3) of the second and third switch units 52, 53 are in the ON-state, the output capacitor (CO) is charged so that the AC voltage output (vO) is a negative half of the sinusoidal signal.
The boost unit 4 is coupled across the second winding (LS) of the transformer (Tr). The boost unit 4 is capable of being charged with the induced voltage across the second winding (LS) of the transformer (Tr), and of charging the output capacitor (CO) through the full-bridge circuit so as to boost the voltage across the output capacitor (CO). The boost unit 4 has a configuration similar to a boost circuit disclosed in U.S. patent application Ser. No. 12/433,039, and includes a first capacitor (CY), a series connection of a first diode (DW) and a second capacitor (CW), and a second diode (DY). The first capacitor (CY) is coupled between the non-polarity end of the second winding (LS) of the transformer (Tr) and the reference node. It is noted that the output capacitor (CO) is further charged through the full-bridge circuit with a voltage across the first capacitor (CY) when the output capacitor (CO) is charged with the induced voltage across the second winding (LS) of the transformer (Tr), as best shown in FIGS. 6 and 7. The series connection of the first diode (DW) and the second capacitor (CW) is coupled in parallel to the second winding (LS) of the transformer (Tr). The first diode (DW) has an anode coupled to the second capacitor (CW), and a cathode coupled to the non-polarity end of the second winding (LS) of the transformer (Tr). When the output capacitor (CO) is charged through the full-bridge circuit with the induced voltage across the second winding (LS) of the transformer (Tr), the second capacitor (CW) is charged through the first diode (DW) with the induced voltage across the second winding (LS) of the transformer (Tr), as best shown in FIGS. 6 and 7. The second diode (DY) has an anode coupled to the reference node, and a cathode coupled to a common node (p) between the anode of the first diode (DW) and the second capacitor (CW). The first capacitor (CY) is capable of being charged through the second diode (DY) with a voltage (VCW) across the second capacitor (CW), as best shown in FIGS. 9, 10 and 11. It is noted that the first diode (DW) and the second diode (DY) do not conduct simultaneously.
The boost unit 4 of the preferred embodiment is operable among first to seventh modes based on the external control signals (vgsi, vgs2) for the first and second switches (S1, S2) of the clamp unit 4 shown in FIGS. 5a and 5b. FIG. 5d illustrates a waveform of an exciting current (iLM) of the transformer (Tr). FIG. 5c illustrates waveforms of currents (iLP, iLS) flowing respectively through the first and second windings (Lp, Ls) of the transformer (Tr). FIG. 5e illustrates waveforms of a current (is1) flowing through the first switch (Si), and a voltage (vs1) across the first switch (S1). FIG. 5f illustrates waveforms of a current (is2) flowing through the second switch (S2), and a voltage (vs2) across the second switch (S2). FIG. 5g illustrates waveforms of a current (i1) flowing through the diode (D1) of the first switch unit 51, and a voltage (vD1) across the diode (D1). FIG. 5h illustrates waveforms of a current (iDw) flowing through the first diode (Dw) of the boost unit 4, and a voltage (vDW) across the first diode (Dw). FIG. 5i illustrates waveforms of a current (iDY) flowing through the second diode (Dy) of the boost unit 4, and a voltage (vDY) across the second diode (Dy).
Referring further to FIGS. 5a to 5i, and 6, the boost unit 4 is operated in the first mode during a period from t0 to t1. In FIG. 6, LM represents an exciting inductance of the transformer (Tr), Lk1 represents a leakage inductance of the first winding (LP), and Lk2 represents a leakage inductance of the second winding (LS). Therefore, a coupling coefficient (k) is represented as follows:

k=LM/(Lk1+LM)=LM/L1  (Equation 1)

where L1 is an inductance of the first winding (LP). In the first mode, the first switch (S1) is in the ON-state, the second switch (S2) is in the OFF-state, and the diodes (D1, D4) and the first diode (DW) conduct. The first winding (LP) is excited by a current (iIN) from the external power source to generate an induced voltage equal to VIN across the first winding (LP). Thus, the induced voltage (vLS) across the second winding (LS) is represented as follows:

νLS=N(VIN−νk1)  (Equation 2)

where vk1 is a voltage across the leakage inductance (Lk1). At the same time, the second capacitor (CW) is charged through the first diode (DW) with the induced voltage (vLS) across the second winding (LS) to N(VIN−νk1) so as to clamp a voltage across the second diode (DY). Thus, the voltage (vCW) across the second capacitor (CW) is represented as follows:

νCW=νLS−νk2=NVIN−2Nνk1  (Equation 3)

where vk2 is a voltage across the leakage inductance (Lk2). In this case, the output capacitor (CO) is charged through the first and fourth switch units 51, 54 with the induced voltage (vLS) across the second winding (LS), and the voltage (vCY) across the first capacitor (CY). Therefore, the AC voltage output (vO) is represented as follows:

νO=νCY+νLS  (Equation 4)

(vCY is equal to NVIN/(1−d)−2Nvk1 which will be described in detail later, where d is a duty cycle of the first switch (S1)). In the first mode, the current (iLP) flowing through the first winding (LP) includes the exciting current (iLM) and an induced current. When the waveform of the current (is1) flowing through the first switch (S1) is close to being a square shape through appropriate configuration of the exciting inductance (LM) and the coupling coefficient (k), the first switch (S1) has relatively low conduction loss and switching loss.

Referring to FIGS. 5a to 5i, and 7, the boost unit 4 is operated in the second mode during a period from t1 to t2. In the second mode, the first and second switches (S1, S2) are in the OFF-state, and the diodes (D1, D4) and the first diode (DW) conduct. Energy attributed to the leakage inductance (Lk1) of the first winding (LP) is released to the transformer (Tr) such that the second winding (LS) is operated as in the first mode. In this case, the current (iLP) flowing through the first winding (LP) begins to charge a parasitic capacitance of the first switch (S1) such that the voltage (vS1) across the first switch (S1) rises (see FIG. 5e). On the other hand, a parasitic capacitance of the second switch (S2) discharges such that the voltage (vS2) across the second switch (S2) reduces to zero (see FIG. 5f). Thus, a sum of the voltage (vS1) across the first switch (S1) and the voltage (vS2) across the second switch (S2) is equal to a sum of a voltage (vCX) across the clamp capacitor (CX) and the DC voltage input (VIN). That is,

νS1+νS2=VIN+νCX  (Equation 5)

Referring to FIGS. 5a to 5i, and 8, the boost unit 4 is operated in the third mode during a period from t2 to t3. In the third mode, the first switch (S1) is in the OFF-state, and the second switch (S2) is in the ON-state. When the voltage (vS2) across the second switch (S2) is zero, a substrate diode (DS2) of the second switch (S2) conducts such that the current (iLX) flowing through the inductor (LX) and the current (iLP) flowing through the first winding (LP) flow to the clamp capacitor (CX). Thus, the voltage (vS1) across the first switch (S1) is clamped. When the duty cycle of the first switch (S1) is represented by “d”, based on the voltage-second theorem, the voltage (vCX) across the clamp capacitor (CX) is determined according to the following Equation 2:

νCX=VINd/(1−d)  (Equation 6)

According to the Equations 5 and 6, a maximum value of the voltage (vS1) across the first switch (S1) is represented as follows:

νS1=VIN+νCX=VIN/(1−d)  (Equation 7)

Since energy attributed to the leakage inductance (LK1) of the first winding (LP) is released, the current (iLS) flowing through the first winding (LP) decreases to zero at t3 (see FIG. 5c). The voltage (vLS) across the second winding (LS) is represented as follows:

νLS=NVINd/(1−d)  (Equation 8)

The current (iLS) flowing through the second winding (S2) is reversed and gradually increases such that a parasitic capacitance of the second diode (DY) of the boost unit 4 discharges and that a parasitic capacitance of the first diode (DW) is charged. Therefore, the relationship among the voltage (vDW) across the first diode (DW), the voltage (vDY) across the second diode (DY) and the voltage (vCY) across the first capacitor (CY) is determined according to the following equation 9:

νDW+νDY=νCY  (Equation 9)

According to the Equation 3, the voltages (vDW, vDY) across the first and second diodes (DW, DY) clamp each other, and each of the voltages (vDW, vDY) across the first and second diodes (DW, DY) has a maximum value equal to vCY. In this case, a part of the current (iLS) flowing through the second winding (LS) flows through the output capacitor (CO) and substrate diodes (DT4′, DT1′) of the switches (T4, T1) such that parasitic capacitances of the diodes (D4, D1) are charged with a small amount of current. Thus, the diodes (D4, D1) become cut off. During the third mode, the first and second diodes (DY, DW) and the diodes (D1, D2, D3, D4) have a very small reversed recovery current as a result of the leakage inductance (Lk2).

Referring to FIGS. 5a to 5i, and 9, the boost unit 4 is operated in the fourth mode during a period from t3 to t4. In the fourth mode, the first switch (S1) is in the OFF-state, the second switch (S2) is in the ON-state, and the second diode (DY) conducts. The current (iLP) flowing through the first winding (LP) decreases to zero at t3, and then reversely increases. In this case, the clamp capacitor (CX) discharges through the second switch (S2). The current (iCX) flowing through the clamp capacitor (CX) and the exciting current (iLM) reversely flow to the first winding (LP). Thus, the induced voltage (vLS) across the second winding (LS) is equal to N times the voltage (vCX) across the clamp capacitor (CX), and the first capacitor (CY) is charged through the second diode (DY) with the induced voltage (vLS) across the second winding (LS) and the voltage (vCW) across the second capacitor (CW). Referring to the Equations 2 and 5, the voltage (vCY) across the first capacitor (CY) is determined according to the following Equation 10:

νCY=νLS+νCW=NVIN/(1−d)−2NVk1  (Equation 10)

According to the Equation 3, the voltages (vD1, vD4) across the diodes (D1, D4) are determined according to the following Equation 11:

νD1+νD4=νO−νCW−NVIN  (Equation 11)

Referring to FIGS. 5a to 5i, and 10, the boost unit 4 is operated in the fifth mode during a period from t4 to t5. In the fifth mode, the first and second switches (S1, S2) are in the OFF-state, and the second diode (DY) conducts. The parasitic capacitance of the second switch (S2) is charged and the parasitic capacitance of the first switch (S1) discharges. When the parasitic capacitance of the first switch (S1) discharges to zero, the substrate diode (DS1) of the first switch (S1) conducts such that the voltage (vS2) across the second switch (S2) is clamped to VIN+vCX. Therefore, the second switch (S2) has the same clamp voltage as that of the first switch (S1).
Referring to FIGS. 5a to 5i, and 11, the boost unit 4 is operated in the sixth mode during a period from t5 to t6. In the sixth mode, the first switch (S1) is switched from the OFF-state to the ON-state, the second switch (S2) is in the OFF-state, and the second diode (DY) conducts. When the first switch (S1) is switched from the OFF-state to the ON-state, due to the leakage inductance (Lk1), an inrush current can be avoided. Therefore, the current (iLP) flowing through the first winding (LP) cannot become positive at once such that the second winding (LS) is operated as in the fifth mode. Energy attributed to the exciting inductance (LM) decreases and is released to the second winding (LS). Since the substrate diode (DS1) of the first switch (S1) still conducts, as shown in FIG. 5e, the first switch (S1) has zero-voltage switching characteristics during transformation from the OFF-state to the ON-state.
Referring to FIGS. 5a to 5i, and 12, the boost unit 4 is operated in the seventh mode during a period from t6 to t7. In the seventh mode, the first switch (S1) is in the ON-state and the second switch (S2) is in the OFF-state. When the current (iLP) flowing through the first winding (LP) has an amplitude equal to that of the exciting current (iLM) of the transformer (Tr), the first winding (LP) receives energy again such that the current (iLS) flowing through the second winding (LS) linearly increases. At the same time, the voltage across the exciting inductance (LM) is induced to the second winding (LS) through the first winding (LP) such that the current flowing through the second winding (LS) reversely increases again. In this case, the parasitic capacitances of the first diode (DW) and the diodes (D1, D4) discharge, and the parasitic capacitance of the second diode (DY) is charged.
When the parasitic capacitances of the first diode (DW) and the diodes (D1, D4) discharge to zero, the first diode (DW) and the diodes (D1, D4) conduct such that the output capacitor (CO) and the second capacitor (CW) are charged through the diodes (D1, D4) with the current flowing through the second winding (LS). Charging paths are the same as that of the first mode. When the exciting current of the transformer (Tr) gradually increases, the induced current flowing through the second winding (LS) gradually decreases, and then, the boost unit 4 returns to the first mode.
According to the Equations 3 and 10, the output voltage (vO) is represented as follows:




  
    
      
        
          v
          O
        
        =
        
          
            
              v
              CW
            
            +
            
              v
              CY
            
          
          =
          
            
              
                NV
                IN
              
              ⁢
              
                
                  (
                  
                    2
                    -
                    d
                  
                  )
                
                
                  (
                  
                    1
                    -
                    d
                  
                  )
                
              
            
            -
            
              4
              ⁢
              
                Nv
                
                  k
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          12
        
        )
      
    
  




Thus, a voltage gain (GV) of the power converting device is represented as follows:





  
    
      
        
          G
          V
        
        =
        
          
            
              
              
                v
                O
              
              
            
            
              V
              IN
            
          
          =
          
            
              N
              ⁢
              
                
                  (
                  
                    2
                    -
                    d
                  
                  )
                
                
                  (
                  
                    1
                    -
                    d
                  
                  )
                
              
            
            -
            
              
                4
                ⁢
                
                  Nv
                  
                    k
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              
                V
                IN
              
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          13
        
        )
      
    
  




where 0≦d<1 such that





  N
  ⁢
  
    
      (
      
        2
        -
        d
      
      )
    
    
      (
      
        1
        -
        d
      
      )
    
  




is greater than 2N.

According to the Equation 13, by appropriately selecting d and vk1, the voltage gain (GV) of less than one can be obtained. Therefore, the power converting device of the present invention can further provide step-down function.
When the power converting device is in a step-down operation, referring to FIGS. 13a and 13b, if the external power source, such as a solar cell unit, provides the current (iIN) during the ON-state of the first switch (S1), iAVG represents an average current during one cycle. VO and IO represent effective values of the voltage across the output capacitor (CO) and the current flowing through the output capacitor (CO), respectively. R represents an impedance of a load (not shown). PIN and PO represent input and output powers, respectively. η represents a power transformation efficiency of the power converting device. As a result, PIN·η=PO. To simplify analysis, assuming η=1, the relationship between the input and output powers (PIN, PO) is represented as follows:

PIN=PO  (Equation 14)

VIN·iAVG=VO·IO=VO2/R  (Equation 15)

Since the second switch (S2) is in the OFF-state, iAVG=iLP. Therefore, the Equation 15 can be represented as follows:





  
    
      
        
          
            V
            IN
          
          ·
          
            
              d
              ·
              
                i
                P
              
            
            2
          
        
        =
        
          
            V
            O
            2
          
          R
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          16
        
        )
      
    
  




where iP is a maximum value of iLP. Thus, iP can be represented as follows:





  
    
      
        
          i
          P
        
        =
        
          
            2
            ·
            
              V
              O
              2
            
          
          
            R
            ·
            
              V
              IN
            
            ·
            d
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          17
        
        )
      
    
  




Referring to the Equation 4, vk1 can be represented as follows:





  
    
      
        
          v
          
            k
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            
              L
              
                k
                ⁢
                
                  
                
                ⁢
                1
              
            
            ⁢
            
              
                Δ
                ⁢
                
                  
                
                ⁢
                
                  i
                  P
                
              
              
                d
                ⁢
                
                  
                
                ⁢
                t
              
            
          
          =
          
            
              2
              ·
              
                
                  L
                  1
                
                ⁡
                
                  (
                  
                    1
                    -
                    k
                  
                  )
                
              
              ·
              
                V
                O
                2
              
            
            
              R
              ·
              
                V
                IN
              
              ·
              
                d
                2
              
              ·
              T
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          18
        
        )
      
    
  




where T is a period of one cycle of vGS1, i.e., a reciprocal of the switching frequency (fS) of the first switch (S1). The Equation 18 is introduced into the Equation 13, the voltage gain (GV) of the power converting device can be represented as follows:





  
    
      
        
          G
          V
        
        =
        
          
            
              v
              O
            
            
              V
              IN
            
          
          =
          
            
              N
              ⁢
              
                
                  (
                  
                    2
                    -
                    d
                  
                  )
                
                
                  (
                  
                    1
                    -
                    d
                  
                  )
                
              
            
            -
            
              8
              ⁢
              N
              ⁢
              
                
                  
                    
                      L
                      1
                    
                    ⁡
                    
                      (
                      
                        1
                        -
                        k
                      
                      )
                    
                  
                  ·
                  
                    V
                    O
                    2
                  
                  ·
                  
                    f
                    S
                  
                
                
                  R
                  ·
                  
                    V
                    IN
                    2
                  
                  ·
                  
                    d
                    2
                  
                
              
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          19
        
        )
      
    
  




Then, the Equation 20 can be determined as follows:





  
    
      
        
          
            
              
                8
                ⁢
                
                  N
                  ·
                  
                    
                      L
                      1
                    
                    ⁡
                    
                      (
                      
                        1
                        -
                        k
                      
                      )
                    
                  
                  ·
                  
                    f
                    S
                  
                
              
              
                R
                ·
                
                  d
                  2
                
              
            
            ·
            
              G
              V
              2
            
          
          +
          
            G
            V
          
          -
          
            
              N
              ⁡
              
                (
                
                  2
                  -
                  d
                
                )
              
            
            
              (
              
                1
                -
                d
              
              )
            
          
        
        =
        0
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          20
        
        )
      
    
  




In the Equation 20, assuming that




  
    a
    =
    
      
        8
        ⁢
        
          N
          ·
          
            
              L
              1
            
            ⁡
            
              (
              
                1
                -
                k
              
              )
            
          
          ·
          
            f
            S
          
        
      
      
        R
        ·
        
          d
          2
        
      
    
  




  
    b
    =
    1
  




  
    
      c
      =
      
        -
        
          
            N
            ⁡
            
              (
              
                2
                -
                d
              
              )
            
          
          
            (
            
              1
              -
              d
            
            )
          
        
      
    
    ,
  



since GV>0, the Equation 20 has a solution of GV as follows:




  
    
      
    
    ⁢
    
      
        
          G
          V
        
        =
        
          
            
              -
              b
            
            +
            
              
                
                  b
                  2
                
                -
                
                  4
                  ·
                  a
                  ·
                  c
                
              
            
          
          
            2
            ·
            a
          
        
      
      ,
      or
    
  




  
    
      G
      V
    
    =
    
      
        [
        
          
            R
            ·
            
              d
              2
            
          
          
            16
            ⁢
            
              N
              ⁡
              
                (
                
                  1
                  -
                  k
                
                )
              
            
            ⁢
            
              
                L
                P
              
              ·
              
                f
                S
              
            
          
        
        ]
      
      ·
      
        [
        
          
            -
            1
          
          +
          
            
              1
              +
              
                
                  32
                  ⁢
                  
                    
                      N
                      2
                    
                    ⁡
                    
                      (
                      
                        2
                        -
                        d
                      
                      )
                    
                  
                  ⁢
                  
                    (
                    
                      1
                      -
                      k
                    
                    )
                  
                  ⁢
                  
                    
                      L
                      P
                    
                    ·
                    
                      f
                      S
                    
                  
                
                
                  
                    (
                    
                      1
                      -
                      d
                    
                    )
                  
                  ⁢
                  
                    (
                    
                      R
                      ·
                      
                        d
                        2
                      
                    
                    )
                  
                
              
            
          
        
        ]
      
    
  



FIG. 14 illustrates experimental results of power transformation efficiency (η) of the power converting device of the preferred embodiment operated under a condition, where the DC voltage input (VIN) is 18 volts. As shown in FIG. 14, the power converting device has maximum power transformation efficiency (η) over 92%.
The following are some of the advantages attributed to the power converting device of the present invention:
1. The first and second switches (S1, S2), the first and second diodes (DW, DY), and the diodes (D1, D2, D3, D4) have soft switching characteristics.
2. Due to the presence of the transformer (Tr), the power converting device of the present invention has electrical isolation capability.
3. The power converting device of the present invention has relatively high power transformation efficiency.
While the present invention has been described in connection with what is considered the most practical and preferred embodiment, it is understood that this invention is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

## Claims

1. A power converting device for converting a DC voltage input from an external power source into an AC voltage output, said device comprising:
a transformer having first and second windings, each having opposite first and second ends, said first end of said first winding being adapted to be coupled to the external power source;
a clamp unit coupled to said transformer and adapted to be coupled to the external power source, said clamp unit including
a first switch coupled between a reference node and said second end of said first winding of said transformer, and operable between an ON-state and an OFF-state, and
a series connection of a clamp capacitor and a second switch coupled across said first winding of said transformer, said second switch being operable between an ON-state and an OFF-state; and
an inverting unit coupled to said first end of said second winding of said transformer, and operable so as to output the AC voltage output based on an induced voltage across said second winding of said transformer
wherein said inverting unit includes
a full-bridge circuit including a first series connection of first and second switch units, and a second series connection of third and fourth switch units, said first and second series connections being coupled in parallel between said first end of said second winding of said transformer and said reference node, each of said first, second, third and fourth switch units including a diode and a switch coupled in series to each other, said switch of each of said first, second, third and fourth switch units being operable between an ON-state and an OFF-state, and
an output capacitor coupled between a first common node between said first and second switch units, and a second common node between said third and fourth switch units, the AC voltage output being a voltage across said output capacitor, said output capacitor being capable of being charged through said full-bridge circuit with the induced voltage across said second winding of said transformer;
said power converting device further comprising a boost unit coupled across said second winding of said transformer, said boost unit being capable of being charged with the induced voltage across said second winding of said transformer, and of charging said output capacitor through said full-bridge circuit so as to boost the voltage across said output capacitor, said boost unit including
a first capacitor coupled between said second end of said second winding of said transformer and said reference node, said output capacitor being further charged with a voltage across said first capacitor when said output capacitor is charged with the induced voltage across said second winding of said transformer,
a series connection of a first diode and a second capacitor coupled in parallel to said second winding of said transformer, said first diode having an anode coupled to said second capacitor, and a cathode coupled to said second end of said second winding of said transformer, said second capacitor being capable of being charged through said first diode with the induced voltage across said second winding of said transformer when said output capacitor of said inverting unit is charged with the induced voltage across said second winding of said transformer, and
a second diode having an anode coupled to said reference node, and a cathode coupled to a common node between said anode of said first diode and said second capacitor, said first capacitor being capable of being charged through said second diode with a voltage across said second capacitor.

2. The power converting device as claimed in claim 1, wherein:
said first switch unit is coupled to said third switch unit, and said second switch unit is coupled to said fourth switch unit;
said switches of said first and fourth switch units are simultaneously in the ON-state, and said switches of said second and third switches are simultaneously in the ON-state; and
when said switch of said first switch unit is in the ON-state, said switch of said second switch unit is in the OFF-state.

3. The power converting device as claimed in claim 2, wherein:
when said switches of said first and fourth switch units are in the ON-state, said output capacitor is charged so that the AC voltage output is a positive half of a sinusoidal signal; and
when said switches of said second and third switch units are in the ON-state, said output capacitor is reversely charged so that the AC voltage output is a negative half of the sinusoidal signal.

4. The power converting device as claimed in claim 1, wherein a duration of the ON-state of one of said first and second switches of said clamp unit does not overlap a duration of the ON-state of the other one of said first and second switches of said clamp unit.

5. The power converting device as claimed in claim 1, wherein said first and second ends of said first winding of said transformer are polarity and non-polarity ends, respectively, said first and second ends of said second winding of said transformer being polarity and non-polarity ends, respectively.