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High-Efficiency CdTe and CIGS 

Thin-Film Solar Cells: Highlights 

and Challenges 

Preprint 

R. Noufi and K. Zweibel 

Presented at the 2006 IEEE 4th World Conference on 

Photovoltaic Energy Conversion (WCPEC-4) 

Waikoloa, Hawaii 

May 7–12, 2006 

Conference Paper 

NREL/CP-520-39894 

May 2006 
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HIGH-EFFICIENCY CDTE AND CIGS THIN-FILM SOLAR CELLS: 

HIGHLIGHTS AND CHALLENGES*

Rommel Noufi and Ken Zweibel 

National Renewable Energy Laboratory, Golden, CO 80401, USA 

ABSTRACT 

Thin-film photovoltaic (PV) modules of CdTe and 

Cu(In,Ga)Se2 (CIGS) have the potential to reach costeffective PV-generated electricity. These technologies 

have transitioned from the laboratory to the market place. 

Pilot production and first-time manufacturing are ramping 

up to higher capacity and enjoying a flood of venturecapital funding. CIGS solar cells and modules have 

achieved 19.5% and 13% efficiencies, respectively. 

Likewise, CdTe cells and modules have reached 16.5% 

and 10.2% efficiencies, respectively. Even higher 

efficiencies from the laboratory and from the 

manufacturing line are only a matter of time. 

Manufacturing-line yield continues to improve and is 

surpassing 85%. Long-term stability has been 

demonstrated for both technologies; however, some 

failures in the field have also been observed, emphasizing 

the critical need for understanding degradation 

mechanisms and packaging options. These two thin-film 

technologies have a common device/module structure: 

substrate, base electrode, absorber, junction layer, top 

electrode, patterning steps for monolithic integration, and 

encapsulation. The monolithic integration of thin-film solar 

cells can lead to significant manufacturing cost reduction 

compared to crystalline Si technology. The CdTe and 

CIGS modules share common structural elements. In 

principle, this commonality should lead to similar 

manufacturing cost per unit area, and thus, the module 

efficiency becomes the discriminating factor that 

determines the cost per watt. The long-term potential of 

the two technologies require R&D emphasis on science 

and engineering-based challenges to find solutions to 

achieve targeted cost-effective module performance, and 

in-field durability. Some of the challenges are common to 

both, e.g., in-situ process control and diagnostics, thinner 

absorber, understanding degradation mechanisms, 

protection from water vapor, and innovation in high-speed 

processing and module design. Other topics are specific to 

the technology, such as lower-cost and fast-deposition 

processes for CIGS, and improved back contact and 

voltage for CdTe devices. 

INTRODUCTION 

Rapid technical progress has occurred in both the CdTe 

and Cu(In,Ga)Se2 (CIGS) thin-film PV technologies. 

Advances have been made in the following areas: 

materials delivery and film growth, control of film 

properties at the micro and nano levels, understanding 

how the device works (device physics) and how to 

improve the properties of individual layers, intrinsic device 

stability, and prototype module reliability. The results from 

these advances have helped both technologies evolve 

from the laboratory to the marketplace. The existing 

industry, joined by new start-up entities supported by 

venture capital, continues to work toward expanded 

capacity from pilot production to first-time manufacturing 

and beyond. Perhaps the most impressive advance is the 

success by First Solar, which is transitioning toward a 75-

MW capacity to produce commercial CdTe modules with 

power output greater than 67 W. 

In this paper, we present highlights of the CIGS and CdTe 

technologies, and address key challenges that need to be 

overcome to accelerate the commercialization of the two 

technologies. 

HIGHLIGHTS OF CIGS AND CdTe TECHNOLOGIES 

Laboratory Devices. The CIGS thin film belongs to the 

multinary Cu-chalcopyrite system, where the bandgap can 

be modified by varying the Group III (on the Periodic 

Table) cations among In, Ga, and Al and the anions 

between Se and S [1,2]. A wide range of bandgaps can 

be obtained using combinations of different compositions. 

The bandgap range of interest for this technology is 

between 1 and 1.7 eV[3]. The CdTe material in the device 

mostly exists as a binary with a slight deviation from 

stoichiometry. Its bandgap is about 1.5 eV, which is a 

good match to the solar spectrum. In the device, this 

bandgap may vary somewhat as a result of its interaction 

with the CdS (~2.4-eV bandgap) heterojunction partner 

during processing [4]. Table 1I summarizes champion 

efficiencies of CdTe devices and Cu(In,Ga,Al)(Se,S)2-

based devices of different compositions. 

Table 2 compares champion efficiency and power of 

different commercial-sized CIGS, CIGSS, and CdTe 

modules from leading companies. The results show that 

the performance of the CIGS and CdTe modules are now 

approaching that of polycrystalline silicon PV. In addition 

to improved efficiency, we also see demonstrated high 

throughputs and/or higher yields. 

Figure 1 shows a schematic of the CdTe and CIGS device 

structure. Individual layer thicknesses are approximate 

and may differ somewhat among laboratories. For 

*This work has been authored by an employee or employees of the Midwest Research Institute under Contract No. DE-AC36-99GO10337 with the U.S. 

Department of Energy. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States 

Government retains a non-exclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this work, or allow others to do so, 

for United States Government purposes. 

1
Area 

(cm2

) 

VOC

(V) 

JSC

(mA/cm2

) 

FF 

(%) 

Efficienc

y (%) 

Comments 

CIGSe 0.410 0.697 35.1 79.52 19.5 CIGSe/CdS/Cell NREL, 3-stage process 

CIGSe 0.402 0.670 35.1 78.78 18.5 CIGSe/ZnS (O,OH) NREL, Nakada et al. 

CIGS 0.409 0.830 20.9 69.13 12.0 Cu(In,Ga)S2/CdS Dhere, FSEC 

CIAS — 0.621 36.0 75.50 16.9 Cu(In,Al)Se2/CdS IEC, Eg = 1.15 eV 

CdTe 1.03 0.845 25.9 75.51 16.5 CTO/ZTO/CdS/CdTe NREL, CSS 

CdTe — 0.840 24.4 65.00 13.3 SnO2/Ga2O3/CdS/CdTe IEC, VTD

CdTe 0.16 0.814 23.56 73.25 14.0 ZnO/CdS/CdTe/Metal U. of Toledo, sputtered

 Table 1. Thin Film CIGS Solar Cells Efficiencies

Fig. 1. CdTe and CIGS Device Structure 

comparison, cross sections of scanning electron 

micrographs are shown to provide true physical 

perspectives of the structures. Note that the CIGS device 

is a substrate configuration that starts with glass/base 

electrode, whereas the CdTe device is a superstrate 

configuration that starts with glass/transparent top 

electrode. The sequence of the growth of the layers in 

both structures may influence the properties of the front 

and back junctions—that is, the p/n interface and the back 

contact—and, in turn, the efficiency of the devices. 

Company Device Aperture Area 

(cm2

)

Efficiency (%) Power (W) Date

Global Solar CIGS 8390 10.2* 88.9* 05/05

Shell Solar CIGSS 7376 11.7* 86.1* 10/05

Würth Solar CIGS 6500 13.0 84.6 06/04

First Solar CdTe 6623 10.2* 67.5* 02/04

Shell Solar GmbH CIGSS 4938 13.1 64.8 05/03

Antec Solar CdTe 6633 7.3 52.3 06/04

Shell Solar CIGSS 3626 12.8* 46.5* 03/03

Showa Shell CIGS 3600 12.8 44.15 05/03

 *NREL Confirmed 

 Table 2. Polycrystalline Thin Film PV Modules

The most common deposition methods for the CdTe 

device involve acquiring commercial SnO2-coated glass, 

or the deposition of cadmium stannate and zinc stannate 

by sputtering, followed by chemical-bath deposition (CBD) 

of CdS. The CdTe thin-film absorber is usually applied by 

close-spaced sublimation, vapor-transport deposition, or 

electrodeposition, followed by CdCl2 treatment. The back 

contact is then applied after a chemical preparation 

(etching) of the back surface of CdTe. The nature of the 

back contact varies—from a carbon paste containing 

CuxTe and HgTe, to a combination of other metals with 

Cu. The inclusion of a form of Cu, with the back contact, is 

necessary; its effect on the performance and stability of 

the device is the subject of intense investigations.[5,6] 

The CIGS device starts with sputtered Mo on glass. The 

Mo film properties have to be optimized for adhesion, 

sheet resistance, and morphology where it allows sodium 

(Na) from the glass to diffuse through to the CIGS layer. 

Sodium aids the CIGS grain growth and increases the 

carrier concentration. The optimum concentration of Na is 

about 0.1% (atomic). Growth on non-Na-containing 

substrates requires dosing of the CIGS film by introducing 

a 60 to 120 Å NaF layer on the Mo back contact, or 

introducing NaF during the CIGS deposition. The absence 

of Na in the device reduces the efficiency by 2% to 3% 

(absolute). The CIGS absorber is deposited using several 

methods of flux delivery: evaporation of elements 

simultaneously or in a prescribed sequence, sputtering of 

metals followed by selenization with H2Se, reactive 

sputtering of metals with Se vapor, or printing of metals 

2
from ink precursors followed by selenization. The latter 

method requires no vacuum. The CdS layer is applied by 

CBD, followed by sputter deposition of a bilayer consisting 

of intrinsic and conducting ZnO. The ZnO layer is also 

applied by using the chemical-vapor deposition process. 

The industrial processes for both technologies basically 

adopt combinations of the techniques, as described 

above. 

The CIGS and CdTe modules share common 

characteristics and device structural elements. Therefore, 

in principle, the cost per unit area should be similar, and, 

thus, the efficiency becomes a discriminating factor for the 

cost/watt. However, in practice, production processes in 

terms of throughput and yield can differ significantly and 

may offset the advantage of higher performance. This is 

the case at this time, where the cost of producing CdTe 

modules has an advantage over CIGS. In future years, 

semiconductor costs may become more prominent drivers. 

The long-term potential of the two technologies requires 

R&D emphasis on science and engineering-based 

challenges to find solutions to achieve targeted, costeffective module performance and in-field durability. 

Scientists and engineers in the thin-film community have 

demonstrated some successes in this regard. 

Transitioning knowledge, especially in the area of 

production processes, from the laboratory to 

manufacturing has proven much more difficult than 

anticipated. Because of the inherent complexity of the two 

compound semiconductors, much more research is 

needed. 

Challenges. We list some key challenges that must be 

addressed to accelerate progress and contribute to 

commercial success. The list is not comprehensive and 

does not go into detail due to lack of space. 

1. Science and Engineering Support. There is a great 

need to enhance the science and engineering knowledge 

base from which to (a) derive measurable material 

properties that are predictive of device and module 

performance, (b) model the relationship between film 

growth and material delivery, and (c) couple this 

knowledge to industrial processes. The beneficial impacts 

expected are higher throughput and yield at every step of 

the process, and a higher degree of reliability and 

reproducibility, which, of course, will lead to higher 

performance. 

2. Long-Term Stability. Both technologies have shown 

long-term stability. However, degradation of performance 

has also been observed. So, why do some modules 

maintain stable performance, while others fail? This 

question begs for a better understanding of degradation 

mechanisms at the device level and prototype module 

level, to distinguish the intrinsic device contributions from 

the extrinsic mechanisms that may result from the 

packaging process. Infiltration of water vapor through the 

encapsulation package has been shown to degrade 

performance. Hence, developing a thin-film barrier to 

water vapor will boost in-field durability. Much work has 

been done to monitor and investigate performance of 

CIGS and CdTe modules in the outdoors. To date, the 

level of understanding the causes of performance 

degradation is inadequate and lacks the coupling of 

feedback from device- and module-level studies. Recently, 

Albin et al. [7,8,9] at NREL investigated the temperaturedependent degradation of CdTe devices. The findings 

point out that different mechanisms dominate degradation 

at different temperatures. From 90°

 to 120°C, the 

degradation is dominated by Cu diffusion from the back 

contact toward the electrical junction, whereas the source 

of possible degradation from 60°

 to 90°C is not currently 

known, and may simply reflect straying outside a process 

window. Such studies help to identify relevant and 

appropriate accelerated test protocols. Another issue 

requiring further consideration is the need for 

encapsulants that can be applied and cured at room 

temperature and that are chemically inert toward the 

semiconductor layer with which they come in contact. 

3. In-Situ Process Diagnostics and Control. To date, 

very little exists in the area of in-situ diagnostics and 

control for both the CIGS and CdTe technologies. This 

situation is because science-based knowledge of material 

properties is inadequate to serve as a solid foundation 

from which diagnostics tools can be developed. These 

tools must be developed such that they can respond to 

rapid processing and feedback for adjusting real-time 

processes. The results will impact throughput and yield, 

and will make the process reproducible and reliable. 

Currently, only a few techniques are in practice, based on 

changes of emissivity from the growing surface, and in-situ 

monitoring of composition using X-ray fluorescence. 

4. Thinner CIGS and CdTe Absorbers. This challenge is 

motivated by concerns over the availability and price of In 

and Te. This concern currently seems more severe for In 

than Te because of competing uses (flat panel displays). 

For example, the availability of In will begin to have a 

significant impact at a production capacity level of tens of 

gigawatts. Reducing the absorber thickness also yields 

other benefits, especially for CIGS—for example, higher 

throughput and less material cost. The primary challenge 

will be to thin the absorber to below 0.5 μm, while 

maintaining state-of-the-art performance. Potential pitfalls 

also exist for going very thin, including nonuniformity, 

shunting/pinholes, lower yields, and a need to change 

device structure from the current norm. Table 3 

summarizes the status of performance for laboratory 

devices for very thin CIGS and CdTe absorbers [10,11]. 

The drop in performance, currently begins to become 

significant below a thickness of 1 μm, but that is likely an 

artifact of our rudimentary knowledge. Studies guided by 

device modeling are under way to understand the loss 

mechanism for very thin absorbers [12,13]. 

5. Need for High-Throughput, Low-Cost Processes. 

This challenge is more relevant to CIGS technology. 

Currently, the best-performing devices and large modules 

are produced in two ways: by evaporation of the elements 

in vacuum; and by sputtering of the metals, followed by 

selenization with H2Se. These two processes suffer from 

3
relatively slow throughput, poor material utilization, and 

relatively high vacuum. Deposition by high-rate cosputtering from cylindrical magnetrons is now being 

pursued; however, to date, this approach has not 

demonstrated state-of-the-art performance. A lower-cost 

process should feature high deposition rates, high material 

utilization, and simpler equipment capable of processing 

very large substrates. One such example is a process that 

uses nano-components to make printable precursors that 

are crystallized into CIGS [14,15]. 

t (μm) VOC (V) JSC

(mA/cm2

) 

 FF 

(%)

Efficiency 

(%)

1.0 CIGS 0.676 31.96 79.47 17.16 

NREL

0.75 CIGS 0.652 26.0 74.0 12.5

0.40 CIGS 0.565 21.3 75.7 9.1

0.47 CIGS 0.576 26.8 64.2 9.9 

EPV

1. CIGSS 

Module

25.26 2.66 69.2 12.8 

Shell 

Solar

0.87 CdTe 0.772 22.0 69.7 11.8 

U. of 

Toledo

Table 3. Summary-Thin Cells Efficiencies 

6. Improved Open-Circuit Voltage (Voc) in CdTe 

Devices. The primary parameter needed to improve and 

achieve high efficiency in CdTe devices is Voc, whose 

magnitude is affected by junction properties, bulk carrier 

concentration, and the back contact. Enhanced Voc may 

be achieved by increasing the net p-type doping of the 

bulk through extrinsic doping, or, more likely, by better 

crystal growth conditions that influence more favorable 

formation of native point defects. 

ACKNOWLEDGEMENTS 

The authors acknowledge contributions to this paper from: 

Polycrystalline Thin Film Group, Measurement and 

Characterization, K. Zweibel, H. Ullal, B. von Roedern – 

NREL, Dale Tarrant – Shell Solar Industries, Robert 

Birkmire – IEC, U. of Delaware, Bernhard Dimmler – 

Wurth Solar, Dennis Hollars – MIASOLE, Jeff Britt and 

Scott Wiedeman – Global Solar Energy, Tim Anderson – 

U. of Florida, and W.S. Sampath – AVA Tech, Peter 

Meyers – First Solar. This work is support or funded 

under DOE Contract No. DE-AC36-99GO10337. 

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