# Patent

## Title
Differential signaling system and flat panel display with the same

## Abstract

A differential signaling system, wherein a first wiring and a second wiring are coupled between a sending end and a receiving end as a differential signal line. A termination resistor is coupled between the first wiring and the second wiring in the receiving end side. A test circuit is coupled to the termination resistor in parallel, and amplifies and detects a variation of a differential impedance due to the differential signal line. The test circuit includes: a differential test amplifier for amplifying a variation in the differential impedance of the first wiring or the second wiring; a switching unit installed at an input terminal of the differential test amplifier for controlling an operation of the differential test amplifier; and a peak detector for converting an output signal of the differential test amplifier into a direct current component.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Application No. 2007-32572, filed Apr. 2, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
Aspects of the present invention relate to a flat panel display that uses a signal transmission method that transmits a differential signal, and more particularly to a flat panel display that includes a differential signaling system for matching impedance in the signal transmission method.
2. Description of the Related Art
In general, a cathode ray tube (CRT) is one of display devices which have been in wide use as a monitor for a television, a measuring instrument, or an information terminal. However, since the CRT is heavy and large, it is not suitable to miniaturization and light-weight requirements of smaller electronic devices.
Accordingly, in order to replace the CRT, various flat panel displays, such as a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting display (OLED) have been studied and developed, which have advantages in light of miniaturization, lighter weight, and low electric power consumption requirements. The above described flat panel displays include various components and wirings for transmitting signals between the components.
Recently, aided by the development in electronic circuits and manufacturing process technologies, signals can be transmitted through the wirings at high speeds. To meet the high speed signal transmission requirements, a drive speed of the components has also become high.
Accordingly, various methods for transmitting the high speed signals between the components through the wirings have been adopted. For example, a signal transmission method such a low voltage differential signaling (LVDS) method or a reduced swing differential signaling (RSDS) method for transmitting a differential signal has been used.
A differential signaling system transmits a signal having different modes but having a same amplitude and a different polarity through a differential transmission line. Accordingly, the differential signaling system tends to remove a concentrated magnetic field and tends to couple an electric field. Accordingly, a high speed signal can be stably transmitted without a signal reflection, a skew (phase delay), or electro magnetic interference (EMI) due to the coupled electric field. A flat panel display will be described with reference the accompanying drawings in detail.
FIG. 1 is a block diagram showing a composition of a flat panel display. With reference to FIG. 1, the flat panel display includes a display panel 40, a gate driver 20, a data driver 30, and a controller 10. Pixels (not shown) are arranged at the display panel 40 in a matrix pattern. The gate driver 20 sequentially applies a scan signal to gate wirings of the display panel 40. The data driver 30 applies an image signal DATA1 to data wirings of the display panel 40. The controller 10 applies the image signal DATA1 from an external graphic controller (not shown) to the data driver 30, and applies a control signal CS1 to the gate driver 20 and the data driver 30 in order to control a drive timing. In the flat panel display, after all gate wirings of the display panel 40 are sequentially scanned and the image signal DATA1 is applied to the pixels through the data wirings to display one frame of an image, a vertical synchronous signal VSYNC is applied to display a next frame of the image.
FIG. 2 is a block diagram showing a controller 10 and a data driver 30 shown in FIG. 1 in detail. FIG. 3 is a view showing a signal transmission method between the controller 110 and the data driver 130. With reference to FIG. 2, the data driver 130 comprises a plurality of data driving circuits 132. The plurality of data driving circuits 132 receive image signals DATA [+,−] from the controller 110 through first and second wirings W1 and W2, and receive a control signal CS11 from the controller 110 through a third wiring W3.
The data driving circuits 132 receive image signals DATA [+,−] from the controller 110, and output the image signals DATA [+,−] to the data wirings according to the control signal CS11 from the controller 110. Although not shown in the drawings, a plurality of data wirings are electrically coupled to the data driving circuits 132, and applies the image signals DATA [+,−] that are applied to the data driving circuits 132 and to the pixels. Here, the image signals DATA [+,−] from the controller 110 are transmitted to the respective data driving circuits using the aforementioned differential signal transmission method.
FIG. 3 shows a signal transmission method between the controller 110 and the data driver 130 using a representative diagram of the controller 110, the data driver 130, and a connection thereof. As shown in FIG. 3, in order to transmit data (as image signals DATA [+,−]), an arrangement of differential transmission lines, namely, first and second wirings W1 and W2, is provided between the controller 110 being a sending end Tx and the data driving circuit 132 being a receiving end Rx. A termination resistor Rt is provided between the differential transmission lines at the receiving end (data driving circuit 132) side. The termination resistor Rt electrically connects the first wiring W1 and the second wiring W2 to each other, and the first wiring W1 and the second wiring W2 are coupled to each data driving circuit 132.
Accordingly, the image signal DATA [+] applied through the first wiring W1 is transferred back to the controller 110 through the termination resistor Rt and the second wiring W2. The termination resistor Rt prevents an excessive current from flowing in the data driving circuit 132, and a voltage across the termination resistor Rt is the image signals DATA [+,−], which are applied to the data driving circuit 132.
A plurality of electric components and wirings are provided in the flat panel display, which are electrically coupled to each other. Since the electric components and wirings have impedance values, a signal is attenuated during transmission of the signal between the electric components. That is, the controller 110 and the data driving circuits 132 have impedance values. Further, the first and second wirings W1 and W2 for connecting the controller 110 and the data driving circuits 132 have an impedance value of Z0.
If the impedance value Z0 of the first wirings W1 and W2 is different from that of the data driving circuits 132, namely, when an impedance mismatch occurs, the image signals DATA [+,−] are not accurately supplied to the data driving circuits 132. That is, a part of the image signals DATA [+,−] is reflected and discharged.
In detail, a reflection coefficient Γ is expressed by a following equation 1.




  
    
      
        Γ
        =
        
          
            
              Z
              diff
            
            -
            
              R
              t
            
          
          
            
              Z
              diff
            
            +
            
              R
              t
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          1
        
        ]
      
    
  




where, a differential impedance Zdiff is a value that is less than a sum (2Z0) of impedance values of the first and second wirings W1,W2, and has a different value according to variations in a manufacturing process and a composition of the flat panel display.
Namely, when the differential impedance Zdiff is identical with a value of the termination resistor Rt, a reflection loss of the signals does not occur due to the matched impedances. However, the differential impedance Zdiff varies in practice. Accordingly, in the typical case, the impedance matching (or matched impedance) is not normally achieved when using the differential signal transmission method. When a reflection wave occurs due to mismatched impedances, an interference with the image signals DATA [+,−] applied through the first wiring W1 occurs to cause an unstable wave, and distortion and attenuation of the image signals DATA [+,−]. Also, the electro magnetic interference (EMI) deteriorates an image quality of the flat panel display.
Accordingly, in the differential signaling method, whether the impedance matching is achieved or whether a minute variation of differential impedance Zdiff occurs should always be monitored. However, since a typical method for detecting the minute variation in the differential impedance Zdiff has a long measuring time and uses measuring equipment of high cost, its disadvantages include increased testing cost and low detection rate for a minute variation in the differential impedance Zdiff.
SUMMARY OF THE INVENTION
Accordingly, it is an aspect of the present invention to provide a differential signaling system which may clearly detect a presence of an impedance matching by a test circuit in a flat panel display that uses a differential signal transmission method and to more accurately perform the impedance matching through the detection of the impedance matching in order to stably transmit a high speed signal without an electro magnetic interference, wherein the test circuit detects a variation of a differential impedance and converts the amplified signal into a direct current component, to thereby easily detect the presence of the impedance matching, and a flat panel display with the same.
The foregoing and/or other aspects of the present invention are achieved by providing a differential signaling system including: a differential signal line having a first wiring and a second wiring coupled between a sending end and a receiving end of the system; a termination resistor coupled between the first wiring and the second wiring in the receiving end side of the system; and a test circuit coupled to the termination resistor in parallel to amplify and to detect a variation of a differential impedance due to the differential signal line, wherein the test circuit includes: a differential test amplifier to amplify the variation in the differential impedance of the first wiring or the second wiring; a switching unit installed at an input terminal of the differential test amplifier for controlling an operation of the differential test amplifier; and a peak detector to convert an output signal of the differential test amplifier into a direct current component.
According to an aspect of the present invention, the test circuit is positioned at an outside of the receiving end. The differential test amplifier has input impedance value and an amplification gain value. The peak detector is embodied by a peak detector having a detection constant of 1.
According to another aspect of the present invention, there is provided a flat panel display including: a display panel in which a plurality of data wirings and gate wirings are arranged to intersect each other; a controller to receive an image signal from an exterior and to generate a control signal, and to output the image signal and the control signal through a differential signal line having the first and second wirings; a gate driver to receive the control signal from the controller and to apply a scan signal to the gate wirings; a data driver including a plurality of data driving circuits to receive an image signal and/or a control signal from the controller through the first and second wirings and to apply the image signal to the data wirings; and a test circuit coupled to the termination resistor in parallel to amplify and to detect a variation of a differential impedance due to the differential signal line, wherein the test circuit includes: a differential test amplifier to amplify the variation in the differential impedance of the first wiring or the second wiring; a switching unit installed at an input terminal of the differential test amplifier used for controlling an operation of the differential test amplifier; and a peak detector to convert an output signal of the differential test amplifier into a direct current component.
According to an aspect of the present invention, a differential signaling circuit, includes: a sending end and a receiving end of the differential signaling circuit; a first wiring and a second wiring to connect the sending end and the receiving end, and to carry a differential signal between the sending end and the receiving end; and a test circuit positioned at the receiving end and connected to the first and second wirings, the test circuit generating an amplified output signal from an output signal that is based on a signal voltage of the differential signal, and a variance in a voltage of the amplified output signal is indicative of an impedance variance in the differential signaling circuit.
According to an aspect of the present invention, a method of detecting a variance in an impedance of a differential signaling circuit, includes: transmitting a differential signal over a first wiring and a second wiring of the differential signaling circuit to connect a sending end and a receiving end of the differential signaling circuit; obtaining a signal voltage of the differential signal and generating an output signal based on the signal voltage of the differential signal; and amplifying the output signal to generate an amplified output signal, and amplifying a variance in a voltage of the amplified output signal that is indicative of an impedance variance in the differential signaling circuit.
Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.



BRIEF DESCRIPTION OF THE DRAWINGS
These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a block diagram showing a composition of a typical flat panel display;
FIG. 2 is a block diagram showing a controller and a data driver of FIG. 1 in detail;
FIG. 3 is a view showing a signal transmission method between the controller and the data driver using a representative diagram of the controller, the data driver, and a connection thereof;
FIG. 4 is a block diagram showing a composition of a flat panel display according to an aspect of the present invention;
FIG. 5 is a detailed view showing an aspect of the controller and the data driver shown in FIG. 4;
FIG. 6 is a block diagram showing a differential signaling system according to an aspect of the present invention; and
FIG. 7 is an equivalent circuitry diagram of the differential signaling system shown in FIG. 6.



DETAILED DESCRIPTION OF THE EMBODIMENTS
Reference will now be made in detail to aspects of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The aspects are described below in order to explain the present invention by referring to the figures.
Hereinafter, aspects of the present invention will be described with reference to the accompanying drawings. Here, when one element is coupled to another element, the one element may be not only directly coupled to another element but also indirectly coupled to another element via yet another element. Further, some elements are not shown for clarity.
FIG. 4 is a block diagram showing a composition of a flat panel display 200 according to an aspect of the present invention. With reference to FIG. 4, the flat panel display 200 includes a display panel 240, a gate driver 220, a data driver 230, and a controller 210. Gate lines (or wirings) 221 and data lines (or wirings) 231 are arranged to intersect each other on the display panel 240. The gate driver 220 sequentially applies a scan signal to the gate wirings 221 of the display panel 240. The data driver 230 applies image signals DATA [+,−] to the data wirings 231 of the display panel 240. The controller 210 applies the image signals DATA [+,−] from an external graphic controller (not shown) to the data driver 230, and applies a control signal CS21 to the gate driver 220 and the data driver 230 in order to control a drive timing.
Further, a flat panel display 200 uses a signal transmission method for transmitting a differential signal (also referred to as a differential signaling method). In the flat panel display 200, a test circuit 235 is attached to each driving circuit 232 of the data driver. The test circuit 235 detects a presence of an impedance matching (or matched impedance) when using the differential signaling method. The test circuit 235 is coupled to a receiving end side of an arrangement (such as a circuit) using the differential signaling method, and amplifies a minute variation of a differential impedance in the arrangement to clearly detect the presence of an impedance matching (or matched impedance).
In the display panel 240, a plurality of gate wirings 221 are arranged to be spaced apart from each other at a constant (or regular) interval in a transverse direction, and a plurality of data wirings 231 are arranged to be spaced apart from each other at a constant (or regular) interval in a longitudinal direction. The gate wirings 221 and the data wirings 231 intersect each other to divide a plurality of regions of the display panel 240. The regions are referred to as ‘pixels’. The pixels are electrically coupled to the gate wirings 221 and the data wirings 231, and are arranged on the display panel 240 in a matrix pattern.
The controller 210 represents a timing controller. The controller 210 receives the image signals DATA [+,−] from an exterior thereof (such as an external graphic controller (not shown)) and generates various control signals CS21 to drive the flat panel display 200. The controller 210 applies the image signals DATA [+,−] to the data driver 230, and applies the control signals CS21 to the gate driver 221 and the data driver 230 to control the drive timing. Here, the controller 210 applies a vertical synchronous signal VSYNC, a horizontal synchronous signal HSYNC, a clock signal, a gate start signal, and a data output enable signal to the gate driver 220 and the data driver 230 as the control signals CS21 to control the drive timing of the gate driver 220 and the data driver 230.
That is, the controller 210 applies the horizontal synchronous signal HSYNC and the gate start signal to the gate driver 220 to sequentially apply a scan signal to the gate wirings 221 of the display panel 240. Further, the controller 220 applies the horizontal synchronous signal HSYNC, the data output enable signal, and the image signals DATA [+,−] to the data driver 230, so that the image signals DATA [+,−] are applied to pixels of the gate wiring 221 to which the scan signal is applied. This causes the drive timing of the gate driver 220 and the data driver 230 to be controlled.
The data driver 230 is electrically coupled to the display panel 240 through the data wirings 231. The data driver 230 comprises a plurality of the data driving circuits 232. Each of the data driving circuits 232 receives the image signals DATA [+,−] and the control signals CS21 from the controller 210, and outputs them to the data wirings 231.
The test circuit 235 is coupled to input terminals of each data driving circuit 232. Here, the data driving circuit 232 receives the image signals DATA [+,−] from the controller 210. The test circuit 235 amplifies a minute variation of a differential impedance from the controller 210 to the data driving circuits 232 to clearly detect the presence of the impedance matching. In aspects of the present invention, the test circuit 235 amplifies a minute variation of the differential impedance by detecting the minute variation of the differential impedance and outputting a voltage (or a variation thereof) corresponding to the minute variation of the differential impedance, and then amplifying the voltage (or the variation thereof).
The test circuit 235 can be mounted at the receiving end of the arrangement that uses the differential signaling method, namely, at an inside of the driving circuit 232. However, as shown in FIG. 4, for a user's control convenience, the test circuit 235 can be installed at an outside of the data driving circuit 232.
The following is a detailed composition and operation of the test circuit 235 with reference to the accompanying drawings. As shown in FIG. 4, the gate driver 220 receives control signals CS21 from the controller 210, and sequentially applies a scan signal to the gate wirings 221 to drive the pixels arranged in a matrix pattern. The data driver 230 applies the image signals DATA [+,−] to the pixels to which the scan signal is applied, through the data wirings 231.
Through the aforementioned operation, after all the gate wirings 221 of the display panel 240 are sequentially scanned and the image signals DATA [+,−] are applied to the pixels through the data wirings 231 to display one frame of an image, the vertical synchronous signal VSYNC is applied to display a next frame of the image.
FIG. 5 is a detailed view showing an aspect of the controller and the data driver shown in FIG. 4. FIG. 6 is a block diagram showing a differential signaling system according to an aspect of the present invention. Namely, FIG. 6 is a view illustrating a signal transmission method between the controller and the data driver shown in FIG. 5. FIG. 7 is an equivalent circuitry diagram of the differential signaling system shown in FIG. 6.
With reference to FIG. 5, the flat panel display 300 includes a controller 310 and a data driver 330. The controller 310 receives the image signals DATA [+,−] from an exterior thereof and applies the image signals DATA [+,−] to first and second wirings W11 and W21. The data driver 330 includes a plurality of data driving circuits 332. The plurality of data driving circuits 332 matches an exterior impedance, and receive the image signals DATA [+,−] from the controller 310 through the first and second wirings W11 and W21.
The controller 310 and the data driving circuits 332 transmit the image signals DATA [+,−] and the control signals CS21, for example, by a low voltage differential signaling (LVDS) transmission method, which transmit the signals (the image signals DATA [+,−] and the control signals CS21) at high speeds. That is, the controller 310 is electrically coupled to the data driver 330 through the first and second wirings W11 and W21. The data driver 330 includes a plurality of the data driving circuits 332. Each of the data driving circuits 332 receives the image signals DATA [+,−] from the controller 310 through the first and second wirings W11 and W21. However, for convenience of a description, wirings for supplying the control signals CS21 are omitted in FIG. 5. As shown in FIG. 5, a pair of first and second wirings W11 and W21 is coupled to each data driving circuit 332. However, in practice, plural pairs of the first and second wirings W11 and W21 can be coupled to each data driving circuit 332.
The first and second wirings W11 and W21 are coupled to the data driving circuit 332, and the first and second wirings W11 and W21 are electrically coupled through respective termination resistors Rt to form a closed circuit. That is, each pair of the first wiring W11 and the second wiring W21 is coupled through one termination resistor Rt. Accordingly, the image signals DATA [+,−] from the controller 310 are applied to the terminal resistor Rt with a voltage. The terminal resistor Rt prevents an excessive current from flowing in the data driving circuit 332, and applies to the data driving circuit 332 a particular or constant voltage that is indicative of the image signals DATA [+,−]
Namely, as shown in FIG. 6, in order to transmit data (as image signals DATA [+,−]), an arrangement of differential transmission lines, namely, first and second wirings W11 and W21, are provided between the controller 310, being a sending end Tx, and the data driving circuit 332, being a receiving end Rx. The termination resistor Rt is provided between the differential transmission lines W11, W21 of the data driving circuit 332 being the receiving end. The termination resistor Rt electrically connects the first and second wirings W11 and W21 coupled to each data driving circuit 332, to form a closed circuit.
As described earlier, when only the termination resistor Rt is coupled between the differential transmission lines W11 and W21, a differential impedance Zdiff can vary due to external factors, and if a variation of the differential impedance Zdiff is not be accurately detected, impedance matching cannot be accurately achieved when using the differential signal transmission method
Accordingly, in an aspect of the present invention, a test circuit 335 is coupled to the termination resistor Rt in parallel. The test circuit 335 amplifies a minute variation of differential impedance Zdiff and converts the amplified signal into a direct current component, to thereby easily detect the presence of an impedance matching (or matched impedance). That is, the test circuit 335 amplifies a minute variation of the differential impedance Zdiff by detecting the minute variation of the differential impedance Zdiff and outputting a signal (or a voltage thereof, and then amplifying the signal (or a voltage thereof.
In aspects of the present invention, the test circuit 335 can be mounted inside a receiving end (such as the data driving circuit 332) of the differential transmission lines W11 and W21, or be coupled to be positioned at an outside thereof. That is, the test circuit 335 can be mounted at a receiving end, namely, inside the data driving circuit 332. However, for a user's control convenience, the test circuit 335 can be installed at an outside of the data driving circuit 332, as shown in FIG. 5.
As shown in FIG. 6, the test circuit 335 includes a differential test amplifier TA, a switching unit that includes first and second switches S1 and S2, or two switches, for example, and a peak detector 337. The differential test amplifier TA amplifies a minute variation in differential impedance Zdiff to output a voltage that varies according to the variation in the differential impedance Zdiff. The first and second switches S1 and S2 are installed at input terminals of the differential test amplifier TA. The peak detector 337 converts the output signal of the differential test amplifier TA into a direct current component.
In an aspect of the present invention, the differential test amplifier TA has an input impedance of 50 ohm, and a predetermined amplification gain of G. The differential test amplifier TA amplifies a minute variation of differential impedance Zdiff together with the gain G. Namely, the differential test amplifier TA amplifies a signal component, but removes a high frequency noise component of the image signals DATA [+,−]. In the aspect shown, it is preferred, but not required, that a high frequency amplifier embodies the differential test amplifier TA.
Further, it is preferred, but not required, that high speed switches having very small loss embody the switches S1 and S2. An operation of the switches S1 and S2 controls measuring of a voltage vT (i.e., the voltage across the termination resistor Rt) inputted through the differential transmission line. Furthermore, a peak detector 337 converts an output signal (vT) of the differential test amplifier TA into a direct current component (VT). Namely, the peak detector 337 converts a high frequency output signal (vT) of the differential test amplifier TA into a direct current component (VT). Here, the peak detector 337 is preferably embodied by a peak detector having an envelope detection constant γ of 1.
As illustrated earlier, in the aspect of the present invention, the differential test amplifier TA amplifies a variation value of an impedance of the differential transmission line, namely, a minute variation of the differential impedance to more clearly detect a degree of variation of the impedance of the differential transmission line, and the peak detector 337 converts a final output signal into a direct current voltage, as shown, to easily measure and detect results thereof using a direct current (DC) meter 340.
FIG. 7 is an equivalent circuitry diagram of the differential signaling system shown in FIG. 6. That is, when it is assumed that an input impedance Zin(TA) is 50Ω, a termination resistance RT is 100Ω, and an impedance Z0 of a transmission line is 50Ω, the differential signaling system can be expressed by an equivalent circuit diagram, as shown in FIG. 7. However, the equivalent circuit diagram shows a case when the first and second switches S1 and S2, included in an input terminal of the differential test amplifier, are closed. When the first and second switches S1 and S2 are closed, a minute variation value of the differential impedance Zdiff can be measured.
The following is a detailed explanation of an operation and a principle for measuring the minute variation of the differential impedance in the differential signaling system according to an aspect of the present invention with reference to FIG. 7. The principle for measuring the minute variation of the differential impedance in the differential signaling system is to detect deviation between an impedance Z0 of the transmission line and two input impedances, namely, the termination resistance RT and an input impedance Zin(TA) of the differential test amplifier.
Namely, the differential test amplifier TA included in the test circuit (235, 335) detects the aforementioned deviation. When defects in the transmission line (W11, W21) or impedance mismatching due to a minute variation of the impedances occur, an output voltage of the differential test amplifier TA is measured to obtain a degree of variation in the impedances.
With reference to FIG. 6 and FIG. 7, input and output voltages of the test circuit (235, 335) when no defects occur in the transmission line (W11, W21), can be expressed by following equations 2, 3, and 4.




  
    
      
        
          
            
              
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                  +
                
                -
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                  -
                
              
              =
              
                
                  
                    (
                    
                      
                        R
                        T
                      
                      //
                      
                        Z
                        
                          i
                          ⁢
                          
                            
                          
                          ⁢
                          
                            n
                            ⁡
                            
                              (
                              TA
                              )
                            
                          
                        
                      
                    
                    )
                  
                  
                    
                      2
                      ⁢
                      
                        Z
                        0
                      
                    
                    +
                    
                      (
                      
                        
                          R
                          T
                        
                        //
                        
                          Z
                          
                            i
                            ⁢
                            
                              
                            
                            ⁢
                            
                              n
                              ⁡
                              
                                (
                                TA
                                )
                              
                            
                          
                        
                      
                      )
                    
                  
                
                ⁢
                
                  v
                  
                    s
                    +
                  
                
              
            
          
        
        
          
            
              =
              
                
                  
                    (
                    
                      100
                      //
                      50
                    
                    )
                  
                  
                    100
                    +
                    
                      (
                      
                        100
                        //
                        50
                      
                      )
                    
                  
                
                ⁢
                
                  v
                  
                    s
                    +
                  
                
              
            
          
        
        
          
            
              =
              
                
                  1
                  4
                
                ⁢
                
                  v
                  
                    s
                    +
                  
                
              
            
          
        
        
          
            
              =
              
                0.25
                ⁢
                
                  v
                  
                    s
                    +
                  
                
              
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          2
        
        ]
      
    
  
  
    
      
        
          v
          T
        
        =
        
          
            G
            ×
            
              (
              
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                  +
                
                -
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                  -
                
              
              )
            
          
          =
          
            0.25
            ⁢
            
              Gv
              
                s
                +
              
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          3
        
        ]
      
    
  
  
    
      
        
          V
          T
        
        =
        
          
            γ
            ⁢
            
              
            
            ⁢
            
              v
              
                T
                ⁡
                
                  (
                  peak
                  )
                
              
            
          
          =
          
            γ
            ⁢
            
              
            
            ⁢
            G
            ×
            
              (
              
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    
                      n
                      ⁡
                      
                        (
                        peak
                        )
                      
                    
                  
                  +
                
                -
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    
                      n
                      ⁡
                      
                        (
                        peak
                        )
                      
                    
                  
                  -
                
              
              )
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          4
        
        ]
      
    
  




where, G represents a voltage gain of the differential test amplifier, νs+ represents an input voltage, which is a data voltage transmitted through the transmission line, and γ is an envelope detection constant of the peak detector.
For example, when the G is 10, γ is 1, and νs+ is 500 mV, input and output voltages of the test circuit are expressed by following equation 5, 6, and 7.

νin+−νin−=0.25×500 mV=75 mV  [Equation 5]

νT=10×75 mV=750 mV  [Equation 6]

VT=1×10×75 mV=750 mV  [Equation 7]

In contrast to this, input and output voltages of the test circuit (235, 335) when defects occur in the transmission line (W11, W21), can be expressed by following equations 8, 9, and 10.




  
    
      
        
          
            
              v
              
                i
                ⁢
                
                  
                
                ⁢
                n
              
              +
            
            -
            
              v
              
                i
                ⁢
                
                  
                
                ⁢
                n
              
              -
            
          
          _
        
        =
        
          
            
              (
              
                
                  R
                  T
                
                //
                
                  Z
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    
                      n
                      ⁡
                      
                        (
                        TA
                        )
                      
                    
                  
                
              
              )
            
            
              
                2
                ⁢
                
                  
                    Z
                    0
                  
                  _
                
              
              +
              
                (
                
                  
                    R
                    T
                  
                  //
                  
                    Z
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      
                        n
                        ⁡
                        
                          (
                          TA
                          )
                        
                      
                    
                  
                
                )
              
            
          
          ⁢
          
            v
            
              s
              +
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          8
        
        ]
      
    
  
  
    
      
        
          
            v
            T
          
          _
        
        =
        
          G
          ×
          
            (
            
              
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                  +
                
                -
                
                  v
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                  -
                
              
              _
            
            )
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          9
        
        ]
      
    
  
  
    
      
        
          
            V
            T
          
          _
        
        =
        
          
            γ
            ⁢
            
              
            
            ⁢
            
              
                v
                
                  T
                  ⁡
                  
                    (
                    peak
                    )
                  
                
              
              _
            
          
          =
          
            γ
            ⁢
            
              
            
            ⁢
            G
            ×
            
              (
              
                
                  
                    v
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      
                        n
                        ⁡
                        
                          (
                          peak
                          )
                        
                      
                    
                    +
                  
                  -
                  
                    v
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      
                        n
                        ⁡
                        
                          (
                          peak
                          )
                        
                      
                    
                    -
                  
                
                _
              
              )
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          10
        
        ]
      
    
  




Namely, the bar (−) indicates input and output voltages of the test circuit (235, 335) when defects occur in the transmission line (W11, W21).
For example, when the impedance Z0 of the transmission line (W11, W21) changes from 50Ω to 25Ω due to unexpected ambient environment, namely, when the differential impedance Zdiff is generated, the equations 8 to 10 can be expressed by following equations 11 to 13.




  
    
      
        
          
            
              
                
                  
                    v
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                    +
                  
                  -
                  
                    v
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                    -
                  
                
                _
              
              =
              
                
                  
                    (
                    
                      100
                      //
                      50
                    
                    )
                  
                  
                    50
                    +
                    
                      (
                      
                        100
                        //
                        50
                      
                      )
                    
                  
                
                ⁢
                
                  v
                  
                    s
                    +
                  
                
              
            
          
        
        
          
            
              =
              
                0.4
                ⁢
                
                  v
                  
                    s
                    +
                  
                
              
            
          
        
        
          
            
              =
              
                0.4
                ×
                500
                ⁢
                
                  
                
                ⁢
                mV
              
            
          
        
        
          
            
              =
              
                200
                ⁢
                
                  
                
                ⁢
                mV
              
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          11
        
        ]
      
    
  
  
    
      
        
          
            v
            T
          
          _
        
        =
        
          
            10
            ×
            200
            ⁢
            
              
            
            ⁢
            mV
          
          =
          
            2
            ⁢
            V
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          12
        
        ]
      
    
  
  
    
      
        
          
            V
            T
          
          _
        
        =
        
          
            1
            ×
            10
            ×
            200
            ⁢
            
              
            
            ⁢
            mV
          
          =
          
            2
            ⁢
            V
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          13
        
        ]
      
    
  




As understood through the aforementioned example, when the impedance Z0 of the transmission line changes by 50%, namely, from 50Ω to 25Ω, it is observed that an output voltage of the test circuit changes from 750 mV to 2V. Since this indicates a great voltage variation, a degree of variation in the impedances can be easily detected.
That is, in aspects of the present invention, a variation value of impedance, namely, minute variation of the differential impedance in the differential transmission line is amplified to clearly detect a variation degree thereof. Further, since the peak detector 337 converts a final output signal into a direct current voltage, as shown, a DC meter 340 can easily measure and detect results thereof.
In other words, aspects of the present invention clearly detects a presence of an impedance matching by a test circuit in a flat panel display using a signal transmission method for transmitting a differential signal and clearly perform an impedance matching through the detection, in which the test circuit amplifies the minute variation of the differential impedance and converts the amplified signal into a direct current component, thereby easily detecting the presence of the impedance matching.
Aspects of the present invention are better in detecting the minute variation in the differential impedance compared to a case of measuring the minute variation in the differential impedance across a termination resistor RT without the test circuit.
For comparison purposes, measuring a voltage variation before and after a 50% variation of impedance in the transmission line in a typical case without the test circuit, when the input voltage vs+ is 500 mV, are expressed by the following equations 14 and 15, respectively.




  
    
      
        
          
            v
            
              i
              ⁢
              
                
              
              ⁢
              n
            
            +
          
          -
          
            v
            
              i
              ⁢
              
                
              
              ⁢
              n
            
            -
          
        
        =
        
          
            
              
                R
                T
              
              
                
                  2
                  ⁢
                  
                    Z
                    0
                  
                
                +
                
                  R
                  T
                
              
            
            ⁢
            
              v
              
                s
                +
              
            
          
          =
          
            
              
                100
                200
              
              ⁢
              
                (
                
                  500
                  ⁢
                  
                    
                  
                  ⁢
                  mV
                
                )
              
            
            =
            
              250
              ⁢
              
                
              
              ⁢
              mV
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          14
        
        ]
      
    
  
  
    
      
        
          
            
              v
              
                i
                ⁢
                
                  
                
                ⁢
                n
              
              +
            
            -
            
              v
              
                i
                ⁢
                
                  
                
                ⁢
                n
              
              -
            
          
          _
        
        =
        
          
            
              
                R
                T
              
              
                
                  2
                  ⁢
                  
                    
                      Z
                      0
                    
                    _
                  
                
                +
                
                  R
                  T
                
              
            
            ⁢
            
              v
              
                s
                +
              
            
          
          =
          
            
              
                100
                150
              
              ⁢
              
                (
                
                  500
                  ⁢
                  
                    
                  
                  ⁢
                  mV
                
                )
              
            
            ≈
            
              333
              ⁢
              
                
              
              ⁢
              mV
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          15
        
        ]
      
    
  




That is, a measured voltage variation rate=(333−250)×100%/250=33%.
In comparison, in the aspect of the present invention described earlier with reference to FIG. 7, a measured voltage variation before and after a 50% variation of impedance in the transmission line are expressed by the equations 7 and 13. Namely, the measured voltage variation rate=(2000−750)×100%/750=140%.
Accordingly, in aspects of the present invention, since a test circuit amplifies and detects a minute variation of differential impedance due to defects in a transmission line, it has a greater measured voltage variation rate in comparison with a typical case. Accordingly, aspects of the present invention can more accurately or readily detect the minute variation of the differential impedance and perform a more accurate impedance matching through the detection of the minute variation of the differential impedance.
Moreover, a typical method uses an expensive oscilloscope to detect or observe the measured voltage. However, in aspects of the present invention, because the peak detector 337 can detect a direct current component VT, a variation and a value of the impedance in the transmission line can be detected by using a simple DC meter 340.
As is seen from the forgoing description, aspects of the present invention may more clearly detect a presence of an impedance matching by using a test circuit in a flat panel display using a differential signal transmission method to transmit a differential signal and more clearly perform an impedance matching through the detection of the matched impedance in order to stably transmit a high speed signal without an electro magnetic interference, in which the test circuit amplifies the minute variation of the differential impedance and converts the amplified signal into a direct current component, thereby easily detecting the presence of the impedance.
In aspects of the present invention, minute variance of the impedance refers to very small changes in the impedances of between several tens of ohms to several milliohms, or smaller.
In aspects of the present invention, a differential signaling system transmits a signal having different modes but having a same amplitude and a different polarity through a differential transmission line.
Various methods for transmitting the high speed signals between components through wirings includes, a signal transmission method such a low voltage differential signaling (LVDS) method or a reduced swing differential signaling (RSDS) method for transmitting a differential signal.
Various flat panel displays includes a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting display (OLED).
In various aspects, and/or refers to alternatives chosen from available elements so as to include one or more of the elements. For example, if the elements available include elements X, Y, and/or Z, then and/or refers to X, Y, Z, or any combination thereof.
Although a few aspects of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in the aspects without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

## Claims

1. A differential signaling system comprising:
a differential signal line having a first wiring and a second wiring coupled between a sending end and a receiving end of the system;
a termination resistor coupled between the first wiring and the second wiring in the receiving end side of the system; and
a test circuit directly coupled to the termination resistor in parallel and configured to amplify and detect a variation of a differential impedance due to the differential signal line,
wherein the test circuit includes:
a differential test amplifier configured to amplify the variation in the differential impedance of the first wiring or the second wiring and output an output signal through an output terminal,
a switching unit installed at an input terminal of the differential test amplifier and configured to control an operation of the differential test amplifier, and
a peak detector coupled to the output terminal of the differential test amplifier and configured to convert the output signal of the differential test amplifier into a direct current component.

2. The differential signaling system as claimed in claim 1, wherein the test circuit is positioned at an outside of the receiving end.

3. The differential signaling system as claimed in claim 1, wherein the differential test amplifier has an input impedance value and an amplification gain value.

4. The differential signaling system as claimed in claim 1, wherein the peak detector has an envelope detection constant of 1.

5. A flat panel display comprising:
a display panel in which a plurality of data wirings and gate wirings are arranged to intersect each other;
a controller configured to receive an image signal from an exterior and to generate a control signal, and to output the image signal and the control signal through a differential signal line having first and second wirings;
a gate driver configured to receive the control signal from the controller and apply a scan signal to the gate wirings;
a data driver including a plurality of data driving circuits configured to receive the image signal and/or the control signal from the controller through the first and second wirings and apply the image signal to the data wirings; and
a test circuit directly coupled to a termination resistor in parallel and configured to amplify and detect a variation of a differential impedance due to the differential signal line, the termination resistor being coupled between the first wiring and the second wiring in a receiving end,
wherein the test circuit includes:
a differential test amplifier configured to amplify the variation in the differential impedance of the first wiring or the second wiring and output an output signal through an output terminal,
a switching unit installed at an input terminal of the differential test amplifier and configured to control an operation of the differential test amplifier, and
a peak detector coupled to the output terminal of the differential test amplifier and configured to convert an output signal of the differential test amplifier into a direct current component.

6. The flat panel display as claimed in claim 5, wherein the test circuit is positioned at an outside of the data driving circuits.

7. The flat panel display as claimed in claim 5, wherein the differential test amplifier has an input impedance value and an amplification gain value.

8. The flat panel display as claimed in claim 5, wherein the peak detector has an envelope detection constant of 1.

9. A differential signaling circuit, comprising:
a sending end and a receiving end of the differential signaling circuit;
a first wiring and a second wiring to connect the sending end and the receiving end, and to carry a differential signal between the sending end and the receiving end;
a termination resistor coupled between the first wiring and the second wiring in the receiving end; and
a test circuit positioned at the receiving end and connected to the first and second wirings, the test circuit generating an amplified output signal from an output signal that is based on a signal voltage of the differential signal, and a variance in a voltage of the amplified output signal is indicative of an impedance variance in the differential signaling circuit, wherein the test circuit includes:
a differential test amplifier configured to amplify the variation in the differential impedance of the first wiring or the second wiring and output an output signal through an output terminal,
a switching unit installed at an input terminal of the differential test amplifier and configured to control an operation of the differential test amplifier, and
a peak detector coupled to the output terminal of the differential test amplifier and configured to convert the output signal of the differential test amplifier into a direct current component.

10. The differential signaling circuit of claim 9, wherein the voltage of the amplified output signal is a predetermined multiple of the signal voltage of the differential signal, if impedances of the circuit are matched, and the voltage of the amplified output signal is another multiple of the signal voltage of the differential signal, if the impedances of the circuit are not matched.

11. The differential signaling circuit of claim 9, wherein a rate of variance in the voltage of the amplified output signal is greater than a rate of the impedance variance in the differential signaling circuit.

12. The differential signaling circuit of claim 9, wherein the variance in the voltage of the amplified output signal is based on the impedance variance in the differential signaling circuit.

13. The differential signaling circuit of claim 9, wherein the impedance variance in the differential signaling circuit corresponds to a change in an impedance of the first and/or second wirings.

14. The differential signaling circuit of claim 9, wherein the test circuit detects and amplifies a variation of a differential impedance in the differential signaling circuit and converts the amplified variation into a direct current component, to thereby easily detect presence of an impedance matching in the differential signaling circuit.

15. A flat panel display including the differential signaling circuit of claim 9, comprising:
a display panel in which a plurality of data wirings and gate wirings are arranged to intersect each other;
a controller to receive an image signal, to generate control signals, and to output the image signal and the control signals as the differential signal through the first and second wirings;
a gate driver to receive the control signals from the controller and apply a scan signal to the gate wirings;
a data driver including a plurality of data driving circuits to receive the image signal and/or the control signals from the controller through the first and second wirings and to apply the image signal to the data wirings.

16. A method of detecting a variance in an impedance of a differential signaling circuit, comprising:
transmitting a differential signal over a first wiring and a second wiring of the differential signaling circuit to connect a sending end and a receiving end of the differential signaling circuit, the first wiring and the second wiring being connected by a termination resistor coupled between the first wiring and the second wiring in the receiving end;
selectively connecting an input terminal of a differential test amplifier to the first wiring and the second wiring;
obtaining a signal voltage of the differential signal and generating an output signal based on the signal voltage of the differential signal;
amplifying the output signal to generate an amplified output signal, and amplifying a variance in a voltage of the amplified output signal that is indicative of an impedance variance in the differential signaling circuit; and
converting the amplified output signal into a direct current component.

17. The method of claim 16, wherein the voltage of the amplified output signal is a predetermined multiple of the signal voltage of the differential signal, if impedances of the circuit are matched, and the voltage of the amplified output signal is another multiple of the signal voltage of the differential signal, if the impedances of the circuit are not matched.

18. The method of claim 16, wherein the impedance variance in the differential signaling circuit corresponds to a change in an impedance of the first and/or second wirings.