# Patent

## Title
Compensation of LDO regulator using parallel signal path with fractional frequency response

## Abstract

A low drop out (LDO) voltage regulator (10) includes a pass transistor (MPpass) having a source coupled by an output conductor (4) to a load and a drain coupled to an input voltage to be regulated. An error amplifier (2) has a first input coupled to a reference voltage, a second input connected to a feedback conductor (4A), and an output coupled to a gate of the pass transistor. A parallel path transistor (MPpa) has a source coupled to the input voltage, a gate coupled to the output (3) of the error amplifier (2), and a drain coupled to the feedback conductor. A feedback resistor (Rf) is coupled between the feedback conductor and the output conductor.

## Background
BACKGROUND OF THE INVENTION
The present invention relates generally to low dropout (LDO) linear voltage regulators of the kind having P-channel pass transistors, i.e., PMOS LDO linear voltage regulators. The invention also relates more particularly to such LDO voltage regulators having very low quiescent current and good phase margin despite large variations in the load and the output capacitance.
Various approaches have been used to address the problems associated with providing such LDO voltage regulators having low quiescent current, as is desirable for battery-powered applications in order to extend battery operating life. In some LDO voltage regulator designs, the P-channel pass transistor is driven by a voltage buffer which pushes the pole associated with the gate capacitance beyond the unity-gain frequency of the feedback loop of the voltage regulator. However, that technique is not suitable for PMOS LDO regulators that need to have a very low quiescent current.
Instead of dissipating a large amount of quiescent current in a voltage buffer as mentioned above, adding a zero in the voltage transfer characteristic of the regulator feedback loop may cancel the pole either from the gate capacitance of the PMOS pass device or from the output capacitor. In some cases, the zero can be obtained by using output capacitors with high equivalent series resistance (ESR). Nevertheless, the “ESR zero” type of compensation provided by the output capacitor is not very efficient in low quiescent current LDO regulator design, especially for the popular low ESR ceramic capacitors whose ESR zeros are far outside of the narrow bandwidth of the low bandwidth characteristic of low quiescent current LDO voltage regulators. Therefore, the “compensation zero” has to be created within the LDO feedback loop in most cases.
Adding a “compensation zero” type of compensation within the LDO feedback loop can achieve very good pole-zero cancellation if the specific values of the LDO voltage regulator output capacitance and its ESR are known. However, because of the wide ranges of output capacitance and the associated ESR values, the zero added into the transfer characteristic of the feedback loop always provides incomplete compensation under certain conditions, resulting in LDO regulator instability.
Referring to FIG. 1, a conventional PMOS linear voltage regulator 1 includes a P-channel pass transistor MPpass which operates as a current source controlled by an error amplifier 2 having a transconductance gmi. The capacitance C1 connected between the gate and source of pass transistor MPpass is CCH+Cgs (the sum of the channel capacitance CCH and gate-source overlap capacitance Cgs), and Cc is the gate-drain overlap capacitance Cgd. For short channel transistors, Cgs and Cgs are comparable to CCH. The transconductance gmo of pass transistor MPpass is a function of the load current IL flowing out of the drain of the pass transistor. It should be noted that without a voltage buffer of the kind mentioned above, the conductor 3 connected to the gate of pass transistor MPpass is a gain node which presents a pole. The pole is related to the gate capacitance of pass transistor MPpass and the output resistance rol of error amplifier 2. The load capacitance CL provided by the user causes another pole that is inversely proportional to the product of CL and RL, where RL is the small signal resistance seen at conductor 4 and includes the load resistance, the divider, and the output resistance ro of pass transistor MPpass.
Therefore, the PMOS LDO voltage regulator 1 in FIG. 1 is a two-pole system which may have very low phase margin under certain load conditions. Due to the different natures of various applications, the equivalent AC load may be either a passive load such as a resistor or an active load such as a current source. The uncertainty regarding the AC impedance of the load makes the design of PMOS LDO voltage regulator 1 very difficult, because the output pole has a strong dependence on the equivalent AC load. Nevertheless, in almost all situations the DC gain gmoRL from the gate conductor 3 to the output conductor 4 is much greater than 1 (i.e., gmoRL>>1), which is quite different from the N-channel pass transistor case in which the NMOS source follower provides a DC gain very close to unity.
The AC voltage gain vo/vi (where vo is Vout and vi is Vin) of the loop can be found as follows, for CL>>Cc:




  
    
      
        
          
            v
            o
          
          
            v
            i
          
        
        =
        
          
            
              
                g
                mi
              
              ⁢
              
                r
                01
              
              ⁢
              
                g
                mo
              
              ⁢
              
                
                  R
                  L
                
                ⁡
                
                  (
                  
                    1
                    -
                    
                      
                        sC
                        c
                      
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                        g
                        mo
                      
                    
                  
                  )
                
              
            
            
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                      ⁢
                      
                        R
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                            C
                            1
                          
                          +
                          
                            C
                            c
                          
                        
                        )
                      
                      ⁢
                      
                        r
                        01
                      
                    
                    +
                    
                      
                        g
                        mo
                      
                      ⁢
                      
                        R
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                  ]
                
              
              +
              
                
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                  2
                
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                  r
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                    L
                  
                  ⁡
                  
                    (
                    
                      
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                        c
                      
                    
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          .
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        
          (
          1
          )
        
      
    
  




From the denominator of Eq. (1) it can be seen that there are two poles. For any particular design, the values of C1, Cc, and rol are given and the poles are functions of CL and RL. Instead of solving Eq. (1), the manner in which the magnitudes and phases of the poles change with respect to CL and RL can be determined for a fixed value of load resistance RL. For a very large CL, the dominant pole p1 and the non-dominant pole p2 are obtained by factoring the second-order denominator as:





  
    
      
        
          
            
              p
              1
            
            =
            
              1
              
                
                  C
                  L
                
                ⁢
                
                  R
                  L
                
              
            
          
          ,
          and
        
        ⁢
        
          

        
        ⁢
        
          
            p
            2
          
          =
          
            
              1
              
                
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                      c
                    
                  
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                ⁢
                
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            .
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        
          (
          2
          )
        
      
    
  




(For more information, see page 241 et seq. of “Analog Integrated Circuit Design”, by D. Johns, and K. Martin, John Wiley & Sons, 1997.) However, for very small CL, the dominant pole p1 and the non-dominant pole p2, respectively, are given by:





  
    
      
        
          
            
              p
              1
            
            =
            
              1
              
                
                  g
                  mo
                
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                  R
                  L
                
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                  01
                
              
            
          
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          and
        
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            p
            2
          
          =
          
            
              
                g
                mo
              
              
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                L
              
            
            ×
            
              
                
                  C
                  c
                
                
                  
                    C
                    1
                  
                  +
                  
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                    c
                  
                
              
              .
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        
          (
          3
          )
        
      
    
  




Sketches of poles p1 and p2 versus CL for a fixed RL are shown in FIG. 2A. For a very small value of load capacitance CL, the value of the dominant pole p1 does not change with CL and can be attributed to the Miller capacitor Cc, and the value of non-dominant pole p2 moves away from that of the dominant pole p1 as the capacitance CL decreases, as shown in FIG. 2A. On the other hand, for a very large CL, the dominant pole p1 is attributed to CL and it moves away from the non-dominant pole p2 which stays at





  1
  
    
      (
      
        
          C
          1
        
        +
        
          C
          c
        
      
      )
    
    ⁢
    
      r
      01
    
  




as CL increases. The magnitudes of poles p1 and p2 are the closest when CL=gmorolCc indicating that the load capacitor and the Miller capacitor pole have the same amount of delay and neither is dominant. Under that worst case condition,





  
    
      
        
          
            
              p
              1
            
            =
            
              
                1
                
                  
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                    mo
                  
                  ⁢
                  
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                    L
                  
                  ⁢
                  
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                    c
                  
                  ⁢
                  
                    r
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              =
              
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                    C
                    L
                  
                  ⁢
                  
                    R
                    L
                  
                
              
            
          
          ,
          and
        
        ⁢
        
          

        
        ⁢
        
          
            p
            2
          
          =
          
            
              1
              
                
                  (
                  
                    
                      C
                      1
                    
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                      C
                      c
                    
                  
                  )
                
                ⁢
                
                  r
                  01
                
              
            
            .
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        
          (
          4
          )
        
      
    
  




The worst case Q factor is




  
    
      
        
          
            Q
            =
            
              
                
                  [
                  
                    
                      
                        A
                        0
                      
                      ⁢
                      
                        p
                        1
                      
                    
                    
                      p
                      2
                    
                  
                  ]
                
                
                  1
                  /
                  2
                
              
              =
              
                
                  [
                  
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
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                      01
                    
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                        C
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                          C
                          1
                        
                        +
                        
                          C
                          c
                        
                      
                    
                  
                  ]
                
                
                  1
                  /
                  2
                
              
            
          
          ,
          where
        
        ⁢
        
          

        
        ⁢
        
          
            A
            0
          
          =
          
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                i
              
            
            ⁢
            
              r
              o
            
            ⁢
            
              g
              mo
            
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              .
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        
          (
          5
          )
        
      
    
  




This is for the case in which the feedback loop has unity gain. In Eq. (5), A0=gmirogmoRL is the overall DC gain of the loop.

The foregoing analysis reveals the poles changing with CL for a fixed load RL. However, in a typical LDO application, the load changes while CL is provided by the user and kept as a constant. Thus, it would provide a better insight to analyze the poles changing with load RL, or gmo, for a fixed CL. Nevertheless, plotting poles p1 and p2 versus gmo is not as straightforward as plotting them versus CL because gmo and RL have no simple relationship. The complexity results not only from the strong application dependencies of RL as pointed out previously, but also from the nonlinear dependency of gmo on the load current IL flowing out of the drain of pass transistor MPpass. In fact, gmo is proportional to IL when pass transistor MPpass is in sub-threshold operation for a very light load current, whereas it is proportional to (IL)1/2 when the pass transistor MPpass is in saturation for a heavy load current. However, in the current range in which the two capacitors “fight for dominance”, pass transistor MPpass is still in sub-threshold operation, which will be shown later. In the sub-threshold operating region, gmoRL can be taken as a constant because gmo is proportional to IL while RL is inversely proportional to IL.
Again, by using a similar asymptotic approach, poles p1 and p2 can be derived by factoring the denominator of Eq. (1) and are given by Eq. (2) for small gmo (or large RL) and by Eq. (3) for large (or small RL), respectively. Based on Eqs. (2) and (3), poles changing with gmo can be sketched as in FIG. 2B, assuming gmoR1 is a constant. For a small value of gmo, the dominant pole p1 can be attributed to the load capacitor CL and its value moves away from the value of the non-dominant pole p2 as gmo decreases (or as RL increases) while pole p2 stays at




  
    1
    
      
        (
        
          
            C
            1
          
          +
          
            C
            c
          
        
        )
      
      ⁢
      
        r
        01
      
    
  
  .




On the other hand, for a large value of gmo, the value of dominant pole p1 does not change with gmo and can be attributed to the Miller capacitor Cc, and the value of non-dominant pole p2 moves away from pole p1 as gmo increases. The magnitudes of poles p1 and p2 are the closest when





  
    
      
        
          
            g
            mo
          
          =
          
            
              C
              L
            
            
              
                C
                c
              
              ⁢
              
                r
                01
              
            
          
        
        ,
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        
          (
          6
          )
        
      
    
  




wherein the load capacitor and the Miller capacitor cause the same amount of delay and neither of them is dominant. Under that condition, the LDO regulator feedback loop has its lowest phase margin, with the pole locations and the Q factor given by Eqs. (4) and (5), respectively.

Not surprisingly, both analyses, poles vs CL and poles vs gmo, give the same worst case condition. To summarize, poles p1 and p2 can be attributed to CL and Cc only when poles p1 and p2 are widely separated. For small gmo, p1 can be attributed to the load capacitor pole; for large gmo, p1 can be attributed to the Miller capacitance pole. For gmo around the value give by Eq. (6), p1 can not be attributed to either of them.
It also can be seen from Eq. (2) and Eq. (3) that the curves of poles p1 and p2 versus gmo shift horizontally for different values of the user-provided load capacitance CL. Poles p1 and p2 versus gmo with a larger value of CL are shown as dashed lines in FIG. 2B. Since the worst case Q factor is independent of CL, there is always a minimum phase margin at a certain load condition for whatever load capacitance is being used.
FIG. 3 shows the simulated phase margins at unity gain versus load current for CL=μF (Curve A), 10 μF (Curve B), and 100 μF (Curve C) for the simple topology PMOS LDO of FIG. 1, illustrating the existence of a minimum phase margin irrespective of load capacitance. Curves A, B and C exhibit approximately 1 degree of phase margin at load currents IL of 300 nA, 3 uA, and 30 uA for CL=1 μF, 10 μF, and 100 μF respectively. With those currents, the pass transistor MPpass with a W/L ratio of 50,000 microns/0.8 micron, still operates in its sub-threshold region, which supports the assumption that gmoRL is a constant.
FIGS. 4A-C show the overall open loop gain Bode plots as solid lines for the simple LDO topology, representing the cases (a) when the output capacitor dominates the frequency response, i.e.,




  
    
      1
      
        
          C
          L
        
        ⁢
        
          R
          L
        
      
    
    <
    
      1
      
        
          g
          mo
        
        ⁢
        
          R
          L
        
        ⁢
        
          C
          c
        
        ⁢
        
          r
          01
        
      
    
  
  ;




(b) when the output capacitor and the Miller capacitor are equally strong in frequency response, i.e.,





  
    
      1
      
        
          C
          L
        
        ⁢
        
          R
          L
        
      
    
    =
    
      1
      
        
          g
          mo
        
        ⁢
        
          R
          L
        
        ⁢
        
          C
          c
        
        ⁢
        
          r
          01
        
      
    
  
  ;




and (c), when the Miller capacitor dominates,





  
    
      1
      
        
          C
          L
        
        ⁢
        
          R
          L
        
      
    
    >
    
      1
      
        
          g
          mo
        
        ⁢
        
          R
          L
        
        ⁢
        
          C
          c
        
        ⁢
        
          r
          
            o
            ⁢
            
              
            
            ⁢
            1
          
        
      
    
  
  ,




respectively. The dashed lines 9-4 and the dot-dash lines 9-2 indicate the gains from the pass transistor gate to the output and from the input of error amplifier 2 to its output, respectively. In FIG. 4A where the output capacitor dominates, the corner frequency 1/(CLRL) of curve 9-4, is on the left hand side of the corner frequency of curve 9-2. The product of curve 9-2 and curve 9-4 gives the overall open loop gain, 9-1. FIGS. 4B and 4C can be analyzed similarly.

In summary, the prior art PMOS LDO voltage regulator of FIG. 1 possesses significant stability shortcomings. It has been shown that under the worst case condition, the Q factor of the closed loop is given by Eq. (5) as [gmirolCc/(Cc+C1)]1/2. Q could be as large as approximately 30, since gmirol could be 60 to 70 dB while Cc/(Cc+C1 is on the order of 1, implying a very low phase margin and, as demonstrated in FIG. 3, leading to very poor transient performance under the worst case condition.
Thus, there is an unmet need for a PMOS LDO voltage regulator which has ultra-low quiescent current and which provides stable operation substantially irrespective of the load supplied thereby.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an LDO voltage regulator which has ultra-low quiescent current and which provides stable operation substantially irrespective of the load supplied thereby.
It is another object of the invention to provide a PMOS LDO voltage regulator which has ultra-low quiescent current and which provides stable operation substantially irrespective of the load supplied thereby.
Briefly described, and in accordance with one embodiment, the present invention provides a low drop out (LDO) voltage regulator (10) which includes a pass transistor (MPpass) having a first electrode coupled to an input voltage to be regulated and a second electrode coupled by an output conductor (4) to a load. An error amplifier (2) has a first input coupled to a reference voltage, a second input connected to a feedback conductor (4A), and an output coupled to a control electrode of the pass transistor. A parallel path transistor (MPpa) has a first electrode coupled to the input voltage, a control electrode coupled to the output (3) of the error amplifier (2), and a second electrode coupled to the feedback conductor. A feedback resistor (Rf and/or R2) is coupled between the feedback conductor and the output conductor.
In one embodiment, the invention provides a low drop out (LDO) voltage regulator (10) including a pass transistor (MPpass) having a first electrode coupled to an input voltage (Vin) and a second electrode coupled by an output conductor (4) to a load. An error amplifier (2) has a first input coupled to a reference voltage (Vref), a second input connected to a feedback conductor (4A), and an output (3) coupled to a control electrode of the pass transistor (MPpass). A parallel path transistor (MPpa) has a first electrode coupled to the input voltage (Vin), a control electrode coupled to the output (3) of the error amplifier (2), and a second electrode coupled to the feedback conductor (4A). A feedback resistance (Rf and/or R2) is coupled between the feedback conductor (4A) and the output conductor (4). In one embodiment, the pass transistor (MPpass) and the parallel path transistor (MPpa) are P-channel MOS transistors, and the first electrodes are sources, the second electrodes are drains, and the control electrodes are gates.
In one embodiment, the gate of the parallel path transistor (MPpa) is coupled to the output (3) of the error amplifier (2) by means of an offset voltage source (VOS). In one embodiment, the offset voltage source (VOS) includes an offset resistor (15) coupled between the gate of the pass transistor (MPpass) and the gate of the parallel path transistor (MPpa), and also includes a first current source (16) coupled to a first terminal of the offset resistor (15) and a second current source (17) coupled to a second terminal of the offset resistor (15). In one embodiment, a third current source (19) is coupled between the input voltage (Vin) and the source of the parallel path transistor (MPpa), a fourth current source (20) is coupled to the drain of the parallel path transistor (MPpa), and a capacitor (Cp) is coupled between the input voltage (Vin) and the source of the parallel path transistor (MPpa).
In one embodiment, the LDO voltage regulator includes a third current source (19) coupled between the input voltage (Vin) and the source of the parallel path transistor (MPpa) a fourth current source (20) coupled to the drain of the parallel path transistor (MPpa), and a fractional frequency response network (24) coupled between the input voltage (Vin) and the source of the parallel path transistor (MPpa). In one embodiment, the fractional frequency response network (24) includes first (ro), second (r1), and third (r2) MOS resistive elements each having a source coupled to the input voltage (Vin) and a gate coupled to a first bias voltage, and first (c0), second (c1), third (c2), and fourth (c3) capacitors. The first capacitor (c0) is coupled between the input voltage (Vin) and a drain (28) of the first MOS resistive element (ro). The second capacitor (c1) is coupled between the drain (28) of the first MOS resistive element (ro) and a drain (27) of the second MOS resistive element (r1). The third capacitor (c2) is coupled between the drain (27) of the second MOS resistive element (r1) and a drain (26) of the third MOS resistive element (r2), and the fourth capacitor (c3) is coupled between the drain (26) of the second MOS resistive element (r1) and the source (5A) of the parallel path transistor (MPpa).
In one embodiment, a current limit transistor (MPlimit) has a source coupled to the drain of the parallel path transistor (MPpa), a gate coupled to a second bias voltage (VBIAS), and a drain coupled to the feedback conductor (4A).
In one embodiment, the error amplifier (2) includes first (MN0A) and second (MN0B) input transistors having sources coupled to a tail current transistor (MN3B). A gate of the first input transistor (MN0A) is coupled to the reference voltage (Vref), a gate of the second input transistor (MN0B) is coupled to the feedback conductor (4A), a drain of the first input transistor (MN0A) is coupled to a drain and gate of a first load transistor (MP1A) and a gate of a first current mirror output transistor (MP1B) having a drain coupled to a drain and gate of a first current mirror input transistor (MN2A) and a gate of a second current mirror output transistor (MN2B) which functions as the second current source (17). A drain of the second input transistor (MN0B) is coupled to a drain and gate of a second load transistor (MP1C) and a gate of a third current mirror output transistor (MP1D) which functions as the first current source (16). A P-channel fourth current mirror output transistor (MP2B) is coupled between the input voltage (Vin) and the source of the parallel path transistor (MPpa) and functions as the third current source (19) and has a gate coupled to a gate and drain of a P-channel second current mirror input transistor (MP2A) and a drain of a N-channel fifth current mirror output transistor (MN4E) having a gate coupled to a gate and drain of a N-channel third current mirror input transistor (MN4A). A N-channel sixth current mirror output transistor (MN4D) has a drain coupled to the feedback conductor (4A) and a gate coupled to the gate and drain of the third current mirror input transistor (MN4A). A N-channel seventh current mirror output transistor (MN4C) has a gate coupled to the gate and drain of the third current mirror input transistor (MN4A) and a drain coupled to a gate and drain of a first diode-connected P-channel transistor (MP3) and the gates of the first (ro), second (r1), and third (r2) MOS resistive elements, and a N-channel eighth current mirror output transistor (MN4B) having a drain coupled to the gate of the current limit transistor (MPlimit) and a gate and drain of a second diode-connected P-channel transistor (MP4) and a gate coupled to the gate and drain of the third current mirror input transistor (MN4A), the third current mirror input transistor (MN4A) having its gate and drain coupled to a bias current source (IBIAS2).
In one embodiment, the invention provides a method of operating a low drop out (LDO) voltage regulator (10) with low quiescent current and at least a predetermined phase margin despite large variations in load current, the method including applying an input voltage (Vin) to a first electrode of a pass transistor (MPpass) and coupling a second electrode of the pass transistor (MPpass) to an output conductor (4) applying an output voltage (Vout) to a load, coupling a first input of an error amplifier (2) to a reference voltage (Vref), and coupling an output (3) of the error amplifier (2) to a control electrode of the pass transistor (MPpass), coupling a feedback resistance (Rf and/or R2) between the output conductor (4) and a second input of the error amplifier (2), and compensating the LDO voltage regulator (10) by coupling a parallel path transistor (MPpa) between the input voltage (Vin) and the second input of the error amplifier (2) and by coupling a control electrode of the parallel path transistor (MPpa) to the output of the error amplifier (2).
In one embodiment, the method includes applying an offset voltage (VOS) between the control electrode of the pass transistor (MPpass) and the control electrode of the parallel path pass transistor (MPpa) In one embodiment, the applying of the offset voltage (VOS) includes forcing a current through an offset resistor (15) to generate the offset voltage (VOS) and coupling a first current source (19) between the input voltage (Vin) and the first electrode of the parallel path transistor (MPpa), coupling a fourth current source (20) to the second electrode of the parallel path transistor (MPpa), and coupling capacitive circuitry (Cp) between the input voltage (Vin) and the first electrode of the parallel path transistor (MPpa).
In one embodiment, the method includes providing the capacitive circuitry in the form of a fractional frequency response network (24) coupled between the input voltage (Vin) and the first electrode of the parallel path transistor (MPpa). In one embodiment, the method includes coupling a current limit transistor (MPlimit) between the second electrode of the parallel path transistor (MPpa) and the second input (4A) of the error amplifier (2), and coupling a control electrode of the current limit transistor (MPlimit) to a second bias voltage (VBIAS).
In one embodiment, the invention provides a low drop out (LDO) voltage regulator (10) with low quiescent current and at least a predetermined phase margin despite large variations in load current, including a pass transistor (MPpass) and means (5) for applying an input voltage (Vin) to a first electrode of the pass transistor (MPpass) and means (4) for coupling a second electrode of the pass transistor (MPpass) to apply an output voltage (Vout) to a load, means for coupling a first input of an error amplifier (2) to a reference voltage (Vref) and means (3) for coupling an output of the error amplifier (2) to a control electrode of the pass transistor (MPpass), means (4A,4,R2) for coupling a feedback resistance (Rf) between the output voltage (Vout) and a second input of the error amplifier (2), and parallel path means (MPpa) coupled between the input voltage (Vin) and the second input of the error amplifier (2) for compensating a feedback loop of the LDO voltage regulator (10).



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a conventional LDO voltage regulator having a P-channel pass transistor.
FIGS. 2A and 2B are sketches of the dominant and non-dominant poles with logarithmic scales for the voltage regulator of FIG. 1, showing poles as a function of CL with RL fixed and as a function of gmo with CL fixed, respectively.
FIG. 3 is a plot showing the unity gain phase margin of the voltage regulator of FIG. 1 versus its load with CL=1 μF, 10 μF, and 100 μF.
FIGS. 4A-C are Bode plots for the voltage regulator of FIG. 1 for the cases when the output capacitor is dominant, the output capacitor and Miller capacitor are equally strong, and the Miller capacitor is dominant, in frequency response, respectively.
FIG. 5 is a schematic diagram which shows the control loop of a LDO voltage regulator having a P-channel pass transistor and also having a parallel signal path from the pass transistor gate voltage vg to the feedback voltage vf in accordance with the present invention.
FIG. 6 is a Bode plot which shows gain versus frequency for a LDO voltage regulator having the parallel signal path shown in FIG. 5.
FIGS. 7A-C are schematic diagrams of implementations of the parallel signal path shown in FIG. 5 wherein an offset voltage VOS is needed to make the parallel signal path adequately strong even though the pass transistor is in deep sub-threshold operation.
FIGS. 8A and 8B are Bode plots for the voltage regulator of FIG. 7C which illustrate that large Cp is needed in order to avoid a gain notch which may cause circuit instability and failure of the parallel path compensation.
FIG. 9A is a schematic diagram of the low dropout voltage regular of FIG. 7C wherein Cp is replaced with an s1/2 frequency response network to avoid a gain notch in the Bode plot.
FIG. 9B is a graph which shows the magnitude and phase versus frequency for the sum of the two signals having 1/s and s1/2 frequency responses, respectively.
FIG. 9C is a Bode plot which illustrates the effect of removal of the gain notch in FIG. 7C by replacing Cp with a s1/2 frequency response network.
FIG. 10A is a schematic diagram of a RC network implementation of fractional frequency response network 24 in FIG. 9A.
FIG. 10B is graph which shows a piece-wise linear representation of the conductance of the RC network shown in FIG. 10A.
FIG. 10C is a graph which shows a piece-wise linear representation of the conductance of the RC network shown in FIG. 10A wherein m=n=2.
FIG. 11 is a detailed schematic diagram of a PMOS LDO with a parallel fractional frequency response signal path to provide loop compensation for a very light load condition.
FIG. 12 is a graph showing phase margin versus load for the circuit of FIG. 11 with and without the parallel signal path.
FIGS. 13A and 13B show simulated transient responses for low dropout regulators with and without parallel compensation paths, respectively.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In battery-powered applications, low dropout (LDO) linear regulators with ultra-low quiescent currents have become more and more desirable, since they greatly increase power efficiency and thereby extend battery operating life. However, design of an ultra-low quiescent current LDO PMOS voltage regulator (e.g., with quiescent current in the microampere range) presents a great challenge. With only a small amount of current available to power the voltage regulator control circuit, the circuit topology must be kept as simple as possible.
Referring to FIG. 5, a PMOS linear voltage regulator 10 in accordance with the present invention includes a P-channel pass transistor MPpass which operates as a current source that is controlled by an error amplifier 2 having a transconductance gmi. The (−) input of error amplifier 2 is coupled to a reference voltage Vref. Error amplifier 2 can be powered by Vin and referenced to ground. The drain of pass transistor MPpass is connected to Vin conductor 5, its gate is connected to error amplifier output conductor 3, and its source is connected to Vout conductor 4. The transconductance gmo of pass transistor MPpass is a function of the total DC load current IL flowing through both internal and external DC components connected to conductor 4, including the current through resistor RL and the current through the divider including resistors R2 and R1 which sets the output voltage of voltage regulator 10. The output capacitor CL, which is also connected to conductor 4, presents an AC load to the LDO. The equivalent ESR resistance RESR associated with load capacitor CL is shown coupled between the lower terminal of capacitor CL and ground in FIG. 5, and also in subsequently described FIG. 11.
In LDO voltage regulator 10 of FIG. 5, a compensation zero is added to the voltage transfer characteristic by means of a parallel signal path including P-channel transistor MPpa, having its source coupled to Vin conductor 5, its gate connected to conductor 3, and its drain connected by feedback conductor 4A to the (+) input of error amplifier 2 and to one terminal of a feedback resistor Rf. Moreover, the other terminal of feedback resistor Rf is connected by conductor 11 to the connection point between resistors R1 and R2. Resistor R1 is connected between conductor 11 and ground, and resistor R2 is connected between conductor 11 and Vout conductor 4. (However, feedback resistor Rf is needed only if R2=0.) Parallel signal path transistor MPpa is designed to have a very small ratio to the pass transistor, which converts the gate signal vg into a current signal being injected into the feedback network including resistors Rf, R1 and R2, as shown in FIG. 5. The added “zero” tracks the pole associated with CL to make the compensation effective for a wide range of output capacitor values CL and associated ESR (equivalent series resistance) values.
The Bode plot for LDO voltage regulator 10 of FIG. 5 is shown as solid line 22-1 in FIG. 6. The gain from node 4A to node 3 is shown as dash-dot lines 22-2, and the gain from node 3 to node 4 is shown as dash lines 22-3. The product of the values represented by lines 22-2 and 22-3 provides the overall open loop gain represented by line 22-1. The contribution to the feedback signal vf from parallel signal path transistor MPpa is approximately gmp(Rf+R2/R1), wherein gmp is the transconductance of parallel path transistor MPpa. Feedback resistor Rf is only needed to isolate transistor MPpa from the load capacitor CL for the unity gain configuration wherein R2 is replaced by a short circuit (as in subsequently described FIG. 11).
Without the foregoing parallel signal path, the gain from node 3 to node 4, represented by line 22-3, would roll off at −20 dB per decade, passing the 0 dB line as shown in the Bode plot of FIG. 6 at gmo/CL and continuing along the thin dashed line 18. This causes the overall loop gain 22-1 in FIG. 6 to roll off at −40 dB per decade along the dash line 21, resulting in a low phase margin.
With the foregoing parallel signal path through transistor MPpa present, the roll-off signal through pass transistor MPpass encounters and combines with the signal through parallel signal path transistor MPpa, gmpRf (for the unity feedback case wherein R2=0), and ceases being dominant. The gain 22-3 will no longer roll off along line 18, and instead makes a turn at the frequency




  
    
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In other words, a zero at the frequency





  
    
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changes the overall gain roll-off back to −20 dB per decade. That zero tracks the pole





  
    
      
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irrespective of how the load or the output capacitor changes. Reasonable phase margin can be achieved by properly choosing the product gmpRf. It should be noted that trade-offs need to be made in choosing the product gmpRf. Specifically, if gmpRf is chosen to be greater than 1, the zero occurs at a lower frequency than the non-dominant pole p2 and the feedback loop is well compensated. However, the signal from the parallel path including transistor MPpa becomes so strong that it significantly undermines the feedback loop controlling the main signal path through MPpas, leading to large transient undershoot and overshoot in Vout on conductor 4. On the other hand, if gmpRf is chosen to be much less than 1, the feedback loop may not be compensated enough. In this design, the value of gmpRf=0.2 may be used.

The current in transistor MPpa is a scaled-down mirror current of that in pass transistor MPpass. The solution of providing the parallel signal path including transistor MPpa as indicated in FIGS. 5 and 6 works for AC signals, but has problems from a DC point of view. First, transistor MPpa injects DC current into feedback node 4A, which causes a DC error resulting in a regulation accuracy problem. Second, that DC current changes with the output load. This implies that the DC error will change with the load, which degrades the load regulation accuracy. Third, when the load current is low, gmp is too small to make any noticeable contribution to the regulator gain function and the loop compensation.
The above mentioned first and the second problems can be resolved by inserting transistor MPpa into a circuit leg having 2 identical current sources 19 and 20 as shown in FIG. 7C. Then the current through transistor MPpa will no longer change with the load. Moreover, there is no net DC current injected into the R1 and R2 divider except for a small amount of mismatch current. However, a large capacitor Cp is needed at the source of MPpa so that the AC signal can go from gate 3 to node 4A through transistor MPpa.
The above mentioned third problem is resolved by introducing a DC offset voltage VOS between the gates of pass transistor MPpass and parallel path transistor MPpa as indicated in FIG. 7A. With a properly chosen VOS, parallel path transistor MPpa is still has enough gate drive and its gmp is “strong enough” to convert the voltage signal on gate 3A of parallel path transistor MPpa to an effective current signal, even though transistor MPpass is in deep sub-threshold operation. FIG. 7B shows resistor 15 as an implementation of the offset voltage VOS.
FIG. 8A shows a Bode plot for the case in which Cp is large enough that corner frequency gmp/Cp is on the left hand side of frequency gmo/(gmpRfCL). Curves 23-5 and 23-8 show the signal transfer function from gate 3 to node 4A by transistor MPpa. At low frequencies, the effect of transconductance from the drain of transistor MPpa is sCp. (“s” is equal to jω, wherein ω is the frequency in radians) and the voltage signal at node 4A due to transistor MPpa is sCpRf (Curve 23-8). At high frequencies, the effect of transconductance from the drain of transistor MPpa is gmp, and the voltage signal at node 4A due to transistor MPpa becomes gmpRf (curve 23-5). A minimum value of Cp is needed in that the corner frequency, gmp/Cp of curves 23-5 and 23-8 has to be lower than




  
    
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so that the signal from MPpass, Curve 23-4, crosses the level portion of the signal from transistor MPpa, Curve 23-5, in order to avoid a gain notch. It can be determined that Cp has to be greater than gmp2RfC1/gmo. FIG. 8B shows a Bode plot wherein Cp is not large enough and the corner frequency gmp/Cp is on the right hand side of frequency gmo/(gmpRfCL) causing a gain notch 29-7, leading to an inadequate compensation.

If a 1 nanoampere (nA) current flows through parallel signal path transistor MPpa, gmp=40 nanoamperes per volt. Without any external load, i.e., if RL=infinity, the current loading transistor MPpass is from the R1/R2 divider, which conducts 50 nanoamperes, so gmo=2 uA/V, and Cp is found to be 400 nanofarads for CL=100 μF, which is prohibitively large for a monolithic (i.e., on-chip) capacitor.
The gain notch stems from two signals (one signal being from the drain of transistor MPpass which has a 1/s frequency response due to CL, and the other signal being from the drain of transistor MPpa which has s frequency response due to Cp), summing at conductor 4A and canceling each other. To resolve this issue, a fractional frequency response network 24 connected between Vin and conductor 5A as shown in FIG. 9A is used to replace Cp of FIG. 7C. The idea is demonstrated by employing an s1/2 frequency response network. With the s1/2 frequency response network connected to its source, the frequency response at the drain of transistor MPpa becomes s1/2 at low frequencies.
The magnitude (30-1) and phase (30-4) of the sum of the two signals with 1/s and s1/2 frequency responses 30-2 and 30-3, from transistors MPpass and MPpa, respectively, respectively, are shown in FIG. 9B. It can be seen that the magnitude of the sum represented by curve 30-1 troops only for 2 dB at the cross-over frequency. FIG. 9C is the Bode plot which shows that a significant gain notch is avoided by replacing Cp with a s/1/2 frequency response network. This implies that corner frequency ωh can be placed at a fairly high frequency and the compensation network may be implemented using much smaller on-chip capacitors.
The fractional frequency response network 24 of FIG. 9A can be implemented by the RC network shown in FIG. 10A. Network 24 includes a capacitor c3 having one terminal connected to the (+) terminal of a voltage source 25, the (−) terminal of which is connected to ground. The other terminal of capacitor c3 is connected by a conductor 26 to one terminal of a capacitor c2 and to one terminal of a resistor r2, the other terminal of which is connected to ground. The other terminal of capacitor c2 is connected by conductor 27 to one terminal of a resistor r1, the other terminal of which is connected to ground. Conductor 27 also is connected to one terminal of a capacitor c1, the other terminal of which is connected by conductor 28 to one terminal of a resistor ro, the other terminal of which is connected to ground. Conductor 28 also is connected to one terminal of a capacitor c0, the other terminal of which is connected to ground. In network 24, ck+1=nck, rk+1=mrk. (For example, c1=2 c0. c2=4c0, etc.) Further information on fractional frequency response networks can be found in the technical article “Fractal System as Represented by Singularity Function”, by A. Charef, H. H. Sun, Y. Y. Tsao, and B. Onaral, IEEE Transactions on Automatic Control, Vol. 37(9), pp. 1465-1470, September 1992.
To analyze the frequency responses of network 24, the conductance of each component is plotted on a logarithmic scale along dashed lines in FIG. 10B. The oblique lines 31-1,2,3,4 represent the conductances for the capacitors which are parallel and evenly spaced. The horizontal lines 33-1,2,3 for the resistors also are parallel and evenly spaced. The oblique lines 33-1,2,3,4 for the capacitors intersect the horizontal lines 33-1,2,3. It is important to note that each of the capacitors c0, c1, c2 and c3 except the last capacitor c0 is used as a series circuit element, and its AC conductance becomes more dominant when its value is smaller, whereas each of the resistors ro, r1 and r2 is used as a shunt circuit element, and its conductance becomes more dominant when its value is larger. With that observation, the network can be analyzed. Starting from very high frequencies, the AC conductance values of capacitors c0, c1, c2 and c3 are much higher than those of resistors ro, r1 and r2 and capacitor c0 gains the dominance in the serial capacitor chain as if the resistors do not exist. The response of network 24 on conductor 5A follows the c0 conductance line 31-4 down to lower conductance values as the frequency decreases until it intersects r0 conductance line 33-1 and r0 gains the dominance as r0 has a higher shunt conductance. The response of network 24 then follows the r0 conductance line to the next intersection point with the conductance line of c1. From that point, it follows the c1 conductance line further downward, and so forth.
The response of network 24 follows the conductance lines of capacitors and resistors alternatively and repeatedly until it reaches the c3 conductance line, and from there on, it stays on the c3 conductance line. The foregoing response of network 24 is shown as a solid line 34 in FIG. 10B. It can be seen that the broken or piecewise-linear lines alternately following the conductance lines of capacitors and resistors, for frequencies spanning from 1/(c0r0) down to 1/[n(mn)kc0r0] (where k is the number of network stages, k=2 in this case), can be taken as an approximation to a fractional frequency response sa (a=ln(m)/ln(mn)<1, where ln is the natural logarithmic function), shown as a line 34 in FIG. 10B. The low frequency end corner, which is the cross-over between lines 31-1 and 33-4, can be extended further by adding more stages, at the expense of more capacitors and resistors. A better approximation to the fractional frequency response line can be achieved by using smaller values of m and n, at the expense of more stages and more total capacitances and resistances if the frequency span is kept the same. In one design, m=n=2, and a=ln(m)/ln(mn)=1⁄2 are used. FIG. 10C shows the conductance of the RC network shown in FIG. 10A, wherein m=n=2.
By replacing the s1/2 function block in FIG. 9A with the RC network, and setting the value r0=1/(2 gmp)=12.5 megohms, the effective transconductance of the parallel signal path including transistor MPpa and resistors Rf, R1 and R2 is shown in FIG. 10C. The corner frequency ωh is given by gmp/c0. Assuming that gmi=530 nanoamperes per volt, C1=78 pF, Cc=14 pF, gmo=2 micromperes per volt, and gmpRf=0.2, it is found that c0>2.5 pF is enough to compensate the loop for 1 μF<C1<100 μF. A higher value, c0=6.4 pF, is selected in order to provide some leeway in the design. The resistances of the RC network are implemented by means of MOS resistors, which otherwise would be too large to be used on an integrated circuit chip.
FIG. 11 shows a schematic diagram of an LDO voltage regulator 10-2 similar to LDO voltage regulator 10-1 of FIG. 9A, including a parallel fractional frequency response signal path for loop compensation. Error amplifier 2 includes source-coupled N-channel input transistors MN0A and MN0B and a tail current source transistor MN3B, biased as shown by a current source I0 and current mirror input transistor MN3A. The drain of input transistor MN0B is connected to a P-channel transistor MP1C which functions as a load device and also functions as a current mirror input transistor that controls a current mirror output transistor MP1D, the drain of which is connected by conductor 3 to drive the gate of pass transistor MPpass and one terminal of resistor 15 across which the offset voltage VOS is produced. Resistor 15 is set to a resistance of 1 megohm, which gives a VOS of 50 millivolts. The other terminal of resistor 15 is connected to the gate of parallel path transistor MPpa and the drain of a N-channel current mirror output transistor MN2B which functions as current source 17. The gate of transistor MN2B is controlled by N-channel current mirror input transistor MN2A, which receives a current that is mirrored from the drain of input transistor MN0A by means of P-channel transistors MP1A and MP1B. The gate of input transistor MN0A is coupled to Vref.
A P-channel current mirror output transistor MP2B, which functions as current source 19 in FIG. 9A, is controlled by a P-channel current mirror input transistor MP2A by means of a current source IBIAS2 and N-channel current mirror transistors MN4A and MN4E. The drain of transistor MP2B is connected by conductor 5A to fractional frequency response network 24 and to the source of parallel path transistor MPpa. Fractional frequency response network 24 includes capacitors c0, c1, c2, and c3 and resistors r0, r1, and r2 as shown in FIG. 10A, with resistors r0, r1, and r2 implemented by means of P-channel MOS resistors as illustrated. The gates of the MOS resistors are connected to the gate of a P-channel current mirror input transistor MP3 which is driven in response to the current source IBIAS2 by means of N-channel current mirror transistors MN4A and MN4C.
The drain of parallel path transistor MPpa is connected to the source of a P-channel limit transistor MPlimit the drain of which is connected by conductor 4A to the gate of input transistor MN0B, one terminal of feedback resistor Rf, and the drain of a N-channel current mirror output transistor MN4D which functions as current source 20 in FIG. 9A. The gates of transistors MN4B-E are connected to the gate of current mirror output transistor MN4A. The sources of N-channel transistors MN3A, MN3B, MN2A, MN2B, and MN4A-E are connected to ground, and the sources of P-channel transistors MP1A-D, MP2A, and MP2B and MOS resistors MP3 and MP4 are connected to Vin.
The parallel signal current from transistor MPpa drives the feedback node 4A through P-channel transistor MPlimit. There are two reasons that transistor MPlimit is used. First, the parallel signal current through parallel path transistor MPpa is used mainly for loop compensation for very light loads. Transistor MPlimit gradually “pushes” transistor MPpa into its linear operating region when the load current IL increases, and the parallel signal gradually diminishes to a negligible value as the load current IL increases. Second, for very low input voltage Vin or VDD, the gate of pass transistor MPpass can be pulled so low for high load current IL that transistor MPpa may go into linear operation. After transistor MPpa enters linear operation, not only is the parallel signal path broken, but also the fractional RC network appears on feedback conductor 4A, which does not help improve the phase margin at all, and instead introduces further phase shift in the feedback signal, making stability problems even worse.
The unity gain phase margins as a function of the load current for LDO voltage regulator 10-2 of FIG. 11 are shown as Curves 40, 39, and 38 in FIG. 12 for CL=1 μF, 10 μF, and 100 μF, respectively. For comparison, the phase margins for the LDO regulator without the parallel signal path compensation are also shown as Curves 35, 36 and 37 for CL=1 μF, 10 μF, and 100 μF, respectively. It can be seen that significant phase margin improvements are achieved under very light conditions. At high loads, the phase margins gradually approach the phase margins without the parallel path signal compensation, which manifests the parallel path signal current gradually diminishing due to transistor MPlimit as mentioned above.
FIGS. 13A and 13B illustrate the output voltage load transient responses for voltage regulator 10-2 of FIG. 11 with the parallel signal path including transistor MPpa under the condition Vin=3.5 volts, voltage regulator gain G=1, CL=100 μF, RESR=50 megohms, temperature T=25 degrees C. In FIG. 13A the load current goes from 10 uA to 5 mA in 1 microsecond. In FIG. 13B the load goes from 5 mA to 10 uA in 1 microsecond. For comparison, the load transient responses with the same condition for the voltage regulator without the parallel signal path compensation are also shown. Without the parallel compensation path, substantial “ringing” (FIG. 13A) is observed in output voltages, demonstrating a very low phase margin. With the parallel compensation path, however, the ringing magnitudes and recovery times are reduced significantly (FIG. 13B), especially under light load conditions. Thus, a great improvement in the performance of the LDO is achieved with the parallel signal current path of the present invention.
The described PMOS LDO voltage regulators use very little quiescent current, and provide stable operation for a wide range of output capacitor values from roughly 0.5 μF to 200 μF at the present state-of-the-art, both for active and resistive loads. The operation is relatively independent of the equivalent series resistance of the load capacitor CL.
While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, although field effect transistors are used in the described embodiments of the invention, the invention also is applicable to embodiments in which bipolar (NPN and/or PNP) transistors are used.

## Claims

1. A low drop out (LDO) voltage regulator comprising:
a pass transistor having a first electrode coupled by an output conductor to a load and a second electrode coupled to an input voltage;
an error amplifier having a first input coupled to a reference voltage, a second input connected to a feedback conductor, and an output coupled to a control electrode of the pass transistor;
a parallel path transistor having a first electrode coupled to the input voltage, a control electrode coupled to the output of the error amplifier, and a second electrode coupled to the feedback conductor, wherein the gate of the parallel path transistor is coupled to the output of the error amplifier by means of an offset voltage source; and
a feedback resistance coupled between the feedback conductor and the output conductor.

2. The LDO voltage regulator of claim 1 wherein the pass transistor and the parallel path transistor are P-channel MOS transistors, and wherein the first electrodes are sources, the second electrodes are drains, and the control electrodes are gates.

3. The LDO voltage regulator of claim 1 wherein a channel-width-to-channel-length ratio of the parallel path transistor is substantially less than a channel-width-to-channel-length ratio of the pass transistor.

4. The LDO voltage regulator of claim 1 wherein the feedback resistance is a resistance of a feedback resistor is coupled directly between the feedback conductor and the output conductor.

5. The LDO voltage regulator of claim 1 wherein the feedback resistance is coupled to an intermediate conductor of a divider network coupled to the output conductor.

6. The LDO voltage regulator of claim 1 wherein the offset voltage source includes an offset resistor coupled between the gate of the pass transistor and the gate of the parallel path transistor, and also includes a first current source coupled to a first terminal of the offset resistor and a second current source coupled to a second terminal of the offset resistor.

7. The LDO voltage regulator of claim 6 including a third current source coupled between the input voltage and the source of the parallel path transistor, a fourth current source coupled to the drain of the parallel path transistor, and a capacitor coupled between the input voltage and the source of the parallel path transistor.

8. The LDO voltage regulator of claim 6 including a third current source coupled between the input voltage and the source of the parallel path transistor, a fourth current source coupled to the drain of the parallel path transistor, and a fractional frequency response network coupled between the input voltage and the source of the parallel path transistor.

9. The LDO voltage regulator of claim 8 wherein the fractional frequency response network includes first, second, and third MOS resistive elements each having a source coupled to the input voltage and a gate coupled to a first bias voltage, and first, second, third, and fourth capacitors, the first capacitor being coupled between the input voltage and a drain of the first MOS resistive element, the second capacitor being coupled between the drain of the first MOS resistive element and a drain of the second MOS resistive element, the third capacitor being coupled between the drain of the second MOS resistive element and a drain of the third MOS resistive element, the fourth capacitor being coupled between the drain of the third MOS resistive element and the source of the parallel path transistor.

10. The LDO voltage regulator of claim 9 including a current limit transistor having a source coupled to the drain of the parallel path transistor, a gate coupled to a second bias voltage, and a drain coupled to the feedback conductor.

11. The LDO voltage regulator of claim 10 wherein the error amplifier includes first and second input transistors having sources coupled to a tail current transistor, a gate of the first input transistor being coupled to the reference voltage, a gate of the second input transistor being coupled to the feedback conductor, a drain of the first input transistor being coupled to a drain and gate of a first load transistor and a gate of a first current mirror output transistor having a drain coupled to a drain and gate of a first current mirror input transistor and a gate of a second current mirror output transistor which functions as the second current source, a drain of the second input transistor being coupled to a drain and gate of a second load transistor and a gate of a third current mirror output transistor which functions as the first current source.

12. The LDO voltage regulator of claim 11 wherein the first and second input transistors, the first current mirror input transistor, and the second current mirror output transistor are N-channel transistors, and wherein the first and second load transistors and the first and third current mirror output transistors are P-channel transistors.

13. The LDO voltage regulator of claim 12 including a P-channel fourth current mirror output transistor coupled between the input voltage and the source of the parallel path transistor functioning as the third current source and having a gate coupled to a gate and drain of a P-channel second current mirror input transistor and a drain of a N-channel fifth current mirror output transistor having a gate coupled to a gate and drain of a N-channel third current mirror input transistor, a N-channel sixth current mirror output transistor and having a drain coupled to the feedback conductor and a gate coupled to the gate and drain of the third current mirror input transistor, a N-channel seventh current mirror output transistor having a gate coupled to the gate and drain of the third current mirror input transistor and a drain coupled to a gate and drain of a first diode-connected P-channel transistor and the gates of the first, second, and third MOS resistive elements, and a N-channel eighth current mirror output transistor having a drain coupled to the gate of the current limit transistor and a gate and drain of a second diode-connected P-channel transistor and a gate coupled to the gate and drain of the third current mirror input transistor, the third current mirror input transistor having its gate and drain coupled to a bias current source.

14. A method of operating a low drop out (LDO) voltage regulator with low quiescent current and at least a predetermined phase margin despite large variations in load current, the method comprising:
applying an input voltage to a first electrode of a pass transistor and coupling a second electrode of the pass transistor to an output conductor applying an output voltage to a load;
coupling a first input of an error amplifier to a reference voltage, and coupling an output of the error amplifier to a control electrode of the pass transistor;
coupling a feedback resistance between the output conductor and a second input of the error amplifier; and
compensating the LDO voltage regulator by coupling a parallel path transistor between the input voltage and the second input of the error amplifier and by coupling a control electrode of the parallel path transistor to the output of the error amplifier, wherein an offset voltage is applied between the control electrode of the parallel path transistor and the output of the error amplifier.

15. The method of claim 14 wherein applying the offset voltage includes forcing a current through an offset resistor to generate the offset voltage and coupling a first current source between the input voltage and the first electrode of the parallel path transistor, coupling a fourth current source to the second electrode of the parallel path transistor, and coupling capacitive circuitry between the input voltage and the first electrode of the parallel path transistor.

16. The method of claim 15 providing the capacitive circuitry in the form of a fractional frequency response network coupled between the input voltage and the first electrode of the parallel path transistor.

17. The method of claim 15 including coupling a current limit transistor between the second electrode of the parallel path transistor and the second input of the error amplifier, and coupling a control electrode of the current limit transistor to a second bias voltage.

18. A low drop out (LDO) voltage regulator with low quiescent current and at least a predetermined phase margin despite large variations in load current, comprising:
a pass transistor and means for applying an input voltage to a first electrode of the pass transistor and means for coupling a second electrode of the pass transistor to apply an output voltage to a load;
means for coupling a first input of an error amplifier to a reference voltage and means for coupling an output of the error amplifier to a control electrode of the pass transistor;
means for coupling a feedback resistance between the output voltage and a second input of the error amplifier; and
parallel path means coupled between the input voltage and the second input of the error amplifier for compensating a feedback loop of the LDO voltage regulator, the parallel path means comprising a second transistor having a gate thereof coupled to the output of the error amplifier via offset voltage means.