# Patent

## Title
ESR zero estimation and auto-compensation in digitally controlled buck converters

## Abstract

One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the estimate.

## Background
CLAIM OF PRIORITY
This application claims priority from the following application, which is hereby incorporated in its entirety: U.S. Provisional Application No. 61/083,398 entitled: “ESR ZERO ESTIMATION AND AUTO-COMPENSATION IN DIGITALLY CONTROLLED BUCK CONVERTERS”, by Zhenyu Zhao, et al., filed Jul. 24, 2008.


BACKGROUND
In DC-DC buck converters, the output capacitor Equivalent Series Resistance (ESR) introduces a left-hand plane zero in converter's transfer function. The zero influences the loop response therefore must be taken into account in compensator design. Otherwise, the system could suffer from low speed, less phase margin or even instability. Since the end customers may use different types of capacitors, the ESR value is not always known/certain during the board design phase. Even for capacitors with known ESRs, their values vary significantly due to tolerances and temperature. Therefore, the application engineers usually have to go through a tedious process of reconfiguring the compensation networks iteratively.
Digital control of dc-dc switch mode power supply has gradually matured over the past 10 years. One of the most attractive features of digital control is the online system identification and auto-compensation. Component variations of the power stage are identified and compensator is redesigned/retuned accordingly to achieve the desired dynamic response. Most of the existing Process Identifier (PID) auto-tuning methods focus on identifying the power stage corner frequency. Another important variable, capacitor ESR zero frequency, is seldom considered or modeled.
In one prior art system, PID compensator design is based on a complete frequency domain identification including the ESR zero. However, the method requires open-loop operation and heavy computations. Therefore, it is not suitable for online operation in low-power cost-effective applications.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a digitally controlled buck converter with ESR zero auto-compensation of one embodiment.
FIG. 2 are diagrams that conceptually illustrate an ESR identification phase of one embodiment.
FIG. 3 is a diagram that conceptually illustrates a Bode plot of a loop transfer function with different ESR zero compensation parameters.
FIGS. 4-10 are diagrams that illustrate the operation of an exemplary buck converter of one embodiment of the present invention.



DETAILED DESCRIPTION
One embodiment of the present invention is a method for estimating and compensating the zero in power stage transfer function introduced by the capacitor ESR. The ESR zero can be estimated by online measuring the output voltage ripple. A PID compensator can be updated based on the identified zero to avoid stability problems.
FIG. 1 shows a digitally controlled buck converter with ESR zero auto-compensation.
A digitally controlled DC-DC converter 100 can comprise a power stage 102 including at least one switch 104 and 105 and an output capacitor 106. A digital controller 108 can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the ESR of the output capacitor 106 and to update the control of the switching of the switch in the power stage based on the indication.
In one embodiment, an ESR zero identification block 110 can determine the indication of the zero resulting from the ESR of the output capacitor 106.
The indication can be an estimate of the total ESR times the capacitance value (RESRC). The indication could alternately be an estimate of the RESR value, an estimate of the ESR zero, or an estimate of the ESR zero frequency.
A PID 112 can use the indication to update the control operations of the digital controller 108.
The digital controller 108 can produce an estimate of an output voltage ripple resulting from the ESR of the output capacitor. The output voltage of the power stage can be sampled at least twice during a duty cycle period to determine the estimate of the output voltage ripple. The duty cycle period can be increased to obtain the estimate of the output voltage ripple or a high sampling rate ADC can be used.
The estimate of the output voltage ripple can be used along with an LC estimate value to produce an estimate of the zero resulting from the equivalent series resistance of the output capacitor.
The LC estimate value can be calculated by the digital controller using LCO identification block 114 or a stored value for the LC estimate can be used.
The power stage can be a buck converter or some other type of circuit.
In one embodiment, an estimate of the equivalent series resistance is calculated from an estimate of an RESRC value.
The buck converter shown in FIG. 1 can have the following output transfer function:




  
    
      
        
          
            i
            .
            
              
            
            ⁢
            
              G
              ⁡
              
                (
                s
                )
              
            
          
          =
          
            
              
                
                  v
                  o
                
                ⁡
                
                  (
                  s
                  )
                
              
              
                δ
                ⁡
                
                  (
                  s
                  )
                
              
            
            =
            
              
                V
                
                  i
                  ⁢
                  
                    
                  
                  ⁢
                  n
                
              
              ·
              
                
                  1
                  +
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    
                      τ
                      ESR
                    
                  
                
                
                  1
                  +
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      ξ
                      
                        ω
                        0
                      
                    
                    ⁢
                    s
                  
                  +
                  
                    
                      s
                      2
                    
                    
                      ω
                      0
                      2
                    
                  
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            
              where
              ⁢
              
                
              
              ⁢
              
                τ
                ESR
              
            
            =
            
              
                R
                ESR
              
              ⁢
              C
            
          
          ,
          
            
              ω
              0
            
            =
            
              
                1
                
                  LC
                
              
              ⁢
              
                
              
              ⁢
              and
            
          
        
        ⁢
        
          
        
        ⁢
        
          

        
        ⁢
        
          ξ
          =
          
            
              
                (
                
                  
                    R
                    dson
                  
                  +
                  
                    R
                    ESL
                  
                  +
                  
                    R
                    ESR
                  
                
                )
              
              2
            
            ⁢
            
              
                
                  C
                  L
                
              
              .
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




It can be seen that the ESR zero in equation (1) is located at the radian frequency of




  
    1
    
      
        R
        ESR
      
      ⁢
      C
    
  
  .




Next, we show how the product RESRC can be obtained from measurements.

Since the output voltage ripple is closely correlated with RESR it can be used to acquire information about the ESR zero. The amplitude of the ripple can be expressed as:

ΔVrip=√{square root over ((ΔVESR2+ΔVC2))}  (2)

where it can be decomposed into two parts, contribution from RESR, ΔVESR and that from the capacitor, ΔVc. They can be further expressed as follows:





  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            ESR
          
        
        =
        
          
            
              
                R
                ESR
              
              ·
              Δ
            
            ⁢
            
              
            
            ⁢
            I
          
          =
          
            
              R
              ESR
            
            ⁢
            
              
                
                  V
                  g
                
                -
                V
              
              L
            
            ⁢
            
              DT
              s
            
          
        
      
    
    
      
        (
        3
        )
      
    
  
  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            C
          
        
        =
        
          
            
              
                ∫
                t
                
                  t
                  +
                  
                    T
                    s
                  
                
              
              ⁢
              
                Δ
                ⁢
                
                  
                
                ⁢
                I
                ⁢
                
                  d
                  τ
                
              
            
            
              4
              ⁢
              C
            
          
          =
          
            
              
                (
                
                  
                    V
                    g
                  
                  -
                  V
                
                )
              
              ⁢
              
                DT
                s
                2
              
            
            
              8
              ⁢
              LC
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




where D is the steady state duty-ratio, ΔI the inductor current ripple, Ts the switching cycle.

Equation (2) can be obtained from phasor analysis where the two ripple components, ΔVESR and ΔVC, are approximated to be 90 degree out of phase. If the total voltage ripple is dominated by the contribution from ESR, i.e. ΔVrip≈ΔVESR, we can use the measured ripple amplitude to backward calculate RESR and ESR zero frequency,




  
    f
    ESR
  
  =
  
    1
    
      2
      ⁢
      π
      ⁢
      
        
      
      ⁢
      
        
          R
          ESR
        
        ·
        C
      
    
  




as shown in the equation below:





  
    
      
        
          
            R
            ESR
          
          ·
          C
        
        =
        
          
            
              LC
              ·
              Δ
            
            ⁢
            
              
            
            ⁢
            
              V
              rip
            
          
          
            
              (
              
                
                  V
                  g
                
                -
                V
              
              )
            
            ⁢
            
              DT
              s
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




Note that only the accurate knowledge of the product of LC is required in (5). Fortunately, LC product can be obtained by measuring intentionally introduced small oscillations at power stage corner frequency.
Let us now show the condition for ΔVESR to dominate in (2). From equation (3) and (4) it is clear that this condition would require that the ratio of




  
    Δ
    ⁢
    
      
    
    ⁢
    
      V
      ESR
    
  
  
    Δ
    ⁢
    
      
    
    ⁢
    
      V
      C
    
  




is greater than 1. By using equations (3-4), this condition can be expressed further in terms of frequency relations as follows:





  
    
      
        
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              ESR
            
          
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              C
            
          
        
        =
        
          
            8
            ⁢
            
              
            
            ⁢
            
              ESR
              ·
              
                Cf
                s
              
            
          
          =
          
            
              4
              ⁢
              
                f
                s
              
            
            
              π
              ⁢
              
                
              
              ⁢
              
                f
                ESR
              
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




This condition indicates that the switch frequency of the converter, fs, needs to be at least 4/π times or higher than that of the ESR zero frequency so that the ripple will be dominated by ΔVESR. In other words, the ripple measurement reflects only the fESR less than fs. In fact, when fESR is higher than half of fs its influence on the digital control loop is negligible.
Based on the above analysis, identifying ESR zero up to half of the switching frequency is of the most interest. To obtain higher measurement accuracy, the switching frequency during identification can be reduced to half of the switching frequency. Halving the frequency also allows for the sampling of the output voltage twice per cycle using the same ADC 116 as in the normal operation. FIG. 2 illustrates the system operation during an ESR identification phase. Two consecutive errors, e1 and e2 (derived from the sampling of the output voltage) can be obtained in one cycle. From the difference between these two sampled errors, Δe, the output voltage ripple, ΔVrip is estimated as ΔVrip=2(1−D)·Δe due to the linear relationship for the case when duty ratio D is less than 50%. If duty ratio D is greater than 50 percent, we can sample twice on the rising slope of the output voltage ripple; in that case the ripple estimate becomes: ΔVrip=2D·Δe. Equation (5) can be computed using a pre-stored look-up table. The following shows how the identified RESRC from the calculation of equation (5) can be used in the PID design.
A proposed discrete-time PID has the form shown below:




  
    
      
        
          
            
              
                PID
                ⁡
                
                  (
                  z
                  )
                
              
              =
              
              ⁢
              
                
                  
                    PID
                    org
                  
                  ⁡
                  
                    (
                    z
                    )
                  
                
                ·
                
                  kz
                  
                    z
                    -
                    d
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    
                      az
                      2
                    
                    +
                    bz
                    +
                    c
                  
                  
                    
                      (
                      
                        z
                        -
                        1
                      
                      )
                    
                    ⁢
                    z
                  
                
                ·
                
                  kz
                  
                    z
                    -
                    d
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  k
                  ⁡
                  
                    (
                    
                      
                        az
                        2
                      
                      +
                      bz
                      +
                      c
                    
                    )
                  
                
                
                  
                    (
                    
                      z
                      -
                      1
                    
                    )
                  
                  ⁢
                  
                    (
                    
                      z
                      -
                      d
                    
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




where a pole at an identified ESR zero will be introduced to the original PID design, PIDorg(z), which has a pole at z=0 meaning a one cycle delay or an equivalent s-plane pole at 1⁄2·fsw. This is equivalent to introduce a lead-lag filter having transfer function:





  
    
      k
      ·
      z
    
    
      z
      -
      d
    
  
  .




The dc gain can be unchanged to ensure the specified bandwidth. Using final value theorem, at s=0 or z=1, the gain of the filter should remain 1, which means





  
    k
    
      1
      -
      d
    
  
  =
  
    
      1
      ⁢
      
        
      
      ⁢
      or
      ⁢
      
        
      
      ⁢
      k
    
    =
    
      1
      -
      
        d
        .
      
    
  




The transformation of ESR zero to discrete domain can be simply performed using pole matching equivalence that is




  d
  =
  
    
      e
      
        
          -
          
            ω
            ESR
          
        
        ⁢
        
          T
          sw
        
      
    
    =
    
      
        e
        
          -
          
            1
            
              
                f
                sw
              
              ⁢
              
                ESR
                ·
                C
              
            
          
        
      
      .
    
  




Again, a look-up table can be employed to perform this transformation in such a low-cost controller. A comparison of loop frequency response using different PID designs is shown in FIG. 3.

FIG. 3 shows Bode plots comparison of loop transfer function PID(z)*G(z) using different ESR zero compensation parameters. Red (lines 306a and 306b): d=0.77; Green (lines 304a and 304b): d=0.5 (matched with ESR zero); Blue (lines 302a and 302b): d=0. One can see the over-compensated PID, lines 306a and 306b, decrease phase margin and cause stability problems. On the other hand, the under-compensated PID, 302a and 302b, makes the system noise sensitive at high frequency. Only the proposed well-matched PID design, lines 304a and 304b, ensures stability and a desired bandwidth.
A Field-Programmable Gate Array (FPGA) based prototype has been built around a 12V-1.5V 500 kHz 10 W buck converter. A complete system identification test is shown in FIG. 4. As we can see, in phase 1, the power stage LC frequency is acquired from intentionally introduced self oscillations and in phase 2, the ESR zero is identified from voltage ripple measurement as switching frequency is reduced. The sudden change in switching frequency introduces a sub-transient that can be seen more evidently in FIG. 5, an enlarged view of phase 2. In one embodiment, the sub-transient induced by the frequency change is insignificant and does not affect regulation. The number of cycles that the system operates at lower switching frequency can be as small as one.
Phase 2 can also be run independently given that a rough knowledge of LC is known a priori. In the case of FIGS. 4 and 5, the measurement of a small voltage ripple indicates that the ESR zero is at high frequency close to half of the switching frequency. A PID compensator is constructed according to provide fast transient response with a control bandwidth of 50 kHz. The load transient response can be found in FIG. 6. However, if a PID designed to compensate low frequency ESR zero is used for the regulation, assuming output capacitors have large ESR, the system will become unstable. This is verified by the results in FIG. 7.
In another scenario, when output capacitors have large ESR, or low frequency ESR zero, larger output ripple is measured in FIG. 8. A PID constructed accordingly delivers satisfactory response shown in FIG. 9. However, as can be seen in FIG. 10, the PID that worked well for small ESR makes the system very sensitive to noise and adds stress to components. This confirms that the ESR identification and compensation is necessary for ensuring the system stability and a well-controlled bandwidth.
The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

## Claims

1. A digitally controlled DC-DC converter comprising:
a power stage including at least one switch and an output capacitor; and
a digital controller to control the switching of the at least one switch; wherein the digital controller includes logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the indication.

2. The digitally controlled DC-DC converter of claim 1, wherein the indication is an estimate of the total ESR of the output capacitor times the capacitance of the output capacitor.

3. The digitally controlled DC-DC converter of claim 1, wherein the power stage is a buck converter.

4. The digitally controlled DC-DC converter of claim 1, wherein the digital controller produces an estimate of an output voltage ripple resulting from the ESR of the output capacitor.

5. The digitally controlled DC-DC converter of claim 4, wherein the output voltage is sampled at least twice during a duty cycle period to determine the estimate of the output voltage ripple.

6. The digitally controlled DC-DC converter of claim 5, wherein the duty cycle period is increased to obtain the estimate of the output voltage ripple.

7. The digitally controlled DC-DC converter of claim 4, wherein an estimate of the output voltage ripple is used along with an LC estimate value to produce an estimate of the zero resulting from the ESR of the output capacitor.

8. The digitally controlled DC-DC converter of claim 7, wherein the LC estimated value is calculated by the digital controller.

9. The digitally controlled DC-DC converter of claim 1, wherein the digital controller includes a Processor Identifier (PID) that is updated with the indication.

10. A digital controller to control the switching of at least one switch of a power stage wherein the digital controller includes logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the indication.

11. The digital controller of claim 10, wherein the indication is an estimate of the total ESR of the output capacitor times the capacitance of the output capacitor.

12. The digital controller of claim 10, wherein the digital controller produces an estimate of an output voltage ripple resulting from the ESR of the output capacitor.

13. The digital controller of claim 12, wherein the output voltage is sampled at least twice during a duty cycle period to determine the estimate of the output voltage ripple.

14. The digital controller of claim 13, wherein the duty cycle period is increased to obtain the estimate of the output voltage ripple.

15. The digital controller of claim 12, wherein the estimate of the output voltage ripple is used along with an LC estimate value to produce an estimate of the zero resulting from the ESR of the output capacitor.

16. The digital controller of claim 15, wherein the LC estimate is value calculated by the digital controller.

17. The digital controller of claim 10, wherein the digital controller includes a Processor Identifier (PID) that is updated with the estimate.

18. A digital controller to control the switching of at least one switch of a power stage wherein the digital controller includes logic to produce an estimate of an equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the estimate.

19. The digital controller of claim 18, wherein the estimate of the equivalent series resistance is calculated from an estimate of an RESDC value.

20. The digital controller of claim 18, wherein the digital controller produces an estimate of an output voltage ripple resulting from the ESR of the output capacitor.

21. The digital controller of claim 20, wherein the output voltage is sampled at least twice during a duty cycle period to determine the estimate of the output voltage ripple.

22. The digital controller of claim 21, wherein the duty cycle period is increased to obtain the estimate of the output voltage ripple.

23. The digital controller of claim 20, wherein the estimate of the output voltage ripple is used along with an LC estimate value to produce an estimate of the zero resulting from the ESR of the output capacitor.

24. The digital controller of claim 23, wherein the LC estimated value is calculated by the digital controller.

25. The digital controller of claim 18, wherein the digital controller includes a PID that is updated with the estimate.