# Patent

## Title
Method and system for efficient decomposition of single-qubit quantum gates into Fibonacci anyon braid circuits

## Abstract

Methods for compiling single-qubit quantum gates into braid representations for non-Abelian quasiparticles described by the Fibonacci anyon model are based on a probabilistically polynomial algorithm that, given a single-qubit unitary gate and a desired target precision, outputs a braid pattern that approximates the unitary to desired precision and has a length that is asymptotically optimal (for a circuit with such property). Single-qubit unitaries that can be implemented exactly by a Fibonacci anyon braid pattern are classified, and associated braid patterns are obtained using an iterative procedure. Target unitary gates that are not exactly representable as braid patterns are first approximated to a desired precision by a unitary that is exactly representable, then a braid pattern associated with the latter is obtained.

## Background
FIELD
The disclosure pertains to methods of decomposing single-qubit quantum gates into asymptotically optimal quantum circuits based on Fibonacci anyon braids.
BACKGROUND
As devices for performing quantum computations mature, the need for efficient quantum compilation methods increases. While conventional quantum devices will require vast amounts of error correction to combat decoherence, certain two-dimensional quantum systems based on non-Abelian anyons, or quasiparticle excitations obeying non-Abelian statistics, will require little to no error correction. These systems are intrinsically protected against local errors by storing information globally rather than locally. When two quasiparticles are kept sufficiently far apart and braided adiabatically, a unitary evolution is realized. Such an evolution is called a braid of world lines, and such braids are topologically protected from local errors.
The use of non-Abelian anyons for topological quantum computation would allow intrinsic fault tolerance. For the so-called Fibonacci anyons, the state may be described by a fractional quantum Hall (FQH) plateau at filling fraction μ=12/5. In fact, it has been shown that in some cases, such anyons can realize universal quantum computation with braiding alone. Fibonacci anyons are thought to enable implementation of topological quantum computing. These quasiparticles allow quantum information to be natively topologically protected from decoherence and also allow a universal set of topologically protected quantum gates called “braiding matrices”, or “braids.”
Practical compilation (referred to herein also as decomposition or synthesis) of quantum circuits into braiding matrices has been an open topic until recently. Conventional compilation procedures are based on the Dawson-Nielsen implementation of the Solovay-Kitaev theorem, which states that any single-qubit quantum gate can be approximated to a desired precision ε using a circuit of depth




  
    O
    ⁡
    
      (
      
        
          ln
          c
        
        ⁡
        
          (
          
            1
            ε
          
          )
        
      
      )
    
  
  ,




wherein c is approximately 3.97.

Methods have been previously developed for approximating a single-qubit unitary based on brute-force searches to find a braid with depth




  
    O
    ⁡
    
      (
      
        
          ln
          c
        
        ⁡
        
          (
          
            1
            ε
          
          )
        
      
      )
    
  
  ,




where c=1, but require exponential time. The number of braids, however, grows exponentially with the depth of the braid, making this technique infeasible for long braids that are required to achieve a required precision. Thus, these methods are not practical for approximating single-qubit unitaries, and improved methods are needed. Disclosed herein are methods and apparatus that produce decompositions of single-qubit quantum gates into circuits drawn from the basis of Fibonacci anyon braid matrices such that circuit depth is





  
    O
    ⁡
    
      (
      
        
          ln
          c
        
        ⁡
        
          (
          
            1
            ε
          
          )
        
      
      )
    
  
  ,




wherein c=1 and ε is the desired decomposition precision.

SUMMARY
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Disclosed herein are methods and apparatus that produce decompositions of single-qubit quantum gates into circuits drawn from the basis of Fibonacci anyon braid matrices such that circuit depth is




  
    O
    ⁡
    
      (
      
        
          ln
          c
        
        ⁡
        
          (
          
            1
            ε
          
          )
        
      
      )
    
  
  ,




wherein c=1 and ε is the desired decomposition precision, in expected polynomial time.

In typical examples, a target gate is evaluated to determine if it is exactly representable as a braid pattern circuit, or “braid circuit.” If so, the target circuit is decomposed as a sequence of F-gates and T-gates, defined below, in an iterative procedure in which circuit complexity is reduced at each iteration. If the target circuit is not exactly representable as a braid pattern circuit, an alternative target gate that is exactly representable as a braid pattern circuit is identified that approximates the target gate within a specified precision. The alternative target gate is then decomposed into a braid pattern circuit that consists of a sequence of F-gates and T-gates. The sequence of gates corresponding to an exact or non-exact unitary target gate includes gates corresponding to a product FTk, wherein k is a non-negative integer, k≦9, and



  
    
      F
      =
      
        (
        
          
            
              τ
            
            
              
                τ
              
            
          
          
            
              
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                -
                τ
              
            
          
        
        )
      
    
    ,
    
      

    
    ⁢
    
      τ
      =
      
        
          (
          
            
              5
            
            -
            1
          
          )
        
        2
      
    
  




  
    
      T
      =
      
        (
        
          
            
              1
            
            
              0
            
          
          
            
              0
            
            
              ω
            
          
        
        )
      
    
    ,
    
      

    
    ⁢
    and
  




  
    ω
    =
    
      
        e
        
          i
          ⁢
          
            
          
          ⁢
          
            π
            /
            5
          
        
      
      .
    
  



Such a sequence of gates also includes gates corresponding to a product ωkTj, wherein j and k are non-negative integers. Upon reduction of circuit complexity to a predetermined value, gates of the form ωkTj are included in the decomposition.

The foregoing and other objects, features, and advantages of the disclosed technology will become more apparent from the following detailed description, which proceeds with reference to the accompanying figures.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a method of obtaining a braid pattern associated with an exact unitary circuit.
FIG. 2 illustrates a norm solver procedure.
FIG. 3 illustrates a construction associated with random selection in Z(ω).
FIG. 4 is a simplified block diagram of a method of obtaining an F, T sequence corresponding to an input qubit circuit that may or may not be an exact unitary.
FIG. 5 is a block diagram of a representative computing environment in which the disclosed methods can be implemented.
FIG. 6 is a block diagram of a representative computing environment that includes classical and quantum processing.
FIG. 7 illustrates a method of establishing an F, T sequence corresponding to an input qubit circuit, and a circuit constructed based on the established F, T sequence.



DETAILED DESCRIPTION
As used in this application and in the claims, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Further, the term “coupled” does not exclude the presence of intermediate elements between the coupled items.
The systems, apparatus, and methods described herein should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and sub-combinations with one another. The disclosed systems, methods, and apparatus are not limited to any specific aspect or feature or combinations thereof, nor do the disclosed systems, methods, and apparatus require that any one or more specific advantages be present or problems be solved. Any theories of operation are to facilitate explanation, but the disclosed systems, methods, and apparatus are not limited to such theories of operation.
Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed systems, methods, and apparatus can be used in conjunction with other systems, methods, and apparatus. Additionally, the description sometimes uses terms like “produce” and “provide” to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art. Terms such as “optimize,” “optimal,” “preferred,” “best,” or other similar terms are used to indicate a choice among alternatives, and do not imply achievement of any specific degree of performance.
The disclosed methods can be implemented using computer-readable media. Computer-readable media are any available tangible media that can be accessed within a computing environment. By way of example, and not limitation, with a computing system, computer-readable media include memory, storage, and combinations of any of the above. Such media can store computer-executable instructions, such as those included in program modules, being executed in a computing system on a target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or split between program modules as desired in various embodiments. Computer-executable instructions for program modules may be executed within a local or distributed computing system.
I. Introduction and Definitions



  
    
      Primitive
      ⁢
      
        
      
      ⁢
      tenth
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      ⁢
      root
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      Golden
      ⁢
      
        
      
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      Inverse
      ⁢
      
        
      
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        ⁢
        
          
        
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          ⁢
          
            
          
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          ⁢
          
            :
          
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        ⁢
        
          
        
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For convenient description, target circuits are sometimes referred to as “unitaries” or “exact unitaries” or “unitary matrices.” They are also sometimes referred to as “gates” or “quantum gates.” In addition, as used herein, “circuits” can refer to either physical implementations of quantum computational devices, or definitions associated with computations to be executed with the quantum computational devices. For convenience, sequences of gates are typically referred to as circuits, but the terms gate and circuit are sometimes used interchangeably, and meaning in a particular situation will be apparent.
Some single-qubit unitaries can be implemented exactly by braiding Fibonacci anyons. Disclosed herein are methods for identifying such unitaries, and finding braid pattern circuits that correspond to such exact unitaries. For ease of description, these approaches are described with reference to T and F gates that define F, T circuits. In other examples, the braiding matrices σ1, σ2 can be used, defining σ1, σ2 circuits. Any circuit that can be implemented as an F, T circuit can also be implemented as a σ1, σ2 circuit.
As used herein, an exact unitary is defined by an integer k and u, vεZ(ω), wherein Z(ω) is the ring of integers extended by the primitive fifth root of unity, i.e., Z(ω)={a+bω+cω2+dω3}, a, b, c, dεZ, Z is the ring of integers, and |u2|+τ|v2|=1. With these definitions, an exact unitary U[u, v, k] can be expressed as:




  
    U
    ⁡
    
      [
      
        u
        ,
        v
        ,
        k
      
      ]
    
  
  :=
  
    (
    
      
        
          u
        
        
          
            
              v
              *
            
            ⁢
            
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    )
  




A unitary can be expressed as a product of F and T gates if and only if it is exact. Methods of determining a suitable sequence of F and T gates are described below for unitaries that are exact. In addition, methods for determining exact unitaries that approximate unitaries that are not exact are provided. These approximating unitaries (which are exact unitaries) can then be assigned suitable sequences of F and T gates.
II. Exact Synthesis
Referring to FIG. 1, a method 100 for obtaining a braid pattern circuit as a product of F gates and T gates includes obtaining an exact unitary U[u, v, k] at 102. At 104, initial values of a reduced matrix Ur are assigned to be those of the input exact unitary, and the associated circuit C is defined to be empty, i.e., as lacking any gates. At 106, a complexity of U is determined as g=G(U). (A representative procedure for obtaining a Gauss complexity measure is described in detail below). If the estimated complexity is greater than two, an integer value J is obtained as arg min G(FTJUr) for Jε{1, . . . , 10} at 110. At 112, the reduced matrix Ur is assigned new values as Ur=FTJUr and a complexity g of the new reduced matrix is obtained. The value of J from 110 is used to define a product FT10−J that is added to the beginning of the circuit C at 114.
The method 100 then returns to 108, and continues as above until the complexity g≦2. Once the complexity g is reduced, at 116, integer values k, j are found so that Ur=ωkTj, and ωkTj is added to the beginning of the circuit at 118. At 120, the circuit C is output as a sequence based on F, T, and ω.
Using the above method, any exact unitary can be associated with a sequence of F gates and T gates. Using the definitions of F and T, it can be shown that F2=I and T10=I, wherein I is the 2×2 identity matrix. Accordingly, any unitary can be represented as a matrix product ωk(m+1)Tk(m)FTk(m−1)FTk(m−2) . . . FTk(0), wherein k(j) are integers from 0 to 9. This sequence of gates thus represents an exact unitary, and m is a number of steps used to obtain the sequence representation. There are no integer sequences k(m−1), . . . , k(1) of the following forms:
4, 4
4, 1, 4
4, 1, 4
4, 1, . . . , 1, 4
Gauss Complexity Measure
The determination of Gauss complexity can be described with reference to an automorphism of Z(ω) based on the Galois automorphism, denoted by (.)●, where the mapping is given by (.)●: Z(ω)→Z(ω) such that (ω)●=ω3. A ring automorphism must preserve the sum and the product, thus

τ●=(ω2−ω3)●=(ω2)●−(ω3)●=(ω●)2−(ω●)3=−φ.

Taking into account that φ=τ+1, and that φ is from Z(τ), then the automorphism restricted on Z(τ) is also an automorphism of Z(τ). It can also be shown that (x●)●=x*. This implies that (x*)●=(x●)* and |x●|*=(|x|2)● since |x|2=xx*.
With the definition of Galois automorphism, the Gauss complexity measure is given by

G(u)=|u|2+|u●|2.

For the general exact unitary, the Gauss complexity measure is given by

G(U[u,v,k])=G(u).

In the exact synthesis methods disclosed above, the complexity of the unitary Ur is reduced by multiplication by FTk at each step.
For any xεZ(ω), G(x) is an integer and

G(a+bω+cω2+dω3)≦5/2(a2+b2+c2+d2).

If G(x)=0, then x=0. If G(x)=2, then x=ωk, wherein k is an integer. Otherwise, G(x)≧3.
An exact synthesis algorithm is given by the following pseudocode.







TABLE 1





Exact Synthesis Procedure

















Input: U - exact unitary










1:
procedure EXACT-SYNTHESIZE(U)



2:
 g ← G(U),Ur ← U,C ← (empty circuit)



3:
 while g > 2 do



4:
  J ← argminj∈{1,...,10}G (FTjUr)



5:
  Ur ← FTJUr,g ← G (Ur)



6:
  Add FT10−J to the beginning of circuit C



7:
 end while



8:
 Find k,j such that Ur = ωkTj



9:
 Add ωkTj to the beginning of circuit C



10:
end procedure









Output: C - circuit over   F,T   that implements U










The exact synthesis algorithm is correct based on the following. For any u, v from Z(ω) such that |u|≠1, |u|≠0, |u|2+τ|v|2=1, there exists k0(u, v) such that




  
    
      
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where r(n) is in





  
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In addition, for any k, the ratio





  
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is upper bounded by





  
    
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For any exact unitary U in the form given by




  
    
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      ⁡
      
        [
        
          u
          ,
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          ,
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        ]
      
    
    :=
    
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  ,




the exact synthesis algorithm terminates and produces a circuit that implements U, n is the minimal length of the F, T circuit implementing U and is in Θ(log(G(U))), and the algorithm requires at most O(n) arithmetic operations and outputs an F, T circuit with O(n) gates.

III. Norm Equation Solution
As discussed above, an exact unitary has the form:




  
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    ⁡
    
      [
      
        u
        ,
        v
        ,
        k
      
      ]
    
  
  :=
  
    
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      )
    
    .
  




Such exact unitaries can be associated with products of the F gates and T gates, without any approximation (i.e., precision ε=0), using the exact synthesis procedure described above. A method is needed to complete an element from the ring Z(ω) such that together it makes a unitary of the form of U[u, v, k].
As an example, consider the case where the target unitary is the Pauli X gate. The off-diagonal element 1 needs to be represented as 1=√{square root over (φ)}√{square root over (τ)} and the √{square root over (φ)} needs to be approximated. Suppose a uεZ(ω) has been found such that |u−√{square root over (φ)}|<ε. Since |u| cannot be made exactly equal to √{square root over (φ)}, the matrix




   
  
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is going to be subtly non-unitary. Thus, the diagonal elements will need to be filled with elements v, v*εZ(ω), however tiny, such that |v|2+|u|2τ=1. This amounts to solving the equation |v|2=1−|u|2 for vεZ(ω).

Representative methods of reconstructing an exact unitary given one of its entries are described below. In the most general setting this problem is hard. Here particular instances of the problem are identified that can be solved in probabilistic polynomial time. Thus, efficient algorithms for both the identification of “easy” instances and solving them are provided.
The are two distinct cases of an exact unitary reconstruction problem and both are reduced to the problem of finding x from Z(ω) such that

|x|2=ξ for ξ from Z[ω].

The first case is finding an exact unitary U[u, v, k] given u and the second is finding an exact unitary when v is given. In the first case, v is found by solving the equation ξ=φ(1−|u|2) and in the second u is found by considering ξ=1−τ|v|2 An equation is introduced called a relative norm equation because mapping |•|2 from Z[ω] to Z[τ] is a relative norm of a relative extension  ̃Z[ω]/Z[τ]
Methods for identification of “easy” instances are provided and efficiently computable criterion for these instances are summarized in Table 2. The key observation for this and for solving the more general instances of the problem is that |•|2 is a multiplicative function. In other words, if the right-hand side of the equation can be written as ξ1·ξ2 we can find solutions for each ξi and combine them to get solution to the original equation. For this reason, the relation of divisibility on elements of Z[τ] is one of the basic tools. As used herein, ξ1 divides ξ if there exist ξ2 from Z[τ] is such that ξ=ξ1ξ2. This relation is denoted as ξ1|ξ. In this case we also write ξ=0 mod ξ1 or, more generally η1=η2 mod ξ1 when ξ1|(η2−η1). The alternative way of understanding the divisibility of elements of Z[τ] is using an algebraic norm of Z[τ], defined as Nτ(a+bτ)=(a+bτ)(a+bτ)●=a2−ab−b2. Then ξ1|ξ if and only if Nτ(ξ1)|Nτ(ξ). The basic instances of the norm equation problem are the elements of Z(τ) such that their algebraic norm Nτ is a prime number and they can be solved in probabilistic polynomial time. An instance is easy if for the right-hand side ξ, Nτ(ξ)=5np, where n is an integer and p is prime. A test EASY-SOLVABLE summarized in Table 2 efficiently determines if the instance is easy.
A norm solving procedure is summarized in Table 3, and procedures used in the norm solver are summarized in Tables 4-8, and some of which are described in further detail.







TABLE 2





Procedure for Determining Easy Solvable Instances

















Input: ξ ∈   [τ]










1:
procedure EASY-SOLVABLE(ξ)



2:
 if ξ < 0 or ξ• < 0 then



3:
  return FALSE



4:
 end if



5:
 n ← Nτ(ξ)



6:
 while n = 0 mod 5 do



7:
  n ← n/5



8:
 end while



9:
 if n = 1 mod 5 then



10:
  return IS-PRIME(n)



11:
 else



12:
  return FALSE



13:
 end if



14:
end procedure









Output: TRUE if ξ is an easy and solvable instance of the









problem: find x from   [ω] such that |x|2 = ξ; FALSE



otherwise.

















TABLE 3





Procedure for Solving a Norm Equation

















Input: a + bτ ∈   [τ], assume EASY-SOLVABLE(a + bτ) is









TRUE










1:
procedure SOLVE-NORM-EQUATION(a + bτ)




  Find integer n and prime p such that N(a + bτ) = 5np



2:
 n ← 0



3:
 while (2 − τ)|a + bτ do



4:
  a + bτ ← (a + bτ)/(2 − τ)



5:
  n ← n + 1












6:
 end while
  Nτ(a + bτ) = p










   Solve the norm equation for prime righthand side












7:
 p ← Nτ(a + bτ)
  p is prime











8:
 t ← (TAU-TO-INT(a + bτ) − 2)mod p












9:
 M ← TONELLI-SHANKS(t,p)
  M2 = t mod p











10:
 xr ← BINARY-GCD(a + bτ, M − (ω + ω4))










  (ω + ω4)2 = τ − 2













11:
 u ← (a + bτ)/|xr|2 
  u - unit, u > 0, u• > 0













12:
 (s,m) ← UNIT-DLOG(u)
  s = 1, m − even











13:
 return rm/2 (ω + ω4)n1 xr



14:
end procedure









Output: x from   [ω] such that |x|2 = a + bτ

















TABLE 4





Procedure UNIT-DLOG for Norm Equation Solution

















Input: unit u = a + bτ ∈ U(   [τ])










1:
procedure UNIT-DLOG(u)



2:
 s ← 1, k ← 0



3:
 if a < 0 then



4:
  a ← −a; b ← −b; s ← −s



5:
 end if



6:
 μ ← ab



7:
 while |μ| > 1 do



8:
  if μ > 1 then



9:
   (a, b) ← (b, a − b); k ← k − 1



10:
  else



11:
   (a, b) ← (a, a − b); k ← k + 1



12:
  end if



13:
  μ ← ab












14:
 end while
   |μ| = 1 here











15:
 match v = a + bτ with one of the {±1, ±τ, ±τ2 , ±τ−1}




 adjust s, k accordingly



16:
 return (s, k)



17:
end procedure









Output: (s, k) such that s = −1, 1, k − integer and u = sτk

















TABLE 5





Procedure BINARY-GCD for Norm Equation Solution

















INPUT: a, b ∈   [ω]










1:
procedure BINARY-GCD(a,b)



2:
 if a = 0 then



3:
  return b



4:
 end if



5:
 if b = 0 then



6:
  return a



7:
 end if



8:
 if (1 + ω)|a and (1 + ω)|b then



9:
  return (1 + ω)BINARY-GCD(a/(1 + ω), b/(1 + ω))



10:
 end if












11:
 u ← 1,v ← 1
  u,v - units











12:
 if (1 + ω)   a and (1 + ω)   b then












13:
  u ← INV-MOD5(a)
  ua = 1 mod (1 + ω)




14:
  v ← INV-MOD5(b)
  vb = 1 mod (1 + ω)



15:
 end if



16:
 if N(a) < N(b) then



17:
  c ← a



18:
 else



19:
  c ← b



20:
 end if










21:
 return BINARY-GCD(c, va − vb)












22:
end procedure
  ua − vb = 0 mod (1 + ω)










Output: c = GCD   [ω](a, b)

















TABLE 6





Procedure TAU-TO-INT for Norm Equation Solution

















Input: a + bτ ∈   [τ] , a + bτ − prime










1:
procedure TAU-TO-INT(a + bτ)












2:
 p ← Nτ(a + bτ)
  GCD(p, b) = 1











3:
 (u, v) ← EXTENDED-EUCLIDEAN(b,p)












4:
 return −au mod p
  bu + (v(a − bτ))(a + bτ) = 1




5:
end procedure









Output: m − integer such that m = τ mod (a + bτ)

















TABLE 7





Procedure INV-TO-MOD5 for Norm Equation Solution















Input: a + bτ ∈   [τ] , (1 + ω) does not divide ξ










1:
procedure INV-MOD5(a + bτ)












2:
 t ← TAU-TO-INT(1 + ω)
  N(1 + ω) = 5




3:
 r ← a + bt mod 5
  = 1, ..., 4



4:
 if r = 1 then



5:
  return 1



6:
 else if r = 4 then



7:
  return −1



8:
 else if r = 2 then



9:
  return (1 − ω)−1



10:
 else if r = 3 then



11:
  return −(1 − ω)−1



12:
 end if



13:
end procedure









Output: u - unit in   [ω] such that u(a + bτ) = 1 mod (1 + ω)

















TABLE 8





Procedure TONELLI-SHANKS for Norm Equation Solution

















Input: n, p ∈   , assume p is an odd prime and n is a









quadratic residue mod p.










1:
procedure TONELLI-SHANKS (n,p)



2:
 Represent p − 1 as p − 1 = q2s, q odd.



3:
 if s = 1 then return ±n(p+1)/4 mod p;



4:
 end if



5:
 By randomized trial select a quadratic non-residue z ,




i.e z ∈ {2,...,p − 1} such that z(p−1)/2 = −1 mod p.



6:
 Let c = zq mod p.



7:
 Let r = n(q+1)/2 mod p, t = nq mod p, m = s.



8:
 while t ≠ 1 mod p do



9:
  By repeated squaring find the smallest i ∈




{1,...,m − 1} such that t2i = 1 mod p



10:
  Let b = c2m−i−1 mod p, r ← rb, t ← tb2, c ←




b2, m ← i



11:
 end while



12:
end procedure









Output: {r,p − r}.










FIG. 2 is a block diagram illustrating a norm equation solution method. Referring to FIG. 2, a Norm Equation Solver Procedure 200 includes receiving the right hand side of the norm equation as input ξ at 202. At 204, a determination is made whether the equation with this right hand side is easy/solvable. If the test at 204 produces the NO answer, procedure terminates with No solution at 222. The test is done using the predicate described at 206. At 208, the τ-norm of ξ is computed. At 210 integer n is set as the maximum power of 5 dividing the norm is taken out. At 212 the n-th power of (2−τ) is factored out from the input yielding a smaller quotient a+bτ and p is set to be the norm of a+bτ. At 214, τ−2 is converted into a residue mod p. At 216, a square root of that residue is computed using the Tonelli-Shanks algorithm. At 218, a key solution factor s is computed using a BINARY-GCD algorithm. At 220, a unit u associating the square norm of s with a+bτ is computed and decomposed into an even power of τ. The procedure outputs the two solutions of the norm equation at 224.
The problem of solving an easy instance is reduced to two subproblems. The first is to solve |x|2=2−τ. The second is to solve |x|2=ξ1 where Nτ(ξ1) is prime. If there is a solution x to the equation x·x*=ξ1, then x divides ξ1. Thus a solution to the norm equation needs to be found that is insider the set of possible divisors ξ1. The procedure UNIT-DLOG gives an efficient way to find this representation in Table 4.
Since Nτ(ξ1)=5n+1, there exists an element z of Z(ω) such that xrxr* is equal to ξ1 up to multiplication by a unit in Z(τ). Finding xr is a key step to solving the norm equation. Once completed, |xr|2=uξ1 for some unit u in Z(τ) is obtained. Conditions ξ>0 and ξ● ensure that unit u is a square of some other unit v and therefore |xrv|2=ξ1.
To find xr, an element z of Z(ω) is constructed with the conditions ξ1z and ξ1z*, and ξ1zz*. If the conditions are satisfied, either xr or xr* must divide both ξ1 and z and xr can be found using the procedure BINARY-GCD in Table 5. To ensure that the first group of conditions are satisfied, a z in the form M+ω+ω4 is sought, for M an integer. The second condition can be written as ξ1|M2+(2−τ). The problem of finding an integer M is reduced to a problem of taking a square root modulo p which can be solved using the procedure TONELLI-SHANKS given in Table 8.
Primality of Nτ(ξ1) implies that there exists at such that t=τ mod ξ1 and it can be computed using procedure TAU-TO-INT given in Table 6. Then M is a square root of (2−t)mod p.
The greatest common divisor of two elements of Z(ω) can be found in polynomial time using BINARY-GCD procedure given in Table 5.
IV. Approximate Synthesis
As discussed above, any exact unitary has the form:




  
    U
    ⁡
    
      [
      
        u
        ,
        v
        ,
        k
      
      ]
    
  
  :=
  
    
      (
      
        
          
            u
          
          
            
              
                v
                *
              
              ⁢
              
                τ
              
              ⁢
              
                ω
                k
              
            
          
        
        
          
            
              v
              ⁢
              
                τ
              
            
          
          
            
              
                -
                
                  u
                  *
                
              
              ⁢
              
                ω
                k
              
            
          
        
      
      )
    
    .
  




Such exact unitaries can be associated with products of the F-gates and T-gates, without any approximation (i.e., precision ε=0), using the exact synthesis procedure described above. Given the availability of the exact synthesis algorithm, the task of approximating a target (non-exact) unitary gate with a braiding circuit to a precision ε>0 can be reduced to approximating the matrix of the target gate by a matrix of the form above. Optimizing the depth of such a desired braid pattern circuit is related to minimizing the sizes of integer coefficients occurring in the elements u, v of the approximating matrix.
Any special unitary gate, defined as




  
    G
    =
    
      [
      
        
          
            u
          
          
            v
          
        
        
          
            
              -
              
                v
                *
              
            
          
          
            
              u
              *
            
          
        
      
      ]
    
  
  ,




with u≠0 can be represented exactly as

G=RZ(α)FRZ(β)FRZ(γ),

wherein α, β, γ are real values which can be interpreted as rotation angles and RZ(θ) is a Z-rotation gate defined as





  
    
      R
      Z
    
    ⁡
    
      (
      θ
      )
    
  
  =
  
    
      (
      
        
          
            
              e
              
                
                  -
                  i
                
                ⁢
                
                  
                
                ⁢
                
                  θ
                  /
                  2
                
              
            
          
          
            0
          
        
        
          
            0
          
          
            
              e
              
                i
                ⁢
                
                  
                
                ⁢
                
                  θ
                  /
                  2
                
              
            
          
        
      
      )
    
    .
  




A special unitary gate G of the form





  G
  =
  
    
      [
      
        
          
            0
          
          
            v
          
        
        
          
            
              -
              
                v
                *
              
            
          
          
            0
          
        
      
      ]
    
    ⁢
    
      (
      
        
          i
          .
          e
          .
        
        ,
        
          u
          =
          0
        
      
      )
    
  




cannot be exactly represented in this form.

In order to build an asymptotically optimal approximation of any special unitary gate G by a braid pattern circuit, it suffices to build asymptotically optimal approximations of unitary rotations of the form




  
    [
    
      
        
          u
        
        
          0
        
      
      
        
          0
        
        
          
            u
            *
          
        
      
    
    ]
  
  ⁢
  
    
  
  ⁢
  
    and
    ⁢
    
      
    
    [
    
      
        
          0
        
        
          v
        
      
      
        
          
            -
            
              v
              *
            
          
        
        
          0
        
      
    
    ]
  




by braid pattern circuits.

As follows from the above, approximations of the vectors




  
    
      
        
          [
          
            
              
                w
              
            
            
              
                0
              
            
          
          ]
        
        ,
        
          

        
        ⁢
        
          
            
            w
            
          
          =
          1
        
        ,
        
          

        
        ⁢
        and
      
    
    
      
        (
        a
        )
      
    
  
  
    
      
        
          [
          
            
              
                0
              
            
            
              
                w
              
            
          
          ]
        
        ,
        
          

        
        ⁢
        
          
            
            w
            
          
          =
          1
        
      
    
    
      
        (
        b
        )
      
    
  




can be found, with





  
    [
    
      
        
          u
        
      
      
        
          
            v
            ⁢
            
              τ
            
          
        
      
    
    ]
  
  ,




u, vεR, |u|2+|v|2τ=1, wherein R is the ring R⊂ generated by elements of the form (a+b i√{square root over (2−τ)}), a, bε[τ].

For the case




  
    [
    
      
        
          w
        
      
      
        
          0
        
      
    
    ]
  
  ,




|w|=1, u approximates w, and v can be an arbitrary sufficiently small element of R. For the case





  
    [
    
      
        
          0
        
      
      
        
          w
        
      
    
    ]
  
  ,




|w|=1, v approximates w/√{square root over (τ)}, and u can be an arbitrary sufficiently small element of R. Thus, approximation of special unitary gates G can be based on finding suitable values of w or w/√{square root over (τ)} subject to the normalization condition

|u|2+|v|2τ=1.

For the case





  
    [
    
      
        
          w
        
      
      
        
          0
        
      
    
    ]
  
  ,




|w|=1, values u, v are based on solutions of:

|v|2=(1−|u|2)/τ.  (1)

For the case





  
    [
    
      
        
          0
        
      
      
        
          w
        
      
    
    ]
  
  ,




|w|=1, values u, v are based on solutions of:

|u|2=(1−|v|2τ).  (2)

Equations (1) and (2) differ in the shapes of the right hand sides, but each can be referred to as a norm equation.

In either of the cases above, |u|2≦1 and |v|2τ≦1. However, the complex square norm |.|2 commutes with the Galois automorphism (.)● that is described above with respect to exact synthesis. Thus, as




  
    
      
        (
        τ
        )
      
      •
    
    =
    
      
        -
        
          1
          τ
        
      
      =
      
        -
        
          (
          
            τ
            +
            1
          
          )
        
      
    
  
  ,




equation (1) implies that

|v●|2=−(1−|u●|2)(τ+1).

In order for this implied equation to be solvable for v●, −(1−|u●|2)≧0. So, while |u|2≦1 by design, it is necessary that |u●|2≧1 for equation (1) to have a solution. An approximate candidate uεR can be always be selected to satisfy this necessary condition.

Approximate Synthesis of RZ(φ)
Given methods for obtaining <F, T>-circuits (or equivalently, <σ1, σ2>-circuits) for exact unitaries, methods are provided for approximating unitaries of the form




  
    
      R
      z
    
    ⁡
    
      (
      φ
      )
    
  
  =
  
    (
    
      
        
          
            e
            
              
                -
                i
              
              ⁢
              
                
              
              ⁢
              
                φ
                /
                2
              
            
          
        
        
          0
        
      
      
        
          0
        
        
          
            e
            
              i
              ⁢
              
                
              
              ⁢
              
                φ
                /
                2
              
            
          
        
      
    
    )
  




with <F, T>-circuits (or equivalently, <σ1, σ2>-circuits). A quality of approximation ε can be based on a global phase invariant distance

d(U,V)=√{square root over (1−|tr(UV†)|/2)}

The quality of approximation ε defines the problem size. The disclosed methods produce circuits of length O(log(1/ε)) which saturates an asymptotic worst-case lower bound. The algorithm is probabilistic in its nature and on average requires time in O(logc(1/ε)) to find an approximation.

There are two main stages in these methods: (1) approximating Rz(φ) with an exact unitary U[u, v, 0]. and then using the exact synthesis methods described above to find a circuit implementing U[u, v, 0]. This second stage is completely described above.
The expression for the quality of approximation in this special case simplifies to

d(Rz(φ),U[u,v,0])=√{square root over (1−|Re(ueiφ/2)|)}

The quality of approximation depends only on u that is the top left entry of U[u, v, 0]. Therefore to solve the first part of the problem it is sufficient to find u from Z(φ) such that √{square root over (1−|Re(ueiφ/2)|)}≦εt. However, there is an additional constraint that must be satisfied: there must exist a v from Z(ω) such that U[u, v, 0] is a unitary, in other words the following equation must be solvable:

|v|2=ξ, for ξ=φ(1−|u|2).

This is a type of norm equation discussed above. In general the problem of deciding whether such a v exists and then finding it is hard. It turns out, however, that in generating values there is enough freedom to pick (find) “easy” instances and obtain a solution in polynomial time without sacrificing too much quality.
There is an analogy to this situation: it is well known that factoring a natural number into prime factors is a hard problem. However, checking that a number is prime can be done in polynomial time. In other words, given a natural number N, one can efficiently decide if it is an easy instance for factoring. Now imagine the following game: one is given a uniformly chosen random number from the interval [0, N] and one wins each time they can factor this number. How good is this game? The key here is the Prime Number Theorem. It states that there are Θ(N log(N)) primes in the interval [0, N]. Therefore one can win the game with probability at least Θ(N/log(N)). In other words, the number of trials one needs to make before winning scales as Θ(N/log(N)). In our case the situation is somewhat similar and N is of order 1/ε.
Table 9 summarizes a representative method of approximating Rz(φ) with an <F, T> circuit with O(log(1/ε)) gates and precision at most ε. Runtime is probabilistic polynomial as a function of log(1/ε). The procedures invoked in Table 9 are described above, with the exception of the procedure RANDOM-SAMPLE.







TABLE 9





Procedure for Approximate Synthesis of R(φ)

















Input: φ - defines Rz(φ), ε - precision










1:
C ← {square root over (φ/4)}



2:
m ← ┌logτ(Cε)┐ + 1



3:
Find k such that θ = −φ/2 − πk/5 ∈ [0,π/5]



4:
not-found ← true, u ← 0, v ← 0



5:
while not-found do



6:
 u0 ← RANDOM-SAMPLE(θ,ε,1)



7:
 ξ ← φ(φ2m − |u0|2)



8:
 if EASY-SOLVABLE(ξ) then



9:
  not-found ← false



10:
  u ← ωkτmu0



11:
  v ← τmSOLVE-NORM-EQUATION(ξ)



12:
 end if



13:
end while



14:
C ← EXACT-SYNTHESIZE(U[u,v,0])









Output: Circuit C such that d(C,Rz(φ)) ≦ ε










At a high level, in the approximation procedure of Table 9, a number of trials are attempted. During each trial, a u is randomly picked from Z(ω) that achieves precision ε, and then the norm equation is checked to determine if it is easily solvable. Once such a u is found, v is computed and a unitary U[u, v, 0] is constructed. With this construction complete, the exact synthesis procedure can be used to find a suitable circuit.
Random Sample Procedure
Pseudocode for a random sampling procedure for use with the method of Table 9 is provided in Table 10. Inputs are an angle θ between 0 and π, and a precision ε.







TABLE 10





Procedure RANDOM-SAMPLE(θ, ε)

















Input: θ - angle between 0 and π/5, ε - Precision, r ≧ 1










1:
procedure RANDOM-SAMPLE(θ,ε,r)



2:
 C ←{square root over (φ/(4r))}



3:
 m ← ┌logτ(Cεr)┐ + 1



4:
 N ← ┌φm┐



5:
 ymin ← rφm(sin(θ) − ε({square root over (4 − ε2)}cos(θ) + ε sin(θ)) /2)



6:
 ymax ← rφm(sin(θ) + ε({square root over (4 − ε2)}cos(θ) − ε sin(θ)) /2)



7:
 xmax ← rφm((1 − ε2/2)cos(θ) − ε{square root over (1 − ε2/4)}sin(θ))



8:
 xc ← x max − rε2φm/(4cos(θ))



9:
 Pick random integer j from [1,N − 1]



10:
 y ← ymin + j(ymax − ymin)/N



11:
 ay+ τby ← APPROX-REAL(y/{square root over (2 − τ)},m)



12:
 x ← xc − ((ay+ byτ){square root over (2 − τ)} − ymin)tan(θ)



13:
 ax + τbx ← APPROX-REAL(x,m)



14:
 return ax + τbx + {square root over (τ − 2)}(ay + τby)



15:
end procedure










This procedure identifies a random element of Z(ω) that is in a region 304 shown in FIG. 3. A number of different outputs of this algorithm is in O(1/ε).

A random element u is generated from Z(ω) having a desired precision using the procedure RANDOM-SAMPLE. To achieve a better constant factor in front of log(1/ε) for the length of a circuit, u0=uφm can be randomly chosen instead of u. Then u can be recovered as τ=φ−1 and u=u0τn. As shown in FIG. 3, a circular segment 302 corresponds to u0 such that U[u, v, 0] is within ε of RZ(φ). The element u0 is a complex number and the x-axis corresponds to the real part and the y-axis to the imaginary part. All random samples that are generated belong to the region 304 and have the form ax+bxτ+i√{square root over (2−τ)}(ay+byτ) (note that i√{square root over (2−τ)}=ω+ω4 and belongs to Z(ω)). An imaginary part is randomly selected, and then a real part. To find an imaginary part, a real number y is randomly chosen and then approximated with √{square root over (2−τ)}(ay+byτ) using the APPROX-REAL procedure. Once √{square root over (2−τ)}(aybyτ) is found, an x-coordinate is chosen as shown in FIG. 3, and approximated with ax+bxτ.
The problem of approximating real numbers with numbers of the form a+bz for integers a, b and irrational z is well studied. The main tool is continued fractions. It is also well known that Fibonacci numbers {Fn}:

F0=0,F1=1,Fn=Fn−1+Fn−2,n≧2

are closely related to the continued fraction of the Golden section φ and its inverse τ. The correctness of procedure APPROX-REAL in Table 11 is based on the following well known result connecting τ and Fibonacci numbers. It is stated herein and a proof is provided for completeness.

Proposition. For any integer n




  
    
      
      
        τ
        -
        
          
            F
            n
          
          
            F
            
              n
              +
              1
            
          
        
      
      
    
    ≤
    
      
        
          τ
          n
        
        
          F
          
            n
            +
            1
          
        
      
      ⁢
      n
    
  
  ,




and Fn≧(φn−1)/√{square root over (5)}.

This can be proved as follows. First define the family of functions ƒn such that ƒ1(x)=x and ƒn(x)=1/(1+ƒn−1(x)) for n≧2. It is not difficult to check that ƒn(τ)=τ. It can be shown by induction on n that x ƒn(1)=Fn/Fn+1. Therefore, to prove the first part of this proposition it can be shown that

|ƒn(τ)−ƒn(1)|≦τn/Fn+1 

This can be done by induction. The statement is true for n=1. Using the definition of ƒn it is not difficult to show

|ƒn+1(τ)−ƒn−1(1)|=ƒn+1(τ)ƒn+1(1)|ƒn(τ)−ƒn(1)|.

Using ƒn+1=τ and the inequality for |ƒn(τ)−ƒn(1) | the proof of the first part is completed. To show the second part it is enough to use the well-known closed form expression for Fibonacci numbers Fn=(φn−(−τ)n)/√{square root over (5)}.

Approximation of a Real Procedure
At a high level, in procedure APPROX-REAL τ is approximated with a rational number p/q and an approximation x as rationals of the form a+bp/q is found. To obtain satisfactory resulting precision we need to ensure that b(τ−p/q) is small, therefore b is chosen such that |b|≦q/2.
It can be demonstrated that procedure APPROX-REAL outputs integers a, b such that |x−(a+bτ)|≦τn−1(1−τn), |b|≦φn and terminates in time polynomial in n. First, identity Fn+1Fn−1−Fn2=(−1)n for Fibonacci numbers implies uv+pq=1. Next, by choice of c we have |xq−c|≦1/2, therefore |x−c/q|≦1/2q. By the result above, 1/2q is less than τn√{square root over (5)}(1−τn)/2; it remains to show that c/q is within distance τn/2 from a+bτ and use a triangle inequality. By choice of a, b we have c=aq+bp and

|c/q−(a+bτ)|=|b∥τ−p/q|

Using the Proposition above, equality q=Fn+1, and inequality |b|≦q/2, it can be concluded that |c/q−(a+bτ)|≦τn/2. The complexity of computing nth Fibonacci number is polynomial in n. Assuming that a number of bits used to represent x is proportional to n all arithmetic operations also has complexity polynomial in n.







TABLE 11





Procedure APPROX-REAL(x, n)

















Input: x - real number, n - defines precision as τn−1(1 − τn)










1:
procedure APPROX-REAL(x,n)












2:
 p ← Fn,q ← Fn+1 
  Fn - Fibonacci numbers













3:
 u ← (−1)n+1Fn,v ← (−1)nFn−1
  up + vq = 1




4:
 c ← └xq┐



5:
 a ← cv + p└cu/q┐



6:
 b ← cu − q└cu/q┐



7:
 return a + τb



8:
end procedure









Output: a + bτ s.t. |x − (a + bτ)| ≦ τn−1(1 − τn),|b| ≦ φn










There are two details of the RANDOM-SAMPLE procedure to clarify. First is that the result is indeed inside a parallelogram region 304 on FIG. 3. This is achieved by picking real values x, y far enough from the border of the parallelogram and then choosing the precision parameter m for APPROX-REAL in such a way that ax+bxτ (close to x) and ay+byτ (close to y/√{square root over (2−t)}) stay inside the parallelogram. The second detail is the size of resulting coefficients x ax, bx, ay, by. Coefficient size is closely related to the number of gates in the resulting circuit. Therefore it is important to establish an upper bound on coefficients size. It can be shown that when the third input r≧1, the procedure RANDOM-SAMPLE has the following properties:
(1) there are O(1/ε) different outputs and each occurs with the same probability;
(2) the procedure outputs an element u0 of Z(ω) from the region 304 in FIG. 3; and
(3) Gauss complexity measure of u0 is in O(1/ε).
The disclosed approximation methods can achieve a desired precision and produce circuits of length O(log(1/ε)). On average the methods involve O(logc(1/ε)) steps. This can be shown based on the following conjecture, similar in nature to the Prime Number Theorem: Let π(M) be the number of elements ξ from Z[τ] such that Nτ(ξ) is a prime representable as 5n+1 and less than M, then π(M) is in Θ(M/log(M)). This conjecture defines the frequency of easy instances of the norm equation during the sampling process. Proof of this conjecture is omitted. Finally it can be shown that the approximation methods output <F, T>-circuits C of length O(log(1/ε)) such that d(C, Rz(φ))≦ε. On average the algorithm runtime is in O(logc(1/ε)) if the above conjecture is true.
There are two necessary conditions for predicate EASY-SOLVABLE to be true:

Nτ(ξ) is prime and equals 5n+1 for integer n, and

ξ>0,ξ●>0.

Let pM be the probability that the first condition is true when ξ is chosen uniformly at random and Nτ(ξ) is bounded by M. It can be assumed that pM is in O(log(1/M)). In our case M is of order φ2m and therefore the probability of getting an instance solvable in polynomial time is in O(1/log(1/ε)). Now we show that the second condition is satisfied by construction. Part ξ>0 is trivial because procedure RANDOM-SAMPLE always generates u0 such that |u0|≦φm. For the second part we note that for non-zero u0τn the value of the Gauss complexity measure is

G(u0τn)=|(u0τn)●|2+|(u0τn)|2≧2

Thus, |(u0τn)●|2≧1 which gives

ξ●=τ2m+1(|(u0τn)●|−1)≧0

as required.

In summary, checking that an instance of ξ is easily solvable can be done in time polynomial in O(log(1/ε)) using a Miller-Rabin Primality Test or other tests, the average number of loop iterations is in O(log(1/ε)) and an instance of the norm equation when ξ is prime can be solved in time that is on average is in O(logd(1/ε)) for some positive d. On average, approximate synthesis algorithms can run in time O(logc(1/ε)) for some positive constant c.
A method of approximation of a non-exact unitary Rz(φ)X is shown in Table 12 and can be constructed as follows. First, the expression for the distance d can be expressed as:

d(U[u,v,0],Rz(φ)X)=√{square root over (1−√{square root over (τ)}|Re(ve−i(φ/2+π/2)|)}

which depends only on the bottom left entry of the unitary U[u, v, 0]. Now u and v have opposite roles in comparison to the method of approximating. To get a better constant factor in front of log(1/ε) in the circuit size, v0 is randomly picked such that d(U[u, φmv0, 0], Rz(φ)X)≦ε. Procedure RANDOM-SAMPLE is used to generate random v0. The third input parameter r is set to √{square root over (φ)} to take into account that bottom left entries of exact unitaries are rescaled by a factor √{square root over (τ)}. Once v0 is selected, a check is made that there exists an exact unitary with bottom right entry v=τmv0√{square root over (τ)}, in other words, the norm equation

|u|2=ξ for ξ=1−τ|v|2 

is solved. The necessary condition ξ●≧0 is always satisfied because 1+φ|v●|2 is always positive. Once an “easy” instance of the norm equation is found, it is solved and an exact unitary is constructed.

It can be shown that the approximation procedure of Table 12 outputs an <F, T>-circuit of length O(log(1/ε)) such that d(C, Rz(φ)X)≦ε. On average, runtime of the procedure is O(logc(1/ε)).







TABLE 12





Procedure for Approximate Synthesis of R(φ)X

















Input: φ - defines Rz(φ)X, ε - precision










1:
r ← {square root over (φ)}, C ← {square root over (φ/(4r))}



2:
m ← ┌logτ(Cεr)┐ + 1



3:
Find k such that θ = Φ/2 + π/2 − πk/5 ∈ [0,π/5]



4:
not-found ← true, u ← 0, v ← 0



5:
while not-found do



6:
 u0 ← RANDOM-SAMPLE(θ,ε,r)



7:
 ξ ← φ2m − τ|u0|2



8:
 if EASY-SOLVABLE(ξ) then



9:
  not-found ← false



10:
  v ← ωkτmu0



11:
  u ← τmSOLVE-NORM-EQUATION(ξ)



12:
 end if



13:
end while



14:
C ← EXACT-SYNTHESIZE(U [u,v,0])









Output: Circuit C such that d(C,Rz(φ)X) ≦ ε










V. General Synthesis with F, T
FIG. 4 is a simplified block diagram of a representative method 400. At 402, a target qubit circuit U is input. At 403, the circuit U is evaluated to determine if it is exactly unitary. If exactly unitary, a suitable F, T sequence is obtained as described above at 406. If not exactly unitary, a suitable approximation that is exactly unitary is found at 404, either by a random search and selection process, or analytically. This approximation of the target qubit circuit is then used at 406 so that an F, T sequence corresponding to the approximation is determined. At 408, an F, T sequence is provided that can be implemented using Fibonacci anyons.
The methods disclosed above can be used to specify braid representations of sequences of gates corresponding to Fibonacci anyons. Such sequences thus define quantum logic or quantum computer hardware that are configured to perform quantum logical operations defined by the braid representations. Quantum circuits can be implemented with, for example, fractional quantum Hall effect devices.
VI. Representative Computing Environments
FIG. 5 and the following discussion are intended to provide a brief, general description of an exemplary computing environment in which the disclosed technology may be implemented. Although not required, the disclosed technology is described in the general context of computer executable instructions, such as program modules, being executed by a personal computer (PC). Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Moreover, the disclosed technology may be implemented with other computer system configurations, including hand held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframe computers, and the like. The disclosed technology may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.
With reference to FIG. 5, an exemplary system for implementing the disclosed technology includes a general purpose computing device in the form of an exemplary conventional PC 500, including one or more processing units 502, a system memory 504, and a system bus 506 that couples various system components including the system memory 504 to the one or more processing units 502. The system bus 506 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. The exemplary system memory 504 includes read only memory (ROM) 608 and random access memory (RAM) 510. A basic input/output system (BIOS) 512, containing the basic routines that help with the transfer of information between elements within the PC 500, is stored in ROM 508. As shown in FIG. 5, RAM 510 can store F, T sequence syntheses of qubit circuits as well as computer-executable instructions for receiving, processing, and output of quantum circuits.
The exemplary PC 500 further includes one or more storage devices 530 such as a hard disk drive for reading from and writing to a hard disk, a magnetic disk drive for reading from or writing to a removable magnetic disk, and an optical disk drive for reading from or writing to a removable optical disk (such as a CD-ROM or other optical media). Such storage devices can be connected to the system bus 506 by a hard disk drive interface, a magnetic disk drive interface, and an optical drive interface, respectively. The drives and their associated computer readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, and other data for the PC 500. Other types of computer-readable media which can store data that is accessible by a PC, such as magnetic cassettes, flash memory cards, digital video disks, CDs, DVDs, RAMs, ROMs, and the like, may also be used in the exemplary operating environment.
A number of program modules may be stored in the storage devices 530 including an operating system, one or more application programs, other program modules, and program data. Storage of quantum syntheses and instructions for obtaining such syntheses can be stored in the storage devices 530. A user may enter commands and information into the PC 500 through one or more input devices 540 such as a keyboard and a pointing device such as a mouse. Other input devices may include a digital camera, microphone, joystick, game pad, satellite dish, scanner, or the like. These and other input devices are often connected to the one or more processing units 502 through a serial port interface that is coupled to the system bus 506, but may be connected by other interfaces such as a parallel port, game port, or universal serial bus (USB). A monitor 546 or other type of display device is also connected to the system bus 506 via an interface, such as a video adapter. Other peripheral output devices, such as speakers and printers (not shown), may be included. In some cases, a user interface is display so that a user can input a circuit for synthesis, and verify successful synthesis.
The PC 500 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 560. In some examples, one or more network or communication connections 550 are included. The remote computer 560 may be another PC, a server, a router, a network PC, or a peer device or other common network node, and typically includes many or all of the elements described above relative to the PC 1500, although only a memory storage device 562 has been illustrated in FIG. 5. The personal computer 500 and/or the remote computer 560 can be connected to a logical a local area network (LAN) and a wide area network (WAN). Such networking environments are commonplace in offices, enterprise wide computer networks, intranets, and the Internet.
When used in a LAN networking environment, the PC 500 is connected to the LAN through a network interface. When used in a WAN networking environment, the PC 500 typically includes a modem or other means for establishing communications over the WAN, such as the Internet. In a networked environment, program modules depicted relative to the personal computer 500, or portions thereof, may be stored in the remote memory storage device or other locations on the LAN or WAN. The network connections shown are exemplary, and other means of establishing a communications link between the computers may be used.
With reference to FIG. 6, an exemplary system for implementing the disclosed technology includes computing environment 600, where compilation into braid pattern circuits is separated from the quantum processing that consumes the compiled circuits. The environment includes a quantum processing unit 602 and one or more monitoring/measuring device(s) 646. The quantum processor executes quantum circuits that are precompiled by classical compiler unit 620 utilizing one or more classical processor(s) 610. The precompiled quantum circuits are downloaded into the quantum processing unit via quantum bus 606.
With reference to FIG. 6, the compilation is the process of translation of a high-level description of a quantum algorithm into a sequence of quantum circuits. Such high-level description may be stored, as the case may be, on one or more external computer(s) 660 outside the computing environment 600 utilizing one or more memory and/or storage device(s) 662, then downloaded as necessary into the computing environment 600 via one or more communication connection(s) 650.
VII. Circuit Synthesis and Construction
Referring to FIG. 7, at 702 a requested circuit U is received. An F, T decomposition is found at 704. As discussed above, for circuits that are exact unitary circuits, the decomposition is obtained without approximation using F-gates and T-gates. For other circuits, an approximation of U that is an exact unitary circuit is determined, which is then decomposed into F-gates and T-gates. At 706, the F, T decomposition is stored. At 708, the stored decomposition is retrieved and a circuit 710 is constructed. As shown in FIG. 7, the circuit 710 includes a sequence of F-gates and T-gates. Representative gate sequences 716, 718 are based on design iterations in which circuit complexity has not been sufficiently reduced; gate sequence 714 is obtained in the design process upon reduction of circuit complexity to a predetermined value.
Having described and illustrated the principles of our invention with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in arrangement and detail without departing from such principles. For instance, elements of the illustrated embodiment shown in software may be implemented in hardware and vice-versa. Also, the technologies from any example can be combined with the technologies described in any one or more of the other examples. We therefore claim as our invention all subject matter that comes within the scope and spirit of these claims. Alternatives specifically addressed in these sections are merely exemplary and do not constitute all possible alternatives to the embodiments described herein.

## Claims

1. A computer-implemented method, comprising:
determining that a single qubit unitary gate is representable exactly as a braid pattern of elementary gates <F, T> wherein





  
    T
    =
    
      (
      
        
          
            1
          
          
            0
          
        
        
          
            0
          
          
            ω
          
        
      
      )
    
  
  ,
  
    F
    =
    
      (
      
        
          
            τ
          
          
            
              τ
            
          
        
        
          
            
              τ
            
          
          
            
              -
              τ
            
          
        
      
      )
    
  
  ,
  
    ω
    =
    
      e
      
        i
        ⁢
        
          
        
        ⁢
        
          π
          /
          5
        
      
    
  
  ,
  
    
      
        and
        ⁢
        
          
        
        ⁢
        τ
      
      =
      
        
          (
          
            
              5
            
            -
            1
          
          )
        
        2
      
    
    ;
  



based on the determining, synthesizing a sequence of elementary gates to exactly represent the single qubit unitary gate; and
configuring a quantum circuit to include the synthesized sequence of elementary gates.

2. The computer-implemented method of claim 1, wherein the elementary gates F and T are used to encode a braid pattern.

3. The computer-implemented method of claim 1, wherein representation of a braid pattern in terms of the F and T gates is an alternative to representation of a braid pattern in terms of the σ1, σ2 gates, wherein




  
    σ
    1
  
  =
  
    (
    
      
        
          
            ω
            
              -
              4
            
          
        
        
          0
        
      
      
        
          0
        
        
          
            ω
            3
          
        
      
    
    )
  




and σ2=F σ1F.

4. The computer-implemented method of claim 1, wherein the sequence of elementary gates includes gates encoding a braid pattern may start with an optional ωmTjfactor and consists of zero or more FTk factors, wherein k is a non-negative integer less than or equal to nine.

5. The computer-implemented method of claim 1, wherein the synthesizing the sequence of elementary gates to exactly represent the single qubit unitary gate comprises iteratively establishing a reduced matrix Ur associated with the single qubit unitary as a product Ur=FTJUr−1, wherein J is an integer and Ur−1 is a prior reduced matrix reduction of a complexity measure.

6. The computer-implemented method of claim 1, wherein the synthesizing the sequence of elementary gates to exactly represent the single qubit unitary gate comprises iterative reduction of a complexity measure, wherein the complexity measure is a Gauss complexity G(u)=|u|2+|u●|2, wherein u is a matrix element associated with the single qubit unitary gate and u● is a Galois automorphism of u such that u●=u3.

7. The computer-implemented method of claim 6, further comprising reducing the single qubit unitary gate by applying gates of the form ωkTjto the sequence until a residual Gauss complexity is less than or equal to two.

8. The computer-implemented method of claim 1, further comprising determining that the single qubit unitary gate is not exactly representable as a braid pattern and obtaining an approximation of the single qubit unitary gate by a gate that is exactly representable as a braid pattern, wherein the approximation is determined based on a requested precision.

9. The computer-implemented method of claim 8, further comprising a sequence of elementary gates so as to represent the approximation of the single qubit unitary gate.

10. The computer-implemented method of claim 1, further comprising ensuring the asymptotic optimality of the length of the resulting sequence of elementary gates.

11. The computer-implemented method of claim 1, further comprising determining that the single qubit unitary gate is representable exactly as a braid pattern by establishing that the single qubit unitary is representable as




  
    (
    
      
        
          u
        
        
          
            
              v
              *
            
            ⁢
            
              τ
            
            ⁢
            
              ω
              k
            
          
        
      
      
        
          
            v
            ⁢
            
              τ
            
          
        
        
          
            
              -
              
                u
                *
              
            
            ⁢
            
              ω
              k
            
          
        
      
    
    )
  
  ,




wherein k is an integer, u, v are elements of a ring of integers extended by a primitive fifth root of unity ω, and |u2|+τ|v2|=1.

12. A compiler system for a quantum computer, comprising;
an input configured to receive a single qubit gate and a desired approximation precision; and
a processor configured to identify a sequence of gates corresponding to the single qubit gate based on a determination of whether the single qubit gate is representable exactly by a braid pattern circuit of F-gates and T-gates and configuring a quantum circuit to include the sequence of gates, wherein





  
    T
    =
    
      (
      
        
          
            1
          
          
            0
          
        
        
          
            0
          
          
            ω
          
        
      
      )
    
  
  ,
  
    F
    =
    
      (
      
        
          
            τ
          
          
            
              τ
            
          
        
        
          
            
              τ
            
          
          
            
              -
              τ
            
          
        
      
      )
    
  
  ,
  
    ω
    =
    
      e
      
        i
        ⁢
        
          
        
        ⁢
        
          π
          /
          5
        
      
    
  
  ,
  
    
      and
      ⁢
      
        
      
      ⁢
      τ
    
    =
    
      
        
          (
          
            
              5
            
            -
            1
          
          )
        
        2
      
      .

13. The compiler system of claim 12, wherein if the single qubit gate is representable exactly by a braid pattern circuit, the processor is configured to identify the sequence of gates by recursively adding one or more F-gates and T-gates to the sequence of gates.

14. The compiler system of claim 13, wherein the processor is configured to include gate sequences corresponding to FT10−j, wherein J is a positive integer that is less than or equal to ten.

15. The compiler system of claim 14, wherein the processor is configured to recursively reduce a unitary gate by a gate of the form FT10−j until a Gauss complexity G(u)=|u|2+|u●|2 of a residual circuit is less than or equal to two, wherein u● is a Galois automorphism of u such that u●=u3.

16. The compiler system of claim 15, wherein the processor is configured to include a gate sequence ωkTj if a Gauss complexity of the reduced circuit is less than or equal to two, wherein k and j are integers.

17. The compiler system of claim 12, wherein if the single qubit circuit is not exactly unitary, the processor is configured to identify an exactly representable unitary circuit that corresponds to the single qubit gate within a predetermined precision.

18. The compiler system of claim 17, further comprising identifying a sequence of one more F gates and T gates that correspond to the exactly representable unitary circuit that approximates the single qubit gate.

19. The compiler system of claim 17, wherein the processor is configured to identify the exactly representable unity circuit that approximates the single qubit gate based on a random search of unitary gates.

20. The complier system of claim 12, wherein the processor is configured to produce the sequence of gates as ωk(m+1)Tk(m)FTk(m−1)FTk(m−2). . . FTk(0), wherein k(j) are integers and 0≦k(j)≦9, wherein the compiler is configured to ensure the asymptotic optimality of the length of the resulting sequence of gates ωk(m+1)Tk(m)FTk(m−1)FTk(m−2). . . FTk(0).

21. A computer storage device, comprising computer-executable instructions for implementing a method of determining a sequence of gates corresponding to a quantum circuit definition, the method comprising:
determining if the defined quantum circuit definition corresponds to an exact unitary and if so, assigning a sequence of F-gates and T-gates that represent the exactly unitary quantum circuit definition, wherein





  
    T
    =
    
      (
      
        
          
            1
          
          
            0
          
        
        
          
            0
          
          
            ω
          
        
      
      )
    
  
  ,
  
    F
    =
    
      (
      
        
          
            τ
          
          
            
              τ
            
          
        
        
          
            
              τ
            
          
          
            
              -
              τ
            
          
        
      
      )
    
  
  ,
  
    ω
    =
    
      e
      
        i
        ⁢
        
          
        
        ⁢
        
          π
          /
          5
        
      
    
  
  ,
  
    
      
        and
        ⁢
        
          
        
        ⁢
        τ
      
      =
      
        
          (
          
            
              5
            
            -
            1
          
          )
        
        2
      
    
    ;
  



determining if the defined quantum circuit definition does not corresponds to an exact unitary and if so, obtaining an exact unitary quantum circuit definition that approximates the defined quantum circuit, and assigning a sequence of F gates and T gates that represent the exact unitary quantum circuit definition that approximates the defined gate; and
configuring a quantum circuit to include the assigned sequence of F gates and T gates.