# Patent

## Title
Reference current source

## Abstract

Systems, methods, and apparatus for generating a reference current. A reference current source can include a current generator circuit; a first resistance circuit that has a positive temperature dependence; and a second resistance circuit that has a negative temperature dependence. The first resistance circuit and the second resistance circuit can be connected in parallel to the current generator circuit.

## Background
BACKGROUND
Integrated circuit (IC) reference current sources are often realized using either an external resistor, or an on chip resistor. However, process tolerance limits of these resistors (i.e., the amount of variation from the nominal value of the resistors) negatively impact the stability of the reference current source. Operating temperature variations can further negatively impact the stability of reference current sources that are realized using an external or on chip resistor.
SUMMARY
This specification relates to IC reference current sources. In general, one innovative aspect of the subject matter described in this specification can be embodied in devices that include a current generator circuit; and a resistance circuit connected to the current generator, wherein the resistance circuit comprises a current controlled resistance circuit. Other embodiments of this aspect include corresponding systems and apparatus.
These and other embodiments can each optionally include one or more of the following features. The resistance circuit can include a voltage controlled resistance circuit that is connected in parallel with the current controlled resistance circuit.
The voltage controlled resistance circuit can include a plurality of MOSFETs. The plurality of MOSFETs can include a first MOSFET having a drain connected to an emitter of a bipolar transistor of the current generator, and having a source connected to ground; a second MOSFET having a drain connected to a voltage source of the current generator and a gate connected to a first current control voltage source; and a third MOSFET having a source connected to ground and a gate connected to a second current control voltage source. A drain of the third MOSFET can be connected to each of a drain of the second MOSFET and a gate of the first MOSFET.
The current controlled resistance circuit can include a plurality of MOSFETs. The plurality of MOSFETs can include a fourth MOSFET having a drain connected to each of the drain of the first MOSFET and the emitter of the bipolar transistor, and having a source connected to the ground; a fifth MOSFET having a source connected to the voltage source of the current generator and a gate connected to the current generator; and a sixth MOSFET having a source connected to ground and a gate connected to each of a gate of the fourth MOSFET, a drain of the fifth MOSFET, and a drain of the sixth MOSFET.
The current controlled resistance circuit can have a positive temperature dependency. The voltage controlled resistance circuit can have a negative temperature dependency. The current controlled resistance circuit and the voltage controlled resistance circuit can be respectively configured so that a combination of the positive temperature dependency and the negative temperature dependency configure the reference current source to be temperature independent. The current controlled resistance circuit and the voltage controlled resistance circuit can be respectively configured so that a combination of the positive temperature dependency and the negative temperature dependency configure the reference current source to have a positive temperature dependence. The current controlled resistance circuit and the voltage controlled resistance circuit can be respectively configured so that a combination of the positive temperature dependency and the negative temperature dependency configure the reference current source to have a negative temperature dependence. The current generator circuit can include a PTAT current generator circuit.
Another innovative aspect of the subject matter described in this specification can be embodied in devices that include a current generator circuit; a first resistance circuit that has a positive temperature dependence; and a second resistance circuit that has a negative temperature dependence, wherein the first resistance circuit and the second resistance circuit are connected in parallel to the current generator circuit. Other embodiments of this aspect include corresponding systems and apparatus.
These and other embodiments can each optionally include one or more of the following features. The first resistance circuit can be a current controlled resistance circuit. The second resistance circuit can be a voltage controlled resistance circuit. An L2/L1 ratio and a p value for MOSFETs of the reference current source can be selected to provide a zero current slope at a given temperature.
Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. Implementations of the reference current sources described in this document can provide less than +/−10% variation from the nominal value despite normal process variations. Implementations of the reference current sources described in this document provide a temperature independent reference current. Reference current sources described in this document can be implemented to have a chosen temperature dependence (e.g., a positive or negative dependence on temperature). The reference current sources described in this document provide a stable current output over process variations using either PMOS or NMOS devices regardless of the availability of isolated wells.
The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of an example prior art reference current source.
FIG. 2 is a schematic of another example reference current source.
FIG. 3 is a schematic of another example reference current source.
FIG. 4A is a graph showing the slopes of I3 for different L2/L1 ratios.
FIG. 4B is a graph showing I3(T) variations over a range of operating temperatures.



Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
The subject matter described below relates to realizing IC reference current sources. The reference current sources described below can provide currents vary less with standard process parameter variation than those realized using on-chip resistors. In particular, the reference current sources described below use a resistance circuit that depends on the most stable parameters in a standard MOS process (e.g., μn and Cox). As discussed below, the reference current sources can be designed to have a specified temperature dependence (e.g., a positive or negative temperature dependence) or to be relatively independent of temperature. These reference current sources provide a stable current source for setting bias currents and/or tuning circuit parameters.
It is often desirable to have a stable voltage, current, and/or resistive reference in an integrated circuit for setting bias currents or for tuning of circuit parameters. Available circuits for reference current generation typically either have poor tolerances (e.g., greater than +/−30%) or require post-fabrication trimming and/or fusing. Also, the typical resistors available in a MOS process have similar tolerance issues. As such, reference current sources realized using available circuits or resistors generally don't provide a sufficiently stable reference current source for purposes of setting bias currents and/or tuning circuit parameters.
A reference current source that depends upon the most stable parameters in a standard MOS process, μn and Cox, can provide a reference current that is sufficiently stable for purposes of setting bias currents and/or tuning circuit parameters. In some implementations, these reference current sources include a current controlled resistance circuit. Generally, this current controlled resistance circuit has a positive temperature coefficient. However, the current controlled resistance circuit can be combined with a voltage controlled resistance circuit having a negative temperature coefficient to create a tunable reference current source (i.e., a reference current source that can be tuned to be independent of temperature, or have a positive or negative temperature dependence).
FIG. 1 is a schematic of an example prior art reference current source 100. The reference current source 100 is a proportional to absolute temperature (PTAT) current source. The reference current source 100 includes a current generator circuit 102 and a resistor R1. The current generator circuit 102 includes the following components: MOSFETS M1 and M2, and bipolar transistors Q1 and Q2, which are interconnected between a source voltage V0 and ground G as shown in FIG. 1.
The reference current source 100 generates a current as provided by relationship (1).




  
    
      
        
          I
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            I
            ⁢
            
              
            
            ⁢
            2
          
          =
          
            
              
                k
                *
                T
              
              
                q
                *
                R
                ⁢
                
                  
                
                ⁢
                1
              
            
            *
            
              ln
              ⁡
              
                (
                N
                )
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




where,

    
    
        k is Boltzmann's constant;
        T is the temperature (in Kelvin);
        q is the magnitude of the electrical charge on an electron;
        R1 is the resistive value of R1; and
        N is the size ratio of Q1 to Q2.
    
    


As shown in relationship (1), the current provided by the reference current source 100 depends on the temperature T and the value of R1. Therefore, variations to either (or both) of the temperature or the value of R1 will cause variations in the current provided by the reference current source 100. As such, the process related variance of resistors can lead to large variations in the current provided by the reference current source 100.
FIG. 2 is a schematic of another example reference current source 200. The reference current source 200 is similar to the current source 100, but includes a resistance circuit instead of the resistor R1. In particular, the reference current source 200 includes a current controlled resistance circuit 202 instead of the resistor R1 that was used in the reference current source 100.
The current controlled resistance circuit 202 includes three MOSFETs M3, M4, and M5, which are interconnected as shown in FIG. 2. More specifically, in the current controlled resistance circuit 202, M5 has its source connected to ground, and its drain connected to the emitter of Q1. The gate of M5 is connected to each of the gate of M4, the drain of M4, and the drain of M3. M4 has its source connected to ground, its gate connected to each of the gate of M5, the drain of M3, and the source of M4. M3 has its source connected to a voltage source of the current generator circuit 102, while its drain is connected to the drain of M4, the gate of M5, and the gate of M4. Meanwhile the gate of M3 is connected to the drain of M1, the collector of Q1, and the gates of M1 and M2.
The resistance provided by the current controlled resistance circuit 202 is provided by relationship (2).




  
    
      
        
          RM
          ⁢
          
            
          
          ⁢
          5
        
        =
        
          1
          
            
              2
              *
              I
              ⁢
              
                
              
              ⁢
              1
              *
              β
              ⁢
              
                
              
              ⁢
              f
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




where,

    
    
        RM5 is the drain to source resistance of M5 in the current controlled current source 200; and
    
    






  
    β
    ⁢
    
      
    
    ⁢
    f
  
  =
  
    μ
    *
    Cox
    ⁢
    
      
    
    ⁢
    
      W
      L
    
  




    
    
         where,
        
            μ is the mobility of silicon;
            Cox is the Capacitance per unit area of the gate-oxide of M5;
            W is the width of the gate of M5; and
            L is the length of the gate of M5.
        
        
    
    


The resistance RM5 shown above can be inserted into relationship (1) in place of R1 to arrive at relationship (3), which provides the current generated by the reference current source 200.




  
    
      
        
          I
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            
              k
              *
              T
            
            q
          
          ⁢
          
            
              2
              *
              I
              ⁢
              
                
              
              ⁢
              1
              *
              β
              ⁢
              
                
              
              ⁢
              f
            
          
          *
          
            
          
          ⁢
          
            ln
            ⁡
            
              (
              N
              )
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




Solving for I1 arrives at relationship (4).




  
    
      
        
          I
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            
              (
              
                
                  
                    k
                    *
                    T
                  
                  q
                
                *
                
                  ln
                  ⁡
                  
                    (
                    N
                    )
                  
                
              
              )
            
            2
          
          *
          2
          *
          β
          ⁢
          
            
          
          ⁢
          f
        
      
    
    
      
        (
        4
        )
      
    
  




According to relationship (4), the current provided by the reference current source 200 depends only on βf when the temperature is constant. βf is generally the best controlled process parameter for MOSFETs. As such, at a constant temperature, the current provided by the reference current source 200 will operate within the process variation of βf (i.e., μCoxW/L). In some processes, the current variation of the reference current source 200 will be within 10% of the nominal current output.
As shown by relationship (4), the current provided by the reference current source 200 is still dependent on the temperature T. As such, the current provided by the reference current source 200 will vary as the operating temperature changes. βf also varies with temperature because μ varies with temperature, as provided by relationship (5).




  
    
      
        
          μ
          ⁡
          
            (
            T
            )
          
        
        =
        
          
            
              μ
              0
            
            ⁡
            
              (
              
                
                  T
                  0
                
                T
              
              )
            
          
          p
        
      
    
    
      
        (
        5
        )
      
    
  




where,

    
    
        μ(T) is the value of μ at temperature T;
        μ0 is the mobility at reference temperature T0;
        T is the temperature in Kelvin; and
        p is process dependent parameter, which is provided by the MOSFET manufacturer, and can be between 1.3 and 2.0.
    
    


The temperature dependence of the reference current source 200 can be determined by inserting the temperature dependence of βf into relationship (3), as shown by relationship (6).




  
    
      
        
          I
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            
              (
              
                
                  
                    k
                    *
                    T
                  
                  q
                
                *
                
                  ln
                  ⁡
                  
                    (
                    N
                    )
                  
                
              
              )
            
            2
          
          *
          2
          *
          β
          ⁢
          
            
          
          ⁢
          
            f
            0
          
          *
          
            
              (
              
                
                  T
                  0
                
                T
              
              )
            
            p
          
        
      
    
    
      
        (
        6
        )
      
    
  




Relationship (6) reduces to arrive at relationship (7).




  
    
      
        
          I
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            
              (
              
                
                  
                    k
                    *
                    
                      T
                      0
                      
                        p
                        2
                      
                    
                  
                  q
                
                *
                
                  ln
                  ⁡
                  
                    (
                    N
                    )
                  
                
              
              )
            
            2
          
          *
          2
          *
          β
          ⁢
          
            
          
          ⁢
          
            f
            0
          
          *
          
            T
            
              2
              -
              P
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




As provided by relationship (7), the temperature dependence of the reference current source 200 depends on the process dependent parameter p, which will vary among different types of MOSFETs and processes. However, for purposes of example, assume that the value of p=1.8, which is in the typical range of p values. In this example, the temperature dependence of the reference current source 200 is T0.2 (i.e., T(2-1.8)), which is a weak positive dependence on temperature.
FIG. 3 is a schematic of another example reference current source 300. The reference current source 300 is similar to the reference current source 200, but includes a voltage controlled resistor circuit 302 in parallel with the current controlled resistor 202.
The voltage controlled resistor circuit 302 includes three MOSFETs M6, M7, and M8, which are interconnected as shown in FIG. 3. More specifically, M8 has its drain connected to the emitter of Q1 and the drain of M5, while M8's source is connected to ground G. M6 has its drain connected to the voltage source V2 for the current generator circuit, and has its gate connected to a first current control voltage source VA. The source of M6 is connected to the drain of M7, and both are connected to the gate of M8. M7 has its source connected to ground G, while its gate is connected to a second current voltage source VB.
The equivalent resistance of the voltage controlled resistor circuit 302 is provided by relationship (7).




  
    
      
        
          RM
          ⁢
          
            
          
          ⁢
          8
        
        =
        
          1
          
            β
            ⁢
            
              
            
            ⁢
            f
            *
            
              N
              
                8
                :
                6
              
            
            *
            
              (
              
                
                  V
                  A
                
                -
                
                  
                    
                      N
                      
                        7
                        :
                        6
                      
                    
                  
                  *
                  
                    V
                    B
                  
                
              
              )
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




where,

    
    
        RM8 is the drain to source resistance of M8 in the voltage controlled resistor circuit 302;
        N7:6 is the (W/L) ratio of M7 to M6 (i.e., W/LM7/W/LM6);
        N8:6 is the (W/L) ratio of M8 to M6; and
        VA and VB are set to keep M6 and M7 in saturation, while keeping M8 in triode.
    
    


In the reference current circuit 300, the drain to source resistance of M5 can be expressed as shown in relationship (8).




  
    
      
        
          RM
          ⁢
          
            
          
          ⁢
          5
        
        =
        
          1
          
            
              N
              
                5
                :
                4
              
            
            ⁢
            
              
                2
                *
                β
                ⁢
                
                  
                
                ⁢
                f
                *
                
                  I
                  3
                
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




where,
N5:4 is the (W/L) ratio of M5 to M4.
Therefore, the equivalent resistance of M5 and M8, which are connected in parallel, is provided by relationship (9).




  
    
      
        
          1
          
            R
            EQ
          
        
        =
        
          
            
              1
              
                RM
                ⁢
                
                  
                
                ⁢
                5
              
            
            +
            
              1
              
                RM
                ⁢
                
                  
                
                ⁢
                8
              
            
          
          =
          
            
              
                N
                
                  5
                  :
                  4
                
              
              *
              
                
                  2
                  *
                  β
                  ⁢
                  
                    
                  
                  ⁢
                  f
                  *
                  
                    I
                    3
                  
                
              
            
            +
            
              
                N
                
                  6
                  :
                  4
                
              
              *
              
                N
                
                  8
                  :
                  6
                
              
              *
              β
              ⁢
              
                
              
              ⁢
              f
              *
              
                (
                
                  
                    V
                    A
                  
                  -
                  
                    
                      
                        N
                        
                          7
                          :
                          6
                        
                      
                    
                    *
                    
                      V
                      B
                    
                  
                
                )
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




where,

    
    
        N5:4 is the (W/L) ratio of M5 to M4 (i.e., W/LM5/W/LM4);
        N6:4 is the (W/L) ratio of M6 to M4;
        N7:6 is the (W/L) ratio of M7 to M6;
        N8:6 is the (W/L) ratio of M8 to M6;
        βf is μ*Cox; and
        VA and VB are set to keep M6 and M7 in saturation, while keeping M8 in triode.
    
    


Relationship (9) can be used to solve for I3, as shown in relationship (10).




  
    
      
        
          I
          3
        
        =
        
          
            N
            
              3
              :
              1
            
          
          *
          
            
              k
              *
              T
              *
              
                ln
                ⁡
                
                  (
                  N
                  )
                
              
            
            
              q
              *
              
                R
                EQ
              
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




Replacing REQ based on relationship (9), rearranging terms, and defining constants L1 and L2 provides relationship (11).




  
    
      
        
          
            I
            3
          
          =
          
            Bf
            ⁢
            
              
            
            ⁢
            
              
                
                  (
                  
                    
                      N
                      
                        3
                        :
                        1
                      
                    
                    ⁢
                    
                      kT
                      q
                    
                    ⁢
                    
                      ln
                      ⁡
                      
                        (
                        N
                        )
                      
                    
                  
                  )
                
                2
              
              2
            
            *
            
              [
              
                
              
              ⁢
              
                
                  L
                  1
                  2
                
                +
                
                  
                    2
                    ⁢
                    
                      L
                      2
                    
                  
                  
                    
                      N
                      
                        3
                        :
                        1
                      
                    
                    ⁢
                    
                      kT
                      q
                    
                    ⁢
                    
                      ln
                      ⁡
                      
                        (
                        N
                        )
                      
                    
                  
                
                +
                
                  
                    
                      L
                      1
                      4
                    
                    +
                    
                      
                        4
                        ⁢
                        
                          L
                          2
                        
                        ⁢
                        
                          L
                          1
                          2
                        
                      
                      
                        
                          N
                          
                            3
                            :
                            1
                          
                        
                        ⁢
                        
                          kT
                          q
                        
                        ⁢
                        
                          ln
                          ⁡
                          
                            (
                            N
                            )
                          
                        
                      
                    
                  
                
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          where
          ,
          
            

          
          ⁢
          
            
              
                L
                1
              
              =
              
                
                  2
                  ⁢
                  
                    
                      (
                      
                        N
                        
                          5
                          :
                          4
                        
                      
                      )
                    
                    2
                  
                
              
            
            ;
            
              
                and
                ⁢
                
                  

                
                ⁢
                L
                ⁢
                
                  
                
                ⁢
                2
              
              =
              
                
                  N
                  
                    6
                    :
                    4
                  
                
                ⁢
                
                  
                    
                      N
                      
                        8
                        :
                        6
                      
                    
                    ⁡
                    
                      (
                      
                        
                          V
                          A
                        
                        -
                        
                          
                            
                              N
                              
                                8
                                :
                                6
                              
                            
                          
                          ⁢
                          
                            V
                            B
                          
                        
                      
                      )
                    
                  
                  .
                
              
            
          
        
      
    
    
      
        (
        11
        )
      
    
  




Adding the temperature dependence of βf to relationship (11) provides relationship (12) below.




  
    
      I
      3
    
    ⁡
    
      (
      T
      )
    
  
  =
  
    β
    ⁢
    
      
    
    ⁢
    
      
        f
        0
      
      (
      
        
          kT
          0
          
            p
            2
          
        
        q
      
      )
    
    ⁢
    
      
        
          (
          
            
              N
              
                3
                :
                1
              
            
            ⁢
            
              ln
              ⁡
              
                (
                N
                )
              
            
          
          )
        
        2
      
      2
    
    *
    
      [
      
        
      
      ⁢
      
        
          
            L
            1
            2
          
          ⁢
          
            T
            
              2
              -
              p
            
          
        
        +
        
          
            2
            ⁢
            
              L
              2
            
            ⁢
            
              T
              
                1
                -
                p
              
            
          
          
            
              N
              
                3
                :
                1
              
            
            ⁢
            
              kT
              q
            
            ⁢
            
              ln
              ⁡
              
                (
                N
                )
              
            
          
        
        +
        
          
            T
            
              2
              -
              p
            
          
          ⁢
          
            
              
                L
                1
                4
              
              +
              
                
                  4
                  ⁢
                  
                    L
                    2
                  
                  ⁢
                  
                    L
                    1
                    2
                  
                
                
                  
                    N
                    
                      3
                      :
                      1
                    
                  
                  ⁢
                  
                    kT
                    q
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      N
                      )
                    
                  
                
              
            
          
        
      
      ]
    
  




Relationship (12) includes temperature dependent terms proportional to T(2-p) and T(1-p). Therefore, when p is between 1 and 2, the temperature dependence of the reference current source 300 can be tuned by changing the ratio of L2 to L1. For example, various ratios of L2/L1 can be evaluated at a given temperature (e.g., T=300K) to identify one or more ratios that make the slope of I3(T) equal to zero. FIG. 4A is a graph 400 showing, for various values of p, the slopes of I3 resulting from various ratios of L2/L1. For example, when the p value is 1.8, the slope of I3(T) is equal to zero when the L2/L1 ratio is near 0.054. Similarly, when the p value is 1.4, the slope of I3(T) is equal to zero when the L2/L1 ratio is near 0.5. Note that FIG. 4A was created based on the following conditions: T=T0=300° K, L1=7.071, N=8, N3:1=1, βf0=180e-6, k=1.38e-23, and q=1.6e-19.
Based on a graph similar to that presented in FIG. 4A, an L2/L1 ratio can be chosen to achieve a desired temperature dependency (or independency) for the reference current source 300. For example, by choosing an L2/L1 ratio that results in an I3(T) slope that is near zero, the reference current source 300 will be tuned to have a current output that is temperature independent Similarly, the reference current source 300 can be tuned to have a positive temperature dependency by selecting an L2/L1 ratio that results in a positive I3(T) slope, and the reference current source 300 can be tuned to have a negative temperature dependency by selecting an L2/L1 ratio that results in a negative I3(T) slope.
Although there are combinations of L2/L1 ratios and p values that provide a zero slope for I3(T) at a given temperature, there may still be some residual temperature variation that occurs over a wide range of temperatures. However, this residual temperature variation is significantly less than that of various current sources realized by other means.
FIG. 4B is a graph 450 showing I3(T) variations over a range of operating temperatures. For example, the curve 452 shows the I3(T) variations over the temperature range of −40 degrees Celsius to +120 degrees Celsius when the p value is 1.8, the L2 value is 0.38, and the L1 value is 7.071. Meanwhile, curve 454 shows the I3(T) variations over the temperature range of −40 degrees Celsius to +120 degrees Celsius when the p value is 1.4, the L2 value is 3.54, and the L1 value is 7.071. According to FIG. 4A, these p value and L2/L1 ratio combinations each correspond to an I3(T) slope of zero at 300° K (27° C.). FIG. 4B shows that there is some current variation over this range of operating temperatures. However, the variation shown in FIG. 4B is on the order of approximately 0.6%, which is substantially better than the variation that would be otherwise experienced.
Example circuits have been provided for purposes of example, but the use of these examples is not intended to limit the scope of the claimed subject matter. For example, specific combinations of various device characteristics (e.g., size ratios, p values, βf values, etc.) have been referred to and used to describe the claimed technology, but other combinations of device characteristics can be used. In particular, different L2/L1 ratios and/or different Nx:y ratios than those discussed above can be used.
While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

## Claims

1. A reference current source, comprising:
a current generator circuit; and
a resistance circuit connected to the current generator circuit, wherein the resistance circuit comprises a current controlled resistance circuit and a voltage controlled resistance circuit that is connected in parallel with the current controlled resistance circuit, wherein the voltage controlled resistance circuit comprises a first plurality of MOSFETs, and wherein the first plurality of MOSFETs comprise:
a first MOSFET having a drain connected to an emitter of a bipolar transistor of the current generator, and having a source connected to ground;
a second MOSFET having a drain connected to a voltage source of the current generator and a gate connected to a first current control voltage source; and
a third MOSFET having a source connected to ground and a gate connected to a second current control voltage source, wherein a drain of the third MOSFET is connected to each of a drain of the second MOSFET and a gate of the first MOSFET.

2. The reference current source of claim 1, wherein the current controlled resistance circuit comprises a second plurality of MOSFETs.

3. The reference current source of claim 2, wherein the second plurality of MOSFETs comprise:
a fourth MOSFET having a drain connected to each of the drain of the first MOSFET and the emitter of the bipolar transistor, and having a source connected to the ground;
a fifth MOSFET having a source connected to the voltage source of the current generator and a gate connected to the current generator; and
a sixth MOSFET having a source connected to ground and a gate connected to each of a gate of the fourth MOSFET, a drain of the fifth MOSFET, and a drain of the sixth MOSFET.

4. The reference current source of claim 1, wherein the current controlled resistance circuit has a positive temperature dependency.

5. The reference current source of claim 4, wherein the voltage controlled resistance circuit has a negative temperature dependency.

6. The reference current source of claim 5, wherein the current controlled resistance circuit and the voltage controlled resistance circuit are respectively configured so that a combination of the positive temperature dependency and the negative temperature dependency configure the reference current source to be temperature independent.

7. The reference current source of claim 5, wherein the current controlled resistance circuit and the voltage controlled resistance circuit are respectively configured so that a combination of the positive temperature dependency and the negative temperature dependency configure the reference current source to have a positive temperature dependence.

8. The reference current source of claim 5, wherein the current controlled resistance circuit and the voltage controlled resistance circuit are respectively configured so that a combination of the positive temperature dependency and the negative temperature dependency configure the reference current source to have a negative temperature dependence.

9. The reference current source of claim 1, wherein the current generator circuit comprises a PTAT current generator circuit.

10. A reference current source comprising:
a current generator circuit;
a current controlled resistance circuit that has a positive temperature dependence; and
a voltage controlled resistance circuit that has a negative temperature dependence, wherein the current controlled resistance circuit and the voltage controlled resistance circuit are connected in parallel to the current generator circuit, and wherein an L2/L1 ratio and a p value for MOSFETs of the reference current source are selected to provide a zero current slope at a given temperature.

11. A reference current source, comprising:
a current generator circuit; and
a resistance circuit connected to the current generator circuit, wherein the resistance circuit comprises a current controlled resistance circuit and a voltage controlled resistance circuit, the current controlled resistance circuit connected to a voltage source of the current generator circuit, the voltage controlled resistance circuit connected to the voltage source of the current generator circuit, a first current control voltage source, and a second current control voltage source.