# Patent

## Title
Timing controlled AC to DC converter and method

## Abstract

A timing controlled converter and method for converting a time varying input signal to a regulated DC output voltage for application to a load circuit. A feedback loop is employed as a control means for switchably coupling the time varying input signal to the load circuit for controlled periods of time in a manner so as to provide an average load voltage equal to a reference voltage. The duration of the controlled periods of time is a function of: the difference between the time varying input signal and the output voltage; and the integral of the difference between the output voltage and the reference voltage.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
The present application is a continuation of U.S. patent application Ser. No. 12/963,598 filed on Dec. 8, 2010, which issued on Jan. 20, 2015 as U.S. Pat. No. 8,937,825 and claims the benefit under 35 U.S.C. §119(e) to U.S. Provisional Application No. 61/285,520, filed on Dec. 10, 2009, both of which are incorporated herein by reference in their entirety.


FIELD OF THE INVENTION
This disclosure relates generally to electronic integrated circuits for use typically in implantable biomedical devices. More specifically, the disclosure relates to a timing controlled AC to DC converter.
BACKGROUND OF THE INVENTION
Many biomedical implantable devices are powered from an external time varying magnetic source. The magnetic source is inductively coupled to a coil housed within the implantable device to induce an AC voltage in the coil which is then converted or rectified to a regulated DC voltage for use to power device electronics. As a general matter, higher supply voltages are often required for analog circuits, such as stimulation circuits in implantable neuro-prosthetic devices, whereas lower supply voltages are usually required for digital circuits and processors. Accordingly, a rectified or regulated DC voltage is typically maintained at a higher value for analog circuits and a linear regulator is implemented to convert the higher value DC voltage to a lower supply voltage for the digital circuits. An example of an implantable stimulator that includes both analog and digital circuitry and voltage supplies providing a range of output voltages is found in U.S. Pat. No. 6,185,452 to Schulman, et al. As has been recognized, the approach taken in the art to generate multiple supply voltages as described above, is not very power efficient especially when considering the limited power availability from weak inductive coupling of the implanted device with the external time varying magnetic source. Attempts have been made to improve power efficiency such as the use of Buck converters and switchable capacitor converters; however they may not be suitable for neuro-prosthetic and biomedical implant applications due to the limited space available within the devices which typically can only accommodate a few discrete components. Accordingly, what is needed to satisfy the shortcomings of the prior art is an approach based on a direct conversion of the induced AC voltage to a regulated DC voltage which achieves high conversion efficiency using circuitry sufficiently small to be housed in small implantable devices.
SUMMARY
An example embodiment of the invention discloses a timing controlled AC to DC converter which supplies a regulated output voltage to a load circuit. The converter switchably couples a time varying input signal for a controlled period of time directly to the load circuit in a manner such that the average value of the regulated output voltage equals a preselected reference voltage. An embodiment of the invention comprises an integrator arranged to integrate the difference between the output or load voltage and the preselected reference voltage to thereby generate a threshold or control signal. A switch is arranged to switchably couple the time varying input signal to the load circuit for controlled periods of time. A controlled period of time commences when the time varying input signal becomes greater than the output voltage and terminates when the time varying input signal becomes greater than the value of the control signal. The duration of the controlled periods of time, so defined, causes the converter to provide an average value of the output voltage being equal to the preselected reference voltage while minimizing power loss and significantly improving converter efficiency.



BRIEF DESCRIPTION OF DRAWINGS
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure, and together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
FIGS. 1A-1C show circuit implementations of conventional power management units known in the art. More particularly, FIG. 1A shows an implementation of a power management unit using a switched-capacitor (SC) converter; FIG. 1B shows an implementation of a power management unit using a buck converter; and FIG. 1C shows an implementation of a power management unit using a linear regulator.
FIG. 2 shows an implementation of a timing controlled converter in accordance with an embodiment of the present invention.
FIG. 3 shows a voltage waveform that illustrates the controlled period of time during which the converter couples the time varying input signal to the load circuit.
FIG. 4 shows a block diagram of an embodiment of the timing controlled converter of the present invention.
FIG. 5 shows a detailed block diagram of the converter of FIG. 4.
FIG. 6 shows voltage waveforms related to the operation of the timing controlled converter of FIG. 5.
FIGS. 7A and 7B show first and second comparators, respectively, used in an implementation of the timing controlled converter of FIG. 4.
FIG. 8 shows an implementation of a boosted switch driver that is used in an implementation of the timing controlled converter of FIG. 4.



DETAILED DESCRIPTION
Power management units or voltage converter circuits housed within implantable medical devices are generally used to generate supply voltages required for operation of electronic circuits within the devices. As an illustration, FIGS. 1A-1C show conventional implementations of power management units housed within implantable devices. Power management units typically generate a high voltage supply VC (100), which may be used by a stimulator to generate stimulation current pulses and a low output voltage VDD (102), which may be used for powering various low voltage circuits. According to several embodiments of the present invention, converter circuits are assumed to receive power through inductive coupling from a radio frequency (RF) magnetic field, which is the case for many implantable biomedical devices. A metric used to characterize the converter is power efficiency, denoted as η. Power efficiency η is defined as a ratio between the output power of the converter to the input power supplied to the converter. Consequently, a high power efficiency η signifies that a large proportion of the input power is available as output power, which is generally desired.
Specifically, according to several embodiments of the present invention converters in implantable biomedical devices are powered from an external time varying magnetic source (not shown). The external magnetic source is magnetically coupled to a coil LE (115). This magnetic coupling results in an induced voltage VRF (110) across the coil LE (115). A tuning capacitor CE (120) is designed to resonate at an operating frequency fin. A conventional rectifier (125) is used to generate the high supply voltage VC (100) measured between Vc and ground (105). The high supply voltage VC (100) derives from the positive peak value and a negative peak value of the induced voltage VRF (110).
In the present disclosure, the induced voltage VRF (110) across the coil LE (115) is assumed to be periodic and has a peak value higher than the required high supply voltage VC (100). In particular, the induced voltage VRF (110) is arbitrarily assumed to be a sinusoidal wave. Consequently, after rectifying the induced voltage VRF (110), the rectifier (125) can produce the high supply voltage VC (100) equal to or less than the peak voltage of the induced voltage VRF (110).
The low supply voltage VDD (102), on the other hand, can be generated by taking the high supply voltage VC (100) of the rectifier (125) and converting it to a desired value for the low supply voltage VDD (102). Specifically, DC to DC converters, such as switched-capacitor converters, buck converters, and linear regulators, may be used to generate the low supply voltage VDD (102).
As seen from FIGS. 1A-1C (and later in FIG. 2), the coil LE (115), tuning capacitor CE (120), and rectifier (125) are common to the different implementations of the converters. Additionally, the induced voltage VRF (110), high supply voltage VC (100), and low supply voltage VDD (102) refer to the same voltages in each of FIGS. 1A-1C. Since the components (115, 120, 125) and the voltages (110, 100, 102) referred to are the same for different implementations of converter units, the same reference numerals are used to refer to the same components (115, 120, 125) and voltages (110, 100, 102) in each of FIGS. 1A-1C. Additionally, a load circuit, which is not part of the converter unit, comprises a bypass capacitor CB (130) and a load resistor RL (135). The bypass capacitor CB (130) is used to remove any AC voltage components from the low supply voltage VDD (102) such that only a DC voltage component is applied to the load resistor RL (135). The same off-chip load circuit will be used in many subsequent figures.
FIG. 1A shows an implementation that utilizes a switched-capacitor (SC) converter (140) for generating the low supply voltage VDD (102). The SC converter (140) can achieve high power efficiency η. However, the SC converter (140) requires a plurality of discrete capacitors (145) comprising C1 through CN.
The number of discrete capacitors (145) in a typical design, denoted as N, is approximately given by the equation N=VC/VDD−1. Consequently, for a typical high supply voltage VC (100) of 10 V to 15 V and typical low supply voltage VDD (102) of 3 V, the number N of discrete capacitors (145) ranges from 2 to 4. This number N does not include the bypass capacitor CB (130).
FIG. 1B shows an implementation that utilizes a buck converter (150) for generating the low supply voltage VDD (102). The number of discrete components is reduced in this implementation because of using a buck converter. However, the disadvantage of this implementation is the necessity for the inclusion of an inductor LB (155).
FIG. 1C shows an implementation of a converter unit that utilizes a linear regulator (160) for generating the low supply voltage VDD (102). This implementation that utilizes the linear regulator (160) does not require extra discrete components aside from the bypass capacitor CB (130). However, current flowing to the load resistor RL (135) also flows through the linear regulator (160). As a result, an equivalent power of (VC−VDD)·VDD/RL is dissipated by the linear regulator (160) for a total power consumption of VC−VDD/RL drawn from the high supply voltage VC (100).
With continued reference to FIG. 1C, for a value of 3V for the low output voltage VDD (102) and a range of 10V to 15V for the large output voltage VC (100), power efficiency η is between 20% and 30%, which is not very efficient. Although the implementations using the SC converter (140) and the buck converter (150) generally have higher power efficiencies compared to the implementation using linear regulators, especially for high load conditions, the implementation of the converter unit using the linear regulator (160), shown in FIG. 1C, is often the only viable choice for implantable devices due to their small size.
FIG. 2 shows an implementation of an AC to DC converter of the present invention using a timing controlled rectifier (200), henceforth referred to as TCR. By comparing FIG. 2 with FIGS. 1A-1C, the coil LE (115), tuning capacitor CE (120), and rectifier (125) are common to the different implementations. The induced voltage VRF (110), high supply voltage VC (100), and low supply voltage VDD (102) in FIG. 2 refer to the same voltages in each of FIGS. 1A-1C. The low supply voltage VDD (102) may be considered the output voltage of the AC to DC converter circuit of the present invention. Additionally, the same off-chip load circuit comprising the bypass capacitor CB (130) and the load resistor (135) is also used in FIG. 2.
The TCR (200) is adapted to generate the output voltage VDD (102) directly from the induced voltage VRF (110). The TCR (200) can achieve relatively good power efficiency without using extra discrete components aside from the bypass capacitor CB (130).
The induced voltage VRF (110) is directly applied to the rectifier (125) and to the TCR (200). The TCR (200) converts the induced voltage VRF (110), which is an AC signal, into the required output voltage VDD (102), which is a DC voltage. The rectifier (125) is used to generate the high supply voltage VC (100) by rectifying the positive peak value and negative peak values of the induced voltage VRF (110).
FIG. 3 shows an exemplary voltage waveform for the induced voltage VRF (110) and also illustrates the method of setting the controlled period of time for coupling VRF (110) to a load circuit, which in this case comprises bypass capacitor CB (130) and load resistor RL (135) and which also defines the basic operation of the TCR (200). As illustrated in FIG. 3, the controlled amount of time for coupling VRF (110) to a load circuit is shown by a turn-on period Δt (300).
The TCR's (200) turn-on period Δt (300) occurs for a time period where the induced voltage VRF (110) is slightly above the output voltage VDD (102), as illustrated in FIG. 3. In particular, the TCR's (200) turn-on period Δt (300) is given as a difference between a turn-on time ts (305) and a turn-off time to (310). During the turn-on period Δt (300), the TCR (200) conducts current from the voltage source VRF (110) to the load circuit (capacitor CB (130) and load resistor RL (135)) otherwise identified as output voltage VDD (102) such that the current is drawn from VRF (110) and stored as accumulated charge in the bypass capacitor CB (130). The turn-on time ts (305) and the turn-off time to (310) will be described in more detail in relation to FIGS. 4 and 5, in which the operation of the TCR (200) will be described in more detail.
FIG. 4 shows an exemplary embodiment of the TCR (200). The same off-chip components, which comprise the bypass capacitor CB (130) and load resistor RL (135), as shown in FIG. 2 are also shown in FIG. 4. As shown in FIG. 4, the value of the output voltage VDD (102) is set by a negative feedback control loop (hereinafter referred to as a “feedback loop”) that switchably controls the operation of transistor MSW (405). Specifically, the feedback loop comprises a digital control unit (410), an integrator (415), a first comparator (420), a second comparator (430), a switch driver (445), and the transistor MSW (405).
As a whole, the feedback loop is used to ensure that the transistor MSW (405) turns on only during the portion of time that the induced voltage VRF (110) is increasing in value. Specifically, with reference to the waveform on FIG. 3, the transistor MSW (405) turns on only during the turn-on period Δt (300). When the induced voltage VRF (110) becomes larger than the output voltage VDD (102), the transistor MSW (405) will turn on at the time ts (305).
Specifically, the digital control unit (410), which comprises a specific arrangement of logic gates, takes a first comparator output VCO1 (435) and a second comparator outputs VCO2 (440) as its inputs and provides a first control voltage Von_b (455) and a second control voltage Von (460) as its outputs. Both Von_b (455) and Von (460) are applied as inputs to the switch driver (445). The switch driver (445) provides a switch driver voltage VBG (465), which is applied to the gate of the transistor MSW (405). Logic gates in the digital control unit (410) are designed in such a way as to ensure that transistor MSW (405) turns on only during a portion of time that the induced voltage VRF (110) is increasing in value.
The integrator (415) takes as its input the output voltage VDD (102) and a reference voltage Vref (400). The integrator (415) integrates the difference between the output voltage VDD (102) and the reference voltage Vref (400) and provides thereby a resultant integrated value identified as the integrator output voltage Vint (425). The voltage Vint (425) is used as a threshold voltage or control signal for application to the second comparator CO2 (430).
The first comparator CO1 (420) has as its inputs the induced voltage VRF (110) and the output voltage VDD (102). The first comparator CO1 (420) detects when the induced voltage VRF (110) becomes larger than the output voltage VDD (102). When the induced voltage VRF (110) becomes larger than the output voltage VDD (102), the first comparator output voltage VCO1 (435) output from the first comparator CO1 (420) will cause transistor MSW (405) to turn on at the turn-on time ts (305). More specifically, the voltage MCO1 (435) is applied to the digital control unit (410), which outputs a first output Von_b (455) and a second output Von (460) to the switch driver (445). The switch driver (445) provides a switch driver output VBG (465) to the gate of the transistor MSW (405), which turns on the transistor MSW (405). When the transistor MSW (405) is turned on, a load current IL (445) is supplied from VRF (110) to the load resistor RL (135).
The second comparator CO2 (430) has as its inputs the voltage VRF (110) and the integrator output voltage Vint (425). The second comparator CO2 (430) detects when the voltage VRF (110) becomes greater than the integrator output voltage Vint (425). When VRF (110) becomes greater than the voltage Vint (425), output voltage VCO2 (440) of the second comparator CO2 (430) will cause transistor MSW (405) to turn off at the turn-off time to (310). The truth table (Table 1) shown below illustrates the relationship between the identified voltages and the corresponding state of transistor MSW (405).












TABLE 1







Voltage
Condition
VBG1
Transistor MSW









VCO1
High if VRFa > VDD
High
ON




Low if VRFa < VDD
Low
OFF



VCO2
High if VRFa > Vint
High
OFF




Low if VRFa < Vint
Low
ON










For the TCR (200) shown in FIG. 4, a load current IL (450) flows from voltage source VRF (110) to the load circuit. Operation of the feedback loop, and thus operation of the TCR (200) itself, is as follows. When the average load current IL (450) increases, the average output voltage VDD (102) decreases. Since the integrator output voltage Vint (415) is a function of the difference between the voltages VDD (102) and Vref (400), the integrator output voltage Vint (415) increases when VDD (102) decreases. Since the first comparator output VCO1 (435) is a function of the difference between the voltages VRF (110) and VDD (102), the first comparator CO1 (420) will have a logic high at the output earlier when the voltage VDD (102) decreases, which causes transistor MSW (405) to turn on earlier. Since the second comparator output VCO2 (440) is a function of the difference between the voltages VRF (110) and Vint (415), the second comparator CO2 (430) will have a logic high at the output later when the voltage Vint (415) increases, which would cause transistor MSW (405) to turn off later. Hence, the turn-on period Δt (300) for the transistor MSW (405) will become longer and more charge will be accumulated in the bypass capacitor CB (130).
Steady state is reached when an average value of the output voltage VDD (102) becomes equal to the reference voltage Vref (400). In the steady state, voltage Vint (425) will become nearly constant and the transistor MSW (405) will turn on and off for an amount of time needed to accumulate just enough charge to keep the average value of the output voltage VDD (102) equal to the reference voltage Vref (400). As a result, the average value for the output voltage VDD (102) is regulated to have a value equal to the reference voltage Vref (400).
With reference to FIG. 4 and later to FIG. 6, it should be noted that transistor MSW (405) and MSW1 (563) in the case of FIG. 6, will be turned on when the polarity of VRF and VDD (535) are the same. Furthermore, it should also be noted that although FIG. 3 and FIG. 6, for example, show and describe VDD as having a positive polarity, the invention contemplates a configuration for operation with VDD having a negative potential with respect to ground. Thus in order to avoid any confusion regarding comparing voltages when referring to relative magnitudes with respect to the use of the terms “greater than”, “larger than”, “exceeds”, and the like, it is to be understood that absolute values of voltage magnitudes are to be considered.
It should be noted that due to any delays attributable to the comparators CO1 (420) and CO2 (430), the voltage VRF (110) at the turn off time to (305), denoted as a voltage VOFF (315) in FIG. 3, may be slightly higher than the voltage Vint (425). However, the feedback loop will adjust the turn-off time to (305) so as to maintain the average value of the output voltage VDD (102) equal to the reference voltage Vref (400).
Consider an ideal case where the transistor MSW (405) has a turn-on resistance RSW (not shown) that is nearly zero and where the comparator (420, 430) delays are zero. The turn-on period Δt (300) required to accumulate sufficient charge on the bypass capacitor CB (130) will approach zero. In this ideal case, the voltage VOFF (315) will equal the output voltage VDD (102). Additionally, in this ideal case, no power is dissipated by the transistor MSW (405) and the power efficiency η for converting power from the induced voltage VRF (110) to the output voltage VDD (102) will approach 100%.
As is recognized, transistor MSW (405) has a finite turn-on resistance RSW, especially when a high-voltage MOSFET is used for the transistor MSW (405). In such cases, the power efficiency η may be about 50% to 90% depending on the frequency and the amplitude of the induced voltage VRF (110), the value of VDD, the turn-on period Δt and the resistance of the transistor MSW. As the frequency of the induced voltage VRF (110) increases, the power efficiency η decreases due to higher dynamic power dissipation in driving MSW more frequently. Compared to the implementation utilizing the linear regulator (160) as shown in FIG. 1C, it can be shown that in a case where VD>VDD/η, the embodiment of the converter using TCR (200) will provide some power savings by a percentage of [1−VDD/(ηVC)] compared to the use of the linear regulator (160). For instance, given an exemplary situation where VC=10 V, VDD=3 V and η=50%, the TCR (200) will provide a power saving of 40% compared to the use of the linear regulator (160).
Referring now to FIG. 5 there is shown an embodiment of the converter that incorporates the timing controlled rectifier (200) shown in FIG. 4. A bypass capacitor CB (580) and a load Rload (585) are off-chip components and thus are not part of the converter.
The converter unit in FIG. 5 is inductively powered from an external magnetic source (not shown). The external magnetic source induces a voltage VRF (500) across receiving coil LE (502). Capacitor CE (504) and coil LE (502) form a parallel resonant circuit and the value of tuning capacitor CE (504) is selected to establish a circuit resonant frequency of fin. The induced voltage VRF (500) comprises a first voltage rail RFA (506) corresponding to a first voltage VRFa (507) and a second voltage rail RFB (508) corresponding to a second voltage VRFb (509). The power management unit further comprises a full-wave rectifier (510), a first converter core (515), a second converter core (520), and integrator (525). The full-wave rectifier (510) generates a high supply voltage VC (530), which is generally used to supply voltage to the converter cores (515, 520) in the power management unit as well as analog circuits in implantable devices (not shown).
The timing controlled rectifier (200) in FIG. 4 comprises one of the converter cores (515, 520) and the integrator (525) shown in FIG. 5. The timing controlled rectifier (200) generates an output voltage VDD (535), which is generally used to power digital control circuits and communication circuits in implantable devices (not shown).
The first converter core (515) comprises a first comparator CO1 (545), a second comparator CO2 (550), a digital control unit (555), and a boosted switch driver (560). Note that the boosted switch driver (560), shown in FIG. 5, is equivalent to the combination of the switch driver (445) and the transistor MSW (405), shown in FIG. 4. The second converter core (520) comprises components, not shown in FIG. 5, similar to those in the first converter core (515). Specifically, the second converter core (520) also comprises its own first comparator, second comparator, digital control unit, and boosted switch driver. An implementation of the integrator (525) is shown in FIG. 5 and comprises a transconductance amplifier (526), a capacitor CC (527), and a resistor RC (528).
As previously described with reference to FIG. 4, basic functionality of the converter cores (515, 520), the integrator (525), the digital control unit (555), and the boosted switch driver (560), which form a feedback loop, is to set the average value of the output voltage VDD (535) equal to a constant reference voltage Vref (540).
The integrator (525) has as one input the preselected reference voltage Vref (540) and the output voltage VDD (535) as another input and provides as an output, a voltage Vint (529) equal to the integral of the difference of Vref (540) and VDD (535). The first comparator CO1 (545) has as one input VRFa (507) and as another input VDD (535) and provides as an output voltage VCO1 (547), which is a function of the difference between VRFa (507) and VDD (535). In a similar fashion, the second comparator CO2 (550) has as inputs VRFa (507) and Vint (529) and provides VCO2 (552) as its output. A more detailed description of the functionality of the converter cores (515, 520) and the integrator (525) is given with reference to both FIGS. 5 and 6.
As shown in FIG. 6, during a first time interval a (600), where the first voltage VRFa (507) is increasing, a first transistor M1 (512) has the voltage VRFa (507) applied at its gate, the voltage VRFb (509) applied at its drain, and ground tied to its source. Since the gate voltage is sufficiently large during the time interval a (600), the second voltage rail RFB (508) is tied to the ground terminal. Consequently, the first transistor M1 (512) is switched on and the second voltage rail RFB (508) is tied to ground.
When the voltage VRFa (507) becomes greater than the output voltage VDD (535), the first comparator output voltage VCO1 (547) of the first comparator CO1 (545) is set to high. When the voltage VCO1 (547) is high, the digital control unit (555) sets a gate drive voltage VBG1 (562) in the boosted switch driver (560) to high. When the gate drive voltage VBG1 (562) is high, a transistor MSW1 (563) is turned on, allowing current to flow from the first voltage rail RFA (506) to the bypass capacitor CB (580) and the load Rload (585). As the result of an equivalent finite impedance attributable to the power receiving coil LE (502) and the tuning capacitor CE (504), the voltage VRFa (507) will be distorted as shown in FIG. 6. As previously mentioned, the feedback loop comprising the converter cores (515, 520), the integrator (525), the digital control unit (555), and the boosted switch driver (560) is utilized to set the average value of the output voltage VDD (535) equal to the constant reference voltage Vref (540).
The integrator (525) integrates the average difference between the constant reference voltage Vref (540) and the output voltage VDD (535). The integrator (525) outputs an integrator output voltage Vint (529), which serves as a threshold value for the second comparator CO2 (550). When the voltage VRFa (507) becomes greater than the voltage Vint (529), such as at point b (605), the second comparator output voltage VCO2 (552) is set to high. When the voltage VCO2 (552) is high, the digital control unit (555) sets the gate drive voltage VBG1 (562) to low and thus turns off the transistor MSW1 (563). Current flow will cease for a time interval c (610) so that the amount of current delivered to the load Rload (585) will keep the average value for the output voltage VDD (535) equal to the constant reference voltage Vref (540). Consequently, duration of time when transistor MSW1 (563) is turned off depends on a load current IL (590).
To prevent current from flowing back from the output voltage VDD (535) to the first voltage rail RFA (506), transistor MSW1 (563) is turned off before the voltage VRFa (507) reaches a peak value VP (615), as shown in FIG. 6. Current flowing from the output voltage VDD (535) to the first voltage rail VRFa (506) would cause the converter to lose regulation and reduce power efficiency η. High values for power efficiency η are obtained if the transistor MSW1 (563) turns on when the voltage VRFa (507) is nearly equal to the voltage VDD (535).
One method to prevent current from flowing back from the output voltage VDD (535) to the first voltage rail RFA (506) requires design of the digital control unit (555) such that transistor MSW1 (563) will not turn on when the voltage VRFa (507) decreases from its peak value VP (615). As seen in FIG. 6, the bias voltage VBG1 (562) is set to low and thus transistor MSW1 (563), is turned off for the time that the voltage VRFa (507) is decreasing from its peak value VP (615).
It should be noted that in FIG. 5 the second converter core (520) is illustrated by a black box for increased clarity. According to several embodiments of the invention, the second converter core (520) comprises a first comparator, second comparator, digital control unit, and boosted switch driver that parallel those used to implement the first converter core (515). The components of the second converter core (520) are not shown in FIG. 6. When the induced voltage VRF (500) enters a second half of its cycle, specifically the cycle where the voltage VRFb (509) starts increasing, the first voltage rail RFA (506) is switched to ground by the second transistor M2 (513). Consequently, operation similar to that described for the time periods a (600) and c (610) will occur, except operation will involve the second converter core (520) as opposed to the first converter core (515).
FIGS. 7A and 7B show a possible implementation of the first comparator CO1 (545) and the second comparator CO2 (550), respectively. The implementations of the comparators (545, 550) are based on an exemplary common-source amplifier topology. FIG. 7A shows one possible implementation of the first comparator CO1 (545) shown in FIG. 5. The voltages VRFa (507), VDD (535), and VCO2 (552) shown in FIG. 7B refer to the same voltages VRFa (507), VDD (535), and VCO2 (552) shown in FIG. 5 and are thus given the same reference numerals in both figures. The first comparator CO1 (545) has the voltages VRFa (507) and VDD (535) as its inputs and provides the voltage VCO1 (547) as its output. The first comparator (545) compares the first voltage VRFa (507) and the output voltage VDD (535). In a first case where the voltage VRFa (507) becomes greater than the voltage VDD (535), a third transistor M3 (700) turns on and comparator output voltage VCO1 (552) is high. In a second case where the voltage VRFa (507) is less than the voltage VDD (535), the third transistor M3 (700) turns off and the comparator output voltage VCO1 (547) is low.
To maximize power efficiency q, the voltage VCO1 (547) should be high when the voltage VRFa (507) is just slightly larger than the voltage VDD (535). One method to achieve this is by minimizing delay attributable to the first comparator CO1 (545). To minimize delays due to the first comparator CO1 (545), a resistor R1 (720) is used in comparator CO1 (545). The resistor R1 (720) introduces a small offset voltage Voffset (722). As a result of the small offset voltage Voffset (722), the comparator output voltage VCO1 (547) starts to turn high when the voltage VRFa (507) is just slightly larger than the voltage VDD (535) minus the offset voltage Voffset (737). The first comparator CO1 (545) sets the voltage VCO1 (547) to high earlier than it would have set the voltage VCO1 (547) to high had there been no offset voltage Voffset (722). The earlier time at which the voltage VCO1 (547) is set to high compensates for any delay attributable to the first comparator CO1 (545).
For a given bias voltage Vbn (725) set on a fourth transistor M4 (705) and a sixth transistor M6 (715), the resistance of the resistor R1 (720) is optimized for a frequency of 1 MHz for fin. A capacitor C1 (730) is used to minimize fluctuations on the gate of transistor M3 due to coupling between the output voltage VDD (535) and the voltage VRFa (507) through a parasitic capacitance CGS3 (not shown) that exists between the gate and source of the third transistor M3 (700).
FIG. 7B shows one possible implementation of the second comparator CO2 (550) shown in FIG. 5. The voltages VRFa (507), Vint (529), and VCO1 (547) shown in FIG. 7B refer to the same voltages VRFa (507), Vint (529), and VCO1 (547) shown in FIG. 5 and are thus given the same reference numerals in both figures.
The second comparator CO2 (550) has as inputs VRFa (507) and Vint (529) and VCO2 (552) as its output. The second comparator CO2 (550) compares the values of VRFa (507) and Vint (529) and in a first case where the voltage VRFa (507) exceeds the voltage Vint (529), transistor M7 (750) turns on and comparator output voltage VCO2 (552) is high. Conversely, in a second case where Vint (529) exceeds VRFa (507), transistor M7 (750) turns off and comparator output voltage VCO2 (552) is low.
An exemplary source follower configuration, comprising transistor M9 (760) and transistor M10 (765), is used for its voltage buffering characteristic. Specifically, the source follower configuration buffers the integrator output voltage Vint (529) from anomalies due to coupling between the voltage VRFa (507) and the voltage Vint (529) through a parasitic capacitance CGS7 (not shown) that exists between gate and source of transistor M7 (750).
Any voltage offsets effecting VRFa (507) and Vint (529) due to a source to gate voltage VSG7 (752) of M7 (750) and a gate to source voltage VGS9 (762) of transistor M9 (760) is automatically compensated for by way of the feedback loop. As noted earlier in relation to FIG. 5, the feedback loop comprises the integrator (525), comparators (545, 550), digital control unit (555), and boosted switch driver (560). The feedback loop will adjust the voltage Vint (529) to compensate for any comparator offsets due to the voltages VSG7 (752) and VGS9 (762). Since the voltage Vint (529) is the output of the integrator (525), as shown in FIG. 5, the value of the output voltage VDD (535) is influenced by any offset voltages attributable to transconductance amplifier (526).
As previously mentioned with regard to FIGS. 5, 7A, and 7B, in order to obtain a high power efficiency η, the output voltage VDD (535) is driven close to the voltage VRFa (507) by the transistor MSW1 (563) and the gate drive voltage VBG1 (562). Similarly, the output voltage VDD (535) is driven close to the voltage VRFb (509) by a transistor MSW2 and a gate drive voltage VBG2. The transistor MSW2 and gate drive voltage VBG2 are not directly shown in FIG. 5. They are implicitly found in the second converter core (520), and the transistor MSW2 and gate drive voltage VBG2 parallel the transistor MSW1 (563) and the gate drive voltage VBG1 (562), respectively, of the first converter core (515). Hence, the transistors MSW1 (563) and MSW2 are generally designed to have low on-resistance which can be accomplished by increasing gate drive voltages VBG1 (562) and VBG2 (not shown) of the transistors MSW1 (563) and MSW2 (not shown), respectively.
FIG. 8 shows an implementation of the boosted switch driver (560) shown in FIG. 5. Specifically, the boosted switch driver (560) is used for generating a large value for the gate drive voltage VBG1 (562). The voltages VRFa (507), VDD (535), VC (530), and VBG1 (562) shown in FIG. 8 refer to the same voltages VRFa (507), VDD (535), VC (530), and VBG1 (562) shown in FIG. 5 and are thus given the same reference numerals in both figures. Similarly, the transistor MSW1 (563) shown in FIG. 8 refers to the same transistor MSW1 (563) shown in FIG. 5 and is thus given the same reference numeral in both figures.
When a driver input ‘IN’ (800) (same as the output of the digital control (555) shown in FIG. 5) is low, capacitor voltage VC2 (805) is driven to a high voltage by a first inverter U1 (810) through capacitor C2 (815). The voltage VC2 (805) is applied to the gate of transistor M16 (840) and transistor M17 (845), and the source of transistor M18 (850). When the voltage VC2 (805) is high, transistor M17 (845) is turned on due to the high gate voltage applied to transistor M17 (845) and transistor M18 (850) is turned off due to the high source voltage applied to transistor M18 (850). As a result, the high supply voltage VC (530) is applied to capacitor C3 (855), charging capacitor C3 (855) such that capacitor voltage VC3 (860) is close to the high supply voltage VC (530). The gate drive voltage VBG1 (562) is driven to ground through transistor M14 (830) and transistor M13 (825).
When the driver input ‘IN’ (800) is high, capacitor voltage VC2 (805) will switch to a low value. Transistor M17 (845) is turned off due to the low value of VC2 (805) applied at its gate. Transistor M18 (850) is turned on due to the low value of VC2 (805) applied at its source. As a result of transistor M18 (850) turning on, the high supply voltage VC (530) is applied to capacitor C2 (815), charging capacitor C2 (815) such that capacitor voltage VC2 (805) is close to the high supply voltage VC (530). Additionally, both capacitor voltage VC3 (860) and the gate drive voltage VBG1 (562) will be driven to a voltage (VBS+VC)C3/(C3+CG_SW1) where CG_SW1 is a total gate capacitance of transistor MSW1 (563) plus other parasitic capacitances. Consequently, a large value for the gate drive voltage VBG1 (562) can be obtained when the capacitance of capacitor C3 (855) is much larger than CG_SW1.
To maximize the gate drive voltage VBG1 (562), capacitor C3 (855) is implemented using both MIM capacitors and MOS capacitors. Although either the high supply voltage VC (530) or the output voltage VDD (535) can be used in place of a bias voltage VBS (862), power efficiency q is found to be slightly higher when the voltage VDD (535) is used. Transistors M14 (830) and M15 (835) are used for reducing the drain-to-gate voltage on transistors M13 (825) and M16 (840), respectively.
Since a deep NWell process can be used, transistor MSW1 (563) is connected to the voltage VDD (535) through the transmission gate U2 (865) to reduce body effect. As a result of reducing the body effect, the on-resistance of the transistor MSW1 (563) is also reduced.
A number of embodiments of the invention have been disclosed. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. For example, the integrator 415 as configured, takes the form of a proportional control circuit that provides a proportional control signal as a function of the difference between the output voltage VDD (102) and the preselected reference voltage. Other types of proportional control circuits are also contemplated by the present invention such as for example, but certainly not limited to, a circuit commonly known as a “bang-bang” controller circuit. Accordingly, other embodiments including circuits configured as proportional control circuits are also within the scope of the following claims.

## Claims

1. A method for supplying a regulated output voltage to a load circuit, utilizing a converter circuit configured to switchably couple a time varying input signal to the load circuit, the method comprising the steps of:
integrating the difference between the regulated output voltage and a preselected reference voltage to thereby provide a control signal; and
switchably coupling the time varying input signal to the load circuit for controlled periods of time when the polarity of the regulated output voltage and the polarity of the time varying signal are the same, said controlled period of time:
commencing when the absolute value of the time varying signal becomes greater than the absolute value of the regulated output voltage; and
terminating when the absolute value of the time varying input signal becomes greater than the absolute value of the control signal for maintaining the average value of the regulated output voltage equal to the preselected reference voltage.

2. The method of claim 1 further comprising the step of providing a first voltage being a function of the difference between the time varying input signal and the control signal.

3. The method of claim 2 further comprising the step of providing a second voltage being a function of the difference between the time varying input signal and the output voltage.

4. The method of claim 3 further comprising the steps of providing a first drive signal when the second voltage indicates that the absolute value of the time varying signal becomes greater than the absolute value of the output voltage and further providing a second drive signal when the first voltage indicates that the absolute value of the time varying signal becomes greater than the absolute value of the control signal.

5. The method of claim 4 further comprising the steps of coupling the time varying input signal to the load circuit upon occurrence of the first drive signal and decoupling the time varying input signal from the load circuit upon the occurrence of the second drive signal.

6. A method of supplying a regulated output voltage to a load circuit, said method utilizing a converter circuit configured to switchably couple a time varying input signal to the load circuit for providing a regulated output voltage having an average value equal to a preselected reference voltage, said method comprising the steps of:
providing a proportional control signal as a function of the difference between the regulated output voltage and the preselected reference voltage for providing the proportional control signal; and
switchably coupling the time varying input signal to the load circuit for controlled periods of time, said controlled period of time:
commencing when the absolute value of the time varying signal becomes greater than the absolute value of the output voltage; and
terminating when the absolute value of the time varying input signal becomes greater than the absolute value of the control signal, for thereby maintaining the average value of the output voltage equal to the preselected reference voltage.