# Patent

## Title
Semiconductor device manufacturing method, and semiconductor device

## Abstract

A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-239332, filed on Nov. 26, 2014, the entire contents of which are incorporated herein by reference.
FIELD
Embodiments described herein relate generally to a semiconductor device manufacturing method, and a semiconductor device.
BACKGROUND
SiC (silicon carbide) is expected to be a material for next-generation semiconductor devices. SiC has excellent physical properties, having a band gap three times wider than that of Si (silicon), a breakdown field strength approximately 10 times higher than that of Si, and a heat conductivity approximately three times higher than that of Si. A semiconductor device that has low loss and is capable of high-temperature operation can be realized by taking advantage of those properties.
In a bipolar device such as a diode using SiC, the lifetime of minority carriers becomes shorter due to defects such as carbon vacancies. If the lifetime of minority carriers becomes shorter, the rate of decrease in reverse recovery current at a time when the device is turned off becomes higher, resulting in increased noise. This problem is particularly noticeable in cases when the lifetime of minority carriers in the vicinity of an electrode which is close to an edge of a depletion layer is short.
So as to reduce noise at a time when the device is turned off, there is a demand for a lower rate of decrease in reverse recovery current, and realization of soft recovery characteristics.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment;
FIG. 2 is a diagram showing a crystalline structure of a SiC semiconductor according to the first embodiment;
FIG. 3 is a diagram showing the profile of the concentration of carbon vacancies in the semiconductor device according to the first embodiment;
FIG. 4 is a schematic cross-sectional view of the semiconductor device being manufactured by a semiconductor device manufacturing method according to the first embodiment;
FIG. 5 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the first embodiment;
FIG. 6 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the first embodiment;
FIG. 7 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the first embodiment;
FIG. 8 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the first embodiment;
FIG. 9 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the first embodiment;
FIG. 10 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the first embodiment;
FIG. 11 is a schematic cross-sectional view of the semiconductor device being manufactured by a semiconductor device manufacturing method according to a second embodiment;
FIG. 12 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the second embodiment;
FIG. 13 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the second embodiment;
FIG. 14 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the second embodiment;
FIG. 15 is a schematic cross-sectional view of the semiconductor device being manufactured by a semiconductor device manufacturing method according to a third embodiment;
FIG. 16 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the third embodiment;
FIG. 17 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the third embodiment;
FIG. 18 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment;
FIG. 19 is a diagram showing the profile of the concentration of carbon vacancies in the semiconductor device according to the fourth embodiment;
FIG. 20 is a schematic cross-sectional view of the semiconductor device being manufactured by a semiconductor device manufacturing method according to the fourth embodiment;
FIG. 21 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the fourth embodiment;
FIG. 22 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the fourth embodiment;
FIG. 23 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the fourth embodiment;
FIG. 24 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the fourth embodiment; and
FIG. 25 is a schematic cross-sectional view of the semiconductor device being manufactured by the semiconductor device manufacturing method according to the fourth embodiment.



DETAILED DESCRIPTION
A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.
The following is a description of embodiments, with reference to the accompanying drawings. In the description below, same or similar components are denoted by same reference numerals, and explanation of components described once will not be repeated.
In the description below, n+, n, n−, p+, p, and p− indicate relative levels of impurity concentrations in the respective conductivity types. Specifically, the concentration of an n+-type impurity is relatively higher than the concentration of the corresponding n-type impurity, and the concentration of an n−-type impurity is relatively lower than the concentration of the corresponding n-type impurity. Likewise, the concentration of a p+-type impurity is relatively higher than the concentration of the corresponding p-type impurity, and the concentration of a p−-type impurity is relatively lower than the concentration of the corresponding p-type impurity. It should be noted that there are cases where an n+-type and an n−-type are referred to simply as an n-type, and a p+-type and a p−-type are referred to simply as a p-type.
First Embodiment
A semiconductor device according to this embodiment includes: a first electrode; a second electrode; an n-type SiC layer provided between the first electrode and the second electrode, the SiC layer including a low-carbon-vacancy-concentration region at the second electrode side, a carbon vacancy concentration being minimized in the low-carbon-vacancy-concentration region; and a p-type impurity region provided between the first electrode and the SiC layer.
FIG. 1 is a schematic cross-sectional view showing the structure of a PIN diode that is a semiconductor device according to this embodiment.
This PIN diode 100 includes an anode electrode (the first electrode) 12, a cathode electrode (the second electrode) 14, an n−-type drift layer (the n-type SiC layer) 16, a low-carbon-vacancy-concentration region 16a, a p-type anode region (the p-type impurity region) 18, and an n-type cathode region (an n-type impurity region) 20.
FIG. 2 is a diagram showing a crystalline structure of a SiC semiconductor. A typical crystalline structure of a SiC semiconductor is a hexagonal crystal system such as 4H—SiC. One of the faces (the top planes of a hexagonal prism) having the c-axis extending in the axial direction of the hexagonal prism as the normal line is the (0001) face. The face equivalent to the (0001) face is referred to as the silicon face (Si face) and is written as the {0001} face. Si (silicon) is arranged in the silicon face.
The other one of the faces (the top planes of the hexagonal prism) having the c-axis extending in the axial direction of the hexagonal prism as the normal line is the (000-1) face. The face equivalent to the (000-1) face is referred to as the carbon face (C face) and is written as the {000-1} face. C (carbon) is arranged in the carbon face.
Meanwhile, a side face (prismatic plane) of the hexagonal prism is an m face equivalent to the (1-100) face, or is the {1-100} face. The face extending along edge lines that are not adjacent to each other is an a face equivalent to the (11-20) face, or is the {11-20} face. Both Si (silicon) and C (carbon) are arranged in the m face and the a face.
The n−-type drift layer 16 is provided between the anode electrode 12 and the cathode electrode 14. The drift layer 16 is a SiC epitaxially grown layer formed on a SiC substrate (not shown) by epitaxial growth, for example.
The concentration of the n-type impurity in the drift layer 16 is not lower than 5×1014 cm−3 and not higher than 5×1015 cm−3, for example. The n-type impurity is N (nitrogen), for example. The thickness of the drift layer 16 is not smaller than 50 μm and not greater than 150 μm, for example.
The surface of the drift layer 16 is a plane tilted zero to eight degrees with respect to the silicon face, for example. A plane tilted zero to eight degrees with respect to the silicon face can be regarded as substantially equivalent to the silicon face in terms of characteristics.
The drift layer 16 has the low-carbon-vacancy-concentration region 16a on the side of the cathode electrode 14. The low-carbon-vacancy-concentration region 16a is the region where the carbon vacancy concentration is minimized in the drift layer 16.
The p-type anode region 18 is provided between the anode electrode 12 and the drift layer 16. The anode region 18 is provided on the surface of the drift layer 16.
The concentration of the p-type impurity in the anode region 18 is not lower than 1×1018 cm−3 and not higher than 1×1020 cm−3, for example. The p-type impurity in the anode region 18 is Al (aluminum), for example. Alternatively, the p-type impurity may be B (boron), Ga (gallium), or In (indium).
The depth of the anode region 18 is approximately 0.3 μm, for example. The surface of the anode region 18 is also a plane tilted zero to eight degrees with respect to the silicon face, for example.
The anode electrode 12 is made of a metal, for example. The metal forming the anode electrode 12 is TiN (titanium nitride), for example. Another metal such as Al (aluminum) may be stacked on the TiN. Other than a metal, it is possible to employ an electrically-conductive material such as polycrystalline silicon containing an n-type impurity.
The anode region 18 and the anode electrode 12 are electrically connected.
The n-type cathode region 20 is provided between the drift layer 16 and the cathode electrode 14. The cathode region 20 has the function to lower the contact resistance of the cathode electrode 14.
The n-type impurity concentration in the cathode region 20 is higher than the n-type impurity concentration in the drift layer 16. The concentration of the n-type impurity in the cathode region 20 is not lower than 1×1018 cm−3 and not higher than 1×1020 cm−3, for example. The n-type impurity is P (phosphorus), for example. Alternatively, the n-type impurity may be N (nitrogen), for example. The thickness of the cathode region 20 is not smaller than 0.1 μm and not greater than 1 μm, for example.
The surface of the cathode region 20 on the side of the cathode electrode 14 is a plane tilted zero to eight degrees with respect to the carbon face. A plane tilted zero to eight degrees with respect to the carbon face can be regarded as substantially equivalent to the carbon face in terms of characteristics.
The cathode electrode 14 is formed with stacked layers that are a Ni (nickel) barrier metal layer and an Al (aluminum) metal layer formed on the barrier metal layer, for example. The Ni barrier metal layer and the Al metal layer may form an alloy through a reaction. Alternatively, the Ni and the cathode region 20 may form a silicide through a reaction.
The cathode region 20 and the cathode electrode 14 are electrically connected.
FIG. 3 is a diagram showing the profile of the concentration of carbon vacancies in the semiconductor device according to this embodiment. This diagram shows the profile of the concentration of carbon vacancies in a cross-section including the p-type anode region (p-type impurity region) 18 and the n-type cathode region (n-type impurity region) 20. The concentration of carbon vacancies can be measured by DLTS (Deep Level Transient Spectroscopy). Specifically, the Z1/2 concentration measured by DLTS is regarded as the concentration of carbon vacancies, for example.
As shown in FIG. 3, the low-carbon-vacancy-concentration region 16a where the carbon vacancy concentration is minimized is provided in a portion of the n-type drift layer (n-type SiC layer) 16 located on the side of the cathode electrode 14. The carbon vacancy concentration is minimized in the interface between the cathode region 20 and the n-type drift layer 16, for example. In the low-carbon-vacancy-concentration region 16a, the Z1/2 level density measured by DLTS is preferably 1×1011 cm−3 or lower. Here, a portion of the drift layer 16 located on the side of the cathode electrode 14 means a location closer to the cathode region 20 than to the middle portion of the drift layer 16 in the thickness direction.
In the low-carbon-vacancy-concentration region 16a, the interstitial carbon concentration is higher than that in any other region in the drift layer 16 of this embodiment. In other words, the PIN diode 100 has the region where the interstitial carbon concentration is maximized in a portion of the n-type drift layer (n-type SiC layer) 16 located on the side of the cathode electrode 14.
Next, a semiconductor device manufacturing method according to this embodiment is described. The semiconductor device manufacturing method according to this embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer. The semiconductor device manufacturing method according to this embodiment is an example of a method of manufacturing the semiconductor device shown in FIG. 1.
FIGS. 4 through 10 are schematic cross-sectional views showing the semiconductor device being manufactured by the semiconductor device manufacturing method according to this embodiment.
First, an n+-type SiC substrate 10 is prepared. The SiC substrate 10 is the SiC of 4H—SiC containing N (nitrogen), for example, as the n-type impurity at an impurity concentration not lower than 1×1018 cm−3 and not higher than 1×1020 cm−3, for example. The SiC substrate 10 is a substrate formed by a sublimation technique, for example. The thickness of the SiC substrate 10 is not smaller than 300 μm and not greater than 500 μm, for example.
One of the planes of the SiC substrate 10 is a silicon face, for example. The other one of the planes of the SiC substrate 10 is a carbon face, for example.
The n−-type drift layer 16 is formed on the silicon face of the SiC substrate 10 by an epitaxial growth technique (FIG. 4).
The p-type anode region (p-type impurity region) 18 is then formed on the opposite side (one side) of the drift layer 16 from the SiC substrate 10. P-type impurity ions are implanted into the drift layer 16 by a known ion implantation technique, to form the anode region 18 (FIG. 5).
The p-type impurity is Al (aluminum), for example. The dose amount in the ion implantation is not smaller than 1×1015 cm−2 and not larger than 1×1017 cm−2, for example. So as to make the anode region 18 a high-concentration region, the dose amount is preferably 1×1016 cm−2 or larger.
At least part of the SiC substrate 10 is then removed, to expose the other side of the drift layer 16 (FIG. 6). Although the entire SiC substrate 10 is removed in this example case, only the peripheral portions of the SiC substrate 10 may be left, or the SiC substrate 10 may be left in a lattice-like fashion, so as to secure the strength of the drift layer 16 after the removal, for example.
The SiC substrate 10 is removed by polishing or grinding, for example. Alternatively, the SiC substrate 10 can be removed by dry etching or wet etching, for example.
Carbon (C) ions are then implanted into the opposite side (the other side) of the drift layer 16 from the anode region 18. Carbon (C) ions are implanted into the exposed part of the drift layer 16. Through the carbon (C) ion implantation, a high-carbon-concentration region 16c is formed in the drift layer 16 (FIG. 7). In the high-carbon-concentration region 16c, the interstitial carbon concentration is high.
The n-type cathode region 20 having a higher n-type impurity concentration than the drift layer 16 is then formed on the opposite side of the drift layer 16 from the anode region 18. N-type impurity ions are implanted into the drift layer 16 by a known ion implantation technique, to form the cathode region 20 (FIG. 8). The impurity ion implantation may be performed prior to the carbon (C) ion implantation.
The n-type impurity is P (phosphorus), for example. Alternatively, the n-type impurity may be N (nitrogen), for example. The dose amount in the ion implantation is not smaller than 1×1015 cm−2 and not larger than 1×1017 cm−2, for example. So as to make the cathode region 20 a high-concentration region, the dose amount is preferably 1×1016 cm−2 or larger.
After n-type impurity ions are implanted, activation annealing (the heat treatment) is performed to activate the p-type impurity and the n-type impurity. During the activation annealing, the C (carbon) implanted into the high-carbon-concentration region 16c through ion implantation enters carbon vacancies, to form the low-carbon-vacancy-concentration region 16a in a portion of the drift layer 16 located on the side of the cathode electrode (FIG. 9).
So as to reduce carbon vacancies, the activation annealing is preferably performed at 1450° C. or higher, and more preferably, at 1550° C. or higher. The activation annealing is performed in an inert gas atmosphere, for example. If the temperature in the activation annealing is too high, the equilibrium concentration of carbon vacancies becomes higher. Therefore, the activation annealing is preferably performed at 1700° C. or lower, and more preferably, at a lower temperature than 1620° C.
The activation annealing is performed for 30 minutes or longer but not longer than two hours, for example.
The anode electrode 12 is then formed on the anode region 18 through a known process. The cathode electrode 14 is formed on the surface of the cathode region 20 (FIG. 10). By the above described manufacturing method, the PIN diode 100 of this embodiment shown in FIG. 1 is manufactured.
The p-type anode region (p-type impurity region) 18 may be formed after the high-carbon-concentration region 16c or the cathode region 20 is formed.
In the description below, the functions and the effects of the semiconductor device and the semiconductor device manufacturing method according to this embodiment are described.
In a bipolar device like the PIN diode 100, the lifetime of minority carriers becomes shorter due to defects such as carbon vacancies. If the lifetime of minority carriers becomes shorter, the rate of decrease in reverse recovery current (dir/dt) at a time when the PIN diode 100 is turned off becomes higher, resulting in increased noise. This problem is particularly noticeable in a case where the lifetime of minority carriers in the vicinity of the cathode electrode 14 near an edge of a depletion layer is short.
In the PIN diode 100 according to this embodiment, the low-carbon-vacancy-concentration region 16a is formed in a portion of the drift layer 16 located on the side of the cathode electrode 14. As the number of carbon vacancies to be minority carrier killers is small, the lifetime of the minority carriers in the portion of the drift layer 16 located on the side of the cathode electrode 14 becomes longer when the PIN diode 100 is turned off. Accordingly, the rate of decrease in reverse recovery current (dir/dt) becomes lower, and so-called soft recovery characteristics are realized. Thus, generation of noise and ringing at a time when the diode is turned off can be reduced.
In the PIN diode 100 according to this embodiment, the lifetime of the minority carriers in the low-carbon-vacancy-concentration region 16a becomes longer. Accordingly, the conductivity modulation effect at a time when the PIN diode 100 is turned on becomes greater. Thus, the on-state current increases, and the PIN diode 100 with a low on-state voltage is realized.
Specifically, the lifetime of the minority carriers in the low-carbon-vacancy-concentration region 16a is preferably 5 μsec or longer, and more preferably, 10 μsec or longer. Meanwhile, in the low-carbon-vacancy-concentration region 16a, the Z1/2 level density measured by DLTS is preferably 1×1011 cm−3 or lower.
The SiC substrate 10 is normally manufactured at a high temperature of 2000° C. or more by a sublimation technique or the like. The higher the SiC manufacturing temperature is, the higher the carbon vacancy concentration in the SiC becomes. Therefore, the SiC substrate 10 normally has a high carbon vacancy concentration.
By the method of manufacturing the PIN diode 100 according to this embodiment, the SiC substrate 10 used when the drift layer 16 is epitaxially grown is removed. Accordingly, the carbon vacancies in the SiC substrate 10 can be prevented from diffusing into the drift layer 16 due to the heat treatment during the manufacturing of the PIN diode 100. Thus, the carbon vacancy concentration in the portion of the drift layer 16 located on the side of the cathode electrode 14 can be easily lowered.
Furthermore, by the method of manufacturing the PIN diode 100 according to this embodiment, C (carbon) ions are implanted into the drift layer 16 after the SiC substrate 10 is removed. The implanted carbon turns into interstitial carbon, and fills carbon vacancies in the heat treatment that follows. As carbon vacancies are filled, the carbon vacancy concentration in the portion of the drift layer 16 located on the side of the cathode electrode 14 can be further lowered.
Also, by the method of manufacturing the PIN diode 100 according to this embodiment, C (carbon) is introduced from the side of the cathode region 20. Therefore, the carbon vacancy concentration in the portion of the drift layer 16 located on the side of the cathode region 20 can be more easily lowered than in a case where C (carbon) is introduced from the side of the anode region 18, for example. Accordingly, lower production costs can be realized through a reduction in the manufacturing time of the PIN diode 100.
By the manufacturing method according to this embodiment, the activation of the p-type impurity and the n-type impurity, and the heat treatment for filling carbon vacancies are conducted at the same time in the above described example case. However, a second heat treatment for filling carbon vacancies may be performed after a first heat treatment for activating the p-type impurity or the n-type impurity is performed. In this case, the temperature in the second heat treatment is preferably lower than the temperature in the first heat treatment, so as to sufficiently activate the p-type impurity or the n-type impurity and sufficiently lower the carbon vacancy concentration.
Through the above described functions, the PIN diode 100 according to this embodiment lowers the rate of decrease in reverse recovery current, and realizes soft recovery characteristics. Also, the lifetime of carriers becomes longer, and the on-state resistance becomes lower.
Further, by the manufacturing method according to this embodiment, the PIN diode 100 that has soft recovery characteristics and a low on-state resistance can be realized at low costs.
Second Embodiment
A semiconductor device manufacturing method according to this embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; forming a thermally-oxidized film at the exposed part of the SiC layer; removing the thermally-oxidized film; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.
The semiconductor device manufacturing method according to this embodiment is another example of a method of manufacturing the semiconductor device of the first embodiment shown in FIG. 1. The manufacturing method according to this embodiment differs from the manufacturing method according to the first embodiment, in that the low-carbon-vacancy-concentration region 16a is formed not through ion implantation but through SiC oxidation. The same explanations as those in the first embodiment will not be repeated.
FIGS. 11 through 14 are schematic cross-sectional views showing the semiconductor device being manufactured by the semiconductor device manufacturing method according to this embodiment. The removal of the SiC substrate 10 and the procedures before that are the same as those by the manufacturing method according to the first embodiment (FIG. 11).
A thermally-oxidized film 22 is then formed on the opposite side (the other side) of the n-type drift layer (n-type SiC layer) 16 from the anode region (p-type impurity region) 18 (FIG. 12). A thermally-oxidized film 22 is formed at exposed part of the n-type drift layer (n-type SiC layer) 16. As the interstitial carbon generated at the time of the formation of the thermally-oxidized film 22 fills carbon vacancies, the low-carbon-vacancy-concentration region 16a is formed on the opposite side of the drift layer 16 from the anode region 18.
The thermal oxidation for forming the thermally-oxidized film 22 is performed in an oxidizing atmosphere at a temperature not lower than 800° C. and not higher than 1500° C., for example. So as to sufficiently lower the carbon vacancy concentration, the temperature is preferably not lower than 900° C. and not higher than 1350° C. More preferably, the temperature is not lower than 1150° C. and not higher than 1300° C.
The thermally-oxidized film 22 is then removed (FIG. 13). For example, the thermally-oxidized film 22 is removed by hydrofluoric-acid wet etching.
The n-type cathode region 20 having a higher n-type impurity concentration than the drift layer 16 is then formed on the opposite side (the other side) of the drift layer 16 from the anode region 18. N-type impurity ions are implanted into the drift layer 16 by a known ion implantation technique, to form the cathode region 20 (FIG. 14).
The n-type impurity is P (phosphorus), for example. Alternatively, the n-type impurity may be N (nitrogen), for example. The dose amount in the ion implantation is not smaller than 1×1015 cm−2 and not larger than 1×1017 cm−2, for example. So as to make the cathode region 20 a high-concentration region, the dose amount is preferably 1×1016 cm−2 or larger.
After n-type impurity ions are implanted, activation annealing (the heat treatment) is performed to activate the p-type impurity and the n-type impurity.
The activation annealing is performed in an inert gas atmosphere, for example. If the temperature in the activation annealing is too high, the equilibrium concentration of carbon vacancies becomes higher. Therefore, the activation annealing is preferably performed at 1700° C. or lower, and more preferably, at a lower temperature than 1620° C.
The anode electrode 12 is then formed on the anode region 18 through a known process. The cathode electrode 14 is formed on the surface of the cathode region 20, so that the PIN diode 100 of this embodiment shown in FIG. 1 is completed.
By the manufacturing method according to this embodiment, the PIN diode 100 that has soft recovery characteristics and a low on-state resistance can be realized.
The p-type anode region (p-type impurity region) 18 may be formed after the thermally-oxidized film 22 is formed.
In this embodiment, the thermally-oxidized film 22 is formed on the carbon face side of the drift layer 16. In the carbon face, the oxidation rate is 10 times as high as that in the silicon face. Accordingly, an oxide film having the same thickness as that in the silicon face can be formed in a shorter time or at a lower temperature than that in the silicon face. Thus, the low-carbon-vacancy-concentration region 16a can be readily formed. Accordingly, lower production costs can be realized through a reduction in the manufacturing time of the PIN diode 100.
Although the n-type impurity ion implantation for forming the cathode region 20 is conducted after the removal of the thermally-oxidized film 22 in the above described example case, the n-type impurity ion implantation may be conducted prior to the formation of the thermally-oxidized film 22. As the thermally-oxidized film 22 is formed after the n-type impurity ion implantation, the n-type impurity piles up in the interface between the thermally-oxidized film 22 and the SiC, so that the thin cathode region 20 with a high concentration can be formed.
In a case where the n-type impurity ion implantation is conducted prior to the formation of the thermally-oxidized film 22, the thermally-oxidized film 22 is preferably formed by performing thermal oxidation to a greater depth than the projected range (Rp) of the n-type impurity ion implantation, so as to form the thin cathode region 20 having a high concentration.
Although the p-type impurity ion implantation for forming the anode region 18 is conducted prior to the formation of the thermally-oxidized film 22 in the above described example case, the p-type impurity ion implantation may be conducted after the formation of the thermally-oxidized film 22.
Although the thermally-oxidized film 22 is formed only on the opposite side of the drift layer 16 from the anode region (p-type impurity region) 18 in the above described example case of this embodiment, another thermally-oxidized film may also be formed on the side of the anode region 18 at the same time. As another thermally-oxidized film is formed on the side of the anode region 18 to be a silicon face, the carbon vacancy concentration in the portion of the drift layer 16 on the side of the anode region 18 becomes lower, and further, the on-state resistance can be lowered.
Third Embodiment
A semiconductor device manufacturing method according to this embodiment is the same as the method according to the first embodiment, except that a thermally-oxidized film is formed on the opposite side of the SiC layer from the p-type impurity region (at the exposed part of the SiC layer) after the heat treatment. Therefore, the same explanations as those in the first embodiment will not be repeated.
The semiconductor device manufacturing method according to this embodiment is yet another example of a method of manufacturing the semiconductor device of the first embodiment shown in FIG. 1. The low-carbon-vacancy-concentration region 16a is formed through both ion implantation and SiC oxidation.
FIGS. 15 through 17 are schematic cross-sectional views showing the semiconductor device being manufactured by the semiconductor device manufacturing method according to this embodiment. The procedures until n-type impurity ions are implanted into the drift layer 16 and activation annealing (the heat treatment) is performed after C (carbon) ions are implanted into the opposite side (the other side) of the drift layer (n-type SiC layer) 16 from the anode region (p-type impurity region) 18 are the same as those of the first embodiment. The low-carbon-vacancy-concentration region 16a is formed with the carbon implanted through the ion implantation (FIG. 15).
A thermally-oxidized film 22 is formed on the opposite side of the n-type drift layer 16 from the anode region 18 (FIG. 16). As the interstitial carbon generated at the time of the formation of the thermally-oxidized film 22 fills carbon vacancies, the carbon vacancy concentration in the low-carbon-vacancy-concentration region 16a becomes even lower.
The n-type impurity piles up in the interface between the thermally-oxidized film 22 and the SiC, so that the thin cathode region 20 with a high concentration can be formed.
The thermally-oxidized film 22 is then removed (FIG. 17). For example, the thermally-oxidized film 22 is removed by hydrofluoric-acid wet etching.
The anode electrode 12 is then formed on the anode region 18 through a known process. The cathode electrode 14 is formed on the surface of the cathode region 20, so that the PIN diode 100 of this embodiment shown in FIG. 1 is completed.
By the manufacturing method according to this embodiment, the PIN diode 100 that has soft recovery characteristics and a low on-state resistance can be realized. Particularly, as the low-carbon-vacancy-concentration region 16a is formed through both ion implantation and SiC oxidation, a PIN diode 100 that has even better soft recovery characteristics and a lower on-state resistance than those of the first and second embodiments is realized.
Fourth Embodiment
A semiconductor device according to this embodiment includes: a first electrode; a second electrode; an n-type SiC layer provided between the first electrode and the second electrode, the SiC layer having a profile indicating that the carbon vacancy concentration increases, decreases, increases, and decreases in the direction from the first electrode toward the second electrode; and a p-type impurity region provided between the first electrode and the SiC layer.
FIG. 18 is a schematic cross-sectional view showing the structure of a PIN diode that is a semiconductor device according to this embodiment.
This PIN diode 200 includes an anode electrode (the first electrode) 12, a cathode electrode (the second electrode) 14, an n−-type drift layer (the n-type SiC layer) 16, a first low-carbon-vacancy-concentration region (a first region) 16d, a second low-carbon-vacancy-concentration region (a second region) 16e, a third low-carbon-vacancy-concentration region (a third region) 16f, a p-type anode region (the p-type impurity region) 18, and an n-type cathode region (an n-type impurity region) 20.
The n−-type drift layer 16 is provided between the anode electrode 12 and the cathode electrode 14. The drift layer 16 is a SiC epitaxially grown layer formed on a SiC substrate (not shown) by epitaxial growth, for example.
The concentration of the n-type impurity in the drift layer 16 is not lower than 5×1014 cm−3 and not higher than 5×1015 cm−3, for example. The n-type impurity is N (nitrogen), for example. The thickness of the drift layer 16 is not smaller than 50 μm and not greater than 150 μm, for example.
The surface of the drift layer 16 is a plane tilted zero to eight degrees with respect to the silicon face, for example. A plane tilted zero to eight degrees with respect to the silicon face can be regarded as substantially equivalent to the silicon face in terms of characteristics.
The drift layer 16 has the low-carbon-vacancy-concentration region 16d in the middle portion thereof. The drift layer 16 has the low-carbon-vacancy-concentration region 16e on the side of the anode electrode 12. The drift layer 16 has the low-carbon-vacancy-concentration region 16f on the side of the cathode electrode 14.
The p-type anode region 18 is provided between the anode electrode 12 and the drift layer 16. The anode region 18 is provided on the surface of the drift layer 16.
The concentration of the p-type impurity in the anode region 18 is not lower than 1×1018 cm−3 and not higher than 1×1020 cm−3, for example. The p-type impurity in the anode region 18 is Al (aluminum), for example. Alternatively, the p-type impurity may be B (boron), Ga (gallium), or In (indium).
The depth of the anode region 18 is approximately 0.3 μm, for example. The surface of the anode region 18 is also a plane tilted zero to eight degrees with respect to the silicon face, for example.
The anode electrode 12 is made of a metal, for example. The metal forming the anode electrode 12 is TiN (titanium nitride), for example. Another metal such as Al (aluminum) may be stacked on the TiN. Other than a metal, it is possible to employ an electrically-conductive material such as polycrystalline silicon containing an n-type impurity.
The anode region 18 and the anode electrode 12 are electrically connected.
The n-type cathode region 20 is provided between the drift layer 16 and the cathode electrode 14. The cathode region 20 has the function to lower the contact resistance of the cathode electrode 14.
The n-type impurity concentration in the cathode region 20 is higher than the n-type impurity concentration in the drift layer 16. The concentration of the n-type impurity in the cathode region 20 is not lower than 1×1018 cm−3 and not higher than 1×1020 cm−3, for example. The n-type impurity is P (phosphorus), for example. Alternatively, the n-type impurity may be N (nitrogen), for example. The thickness of the cathode region 20 is not smaller than 0.1 μm and not greater than 1 μm, for example.
The surface on the side of the cathode electrode 14 is a plane tilted zero to eight degrees with respect to the carbon face. A plane tilted zero to eight degrees with respect to the carbon face can be regarded as substantially equivalent to the carbon face in terms of characteristics.
The cathode electrode 14 is formed with stacked layers that are a Ni (nickel) barrier metal layer and an Al (aluminum) metal layer formed on the barrier metal layer, for example. The Ni barrier metal layer and the Al metal layer may form an alloy through a reaction. Alternatively, the Ni and the cathode region 20 may form a silicide through a reaction.
The cathode region 20 and the cathode electrode 14 are electrically connected.
FIG. 19 is a diagram showing the profile of the concentration of carbon vacancies in the semiconductor device according to this embodiment. This diagram shows the profile of the concentration of carbon vacancies in a cross-section including the p-type anode region (p-type impurity region) 18 and the n-type cathode region (n-type impurity region) 20. The concentration of carbon vacancies can be measured by DLTS (Deep Level Transient Spectroscopy). Specifically, the Z1/2 concentration measured by DLTS is regarded as the concentration of carbon vacancies, for example.
As shown in FIG. 19, the n-type drift layer (n-type SiC layer) 16 has a profile indicating that the carbon vacancy concentration increases, decreases, increases, and then decreases in the direction from the anode electrode (first electrode) 12 toward the cathode electrode (second electrode) 14.
Next, a semiconductor device manufacturing method according to this embodiment is described. The semiconductor device manufacturing method according to this embodiment is an example of a method of manufacturing the semiconductor device shown in FIG. 18.
FIGS. 20 through 25 are schematic cross-sectional views showing the semiconductor device being manufactured by the semiconductor device manufacturing method according to this embodiment.
First, an n+-type SiC substrate 10 is prepared. The SiC substrate 10 is the SiC of 4H—SiC containing N (nitrogen), for example, as the n-type impurity at an impurity concentration not lower than 1×1018 cm−3 and not higher than 1×1020 cm−3, for example. The SiC substrate 10 is a substrate formed by a sublimation technique, for example. The thickness of the SiC substrate 10 is not smaller than 300 μm and not greater than 500 μm, for example.
One of the planes of the SiC substrate 10 is a silicon face, for example. The other one of the planes of the SiC substrate 10 is a carbon face, for example.
The n−-type drift layer 16 is formed on the silicon face of the SiC substrate 10 by an epitaxial growth technique (FIG. 20).
Carbon (C) ions are then implanted into the silicon face side of the drift layer 16 (FIG. 21). Through the carbon (C) ion implantation, a high-carbon-concentration region 16g is formed in the drift layer 16.
The drift layers 16 on two substrates manufactured by the above method are then bonded to each other (FIG. 22). In this case, the silicon faces of the two substrates are bonded to each other.
Both surfaces of the bonded substrates are polished, and at least part of each SiC substrate 10 is removed, so that the drift layer 16 is exposed. Although the entire SiC substrates 10 are removed in this example case, only the peripheral portions of the SiC substrates 10 may be left, or the SiC substrates 10 may be left in a lattice-like fashion, so as to secure strength after the removal, for example.
Carbon (C) ions are then implanted into both of the exposed surfaces of the drift layer 16 (FIG. 23). Through the carbon (C) ion implantation, high-carbon-concentration regions 16h and 16i are formed in the drift layer 16.
The p-type anode region (p-type impurity region) 18 is then formed on one of the surfaces of the drift layer 16. P-type impurity ions are implanted into the drift layer 16 by a known ion implantation technique, to form the anode region 18 (FIG. 24).
The p-type impurity is Al (aluminum), for example. The dose amount in the ion implantation is not smaller than 1×1015 cm−2 and not larger than 1×1017 cm−2, for example. So as to make the anode region 18 a high-concentration region, the dose amount is preferably 1×1016 cm−2 or larger.
The n-type cathode region 20 having a higher n-type impurity concentration than the drift layer 16 is then formed on the opposite side of the drift layer 16 from the anode region 18. N-type impurity ions are implanted into the drift layer 16 by a known ion implantation technique, to form the cathode region 20 (FIG. 25).
The n-type impurity is P (phosphorus), for example. Alternatively, the n-type impurity may be N (nitrogen), for example. The dose amount in the ion implantation is not smaller than 1×1015 cm−2 and not larger than 1×1017 cm−2, for example. So as to make the cathode region 20 a high-concentration region, the dose amount is preferably 1×1016 cm−2 or larger.
After n-type impurity ions are implanted, activation annealing (the heat treatment) is performed to activate the p-type impurity and the n-type impurity. At the time of the activation annealing, the C (carbon) implanted through the ion implantation enters carbon vacancies, and the first low-carbon-vacancy-concentration region (first region) 16d, the second low-carbon-vacancy-concentration region (second region) 16e, and the third low-carbon-vacancy-concentration region (third region) 16f are formed in the drift layer 16.
So as to reduce carbon vacancies, the activation annealing is preferably performed at 1450° C. or higher, and more preferably, at 1550° C. or higher. The activation annealing is performed in an inert gas atmosphere, for example. If the temperature in the activation annealing is too high, the equilibrium concentration of carbon vacancies becomes higher. Therefore, the activation annealing is preferably performed at 1700° C. or lower, and more preferably, at a lower temperature than 1620° C.
The activation annealing is performed for 30 minutes or longer but not longer than two hours, for example.
The anode electrode 12 is then formed on the anode region 18 through a known process. The cathode electrode 14 is formed on the surface of the cathode region 20, so that the PIN diode 200 of this embodiment shown in FIG. 18 is completed.
With the semiconductor device and the semiconductor device manufacturing method according to this embodiment, the rate of decrease in reverse recovery current is lowered, and soft recovery characteristics are realized, as in the first embodiment. Also, the lifetime of carriers becomes longer, and the on-state resistance becomes lower. The on-state resistance is further lowered, as the first low-carbon-vacancy-concentration region (first region) 16d is formed in the middle portion of the drift layer 16, and the second low-carbon-vacancy-concentration region (second region) 16e is formed on the side of the anode electrode 12.
By the manufacturing method according to this embodiment, the PIN diode 200 that has the thick drift layer 16, has a high breakdown voltage, and has a low on-state resistance can be readily manufactured.
Although silicon faces are bonded to each other in the above described example of this embodiment, carbon faces may be bonded to each other, or a silicon face and a carbon face may be bonded to each other, for example. Particularly, in a case where a silicon face and a carbon face are bonded to each other, the crystalline characteristics at the junction portion are excellent.
Although silicon carbide crystalline structures are 4H—SiC in the above described embodiments, the present disclosure can also be applied to silicon carbides having other crystalline structures such as 6H—SiC and 3C—SiC. Also, in the above described embodiments, an electrode is formed on a Si face or a C face. However, the present disclosure can also be applied in cases where a contact electrode is formed on an a face, an m face, or an intermediate face between those faces.
Although examples of PIN diodes have been described in the above embodiments, the present disclosure can also be applied to other bipolar devices such as IGBTs (Insulated Gate Bipolar Transistors).
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the semiconductor device manufacturing method, and the semiconductor device described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

## Claims

1. A semiconductor device manufacturing method comprising:
forming an n-type SiC layer on a SiC substrate;
forming a p-type impurity region at one side of the n-type SiC layer;
performing a first heat treatment;
exposing another side of the n-type SiC layer by removing at least part of the SiC substrate;
implanting carbon (C) ions into exposed part of the n-type SiC layer;
forming an n-type impurity region on exposed part of the n-type SiC layer, an n-type impurity concentration in the n-type impurity region having a higher n-type impurity concentration than an n-type impurity concentration in the n-type SiC layer;
performing a second heat treatment to form a low-carbon-vacancy concentration region, a temperature in the second heat treatment being lower than a temperature in the first heat treatment;
forming a first electrode on the p-type impurity region; and
forming a second electrode on the n-type impurity region,
wherein the low-carbon-vacancy-concentration region is formed in a portion of the n-type SiC layer and on the side of the second electrode, and a Z1/2 level density measured by DLTS (Deep Level Transient Spectroscopy) in the low-carbon-vacancy-concentration region is 1×1011 cm−3 or lower.

2. The method according to claim 1, wherein a temperature in the second heat treatment is 1450° C. or higher.

3. The method according to claim 1, further comprising,
forming a thermally-oxidized film at the exposed part of the SiC layer after the performing the second heat treatment prior to the forming the second electrode.

4. The method according to claim 1, wherein the p-type impurity region is formed through p-type impurity ion implantation.

5. The method according to claim 3, wherein a temperature for the forming the thermally-oxidized film is not lower than 1150° C.

6. The method according to claim 1, wherein a lifetime of a minority carrier in the low-carbon-vacancy-concentration region is 5 μsec or longer.

7. The method according to claim 1, wherein the temperature in the second heat treatment is higher than the temperature when implanting carbon (C) ions into exposed part of the n-type SiC layer.

8. A semiconductor device manufacturing method comprising:
forming an n-type SiC layer on a SiC substrate; then
forming a p-type impurity region at one side of the n-type SiC layer; then
exposing another side of the n-type SiC layer by removing at least part of the SiC substrate; then
forming an n-type impurity region on exposed part of the n-type SiC layer, an n-type impurity concentration in the n-type impurity region having a higher n-type impurity concentration than an n-type impurity concentration in the n-type SiC layer; then
performing a first heat treatment; then
implanting carbon (C) ions into exposed part of the n-type SiC layer; then
performing a second heat treatment to form a low-carbon-vacancy concentration region, a temperature in the second heat treatment being lower than a temperature in the first heat treatment; and then
forming a first electrode on the p-type impurity region and a second electrode on the n-type impurity region,
wherein the low-carbon-vacancy-concentration region is formed in a portion of the n-type SiC layer and on the side of the second electrode, and a Z1/2 level density measured by DLTS (Deep Level Transient Spectroscopy) in the low-carbon-vacancy-concentration region is 1×1011 cm−3 or lower.

9. The method according to claim 8, wherein a temperature in the second heat treatment is 1450° C. or higher.

10. The method according to claim 8, wherein the p-type impurity region is formed through p-type impurity ion implantation.

11. The method according to claim 8, wherein a lifetime of a minority carrier in the low-carbon-vacancy-concentration region is 5 μsec or longer.

12. The method according to claim 8, wherein the temperature in the second heat treatment is higher than the temperature when implanting carbon (C) ions into exposed part of the n-type SiC layer.